Management method for storage device, controller and storage device

Abstract

The invention discloses a management method for a storage device, a controller and the storage device. According to the management method, for an NAND type flash memory of an N-order storage unit, when some conditions are met, writing data can be processed by adopting an M-order storage unit mode (M is smaller than N), so that high writing performance of a low-order storage unit mode is obtained, and meanwhile, when other conditions (for example, low load or idle duration exceeds set time) are met, high writing performance of a low-order storage unit mode is obtained. And the data written in the low-order storage unit mode is carried to the free space according to the high-order storage unit mode, so that the data storage density is improved, and the space utilization rate is improved. Further, for the NAND type flash memory of the N-order storage unit, a single-order storage unit mode is adopted to process write data.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a management method, controller, and storage device for storage devices. Background Technology

[0002] Currently, many storage devices, such as USB flash drives, SD cards, CF cards, SSDs, eMMC embedded storage cards, and UFS devices, primarily use NAND flash memory as their storage medium, and it is gradually becoming the mainstream form. Compared to traditional magnetic media storage devices, its performance represents a qualitative leap. NAND flash memory consists of a large number of storage cells, each capable of storing one or more bits of data. Storage cells storing one bit are called Single-Level Cells (SLC), while multi-level cells storing multiple bits (also known as XLC) can be further categorized into two levels: two-level cells (MLC) storing two bits, three-level cells (TLC) storing three bits, four-level cells (QLC) storing four bits, five-level cells (PLC) storing five bits, and so on. Higher-order storage units have a higher data storage density than lower-order storage units, but writing data to higher-order storage units takes longer and has lower performance than writing data to lower-order storage units. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a management method, controller, and storage device for a storage device, the management method being able to achieve a balance between space utilization and write performance of NAND flash memory in high-order storage cells.

[0004] According to a first aspect of the present invention, a management method for a storage device is provided, the storage device including a controller and a storage medium, the storage medium being a NAND flash memory having N-level storage cells, the management method comprising:

[0005] When the host writes data to the storage device, if the current state meets the first condition, the data is written to the NAND flash memory in the M-level storage cell mode, where N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M is less than N.

[0006] If the current state meets the second condition, then the data written in the M-level storage unit mode will be moved to the free storage space according to the N-level storage unit mode.

[0007] In some embodiments, the method further includes: for a host writing data to the storage device, if the current state does not meet a first condition, then for a write command, writing data to the NAND flash memory in an N-level storage cell mode.

[0008] In some embodiments, the first condition is the union or intersection of one or more of the following conditions:

[0009] The remaining useful life of the storage device is less than a first threshold.

[0010] The remaining storage space of the storage device is greater than the second threshold.

[0011] The amount of data written to the storage device in the M-level storage cell mode is less than the third threshold.

[0012] In some embodiments, the second condition is that the host remains idle for more than a set time or the host remains under low load for more than a set time.

[0013] In some embodiments, the method further includes setting a mode flag to indicate whether the corresponding mode is enabled.

[0014] In some embodiments, during the process of the host writing data to the storage device, when the amount of data written according to the M-level storage cell mode exceeds a fourth threshold, the system switches to the N-level storage cell mode to continue writing data.

[0015] In some embodiments, in a multi-user scenario, multiple different third thresholds are set for multiple users.

[0016] In some embodiments, the M-level storage cell mode is a single-level storage cell mode.

[0017] According to a second aspect of the present invention, a controller is provided for performing any of the above-described methods for managing a storage device.

[0018] According to a third aspect of the present invention, a storage device is provided, comprising: a coupled controller and a NAND flash memory having N-level storage cells, wherein the controller performs any of the above-described management methods for the storage device.

[0019] The storage device management method proposed in this invention, for NAND flash memory with N-level storage cells, allows data to be written in an M-level (M < N) storage cell mode under certain conditions, thereby achieving high write performance in the lower-level storage cell mode. Simultaneously, under other conditions (e.g., low load or idle time), data written in the M-level storage cell mode is then moved to idle storage space in the N-level storage cell mode, thereby increasing data storage density and improving the space utilization of the storage medium. Furthermore, for NAND flash memory with N-level storage cells, a single-level storage cell mode is used to process written data. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic block diagram of a host system 100 according to an embodiment of the present invention is shown;

[0022] Figure 2 A flowchart of a management method for a storage device according to an embodiment of the present invention is shown;

[0023] Figure 3 A flowchart of a management method for a storage device according to another embodiment of the present invention is shown. Detailed Implementation

[0024] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0025] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0026] Unless the context explicitly requires it, the terms "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than exclusive or exhaustive; that is, meaning "including but not limited to." In the description of this invention, it should be understood that terms such as "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0027] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0028] Figure 1 A schematic block diagram of a host system 100 according to an embodiment of the present invention is shown. The host system 100 is, for example, a personal computer, a laptop computer, or a server.

[0029] Host system 100 includes host device 110 (e.g., a computer system including a main processor and memory) and storage devices. Host device 110 can issue host commands to the storage device, causing the storage device to manage host data stored therein according to the commands. For example, host device 110 can be communicatively connected to the storage device (e.g., via host interface 121) and can issue various commands to the storage device (e.g., READ, WRITE, UNMAP, REASSIGNBLOCK, TRIM, etc.). The storage device can store, update, read, and / or otherwise manage host data according to the address range prompted by the command. Once a command is executed, the storage device can transmit a response to host device 110, indicating that the command has been successfully completed.

[0030] The storage device comprises a controller 120 and a storage medium 130. The controller 120 includes a host interface 121, a processor 123, a cache unit 124, and a storage medium interface 128. The host interface 121 of the controller 120 is connected to the host device 110 to transmit host commands and host data. The processor 123 is connected to the host interface 121, the cache unit 124, and the storage medium interface 128; the processor 123 parses the host commands and executes the corresponding operations. The cache unit 124, for example, is SRAM and / or DRAM, and can be used to store the mapping relationship between logical addresses and physical addresses, as well as some configuration data. The storage medium interface 128 includes interface circuitry for implementing data transmission between the controller 120 and the storage medium 130.

[0031] The controller 120 also has a core software layer, consisting of several programs executed by the processor 123 to perform corresponding functions, including: data read / write, bad block management, wear leveling, garbage collection, power-off recovery, write balancing technology, etc. The core software layer is typically formed as firmware.

[0032] Storage medium 130 is, for example, a flash memory chip array. To improve data read / write performance, the storage medium interface 128 of controller 120 can access the individual flash memory chips of storage medium 130 in parallel via multiple channels (e.g., CH0 and CH2), with each channel connecting a group of flash memory chips. In this embodiment of the invention, storage medium 130 is defined as a NAND flash memory with N-level memory cells, where N is a positive integer greater than or equal to 2.

[0033] Figure 2 This is a flowchart of a method for managing a storage device according to an embodiment of this disclosure. The method can be formed as a computer program and executed by a processor 123 in a controller 120. Furthermore, the formed computer program can become the firmware of the controller 120 and run continuously after the storage device is powered on.

[0034] like Figure 2 As shown, the management method for storage devices includes the following steps.

[0035] In step S210, it is determined whether the current state meets the first condition. If yes, step S220 is executed; otherwise, step S230 is executed.

[0036] In step S220, data is written to the NAND flash memory according to the M-level storage cell mode.

[0037] In step S230, data is written to the NAND flash memory according to the N-level storage cell mode.

[0038] In step S240, it is determined that the current state meets the second condition. If so, step S250 is executed.

[0039] In step S250, the data written in the M-level storage cell mode is moved to the free storage space according to the N-level storage cell mode.

[0040] The method provided in this embodiment is for storage devices using NAND flash memory with N (N greater than or equal to 2) levels of storage cells as the storage medium. Generally, when writing data to an N-level storage cell, N bits of data are written. However, in special cases, the characteristic that an N-level storage cell can also store M bits of data can be utilized, allowing only M bits of data to be written to the N-level storage cell. For ease of description, this document refers to the writing method of writing N bits of data as the N-level storage cell mode, and the writing method of writing M bits of data as the M-level storage cell mode. For example, for a two-level storage cell, only one bit of data can be written to the two-level storage cell according to the single-level storage cell mode, or two bits of data can be written to the two-level storage cell according to the two-level storage cell mode.

[0041] According to this embodiment, for NAND flash memory with N-level storage cells, when the first condition is met, data is written to it using the M-level (M < N) storage cell mode to obtain high write performance of the low-level storage cell mode. Simultaneously, when the second condition is met (e.g., low host load or host idle time exceeding a set time), the data written in the M-level storage cell mode is then moved (i.e., written) to the idle storage space according to the N-level storage cell mode, thereby increasing data storage density and improving the space utilization of the storage medium. The determination of low load is mainly based on not affecting user experience; for example, a host access speed of less than a few MB / s can be defined as low load, and the duration threshold is set to 6 seconds.

[0042] The first condition in this embodiment can be defined according to actual needs. For example, the first condition can be defined as the remaining lifespan of the storage device being less than a first threshold. Specifically, the product specifications of flash memory chips usually specify the maximum number of write / erase cycles, and the remaining lifespan being less than the first threshold is equivalent to the remaining number of write / erase cycles being less than the set number. The first condition can also be defined as the remaining storage space of the storage device being greater than a second threshold. The first condition can also be defined as the amount of data written in the M-level storage cell mode in the storage device not exceeding a third threshold. Specifically, before writing host data to the storage device, it is determined whether the amount of data already written in the M-level storage cell mode does not exceed the third threshold. In addition, in multi-user scenarios, multiple different third thresholds can be set for multiple users. For example, an administrator needs 10GB to 40GB of hard disk space to install an operating system, so the third threshold configured for the administrator user can be larger, while the third threshold configured for ordinary users can be smaller, so as to adapt to the application needs of different users. Multiple of the above conditions can also be combined in the form of an intersection, that is, the current state needs to satisfy the intersection of the above conditions to execute step S220.

[0043] The first condition can be determined after the controller of the storage device receives the write command sent by the host. The write command is the host requesting the storage device to write data. If the storage device determines that the current state meets the first condition, it will receive the host data from the host and write the data into the storage medium according to the M-level storage cell mode.

[0044] The second condition in this embodiment is typically that the host is idle or under low load for more than a set time. For example, the host being idle for more than a set time means that the host has no interaction with the storage device for more than 3 seconds; the host being under low load for more than a set time means that the host has only a small amount of interaction with the storage device (e.g., read and write loads are both below 6MB / s) for 6 seconds. In this case, the bandwidth inside the NAND flash memory is sufficient to execute the operation in step S250 while interacting with the host. Furthermore, the storage device will also perform normal background garbage collection or inspection tasks after the host has been idle or under low load for a period of time.

[0045] It should be understood that in most user scenarios, the demand for continuous high-speed writes is quantifiable. A threshold is set based on this quantifiable value, allowing the amount of data continuously written in low-order cell mode to not exceed this threshold. Once this threshold is exceeded, the system switches to high-order cell mode, reducing write amplification caused by the conversion from low-order to high-order cell mode. This ensures consistently high performance even with intermittent writes. In a further embodiment, if the same write command requires multiple write operations to write data to the NAND flash memory, the data is first written to the NAND flash memory in M-order cell mode. After each write operation, the amount of data written in M-order cell mode is calculated. If this amount exceeds a fourth threshold, the next write operation switches to N-order cell mode.

[0046] In some embodiments, for NAND flash memory with N-level storage cells, data is written in single-level storage cell mode when the first condition is met. This is because data written in single-level storage cell mode has higher retention capacity, which is very useful in certain scenarios. For example, for solid-state drives that only have an operating system pre-installed, they need to be stored in a warehouse for a long time before being provided to users. In this case, writing the operating system data to the solid-state drive in single-level storage cell mode will greatly reduce the risk of losing the operating system data due to the solid-state drive being idle for a long time and needing to be reinstalled (the data retention capacity of single-level storage cell mode is far superior to other modes).

[0047] Furthermore, it should be noted that although steps S210 to S250 are drawn in the same flowchart, these steps are not necessarily executed sequentially or consecutively. Steps S210 to S230 handle the host writing data to the storage device; in this case, steps S40 and S2250 are usually not executed. In fact, the combination of steps S210 to S230 and the combination of steps S240 to S250 are usually executed as independent tasks.

[0048] Figure 3This is a flowchart of a method for managing a storage device according to another embodiment of this disclosure. It includes the following steps.

[0049] In step S200, is the mode flag enabled? If so, proceed to step S210.

[0050] In step S210, it is determined whether the current state meets the first condition. If yes, step S220 is executed; otherwise, step S230 is executed.

[0051] In step S220, data is written to the NAND flash memory according to the M-level storage cell mode.

[0052] In step S230, data is written to the NAND flash memory according to the N-level storage cell mode.

[0053] In step S240, it is determined that the current state meets the second condition. If so, step S250 is executed.

[0054] In step S250, the data written in the M-level storage cell mode is moved to the free storage space according to the N-level storage cell mode.

[0055] According to this embodiment, the mode flag acts as a switch; when the mode flag is on, the storage device is allowed to execute... Figure 2 The illustrated embodiment. For NAND flash memory with N-level memory cells, data can be written to it using single-level memory cell mode, double-level memory cell mode, ..., N-level memory cell mode. To support mode switching, in some embodiments, N bits are set to correspond to single-level memory cell mode, double-level memory cell mode, ..., N-level memory cell mode respectively. A bit value of 0 indicates that the corresponding mode is off, and a bit value of 1 indicates that the corresponding mode is on. In other embodiments, the storage device using NAND flash memory with N-level memory cells only supports single-level memory cell mode and N-level memory cell mode. In this case, a flag bit can be set to 1. When the flag bit is equal to 1, it indicates that data can be written using single-level memory cell mode, and when the flag bit is equal to 0, it indicates that data can not be written using single-level memory cell mode.

[0056] In some embodiments, a mode flag is set based on the physical characteristics of the storage device, and the user is allowed to set the mode flag himself. For example, if multiple channels are stored between the controller of the storage device and the flash memory storage medium, when the controller writes data to the flash memory storage medium, data can be written to the flash memory storage medium in parallel through multiple channels. In this case, even if the N-level storage cell mode is used to write data to the flash memory storage medium, the performance is high enough. Therefore, the mode flag can be set to disallow the use of the M-level storage cell mode. Conversely, the mode flag can be set to allow the use of the M-level storage cell mode.

[0057] In some embodiments, the mode can be set based on the application scenario. For example, for the solid-state drive with a pre-installed operating system submitted above, the mode flag can be set to allow writing data in single-level storage cell mode.

[0058] It should be understood that the above-mentioned modes can be set according to actual circumstances, and the embodiments of the present invention are not limited thereto.

[0059] In summary, the embodiments of the present invention have the following advantages: First, the present invention takes into account both the data write volume and performance requirements of flash storage devices, thereby improving the user experience. In some scenarios, users can continuously obtain a high performance experience, while in other scenarios, the overall write volume of the flash storage device is guaranteed. Second, by setting the mode flag, the use of the low-level storage unit mode is restricted to certain conditions to avoid wasting storage resources.

[0060] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A management method for a storage device, the storage device comprising a controller and a storage medium, the storage medium being a NAND flash memory having N-level storage cells, the management method comprising: When the host writes data to the storage device, if the current state meets the first condition, the data is written to the NAND flash memory in the M-level storage cell mode, where N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M is less than N. If the current state meets the second condition, then the data written in the M-level storage unit mode will be moved to the free storage space according to the N-level storage unit mode.

2. The management method according to claim 1 further includes: When the host writes data to the storage device, if the current state does not meet the first condition, the data is written to the NAND flash memory in the N-level storage cell mode.

3. The management method according to claim 1, wherein, The first condition is the intersection of one or more of the following conditions: The remaining useful life of the storage device is less than a first threshold. The remaining storage space of the storage device is greater than the second threshold. The amount of data written to the storage device in the M-level storage cell mode is less than the third threshold.

4. The management method according to claim 1, wherein, The second condition is that the host is idle for more than a set time or the host is under low load for more than a set time.

5. The management method according to claim 1 further includes: Set a mode flag to indicate whether the corresponding mode is enabled.

6. The management method according to claim 1, wherein, During the process of the host writing data to the storage device, when the amount of data written according to the M-level storage cell mode exceeds the fourth threshold, the host switches to the N-level storage cell mode to continue writing data.

7. The management method according to claim 3, wherein, In multi-user scenarios, multiple different third thresholds can be set for multiple users.

8. The management method according to any one of claims 1 to 7, wherein, The M-level storage cell mode is a single-level storage cell mode.

9. A controller for a storage device, configured to perform the management method according to any one of claims 1 to 8.

10. A storage device, comprising: A coupled controller and a NAND flash memory having N-level storage cells, the controller performing the management method as described in any one of claims 1 to 8.

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