Multi-thread synchronous simulator method for self-reconstruction and self-evolution AI chip

Abstract

The invention discloses a multi-thread synchronous simulator method for a self-reconfiguration and self-evolution AI chip. The method is used for efficient function simulation of the code execution process of a processor comprising a master controller module, a data transmission module, a storage and calculation integrated module, a coprocessor module, a coprocessor cache module and other various units. According to the method, modeling is carried out on a functional unit organization, a register organization, a cache mechanism and the like of the self-reconstruction and self-evolution intelligent computing chip, and executable code file content is loaded, analyzed and executed in a software simulation mode. According to the method disclosed by the invention, a multi-thread parallel mechanism is established, and simulation of effects such as instruction execution and synchronization among units on each unit in the chip on a beat level is realized. A unified data management mechanism and a user interaction mechanism are established, and efficient data access and debugging support are realized.

Description

Technical Field

[0001] This invention relates to the field of computer system simulation, specifically to a hardware behavior simulator for a particular chip. Through object-oriented programming and hardware modeling techniques, this invention constructs a functional-level and clock-step precision simulator for the chip. This simulator is used to simulate the instruction set architecture, microarchitecture, and other functions of the target chip on a general-purpose computer platform, significantly reducing hardware development costs and improving development efficiency. Background Technology

[0002] A simulator is a software tool that mimics specific behaviors, its core purpose being to reproduce the functionality and characteristics of a target chip under specific conditions. The working principle of a simulator is primarily based on model building and real-time simulation. First, the simulator needs to build a mathematical model of the target chip, which should accurately reflect the chip's dynamic behavior and interactive characteristics. Then, this model is run in real-time through a computer program or dedicated hardware to simulate the target chip's response under different conditions. Simulators typically also include a user interface and feedback system to allow users to interact with and monitor the simulation environment. The core of object-oriented programming is to achieve modular design through encapsulation, inheritance, and polymorphism. Object-oriented programming abstracts real-world problems into objects and classes, improving code reusability and maintainability, and has become the mainstream paradigm in modern software development. Hardware simulation typically involves a large number of parallel tasks. Multithreading can allocate different hardware modules to run on independent threads, significantly improving throughput. The behavior of unit modules depends on strict timing, and multithreading can simulate the interaction timing between unit modules through synchronization mechanisms. Summary of the Invention

[0003] The technical problem solved by this invention is as follows: for a specific chip architecture, modeling the chip's functional units, registers, cache space, and other resources, and loading, parsing, and executing the binary code file content through software simulation. It interacts with the user to obtain the starting address and number of instructions for the main controller module, the starting address and number of tasks, etc., and performs functional simulation of the target code of each chip unit at the instruction level and clock cycle. To achieve the above objectives, this invention provides a multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips, including simulation of a main controller module, simulation of a data transmission module, simulation of an in-memory computing module, simulation of a coprocessor module, simulation of a coprocessor cache module, and a high-concurrency multi-threaded execution model. Note that the hardware components such as registers and caches mentioned below are all abstract implementations of physical hardware storage structures at the software technology level, specifically manifested as pointers or STL containers, which are logical simulations of memory address space and data storage. Furthermore, the present invention provides a multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips, wherein the task instructions of each module are issued by the central controller simulation module, and each module has the function of instruction execution or parameterized operation. Furthermore, this invention provides a multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips. The main controller simulation module receives dynamically input messages from the user, loads its own instructions and task information from other modules, then fetches, decodes, and executes instructions from the main controller cache. The main controller simulation module also distributes task information to other simulation modules. After completing their assigned tasks, other simulation modules modify predefined integer semaphores and send feedback to the main controller simulation module to notify it to change its status register. Furthermore, the present invention provides a multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips. The data transmission simulation module parses the task information issued by the main controller simulation module and performs specific work according to the predetermined content of the configuration information, including but not limited to moving the source data of this task from external storage to the coprocessor cache module or the in-memory computing module. Furthermore, this invention provides a multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips. The coprocessor simulation module parses the task information issued by the main controller simulation module and executes instruction-related simulation functions. Data exchange between coprocessor simulation modules occurs through shared registers. Furthermore, the present invention provides a multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips, wherein the coprocessor cache simulation module parses the task information issued by the main controller simulation module, distributes the cached data of this module to the coprocessor simulation module according to the task information, and receives the output data of the coprocessor simulation module. Furthermore, the present invention provides a multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips, wherein the in-memory computing simulation module parses the task information issued by the central controller simulation module and executes instruction simulation functions related to the instructions. Furthermore, the present invention provides a multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips. The high-concurrency multi-threaded execution model is responsible for managing the threads of each simulation module, synchronizing the state of the main thread and the sub-threads, and ensuring that each simulation module executes in parallel. Compared with existing technologies, this invention provides a multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips. Each simulation module is managed independently. By encapsulating class member variables, each module maintains its private state and resources, exposing only standardized interfaces for interaction. This reduces the coupling between simulation modules within the project, achieving a design goal of high cohesion and low coupling. This invention allocates a contiguous address space on the heap and continuously distributes the resources of each module within this space, which not only conforms to the hardware design scheme but also expands the freedom of debugging during program runtime. Furthermore, this invention uniformly encapsulates the static attributes of each module, so subsequent architecture adjustments only require modification of this configuration file, reducing maintenance costs. Attached Figure Description

[0004] Figure 1 Functional unit framework diagram of the present invention Figure 2 Program framework diagram of the embodiment of the present invention Figure 3 Address space allocation diagram of the present invention Figure 4 Multithreaded framework diagram of this invention embodiment Figure 5 Multithreaded execution flowchart of this invention embodiment Figure 6 Schematic diagram of double-beat data transmission timing in an embodiment of the present invention Detailed Implementation

[0005] The following description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed explanation of the multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips proposed in this invention. like Figure 1 As shown in the figure, the multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips provided in this embodiment of the invention implements functional modules including a main controller simulation module, a data transmission simulation module, a coprocessor simulation module, a coprocessor cache simulation module, and a memory-to-computer simulation module. All the above simulation modules have the function of parsing instructions or configuration information and can perform specified operations based on the instructions or configuration information. Specifically, the information parsed by each module is stored in a structure pointer of that module, and a mapping table between instruction information and functional simulation functions is established. Each functional simulation function is responsible for implementing the semantic operation of the corresponding instruction. Using the instruction information as an index, the instruction functional simulation function is called to achieve the predetermined function of the task. Since the parsing mechanisms of each functional module are similar, the parsing of instructions will not be explained separately below. like Figure 2 As shown, the program framework of this embodiment consists of a global data module, a main control module, a unit space initialization module, and a unit function module. The global data module includes instruction information, constants, cross-module information, and their initialization, such as semaphores for interaction between functional modules. In scenarios involving cross-module access to shared data, a mutex lock mechanism is used to ensure thread safety. The main control module includes object initialization, user interaction, and flow control. As the overall controller in this embodiment, the main control module needs to initialize various objects at the start of the program, such as the coordinates, status, and other attributes of each coprocessor, as well as strings used to display help information. During user interaction in this embodiment, the main control module needs to call different functions based on the user's dynamic input, such as checking the register values ​​of the main controller module or executing a cycle for each simulation module. As the main thread in the high-concurrency multi-threaded execution model, the main control module creates and drives the sub-threads of each functional unit to perform flow control. The unit space initialization module contains the space occupied by resources such as registers and caches within this module. All unit space initialization modules inherit from the same base class, which encapsulates the common characteristics of each unit initialization, namely the memory space occupied by this module. For example... Figure 3 As shown, after determining the memory space occupied by each unit member, based on the sum of the space sizes of all units, a corresponding contiguous storage area is allocated in the heap memory. Starting from the first address of the heap memory, contiguous memory space is allocated to each unit member in sequence. The unit functional modules simulate the code functionality of each unit. An object-oriented class structure is adopted. The root class defines the common characteristics of all unit functional modules, including module running state, execution cycle function, and module member initialization function. The first-level derived classes define the common characteristics of instruction execution functional modules, such as instruction buffer, program counter, and instruction mapping function. Unit modules with instruction execution capabilities inherit from the first-level derived classes, such as the overall controller simulation module, coprocessor simulation module, and in-memory computing simulation module. Unit modules that perform parameterized operation based on task configuration information inherit from the root class, such as the data transmission module and coprocessor cache module. Each unit functional module overrides the virtual functions of the base class, initializes module members, and allocates space for module members. It is important to note that in the multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips provided in each embodiment of this invention, the hardware simulation entity resources are allocated in the global address space described above; while logical entities designed for functional expansion, such as structure pointers, are allocated in the local memory space managed autonomously by each functional module instance. The allocation order of the global space unit modules and the storage order of the members within the unit modules are dynamically variable and do not depend on any fixed predefined pattern. like Figure 4As shown in the embodiment of the present invention, the high-concurrency multithreaded execution model consists of a main thread and sub-threads corresponding to each module. Each module thread has an independent mutex and condition variable with respect to the main thread. Through these mutexes and condition variables, the main thread can precisely control each thread individually and can also strictly synchronize stages to ensure that the program continues to run only after all module threads have reached a specific state. Because each simulation module has its own dedicated thread resource, and the thread's lifecycle is completely consistent with the module's, a crash in a single thread only affects that single module, avoiding cache invalidation issues caused by thread switching. Therefore, the design is more consistent with real hardware architecture models. like Figure 5 As shown, the high-concurrency multi-threaded execution model established in this embodiment of the invention has each thread possessing a lifecycle state and a periodic scheduling execution state. First, the program initializes global data blocks, simulates module attributes, etc., then creates instance threads for each module and initializes their lifecycle states and periodic scheduling execution states. Afterward, user input is obtained to drive the thread's work. In each tick, the master and slave threads need to synchronize the periodic scheduling execution states of the module threads multiple times using mutexes and condition variables. Within the current tick, the module thread performs different operations based on its own lifecycle state, such as initializing its own members or performing a tick operation. After the functional module completes the assigned task, it changes its thread state and destroys the thread. The specific steps for simulating the main controller module in this invention example are as follows: 1. Initialize the main controller module members, allocate space for the main controller module members in the global address space, and establish a mapping between the main controller instruction name and the instruction function simulation function. 2. Based on the user-input start address and number of instructions for the main controller, and the start address and number of tasks for the task information, load the instructions and task information from external storage into the instruction cache and task information cache of the main controller simulation module. 3. Using the program counter (PC) as an index, fetch and decode instructions from the instruction buffer. Based on the master controller instruction field specified in the binary code file, obtain the instruction name, operands, etc., and store them in the master controller instruction structure pointer. Using the decoded instruction name as an index, execute the corresponding mapped simulation function. 4. Set a Boolean global semaphore. The main controller synchronizes other unit simulation modules by reading and writing the semaphore. After issuing a task, it notifies other modules that they can start execution. After other modules complete their tasks, they notify the main controller, which then changes the status register. 5. When the program counter PC of the main controller is equal to the instruction counter IP, the main controller instruction has been executed and the main controller thread is destroyed in the multi-threaded process. The specific steps for simulating the data transmission module in this invention example are as follows: 1. Initialize the data transmission module members and allocate space for them in the global address space. 2. For each cache unit of the data transmission simulation module, establish an independent structure for its different data transmission paths (such as data transmission from external storage to the cache of the data transmission simulation module, data transmission from the cache of the data transmission simulation module to the coprocessor cache simulation module, etc.) to store the transmission information of each path obtained after parsing the configuration information of this module. 3. Parse the data transmission module instructions and store the extracted configuration information into the structure corresponding to the associated cache unit. 4. Determine the direction of the data transmission path for this operation and call the corresponding simulation function. 5. Set a Boolean global semaphore. When the data transmission module transmits data to other functional units, change the semaphore to notify other modules that the data transmission is complete. The specific steps for simulating the coprocessor module in this invention example are as follows: 1. Initialize coprocessor module members by allocating space for them in the global address space. Establish a mapping between instruction names and instruction simulation functions. 2. Coprocessors with different working modes inherit from the same base class, and enumeration members are established to distinguish the working modes of dual-mode coprocessors. 3. Depending on the operating mode, the coprocessor module fetches instructions from the instruction cache or configuration register, decodes the instruction fields, and stores the obtained instructions or configuration information into the structure members. 4. The decoded structure members are passed as parameters. The instruction stream coprocessor unit executes the corresponding mapping function according to the instruction name stored in the structure members. The data stream coprocessor module executes the corresponding calculation operation or data transmission according to the configuration information stored in the structure members, such as convolution calculation or data transmission between coprocessors through adjacency registers. 5. Data transfer between coprocessors is achieved through adjacency registers. Each pair of adjacent coprocessor units shares one adjacency register resource, and the coprocessor emulation module uses pointers to point to the adjacency register address. To resolve adjacency register read / write conflicts in each cycle, a double-buffered architecture is adopted, establishing adjacency register copies and dividing the adjacency registers into two versions, A and B. Within each cycle, the data flow coprocessor reads the predetermined version B adjacency register according to the configuration information and writes to the version A adjacency register, then synchronizes the data in the version A adjacency register to the version B adjacency register. For example... Figure 6As shown, taking the data transfer from coprocessor 00 to coprocessor 01 as an example, coprocessor 00 and coprocessor 01 need to access their shared adjacent register space in parallel. During the parallel execution phase of steps ① and ②, coprocessor 00 performs a write operation on the adjacent register (step ①), while coprocessor 01 synchronously performs a read operation on the adjacent register data from the previous cycle (step ②). Subsequently, step ③ completes the synchronous update of the register data between the two processors. This ensures data consistency between adjacent cycles through a timing isolation mechanism, effectively eliminating read / write hazards. 6. Set a Boolean global semaphore. When the coprocessor finishes loading the data in the cache or the data in the cache is invalid, change the semaphore to notify the coprocessor cache module to update the cache data. The specific steps for simulating the in-memory computing module in this invention example are as follows: 1. Initialize the members of the in-memory computing module, allocate space for the members of the in-memory computing module in the global address space, and establish a mapping between instruction names and instruction simulation functions. 2. The in-memory computing module fetches instructions from the instruction cache, obtains the instruction name, operands, etc., based on the specified instruction fields, and stores them in a structure pointer. Based on the decoded instruction name, it executes the corresponding mapped simulation function. The specific steps for simulating the coprocessor cache module in this invention are as follows: 1. Initialize the coprocessor cache module members and allocate space for them in the global address space. 2. The coprocessor cache module parses the configuration information issued by the main controller module, stores the configuration information in the structure of this module, and performs functional simulation of the module according to the method specified in the configuration information. 3. Set a Boolean global semaphore. When the data transmission module receives a signal indicating that the transmission is complete, the coprocessor cache module loads the data into the cache and changes the semaphore to notify the coprocessor that it can load the data.

Claims

1. A multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips, which implements: simulation of the main controller module, simulation of the data transmission module, simulation of the in-memory computing module, simulation of the coprocessor module, simulation of the coprocessor cache module, and a high-concurrency multi-threaded execution model. Note that the hardware components such as registers and caches mentioned below are all functional abstractions of physical hardware at the software technology level, specifically manifested as logical simulations of memory address space and data storage, such as pointers or STL containers. a. A multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips according to claim 1, characterized in that, In the multi-threaded synchronous simulator for self-reconfigurable and self-evolving AI chips, the task instructions for each module are issued by the central controller simulation module, and each module has the function of instruction execution or parameterized operation. b. A multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips according to claim 1, characterized in that, The main controller simulation module receives dynamically input messages from the user, loads its own instructions and task information from other modules, then fetches, decodes, and executes the instructions from the main controller's cache. The main controller simulation module also distributes task information to other simulation modules. After completing their assigned tasks, other simulation modules modify predefined integer semaphores and send feedback to the main controller simulation module to notify it to change its status register. c. A multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips according to claim 1, characterized in that, The data transmission simulation module parses the task information issued by the main controller simulation module and performs specific tasks according to the predetermined content of the configuration information, including but not limited to moving the source data of this task from external storage to the coprocessor cache module or the in-memory computing module. d. A multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips according to claim 1, characterized in that, The coprocessor simulation module parses the task information issued by the main controller simulation module and executes the instruction simulation functions related to the instructions. Data exchange between coprocessor simulation modules occurs through shared registers. e. A multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips according to claim 1, characterized in that, The coprocessor cache simulation module parses the task information issued by the main controller simulation module, distributes the cached data of this module to the coprocessor simulation module according to the task information, and receives the output data of the coprocessor simulation module. f. A multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips according to claim 1, characterized in that, The in-memory computing simulation module parses the task information issued by the central controller simulation module and executes the instruction simulation functions related to the instructions. g. A multi-threaded synchronous simulator method for self-reconfigurable and self-evolving AI chips according to claim 1, characterized in that, The high-concurrency multithreaded execution model is responsible for managing the threads of each simulation module, synchronizing the state of the main thread and child threads, and ensuring that each simulation module executes in parallel.

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