FPGA (Field Programmable Gate Array)-based I2C (Inter-Integrated Circuit) hanging prevention method

Abstract

The invention relates to an I2C (Inter-Integrated Circuit) hanging prevention method based on an FPGA (Field Programmable Gate Array). The method comprises the following steps of S100, sampling SDA and SCL signals on an I2C bus; s200, a synchronous processing module carries out synchronous processing on the input SDA and SCL signals, and the synchronized signals are sent to an overtime detection module; s300, a timeout detection module carries out duration time monitoring on the level states of the SDA line and the SCL line, and sends a detection result to a state control machine; s400, the state control machine judges whether the bus is abnormal or not, and if yes, abnormal information is sent to a pulse generation module; and S500, the pulse generation module enters a pulse generation state and sends a pulse generation signal to the three-state gate control module, the SDA and SCL levels are actively lowered, 16 standard I2C clock pulses are generated and output, then the three-state gate control module releases control over the SDA and SCL lines, the bus is recovered to a high-resistance state, and the bus enters the idle mode again. According to the method, synchronous detection of two abnormal conditions of SCL deadlock and SDA deadlock can be realized, and a bus fault blind area is comprehensively eliminated.

Description

Technical Field

[0001] This invention relates to the field of chipless I2C anti-hangover technology, and in particular to an FPGA-based I2C anti-hangover method. Background Technology

[0002] In industrial Ethernet switches, I2C is frequently used for chip-to-chip communication. However, in real-world applications, the I2C bus often enters an abnormal state due to electromagnetic interference, power fluctuations, hot-plugging, or device failure. A typical abnormal state manifests as the serial clock (SCL) or serial data (SDA) line being continuously pulled low by a device and unable to be released, causing the entire bus communication to hang and the system unable to recover automatically. To address this issue, existing technologies mainly propose two solutions: one is a software watchdog timer for the main controller; the other is a dedicated hardware reset chip. However, both solutions suffer from the following common problems:

[0003] (1) Slow response speed and poor system real-time performance: For the "software watchdog solution", its timeout detection relies on CPU polling, while the CPU usually needs to handle multiple tasks and cannot focus on bus monitoring in real time. There is a significant delay (usually more than 100ms) from the occurrence of an exception to the CPU responding to the interrupt and processing it, which cannot meet the requirements of industrial control or high-speed data acquisition systems with high real-time requirements.

[0004] (2) Incomplete detection mechanisms with blind spots: Existing solutions (especially dedicated chips) mostly focus on detecting abnormal situations where the SCL line is pulled low. However, in practice, the SDA line may also be continuously pulled low due to device failure, leading to communication interruption. Existing technologies lack sufficient or complete detection capabilities for such SDA line deadlocks, resulting in an inability to fully cover all bus fault modes.

[0005] (3) When using a software reset scheme, its effective operation requires all devices to be connected to the same I2C bus. However, in a switch system, the optical modules connected to the optical ports often have the same I2C device address. If they are not physically or logically distinguished, directly reading this address will result in simultaneous access to all optical modules, making individual identification and communication impossible. Therefore, in practical designs, it is usually necessary to use hardware circuits such as FPGAs or data selectors to physically isolate and select the I2C lines of each optical port to form independent communication channels. Under this architecture, the software reset mechanism can only operate on the I2C backbone bus directly connected to the main control CPU, and cannot effectively control the I2C slave devices on the branch lines isolated by the FPGA or data selector. Once the bus hangs on an isolated optical module's I2C line, the software reset cannot cover that branch, resulting in the communication fault still existing and failing to fundamentally solve the problem.

[0006] (4) System resource consumption and cost issues: The "software watchdog solution" consumes valuable CPU computing and interrupt resources; while the "dedicated hardware chip solution" increases the number of additional components, circuit board area and system BOM cost, which is not conducive to miniaturization and cost-sensitive applications.

[0007] To address the aforementioned issues, this invention proposes a highly reliable, real-time, comprehensive, and low-cost I2C bus integrity solution. It not only effectively addresses bus deadlock problems but also significantly improves the reliability and availability of the entire I2C system, making it particularly valuable for applications in industrial control and communication equipment sectors where stability requirements are extremely high. Summary of the Invention

[0008] In view of the defects or deficiencies in the existing technology, the technical problem to be solved by the present invention is to provide an FPGA-based I2C anti-hang-up method.

[0009] To achieve the above objectives, the technical solution adopted by the present invention is to provide an FPGA-based I2C anti-hang-up method, comprising the following steps:

[0010] S100: Samples the SDA and SCL signals on the I2C bus;

[0011] S200: The synchronization processing module performs synchronization processing on the input SDA and SCL signals, and the synchronized signals are sent to the timeout detection module.

[0012] S300: The timeout detection module monitors the duration of the level status of the SDA and SCL lines respectively, and sends the detection results to the state control machine;

[0013] S400: The status controller determines whether there is an abnormality on the bus. If there is an abnormality, it immediately sends the abnormality information to the pulse generation module.

[0014] S500: The pulse generation module enters the pulse generation state and sends a pulse generation signal to the tri-state gate control module. The tri-state gate control module controls the bus to actively pull SDA and SCL low. The pulse generation module then generates 16 standard I2C clock pulses at a preset frequency and outputs them. After that, the tri-state gate control module releases its control over the SDA and SCL lines, the bus returns to the high impedance state, and re-enters the idle mode.

[0015] As a further improvement of the present invention, in step S200, two-stage D flip-flops are independently designed for the SCL and SDA signal lines in the synchronization processing module.

[0016] As a further improvement of the present invention, the synchronization processing module performs the signal synchronization processing as follows:

[0017] Set 2 indicator signals

[0018] sda_sync<={scl_sync[0],sda_in};

[0019] sda_sync<={sda_sync[0],sda_in};

[0020] Among them, scl_sync is a 2-bit register;

[0021] scl_in is an asynchronous input signal from the external I2C bus of the master device, and it does not have a fixed timing relationship with the internal clock of the master device;

[0022] {scl_sync[0],scl_in} is a bit concatenation operation that creates a new 2-bit number where the highest bit is scl_sync[0] and the lowest bit is the new input scl_in;

[0023] <= is a non-blocking assignment, which means that at the instant the clock edge is triggered, all register updates occur simultaneously;

[0024] Before the rising edge of the clock arrives, the value of scl_sync is [A,B], where A is scl_sync[1] and B is scl_sync[0]. When a rising edge of the clock arrives, the master device calculates the right side of the equation: {scl_sync[0], scl_in} is equal to {B, scl_in}, which means that scl_sync[1] has obtained the value of scl_sync[0] of the previous clock cycle and scl_sync[0] has obtained the value of scl_in input in the current clock cycle.

[0025] The B position of scl_sync is the first-stage flip-flop, which directly contacts the external signal scl_in. The A position of scl_sync is the second-stage flip-flop. The synchronization processing module samples the signal from the B position of scl_sync, which has already cooled down by one clock cycle and stabilized to a definite logic value of 0 or 1.

[0026] As a further improvement of the present invention, step S300 includes the following steps:

[0027] S310: Receives the synchronized SDA and SCL signals;

[0028] S320: Continuously compares the received synchronized SDA and SCL signals;

[0029] S330: The counter starts incrementing until it reaches the preset timeout threshold, then stops incrementing and remains in a saturated state;

[0030] S340: After the counter starts incrementing to the preset timeout threshold, the recovery mechanism is triggered, and abnormal state information is generated and sent to the state control machine.

[0031] As a further improvement of the present invention, in step S320, the SDA and SCL signals after receiving synchronization processing are continuously compared. The counting starts from the SCL timeout counter scl_counter and is incremented to accurately accumulate the duration of the signal holding the current level. When the count value reaches the preset timeout threshold, the SCL timeout counter will stop incrementing and remain in a saturated state. During the timeout detection process, if the SDA or SCL line holds the same level continuously and the duration does not reach the set timeout threshold before a jump occurs, the corresponding counter will be automatically cleared and the timing will restart. When the level holding time of the SDA signal or SCL signal line reaches the preset timeout time, the timeout counter will generate a timeout signal and send it to the state controller.

[0032] As a further improvement of the present invention, in step S500, the pulse generation module then generates 16 standard I2C clock pulses at a preset frequency. The length of these pulses ensures that, regardless of where the fault originates in the clock sequence, the sequence contains at least one complete 8-bit byte and its immediately following 9th NACK clock, providing a termination signal and returning to the idle state.

[0033] As a further improvement of the present invention, the control process of the three-state gate control module on the SDA and SCL lines is as follows:

[0034] Setting control instructions and control methods

[0035] scl_oe=(state!=2'b00)? 1'b1:1'b0;

[0036] assignscl_sfp=scl_oe? scl_out:MUX_out;

[0037] Y = A? B:C When A is true (1), Y equals B; when A is false (0), Y equals C.

[0038] The first control method, scl_oe = (state != 2'b00) ? 1'b1 : 1'b0, defines the conditions for generating the output enable signal scl_oe: when the state control module is in a state requiring pulse recovery, i.e., state is not equal to 2'b00, the output enable signal to the tri-state gate control module is valid; when the state control module is in an idle state, the output enable signal to the tri-state gate control module is invalid.

[0039] Second control method: assign scl_sfp = scl_oe? scl_out: MUX_out; When the output enable signal scl_oe is valid, the internally generated recovery clock signal scl_out is output to the SCL bus; when the output enable signal is invalid, the normal communication signal MUX_out from the multiplexer is output to the SCL bus.

[0040] The beneficial effects of this invention are:

[0041] (1) In this invention, the master control device communicates with multiple slave devices via the I2C bus. Addressing the issue of address conflicts in optical module connections, the FPGA module implements physical channel isolation and selection, providing an independent I2C communication path for each optical port, thereby ensuring the accuracy and reliability of addressing. Furthermore, the FPGA, a pure digital logic circuit, monitors the SCL and SDA buses in parallel, achieving a microsecond (μs) response speed. This completely overcomes the drawbacks of high latency and high resource consumption associated with software solutions, greatly improving system reliability and real-time performance. Additionally, using the FPGA for I2C anti-hangover eliminates the need for external dedicated chips, significantly saving peripheral circuitry, board space, and overall cost.

[0042] (2) In this invention, two independent timeout detection counters (SCL timeout counter and SDA line timeout counter) are designed to accurately time the stable level states of the SCL line and SDA line respectively (for example, a continuous low level or high level for more than 30ms is judged as a fault). This enables synchronous detection of two abnormal conditions, SCL deadlock and SDA deadlock, and completely eliminates the bus fault blind spot.

[0043] (3) In this invention, after the recovery condition is triggered, the state machine control module and the pulse generation module generate a set of 16 clock pulses that fully conform to the I2C protocol standard timing. The pulse generation rate is configurable and is usually consistent with the normal I2 communication frequency to ensure that the rising edge, falling edge, frequency, and duty cycle of the pulses meet the specification requirements, so as to avoid the slave device identification error caused by timing differences, further improve the accuracy and compatibility of the recovery operation, minimize interference with the normal communication of the bus, and ensure the integrity of data transmission. In addition, the length of the 16 standard I2C clock pulses is mathematically strictly guaranteed to ensure that no matter where the fault starts in the clock sequence, the sequence contains at least one complete 8-bit byte and its immediately following 9th NACK clock. When the I2C bus hangs, no matter which state the fault is in during the communication process ("stuck" state), sufficient clock edges can be injected into this "stuck" state machine. No matter where it is stuck, it can be forced back to the IDLE state to avoid hanging. Attached Figure Description

[0044] Figure 1 The method provided by this invention applies the I2C hardware topology of the system;

[0045] Figure 2 This is a block diagram of the main control device provided by the present invention;

[0046] Figure 3 This is the overall control flowchart of the method provided by the present invention;

[0047] Figure 4 This is a flowchart of the method provided by the present invention;

[0048] Figure 5 This is a flowchart of step S300 of the method of the present invention. Detailed Implementation

[0049] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0050] like Figure 1-5 As shown, the present invention provides an FPGA-based I2C anti-hang-up method, which includes the following steps:

[0051] S100: Samples the SDA and SCL signals on the I2C bus;

[0052] The master control device obtains the SDA and SCL signals on the I2C bus from the FPGA module and communicates with multiple slave devices through the I2C bus to achieve control.

[0053] S200: The synchronization processing module performs synchronization processing on the input SDA and SCL signals, and the synchronized signals are sent to the timeout detection module.

[0054] Because the I2C bus signal is asynchronous with respect to the FPGA's internal clock domain, its level changes do not have a fixed timing relationship with the master clock edge. Direct sampling / acquisition can easily cause the output signal to oscillate at an indeterminate logic level for a period of time, i.e., metastability. This invention designs a synchronization processing module to solve the metastability problem. Specifically, in the synchronization processing module, a synchronizer chain consisting of two-stage D flip-flops is independently designed for the SCL and SDA signal lines respectively. The asynchronous input signal is sequentially fed into this synchronizer chain, and latched and passed stage by stage at each effective edge of the master clock. Although the output of the first-stage flip-flop may enter a metastable state within a specific setup / hold time window, it has nearly a complete clock cycle to stabilize, ensuring that when passed to the second-stage flip-flop, its output has become a stable, clean digital signal synchronized with the master clock.

[0055] The signal synchronization processing procedure sets the indicator signal as follows:

[0056] sda_sync<={scl_sync[0],sda_in};

[0057] sda_sync<={sda_sync[0],sda_in};

[0058] Among them, scl_sync is a 2-bit register;

[0059] scl_in is an asynchronous input signal from the external I2C bus of the master device, and it does not have a fixed timing relationship with the internal clock of the master device;

[0060] {scl_sync[0], scl_in} is a bit concatenation operation that creates a new 2-bit number, where the most significant bit (bit 1) is scl_sync[0] (i.e., the current low-order value of the scl_sync register), and the least significant bit (bit 0) is the new input scl_in. <= is a non-blocking assignment, which means that at the instant the clock edge is triggered, all register updates occur simultaneously.

[0061] Suppose that before a rising edge of a clock arrives, the value of scl_sync is [A, B] (where A is scl_sync[1] and B is scl_sync[0]). When a rising edge of a clock arrives, the master device calculates the right side of the equation: {scl_sync[0], scl_in} is equal to {B, scl_in}. Thus, scl_sync[1] obtains the value of scl_sync[0] from the previous clock cycle, and scl_sync[0] obtains the value of scl_in input in the current clock cycle.

[0062] Based on the assumptions, position B of scl_sync is a first-stage flip-flop, directly interacting with the external signal scl_in. It is most prone to metastability, but it has a full clock cycle to "cool down" and stabilize to a definite logic value (0 or 1). Position A of scl_sync is a second-stage flip-flop. The synchronization processing module samples the signal from position B of scl_sync, which has already cooled down. At this point, the signal is very stable, and metastability is avoided, effectively preventing signal jitter or glitches from causing misjudgments of the system state.

[0063] S300: The timeout detection module monitors the duration of the level status of the SDA and SCL lines respectively, and sends the detection results to the state control machine;

[0064] In step S300 of the present invention, the following steps are included:

[0065] S310: Receives the synchronized SDA and SCL signals;

[0066] S320: Continuously compares the received synchronized SDA and SCL signals;

[0067] S330: The counter starts incrementing until it reaches the preset timeout threshold, then stops incrementing and remains in a saturated state;

[0068] S340: After the counter starts incrementing to the preset timeout threshold, the recovery mechanism is triggered, and abnormal state information is generated and sent to the state control machine.

[0069] The specific process is as follows: Instructions are designed within the timeout detection module, for example:

[0070] if(scl_sync[1]==scl_sync[0]

[0071] begin

[0072] / / The SCL line remains unchanged, and the counter is incrementing.

[0073] scl_counter<=scl_scounter+1;

[0074] if(scl_counter>=TIMEOUT_CYCLES)

[0075] scl_counter<=TIMEOUT_CYCLES;

[0076] The SCL signals (i.e., scl_sync[1] and scl_sync[0]) after synchronization processing are continuously compared. When the values ​​of the two synchronization registers are equal, it indicates that the SCL signal has maintained a stable state for two consecutive clock cycles without any jump. At this time, the SCL timeout counter scl_counter starts to increment, accurately accumulating the count to the duration of the current level. To prevent the SCL timeout counter from overflowing and causing system abnormalities, when the count value reaches the preset timeout threshold TIMEOUT_CYCLES, the SCL timeout counter will stop incrementing and remain in a saturated state. During the timeout detection process, if the SDA or SCL line maintains the same level continuously, but the duration does not reach the set timeout threshold before a jump occurs, the corresponding counter will be automatically cleared and the timing will restart. Once the level holding time of the SDA signal or SCL signal line reaches the preset timeout time, the timeout counter will generate a timeout signal and send it to the state controller. In this process, the SDA signal synchronization processing principle is the same as that of the SCL signal processing, and it is counted by the SDA timeout counter. This process ensures accurate capture of abnormal bus states. The subsequent recovery mechanism is triggered only when the signal remains stable for more than a preset time window. This avoids misjudgment caused by normal signal transitions and can reliably detect real bus deadlock faults.

[0077] It should be noted that in this invention, the timeout threshold can be flexibly adjusted through register configuration to adapt to the needs of different application scenarios.

[0078] S400: The status controller determines whether there is an abnormality on the bus. If there is an abnormality, it immediately sends the abnormality information to the pulse generation module.

[0079] Once the state controller receives a timeout signal from the timeout counter, it immediately determines that the bus is abnormal, generates an abnormal signal and sends it to the pulse generation module, which then enters the pulse generation state.

[0080] S500: The pulse generation module enters the pulse generation state and sends a pulse generation signal to the tri-state gate control module; the tri-state gate control module controls the bus to actively pull the SDA and SCL line levels (voltages) low, and the pulse generation module then generates 16 standard I2C clock pulses at a preset frequency and outputs them. After that, the tri-state gate control module releases its control over the SDA and SCL lines, the bus returns to the high impedance state, and re-enters the idle mode.

[0081] The specific process principle of step S500 is as follows:

[0082] (1) The pulse generation module randomly generates 16 standard I2C clock pulses at a preset frequency.

[0083] In normal I2C data transmission, the host needs 8 clock pulses to send one byte (8 bits of data). The 9th clock pulse is used by the slave device to return an acknowledgment (ACK) or non-acknowledgment (NACK), generating a NACK condition. In the standard protocol, this is an explicit "stop signal" that tells the slave device that the host will no longer send data. Many slave devices, upon receiving a NACK, expect the host to generate a stop condition and end the transmission, and therefore their state machine will prepare to return to the idle state. Based on this standard protocol, this invention proposes a pulse generation module that randomly generates 16 standard I2C clock pulses at a preset frequency. The core value of these 16 standard I2C clock pulses lies in the fact that their length mathematically guarantees that regardless of where the fault originates in the clock sequence, the sequence will always contain at least one complete 8-bit byte and its immediately following 9th NACK clock, providing the slave device's state machine with the strongest termination signal at the protocol level, forcing it to return to the idle state. In other words, the 16 standard I2C clock pulses designed in this invention can inject sufficient clock edges into the "stuck" state machine when the I2C bus is stuck, regardless of which state the fault is in during the communication process (the "stuck" state). No matter where it is stuck, it can be forced back to the idle state, thus avoiding a hang.

[0084] (2) Principle of the tri-state gate control module releasing control over SDA and SCL lines

[0085] A tri-state gate is a digital logic gate circuit with three output states: in addition to the conventional high level (logic 1) and low level (logic 0) states, it also has a third high-impedance state. In the high-impedance state, the output terminal is electrically isolated from the internal circuitry, equivalent to being physically disconnected. At this time, the device will not drive the bus or affect the signal transmission on the bus. This characteristic allows multiple devices to safely share the same bus without signal conflicts.

[0086] This invention establishes a control method by setting conditions (control instructions) as follows:

[0087] scl_oe=(state!=2'b00)? 1'b1:1'b0;

[0088] assignscl_sfp=scl_oe? scl_out:MUX_out;

[0089] The specific control method of the three-state gate is: Y = A? B:C. When A is true (i.e., 1), Y is equal to B, and when A is false (i.e., 0), Y is equal to C.

[0090] The first control method, `scl_oe = (state != 2'b00) ? 1'b1 : 1'b0;`, defines the conditions for generating the output enable signal `scl_oe`: when the state control module is in a pulse recovery state (i.e., `state` is not equal to 2'b00), the output enable signal is valid (set to logic 1) to the tri-state gate control module; when the state control module is in an idle state, the output enable signal is invalid (set to logic 0) to the tri-state gate control module. This ensures that the SCL line is only driven during the bus recovery operation period when the tri-state gate control module is in an abnormal state.

[0091] The second control method, `assign scl_sfp = scl_oe ? scl_out : MUX_out`, implements a tri-state gate selector function: when the output enable signal `scl_oe` is valid, the internally generated recovery clock signal `scl_out` is output to the SCL bus; when the output enable signal is invalid, the normal communication signal `MUX_out` from the multiplexer is output to the SCL bus. This signal switching mechanism fundamentally avoids signal conflicts caused by multiple drivers simultaneously contending for the bus, ensuring safe and seamless takeover and release of the bus.

[0092] The FPGA-based I2C anti-hang-up method of this invention is mainly applied to FPGA-based systems, such as... Figure 1-2 In the topology shown, the I2C bus data line (SDA) from the main control chip is connected in parallel to all optical modules and the FPGA module. The main control chip's SCL line is not directly connected to the optical modules, but first connected to the FPGA module; simultaneously, each optical module's independent SCL line is also connected to different general-purpose I / O pins of the FPGA module. Furthermore, the main control device is connected to the FPGA module via several additional control signal lines. When the main control needs to communicate with a specific optical module, it first sends a specific strobe address code to the FPGA module via the control signal lines. The digital logic circuitry inside the FPGA module (equivalent to a high-performance multiplexer) decodes this code and dynamically connects the main control device's SCL line to the corresponding SCL pin of the target optical module internally, thus establishing a complete point-to-point I2C communication link. Meanwhile, the SCL lines of unselected optical modules are either open or in a high-impedance state inside the FPGA module, ensuring they are completely isolated at the physical level and cannot respond to any activity on the bus. This invention achieves effective channel isolation and dynamic selection of multiple optical modules sharing the same I2C address at the physical layer through this hardware channel management mechanism based on FPGA modules. This allows the master control device to accurately perform read and write operations on any specified optical module as if it were an independent device, fundamentally solving the address conflict problem.

[0093] The FPGA module can be selected from, but is not limited to, the EF2L15LG100B module from Anlu.

[0094] In this invention, the master control device communicates with multiple slave devices via the I2C bus. Addressing the issue of address conflicts in optical module connections, an FPGA module is used to implement physical channel isolation and selection, providing an independent I2C communication path for each optical port, thereby ensuring accurate and reliable addressing. Furthermore, the FPGA, a pure digital logic circuit, monitors the SCL and SDA buses in parallel, achieving microsecond-level (μs) response speeds. This completely overcomes the drawbacks of high latency and high resource consumption associated with software solutions, significantly improving system reliability and real-time performance. Additionally, using the FPGA for I2C anti-hang-up eliminates the need for external dedicated chips, significantly saving on peripheral circuitry, board space, and overall cost.

[0095] In this invention, two independent timeout detection counters (SCL timeout counter and SDA line timeout counter) are designed to accurately time the stable level states of the SCL and SDA lines respectively (for example, a continuous low or high level exceeding 30ms is considered a fault). This enables synchronous detection of both SCL deadlock and SDA deadlock abnormalities, completely eliminating bus fault blind spots.

[0096] In this invention, after the recovery condition is triggered, the state machine control module and the pulse generation module generate a set of 16 clock pulses that fully conform to the I2C protocol standard timing. The pulse generation rate is configurable and is usually consistent with the normal I2 communication frequency, ensuring that the rising edge, falling edge, frequency, and duty cycle of the pulses all meet the specification requirements. This avoids slave device identification errors caused by timing differences, further improving the accuracy and compatibility of the recovery operation, minimizing interference with normal bus communication, and ensuring the integrity of data transmission. Furthermore, the 16 standard I2C clock pulses are mathematically guaranteed to contain at least one complete 8-bit byte and its immediately following 9th NACK clock, regardless of where the fault originates in the clock sequence. When the I2C bus hangs, regardless of which state the fault is in during communication (the "stuck" state), sufficient clock edges can be injected into the "stuck" state machine, forcing it back to the IDLE state no matter where it is stuck, thus preventing a hang.

[0097] In summary, the method of this invention is a highly reliable, real-time, comprehensive, and low-cost I2C bus integrity solution. It can not only effectively address the bus deadlock problem, but also significantly improve the reliability and availability of the entire I2C system. It has particularly high application value in the industrial control and communication equipment industries where stability requirements are extremely high.

[0098] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for preventing I2C hang-ups based on FPGA, characterized in that, Includes the following steps: S100: Samples the SDA and SCL signals on the I2C bus; S200: The synchronization processing module performs synchronization processing on the input SDA and SCL signals, and the synchronized signals are sent to the timeout detection module. S300: The timeout detection module monitors the duration of the level status of the SDA and SCL lines respectively, and sends the detection results to the state control machine; S400: The status control unit determines whether there is an abnormality in the bus; An anomaly is detected, and the anomaly information is sent to the pulse generation module. S500: The pulse generation module enters the pulse generation state and sends a pulse generation signal to the tri-state gate control module; The tri-state gate control module controls the bus, actively pulling the SDA and SCL lines low. The pulse generation module then generates 16 standard I2C clock pulses at a preset frequency and outputs them. After that, the tri-state gate control module releases its control over the SDA and SCL lines, and the bus returns to a high-impedance state, re-entering the idle mode.

2. The FPGA-based I2C anti-hang-up method according to claim 1, characterized in that, In step S200, two-stage D flip-flops are designed independently for the SCL and SDA signal lines in the synchronization processing module.

3. The FPGA-based I2C anti-hang-up method according to claim 2, characterized in that, The synchronization processing module performs the following signal synchronization processing: Set 2 indicator signals sda_sync<={scl_sync[0],sda_in}; sda_sync<={sda_sync[0],sda_in}; Among them, scl_sync is a 2-bit register; scl_in is an asynchronous input signal from the external I2C bus of the master device, and it does not have a fixed timing relationship with the internal clock of the master device; {scl_sync[0],scl_in} is a bit concatenation operation that creates a new 2-bit number where the highest bit is scl_sync[0] and the lowest bit is the new input scl_in; <= is a non-blocking assignment, which means that at the instant the clock edge is triggered, all register updates occur simultaneously; Before the rising edge of the clock arrives, the value of scl_sync is [A,B], where A is scl_sync[1] and B is scl_sync[0]. When a rising edge of the clock arrives, the master device calculates the right side of the equation: {scl_sync[0], scl_in} is equal to {B, scl_in}, which means that scl_sync[1] has obtained the value of scl_sync[0] of the previous clock cycle and scl_sync[0] has obtained the value of scl_in input in the current clock cycle. The B position of scl_sync is the first-stage flip-flop, which directly contacts the external signal scl_in. The A position of scl_sync is the second-stage flip-flop. The synchronization processing module samples the signal from the B position of scl_sync, which has already cooled down for a full clock cycle and stabilized to a definite logic value of 0 or 1.

4. The FPGA-based I2C anti-hang-up method according to claim 1, characterized in that, Step S300 includes the following steps: S310: Receives the synchronized SDA and SCL signals; S320: Continuously compares the received synchronized SDA and SCL signals; S330: The counter starts incrementing until it reaches the preset timeout threshold, then stops incrementing and remains in a saturated state; S340: After the counter starts incrementing to the preset timeout threshold, the recovery mechanism is triggered, and abnormal state information is generated and sent to the state control machine.

5. The FPGA-based I2C anti-hang-up method according to claim 4, characterized in that, In step S320, the SDA and SCL signals after receiving synchronization processing are continuously compared. The count starts from the SCL timeout counter scl_counter and is incremented to accurately accumulate the duration of the signal holding the current level. When the count value reaches the preset timeout threshold, the SCL timeout counter will stop incrementing and remain in a saturated state. During the timeout detection process, if the SDA or SCL line holds the same level continuously and the duration does not reach the set timeout threshold before a jump occurs, the corresponding counter will be automatically cleared and the timing will restart. When the level holding time of the SDA or SCL signal line reaches the preset timeout time, the timeout counter will generate a timeout signal and send it to the state controller.

6. The FPGA-based I2C anti-hang-up method according to claim 1, characterized in that, In step S500, the pulse generation module then generates 16 standard I2C clock pulses at a preset frequency. The length of these pulses ensures that, regardless of where the fault originates in the clock sequence, the sequence contains at least one complete 8-bit byte and its immediately following 9th NACK clock, providing a termination signal and returning to the idle state.

7. The FPGA-based I2C anti-hang-up method according to claim 1, characterized in that, The control process of the three-state gate control module on the SDA and SCL lines is as follows: Setting control instructions and control methods scl_oe=(state!=2'b00)? 1'b1:1'b0; assignscl_sfp=scl_oe? scl_out:MUX_out; Y = A? B:C When A is true (1), Y equals B; when A is false (0), Y equals C. The first control method, scl_oe = (state != 2'b00) ? 1'b1 : 1'b0, defines the conditions for generating the output enable signal scl_oe: when the state control module is in a state requiring pulse recovery, i.e., state is not equal to 2'b00, the output enable signal to the tri-state gate control module is valid; when the state control module is in an idle state, the output enable signal to the tri-state gate control module is invalid. Second control method: assign scl_sfp = scl_oe? scl_out: MUX_out; When the output enable signal scl_oe is valid, the internally generated recovery clock signal scl_out is output to the SCL bus; when the output enable signal is invalid, the normal communication signal MUX_out from the multiplexer is output to the SCL bus.

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