System and method for providing fault injection

Abstract

The invention relates to a system and method for providing fault injection. A system includes fault simulation test circuitry (116). The system may implement the fault simulation test circuitry in a processing core (110) rather than in interconnects (120, 122). The fault simulation test circuitry may inject a fault into the error correction hash.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application 63 / 686,274, filed August 23, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to computer systems, and more specifically, to systems and methods for providing fault injection in computer systems. Background Technology

[0004] Safety protocols are used to ensure safety in electrical and / or electronic systems. For example, the International Organization for Standardization (ISO) 26262 is an international standard for the functional safety of electrical and / or electronic systems in automobiles. Such safety protocols analyze the risks associated with electronic failures (e.g., a combination of the frequency of injury and the severity of said injury). Failures corresponding to electronic components can be random or systematic. Random failures can correspond to hardware-related permanent or transient failures due to the loss of functionality of system components. System failures can correspond to design flaws, incorrect specifications, and / or inapplicability errors in software. Such safety protocols can also analyze electrical risks associated with hardware processors that process signals to enhance vehicle safety. Summary of the Invention

[0005] In one arrangement, a method includes: transmitting an information signal from a transmitting circuit to a receiving circuit; calculating a first error correction value for the information signal; injecting an error into the first error correction value to generate a second error correction value; transmitting the second error correction value to the receiving circuit; receiving a result of an error correction check from the receiving circuit; and determining whether an error has been detected based on the result of the error correction check.

[0006] In one arrangement, a system includes: a transmitting circuit comprising: a first sequential logic configured to transmit an information signal; an error correction calculator configured to generate a first error correction value based on the information signal; a fault injection circuit configured to modify the first error correction value by injecting an error, thereby generating a second error correction value; and a second sequential logic configured to transmit the second error correction value; and a receiving circuit coupled to the transmitting circuit and configured to receive the information signal and the second error correction value, wherein the receiving circuit includes: an error correction circuit system configured to process the information signal and the second error correction value and return the result to the transmitting circuit.

[0007] In another arrangement, a circuit includes: a first sequential logic circuit configured to transmit an information signal to a receiving circuit; an error correction calculator circuit configured to generate a first error correction value based on the information signal; a fault injection circuit configured to modify the first error correction value by injecting an error, thereby generating a second error correction value; a second sequential logic circuit configured to transmit the second error correction value to the receiving circuit; and an error detector circuit configured to receive a response from the receiving circuit and determine whether the error has been detected based on the response. Attached Figure Description

[0008] Having thus generally described the invention, reference will now be made to the accompanying drawings, in which:

[0009] Figure 1 These are illustrations of example systems based on some embodiments.

[0010] Figure 2 This is a diagram of an example fault simulation module based on some embodiments.

[0011] Figure 3 These are illustrations of example symbols, information signals, correctors, and ECC data based on some embodiments.

[0012] Figure 4 This is a diagram of an example correction subtable based on some embodiments.

[0013] Figure 5 This is an illustration of an example method for fault simulation based on some embodiments. Detailed Implementation

[0014] This disclosure is described with reference to the accompanying drawings. The drawings are not to scale and are provided for illustrative purposes only. Several aspects of this disclosure are described below with reference to illustrative examples. It should be understood that many specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited to the described order of actions or events, as some actions may occur in a different order and / or simultaneously with other actions or events. Furthermore, not all described actions or events are required to implement the method according to this disclosure.

[0015] Automotive Safety Integrity Levels (ASIL) fall under the scope of ISO 26262 and specify the safety levels of automotive components. ASIL compliance requires systems to have a high level of Latent Fault Metrics (LFM), and a given ASIL level can define specific fault detection and / or fault correction requirements. For example, the diagnostic mechanisms of a processor device may need to have at least 90% fault detection coverage to meet a specific ASIL level. In some systems, the diagnostic mechanisms ensure the detection and / or correction of faults by simulating (e.g., intentionally creating) faults that are typically encountered. By configuring registers to specify when and where faults are injected, a given fault or a set of faults can be simulated for a given access.

[0016] One hardware diagnostic and repair technique that can be used in such systems is a single-error correction, double-error detection (SECDED) error correction code (ECC) check of bus access information from the initiator to one or more interconnects. Fault simulation may be required for each bit of the bus access information to verify the ECC check's effectiveness.

[0017] In embodiments of this disclosure, whenever the initiator makes an access request, an access information bus containing the access address and size is broadcast by the initiator to the rest of the system-on-chip (SoC), which may contain the intended destination (e.g., memory and / or peripheral devices) and one or more other unintended destinations. Simultaneously, ECC data calculated for the information flowing from the initiator to the intended destination (e.g., the content of the access request) is also transmitted as sideband signals (e.g., via a different set of conductive traces, via different data paths, and / or via different modes). Once the access request reaches the interconnect associated with the destination, the access information is checked against the previously calculated ECC data in an ECC checker block. Some instances of the ECC checker can detect and correct single faults and detect double faults.

[0018] Fault simulation for testing the ECC checker block can be achieved by configuring the associated memory-mapped register (MMR) to specify where to inject the fault. User software sets the address for read, write, or fetch access, and when the processor core provides an access request, this address is modified by changing the corresponding bit fields to inject the fault as specified. The fault simulation logic, including the configuration register, can reside in each of the interconnects serving the corresponding memory or peripheral device. This is because if faults were injected at the initiator level instead, the access routing address multiplexing gate might receive fault-corrupted address values, and the access might even fail to reach the intended destination interconnect for testing the associated ECC checker block. Therefore, if fault simulation is performed at the initiator level, it can be difficult to inject faults and check their coverage.

[0019] Instead of implementing fault emulation logic in the system's interconnects (e.g., peripheral bridges, memory controllers), various embodiments implement fault emulation logic in the initiator (e.g., processor core). Furthermore, instead of injecting faults into the information signals themselves (e.g., data indicating a read, write, or fetch address), various embodiments can manipulate ECC data. As a result, information signals with access requests can avoid being routed to unintended destinations. Moreover, various embodiments can save semiconductor area by avoiding duplication compared to systems that would otherwise implement multiple and identical fault emulation logics at interconnects. In other words, various embodiments can implement fault emulation logic at the processor core and omit fault emulation logic at multiple interconnects, which is generally expected to reduce the number of instances of fault emulation logic.

[0020] Figure 1 This is an illustration of an example system 100 according to some embodiments. Example system 100 can be implemented on one or more semiconductor dies. For example, each of components 110-125 can be contained on the same semiconductor die, or even together with additional components (not shown), as a SoC. In another example, processor core 110 can be implemented on a semiconductor die, and interconnects 120, 122 and their respective memory or peripheral devices 124, 125 can be implemented on one or more other semiconductor dies. In yet another example, processor core 110 and interconnects 120, 122 can be implemented on a first semiconductor die, and memory or peripheral devices 124, 125 can be implemented on one or more semiconductor dies separate from the first semiconductor die. One or more given semiconductor dies can be contained within a semiconductor package, and the package can be mounted to a printed circuit board or other components.

[0021] In addition, although Figure 1 Only a single processor core 110 is shown, but the scope of the implementation can include systems with two or more processor cores. Furthermore, the number of interconnects and peripheral devices can be appropriately scaled to accommodate any suitable number and type of memory devices and / or peripheral devices.

[0022] Processor core 110 can contain any suitable processor core according to any suitable processor architecture. For example, processor core 110 can be a general-purpose processor core, a special-purpose processor, a reduced instruction set computer, a graphics processing unit, or other processor core.

[0023] Processor core 110 includes access generation logic 114, which generates bits associated with read or write access requests to memory or peripheral devices 124, 125. For example, access generation logic 114 can generate bits indicating a bus access address, access size, and any appropriate sideband signals to cause a read or write access to occur. During an instance read access, processor core 110 can request data from either memory or peripheral device 124, 125. During an instance write access, processor core 110 can request data to be written to either memory or peripheral device 124, 125.

[0024] Access generation logic 114 generates data bits constituting the access request (e.g., bits specifying the access type, address, other metadata, and / or data payload), which in some instances may be referred to as an information signal. The information signal received by sequential logic circuitry 111 from access generation logic 114 may differ from error correction data 130 used to verify the integrity of the data bits. In this example, error correction code (ECC) calculator 115 receives the information signal from access generation logic 114 and generates ECC data 130 from it. ECC calculator 115 may use any suitable error correction algorithm to generate ECC data 130. In some instances, ECC calculator 115 may generate a hash based on a hash function. Therefore, in some instances, ECC data 130 may be computed from the information signal, and said ECC data may be used to correct errors in the information signal.

[0025] The processor core 110 also includes a fault simulation module 116, which is related to... Figure 2 To explain in more detail, the fault simulation module 116 can inject faults into the bus 119 in two different ways. In one way, the fault simulation module 116 can send the entire hash to the sequential logic circuit 112. In another way, the fault simulation module 116 can manipulate one bit of the ECC data 130 at a time, and the combinational logic 113 then loads the erroneous ECC data into the sequential logic circuit 112. Therefore, the fault simulation module 116 can inject one or more false bits (errors) into the ECC data 130.

[0026] The fault simulation module 116 can inject errors into the ECC data 130 during fault simulation operations of system 100. For example, the fault simulation operation can be performed when system 100 is powered on, during the manufacture of system 100, periodically from time to time, or otherwise as needed. However, during normal operation of system 100, combinational logic 113 can be configured such that the ECC data 130 is not modified to contain errors, and the ECC data can be placed on bus 119 without modification.

[0027] The memory or peripheral devices 124 and 125 can each be implemented as a memory device or a peripheral device. Examples of peripheral devices include hard disk drives, solid-state drives, analog-to-digital converters, communication interfaces such as network interfaces, and so on. Examples of memory devices can include various types of random access memory (RAM), such as static random access memory (SRAM) devices, dynamic random access memory (DRAM) devices, or other volatile or non-volatile RAM devices.

[0028] Depending on the requirements, interconnect 120 can be implemented as a peripheral bridge or a memory controller. For example, if device 124 is implemented as a memory device, then interconnect 120 can be implemented as a memory controller. If device 124 is implemented as a peripheral device, then interconnect 120 can be implemented as a peripheral bridge. The same applies to interconnect 122 and device 125.

[0029] In one aspect, processor core 110 acts as the initiator of access requests, and interconnects 120 and 122 act as the targets of those access requests. Looking at interconnect 120, if it is implemented as a memory controller, it can be configured to receive read or write requests from processor core 110, perform input or output operations on memory device 124 to read or store data, and then return the result of the read or write request to processor core 110. The same applies to interconnects 122 and device 125. If interconnect 120 is implemented as a peripheral bridge, it can be configured to receive access requests, such as read or write requests, interact with the hardware of device 125 that matches the access request, and then return the result of the access request to processor core 110. The same applies to interconnects 122 and device 125.

[0030] Interconnect 120 includes ECC check circuitry 121. Similarly, interconnect 122 includes ECC check circuitry 123. For a given access request, sequential logic 111 sends an information signal to bus 118, where the information signal is broadcast to interconnects 120 and 122. During the access request, sequential logic circuitry 112 transmits ECC data to bus 119, where the ECC data is broadcast to interconnects 120 and 122. A given interconnect 120 or 122 can then resolve the bus access address and determine whether the bus access address points to the specific interconnect 120 or 122. If interconnect 120 or 122 determines that it is not the target of the access request, then interconnect 120 or 122 can ignore the access request. If interconnect 120 or 122 determines that it is the target of the access request, then it can continue to perform further actions regarding the access request.

[0031] In one instance, an access request can be broadcast on bus 118 and addressed such that interconnect 120 is its target. Interconnect 122 can then ignore the access request. ECC check circuitry 121 is configured to perform an ECC check on the information signal using ECC data on bus 119. This may include generating a second set of ECC data and comparing it with a first set of ECC data received via ECC bus 119 and generated by ECC calculator 115, with or without a fault injected by combinational logic 113.

[0032] In one instance, ECC check circuit 121 can be configured to perform SECDED. For example, if a single bit of data on bus 118 has an error (sometimes called a bit flip), then ECC check circuit 121 can identify the specific bit with the error and can output a correction for said single bit. For example, ECC check circuit 121 can output the complete word in its correct form, or it can simply indicate which bit has an error. In an instance where two bits have errors, ECC check circuit 121 can output an indication of an uncorrected error. The indication of an uncorrected error can be interpreted by processor core 110 as an indication that two bits have errors, although the identity of these two bits may be undetermined. More than two bits with errors can be handled in any suitable manner, although the SECDED output in such a scenario may be unrestricted. ECC check circuit 123 can perform similarly.

[0033] During normal operation, the fault simulation module 116 can be idle, and the combinational logic 113 can be configured to output ECC data 130 as is. During fault simulation operation, the fault simulation module 116 is configured to receive and aggregate the outputs from the ECC check circuits 121 and 123. Specifically, the fault simulation module 116 can be configured to receive and aggregate ECC corrected and uncorrected errors to perform fault analysis on system 100. About Figures 2 to 5 Fault analysis will be discussed in more detail. In some instances, fault analysis may include checking the functionality of ECC circuits 121 and 123.

[0034] The results of the fault analysis can be processed in any appropriate manner, but in some implementations, the detection of a fault in the ECC check circuits 121 or 123 may cause the fault simulation module 116 to issue a fault flag to the interrupt handler 117. Although not described in detail herein, system 100 may be implemented with self-healing capabilities so that faults discovered during fault simulation can be fully or partially repaired.

[0035] Figure 2 According to some embodiments Figure 1An illustration of the instance fault simulation module 116 is provided. The instance fault simulation module 116 can be implemented using software, firmware, and / or hardware logic as appropriate. For example, in one instance, the fault simulation module 116 can be implemented using hardware logic within the processor core 110, but the hardware logic can respond to signals sent from the software to, for example, control the selection of tests. In another instance, the fault simulation module 116 can be implemented using firmware logic, or it can be implemented in the Basic Input / Output System (BIOS). Furthermore, any suitable technique (e.g., signals from software) can be used to enable the fault simulation module 116 to limit whether the processor core 110 operates in fault simulation mode or normal access mode.

[0036] The fault simulation module 116 includes a test selector 203. The test selector 203 can be configured to select which bit error to test relative to the information signal. For example, given a first known good information signal and a first set of ECC data associated with the first information signal, the test selector 203 can select a corrector from a corrector table 202, wherein the specific corrector corresponds to a specific bit error. (Regarding...) Figure 3 To explain the corrector in more detail, but in summary, the corrector can be used to generate a second set of ECC data corresponding to a second information signal having one or more bits different from the first information signal. Unlike the first information signal, the second information signal does not need to be correct and may not even be recognized or processed by any destination. By transmitting the first known-good information signal and the second set of ECC data, both the information signal and the ECC data will be received and processed by one of the interconnects (e.g., checked by an ECC checking circuitry system). If operating properly, the ECC checking circuitry system of the interconnect will detect a specified bit error in the first information signal, even if the first information signal is correct.

[0037] To generate the second set of ECC data, test selector 203 can apply the selected corrector to the first set of ECC data via XOR function 204. XOR function 204 can also receive the first set of ECC data from ECC calculator 115. XOR function 204 can perform an XOR function on the selected corrector and the first set of ECC data. The output of XOR function 204 is a series of bits, which can correspond to the second set of ECC data associated with a specific bit error. The output of XOR function 204 can be transmitted to sequential logic circuit 112 via sequential logic 113 and then placed in bus 119.

[0038] During fault simulation operation, one or more of the ECC checking circuits 121 and 123 may then receive a first information signal on bus 118 and a second set of ECC data (e.g., the result of XOR function 204) on bus 119. Using these inputs, the ECC checking circuits 121 and 123 can perform ECC correction. In this example, the fault simulation injects a fault into the second set of ECC data such that the modified ECC data does not match the first information signal on bus 118.

[0039] In an instance where the first information signal is all zeros and the modified ECC data is associated with a single one value at the m-th bit, ECC check circuits 121 and 123 will each detect an incorrect information signal at the m-th bit and return the detected error to the fault simulation module 116 at the aggregated ECC corrected and uncorrected error block 206. For example, ECC check circuits 121 and 123 may each return a data word that is all zeros with a single one at the m-th bit, and this data word may be received by the aggregated ECC corrected and uncorrected error block 206. Fault returns during the operation of either ECC check circuit 121 or 123 can be expected to include something other than an indication of a bit error at the m-th bit.

[0040] The test selector can perform further tests, each corresponding to a specific bit error, and the outputs of the ECC check circuits 121 and 123 can be returned to the aggregated ECC-corrected and uncorrected error module 206. After a period of time, the error detector module 207 can parse the data stored in the aggregated ECC-corrected and uncorrected error module 206 to determine whether the ECC check circuits 121 and 123 have performed correctly.

[0041] about Figure 3 Explain the corrector stored in corrector table 202.

[0042] The information signal can contain any appropriate number of bits in a word, and the ECC data can also contain any appropriate number of bits. For the purposes of this description, the number of bits in the information signal is 32, and the number of bits in the ECC data is seven, and it should be understood that in other embodiments, these numberings can be scaled as needed.

[0043] Information signal 301 is a 32-bit binary number consisting entirely of zeros. Information signal 302 is a 32-bit binary number where the least significant bit has been changed to one, and the other bits are zero. Information signal 303 is a 32-bit binary number where the digit immediately preceding the least significant bit has been changed to one, and the other bits are zero. Information signals 302-304 show a sequence in which all bits of the information signal except for a single bit that is one are zero, and said bits are shifted one position relative to the previous information signal. The ellipse indicates that the illustration is truncated for convenience. Information signal 304 is the last information signal in the group, where the most significant bit is one, and the other bits are zero. Therefore, the group of information signals shown by information signals 301-304 contains a single information signal with all zeros, and 32 unique information signals where a single bit has been changed to one and the remaining bits are zero.

[0044] The hash operation includes any appropriate hash operation that can be performed by the ECC calculator 115 to generate ECC data from the corresponding information signal. For the purposes of this example, the ECC data generated from information signal 301 is referred to as ECC 32. Applying a hash operation to information signal 302 produces ECC data ECC 31 as a result; applying a hash operation to information signal 303 produces ECC data ECC 30 as a result; and applying a hash operation to information signal 304 produces ECC data ECC 0 as a result. Each of the 32+1 information signals corresponds to a corresponding and unique ECC data hash ECC 32-ECC 0.

[0045] In this example, there are 32 correctors, each corresponding to one of the information signals 302-304. In one aspect, each of the information signals 302-304 represents a bit flip error that may occur between sequential logic 111 and ECC check circuits 121 or 123. Therefore, each of the correctors corresponds to a bit flip error.

[0046] Various embodiments can compute the correctors 31-0 according to any suitable technique. In this example, corrector 31 can be computed by performing an XOR operation on ECC 32 and ECC 31, corrector 30 can be computed by performing an XOR operation on ECC 32 and ECC 30, and so on, so that corrector 0 can be computed by performing an XOR operation on ECC 32 and ECC 0. Therefore, the corrector itself can be considered as a hash, and each corrector corresponds to a corresponding bit flip error.

[0047] The calibrators can be arranged in a table, such as at calibrator table 202, e.g. Figure 4As shown in the example, in the corrector table 202, each corrector can be associated with the corresponding bit position of a bit flip error. For example, a bit flip error at the most significant bit position (bit 0) can be associated with corrector 0, a bit flip error at the next most significant bit position (bit 1) can be associated with corrector 1, and so on, until the least significant bit position (bit 31) is associated with corrector 31. In this way, correctors can be accessed in the corrector table 202 by using the bit position as a key.

[0048] Now return to Figure 2 ,about Figures 3 to 4 The concept discussed herein illustrates an example of a fault simulation specifically for a flip-flop error. The test selector module 203 operates via an algorithm in which it tests each of the bit positions, starting at the least significant bit position, as shown by information signal 302, bit 31, and corrector 31. Therefore, the test selector module can select corrector 31 from corrector table 202 and provide corrector 31 to XOR function module 204. In this example, access generation logic 114 can output information signal 301 for each of the tests, enabling ECC simulator 115 to output ECC data hash ECC 32. XOR function module 204 applies an XOR operation to ECC 32 and corrector 31. The XOR operation of ECC 32 and corrector 31 generates an ECC data hash equal to ECC 31. The XOR function module 204 outputs the resulting data hash (ECC 31) to combinational logic 113, and then to sequential logic circuit 112, which transmits the data hash to bus 119.

[0049] At this point, ECC check circuit 121 receives information signal 301 (all zeros) on bus 118 and ECC 31 on bus 119. From the perspective of ECC check circuit 121, if it receives information signal 301 and the corresponding ECC data hash (i.e., ECC 32), then no error needs to be detected. However, ECC check circuit 121 instead receives the ECC data hash ECC 31 corresponding to information signal 302. Therefore, ECC check circuit 121 (assuming it is working correctly) can detect that the least significant bit has been incorrectly received as zero on bus 118. This is because ECC 31 and ECC 32 differ by more than two bits, and the SECDED hardware of ECC check circuit 121 is configured to determine that ECC 31 is correct in this situation and that bus 118 has a unit toggle.

[0050] ECC checking circuit 121 can employ any suitable technique. For example, in this instance, ECC checking circuit 121 can calculate an ECC data hash based on the received information signal 301, which is expected to generate ECC 32, and then ECC checking circuit 121 can determine whether ECC 32 matches ECC 31. Assuming ECC checking circuit 121 operates successfully, then ECC checking circuit 121 can determine that no match exists. In this instance, ECC checking circuit 121 can then use the ECC data hash ECC31 to repair the received information signal 301 by changing the least significant bit from zero to one. In other words, changing the least significant bit from zero to one will generate information signal 302. Continuing the instance, ECC checking circuit 121 can then return the result of its operation to fault simulation module 116. For example, ECC checking circuit 121 can return the result in any suitable manner, such as by returning the repaired information signal (information signal 302), returning an identifier of the position of the repaired bit, etc.

[0051] The result from the ECC check circuit 121 can then be stored at the aggregated ECC corrected and uncorrected error module 206. As described above, assuming the ECC check circuit 121 operates correctly, the returned result should indicate a corrected error in the least significant bit. If the ECC check circuit 121 does not operate correctly, the returned result will be different, and in some embodiments, it can be any result other than indicating a corrected error in the least significant bit.

[0052] It is worth noting that in this example, a given ECC data hash (ECC YZ) can be XORed with ECC 32 to generate the corresponding corrector (corrector YZ). Furthermore, in this example, a given corrector can be XORed with ECC 32 to generate the corresponding ECC data hash (e.g., XOR (ECC 32, corrector YZ) to generate ECC YZ).

[0053] Then, test selector 203 can access the corrector table 202 again to receive corrector 30, which corresponds to a bit flip error in the next least significant bit (as in information signal 303). Test selector 203 can then provide corrector 30 to XOR function module 204, and XOR function 204 also receives ECC 32 from ECC calculator 115. XOR function module 204 can then perform an XOR operation on ECC 32 and corrector 30 to generate ECC hash data ECC 31, which is provided to sequential logic circuit 112. ECC check circuit 121 also receives information signal 301 on bus 118. ECC check circuit 121 then performs a similar check as described above. Assuming ECC check circuit 121 performs correctly, it should return a result indicating that the next least significant bit has been corrected. Otherwise, ECC check circuit 121 may return a different result, which would indicate a fault in ECC check circuit 121. The results can then be stored in the aggregated ECC-corrected and uncorrected error module 206.

[0054] Test selector 203 can then continue through table 202 one after another, so that fault simulation module 116 injects each of the different bit error bits 0-31 and aggregates the results at module 206.

[0055] Then, the error detector module 207 parses the contents of module 206 to determine if the contents indicate any fault with the ECC check circuit 121. For example, if all the results in module 206 indicate their corresponding bit errors, then there may be no fault. On the other hand, if one or more of the results in module 206 indicate that the ECC check circuit 121 failed to catch the bit errors, then the error detector module 207 can issue a fault flag to the interrupt handler 117.

[0056] Although the above examples refer to tests for faults in ECC check circuit 121, fault simulation module 116 can perform the same or similar tests to check the functionality of any other ECC check circuit (such as ECC check circuit 123).

[0057] The example just described above tests the functionality of an ECC check circuit relative to the information signal on bus 118 by using a known good information signal having a set of ECC data manipulated to indicate that the information signal has one or more incorrect bits. However, there may be a fault in the ECC check circuit relative to the ECC data on bus 119. Therefore, various embodiments can provide techniques to check whether the ECC check circuit is operating properly relative to the ECC data on bus 119 by using a known good information signal having a set of ECC data manipulated to indicate that the ECC data has one or more incorrect bits. For example, test selector 203 can cause toggle module 205 to control combinational logic 113 to toggle one bit of ECC data 130 at a time.

[0058] In one example, test selector 203 can be configured to control XOR function module 204 such that XOR function module 204 passes ECC data from ECC calculator to toggle module 205 without performing an XOR operation. Test selector 203 can then be configured to control toggle module 205 to toggle individual bits (e.g., least significant bits) of ECC data. For example, toggle module 205 can cause combinational logic 113 to toggle individual select bits of ECC data 130 at a time. In this way, test selector 203 can inject unit errors into the ECC data hash. In an example, ECC check circuits 121, 123 can be configured to detect unit errors in the ECC data hash, correct the unit errors, and report the corrected bits back to fault simulation module 116. In other words, ECC check circuits 121, 123 can be configured to perform SECDED on both the information signals on bus 118 and the ECC data hash on bus 119.

[0059] Test selector 203 can be configured to inject errors one at a time into each of the subsequent bits of the ECC data hash, receive results from ECC check circuits 121, 123, perform error detection at error detection module 207, and issue a fault flag to interrupt handler 117 as needed.

[0060] Figure 5 This is an illustration of an example method 500 for fault simulation according to some embodiments. Method 500 may be derived from, for example... Figure 1 The fault simulation module 116 and other fault simulation modules are executed. For example, the fault simulation module may contain modules that can be executed in, for example,... Figure 1The system 100 and similar systems provide hardware logic, firmware logic, and / or software logic for fault simulation. In some embodiments, some or all of the functions of the fault simulation module 116 can be executed under the control of a separate test control module, such as by using software or firmware, and can be executed on the same processor core as the processor core hosting the fault simulation module or on a different processor core. For example, the separate test control module can control... Figure 2 The test selector 203 selects a set of tests, selects a test for bit flip errors of information signals or selects a test for bit flip errors of ECC data hashes, and places the fault simulation module 116 in idle mode (e.g., normal access operation of processor core 110) or in active mode (e.g., fault simulation mode).

[0061] At action 502, an information signal is transmitted from the transmitting circuit to the receiving circuit. An example of the transmitting circuit may include a processor core 110 that transmits the information signal on bus 118 via sequential logic 111. An example of the receiving circuit may include interconnects, such as a memory controller, a peripheral bridge, or another component that provides access to a downstream resource.

[0062] At action 504, the processor core can calculate the ECC data hash of the information signal. This can be done before or simultaneously with the transmission of the information signal. Figure 1 In this example, the ECC calculator 115 can use any suitable technique to calculate the ECC data hash of the information signal. In some embodiments, the ECC data hash can allow for the repair of sufficient bits for at least one data bit in the information signal. (The above text is incomplete and requires further context.) Figure 3 An example of an ECC data hash is shown below, where the ECC data hash is shown as ECC 0-ECC 32. In the examples discussed above, the information signal may contain appropriate signals, such as an all-zero signal (e.g., information signal 301), and its associated ECC data hash is shown as ECC 32.

[0063] At action 506, the fault simulation module can inject an error into the error-corrected data hash. In this example, action 506 generates an indication signal with at least one bit of an incorrect modified ECC data hash. For example, action 506 may involve performing a Boolean operation (e.g., XOR operation) using the error-corrected data hash and a second hash (e.g., a corrector). An error can be injected by changing one or more bits of the calculated ECC data hash to conform to the result of the Boolean operation. In one example, the result of the Boolean operation may contain a modified ECC data hash corresponding to a specific bit flip.

[0064] Action 508 includes transmitting the modified ECC data hash to the receiving circuitry. In the above example, the fault simulation module 116 is configured to transmit the modified ECC data hash to an interconnect, such as interconnect 120 or 122. As a result of actions 502 and 506, the ECC checking circuitry (e.g., circuit 121 or 123) can receive both the information signal and the modified ECC hash. For example, the information signal could be an all-zero information signal, and the modified ECC hash could correspond to a similar signal where one bit has been flipped.

[0065] Therefore, the ECC check circuit can perform an ECC check on the information signal using an ECC data hash. Assuming the ECC check circuit is working correctly, it should identify unit toggle errors in the information signal.

[0066] At action 510, the fault simulation module receives the result of an error correction check from the receiving circuit. The error correction check can indicate the toggling of a single bit in the information signal, which indicates that the receiving circuit is not faulty. Alternatively, the error correction check can indicate the toggling of something other than a single bit in the information signal, which indicates a fault in the receiving circuit.

[0067] At action 512, the fault simulation module can determine whether an error has been detected based on the results of the error correction check. For example, the fault simulation module may include an error detector module configured to parse the results from the receiving circuit and determine whether the receiving circuit has failed.

[0068] Method 500 can be performed as part of a larger fault simulation operation. For example, method 500 may further include selecting the corrector one bit at a time to simulate a bit flip of the information signal. The fault simulation module or the entity controlling the fault simulation module can cause the fault simulation module to select the corrector according to the bit order, such that each possible bit flip is tested from the least significant bit to the most significant bit (or vice versa). Therefore, the results from the receiving circuit can be batched, and action 512 can be performed on a batch of results.

[0069] Method 500 can be performed at any appropriate time, such as during the manufacture and testing of system 100, during the power-on or reset of system 100, or at other times.

[0070] The term "semiconductor die" is used herein. A semiconductor device can be a discrete semiconductor device, such as a bipolar transistor, a plurality of discrete devices, such as a pair of power FET switches fabricated together on a single semiconductor die, or a semiconductor die can be an integrated circuit having multiple semiconductor devices, such as multiple capacitors in an A / D converter. A semiconductor device can contain passive devices such as resistors, inductors, filters, sensors, or active devices such as transistors. A semiconductor device can be an integrated circuit having hundreds or thousands of transistors coupled to form functional circuitry (e.g., a microprocessor or memory device). A semiconductor device may also be referred to herein as a semiconductor device or an integrated circuit (IC) die.

[0071] The term "semiconductor package" is used herein. A semiconductor package has at least one semiconductor die electrically coupled to terminals and a package body that protects and covers the semiconductor die. In some arrangements, multiple semiconductor dies may be packaged together. For example, a power metal-oxide-semiconductor (MOS) field-effect transistor (FET) semiconductor device and a second semiconductor device (e.g., a gate driver die or a controller die) may be packaged together to form a single packaged electronic device. Additional components, such as passive components (e.g., capacitors, resistors, and inductors or coils), may be included in the packaged electronic device. The semiconductor die is mounted on a package substrate that provides conductive leads. A portion of the conductive leads forms terminals for the packaged device. In wire bonding integrated circuit packages, bonding wires couple the conductive leads of the package substrate to bonding pads on the semiconductor die. The semiconductor die may be mounted to the package substrate with the device-side surface facing away from the substrate and the back-side surface facing the die pads of the package substrate and mounted to said die pads. Semiconductor packages may have a package body formed from a thermosetting epoxy molding compound in a molding process or formed using an epoxy resin, plastic, or resin that is liquid at room temperature and subsequently cures. The package body provides a hermetically sealed enclosure for a packaged device. The package body can be formed in a mold using an encapsulation process; however, a portion of the leads of the package substrate is not covered during encapsulation, and these exposed lead portions form terminals for the semiconductor package. Semiconductor packages may also be referred to as "integrated circuit packages," "microelectronic device packages," or "semiconductor device packages."

[0072] While various examples of this disclosure have been described above, it should be understood that these examples are presented by way of illustration only and not as a limitation. Numerous changes may be made to the disclosed examples based on the disclosure herein without departing from the spirit or scope of this disclosure. Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible. Therefore, the breadth and scope of the invention should not be limited to any of the examples described above. In fact, the scope of this disclosure should be defined by the appended claims and their equivalents.

Claims

1. A method comprising: Transmit the information signal from the transmitting circuit to the receiving circuit; Calculate the first error correction value of the information signal; The error is injected into the first error correction value, thereby generating the second error correction value; The second error correction value is transmitted to the receiving circuit; Receive the result of the error correction check from the receiving circuit; as well as Whether the error has been detected is determined based on the results of the error correction check.

2. The method of claim 1, wherein injecting the error into the first error correction value comprises: Retrieve the value associated with the error; Perform a Boolean operation on the value associated with the error and the first error correction value to generate the second error correction value; as well as Place the second error correction value on the bus.

3. The method according to claim 2, wherein the Boolean operation includes an XOR operation.

4. The method of claim 1, further comprising: A value is selected from a plurality of correction values, wherein each of the plurality of correction values ​​is based on the first error correction value and the corresponding bit error; Perform a Boolean operation on the value and the first error correction value to generate the second error correction value; as well as Place the second error correction value on the bus.

5. The method of claim 4, wherein the selection of the value is performed based on the corresponding bit error associated with the value.

6. The method of claim 4, wherein the value includes the result of an XOR operation on the first error correction value and the corresponding bit error value.

7. The method of claim 1, wherein injecting the error into the first error correction value comprises: Flip a single bit of the first error correction value; as well as Determining whether the error has been detected includes determining whether the error exists based on whether the receiving circuit detects a unit error in the first error correction value.

8. The method of claim 1, wherein transmitting the second error correction value to the receiving circuitry comprises transmitting the second error correction value from the processor core to a memory controller or a peripheral bridge.

9. The method of claim 1, wherein determining whether the error has been detected includes determining whether the error exists based on the receiving circuit detecting a unit error in the information signal.

10. A system comprising: The transmitting circuit includes: The first sequential logic is configured to transmit information signals; An error correction calculator is configured to generate a first error correction value based on the information signal; A fault injection circuit is configured to modify the first error correction value by injecting an error, thereby generating a second error correction value; as well as A second sequential logic is configured to transmit the second error correction value; as well as A receiving circuit, coupled to the transmitting circuit, is configured to receive the information signal and the second error correction value, wherein the receiving circuit comprises: An error correction circuit system is configured to process the information signal and the second error correction value and return the result to the transmitting circuit.

11. The system of claim 10, wherein the transmitting circuit includes a processor core.

12. The system of claim 11, wherein the receiving circuitry includes a peripheral bridge or a memory controller.

13. The system of claim 10, wherein the error correction circuit system is configured to return the result as an indication of a corrected error or an uncorrected error to the transmitting circuit, and wherein the transmitting circuit is configured to determine whether the error has been detected by processing the result.

14. The system of claim 10, wherein the fault injection circuit is configured to: A correction value is selected from a plurality of correction values, wherein each correction value is based on the first error correction value and a corresponding bit error value; and Perform a Boolean operation on the correction subvalue and the first error correction value to generate the second error correction value.

15. The system of claim 14, wherein the fault injection circuit includes an XOR gate configured to perform the Boolean operation.

16. The system of claim 10, wherein the fault injection circuit is configured to modify the first error correction value by toggling a single bit of the first error correction value.

17. A circuit comprising: The first sequential logic circuit is configured to transmit information signals to the receiving circuit. An error correction calculator circuit is configured to generate a first error correction value based on the information signal; A fault injection circuit is configured to modify the first error correction value by injecting an error, thereby generating a second error correction value; A second sequential logic circuit is configured to transmit the second error correction value to the receiving circuit. as well as An error detector circuit is configured to receive a response from the receiving circuit and determine whether the error has been detected based on the response.

18. The circuit of claim 17, wherein the fault injection circuit and the error detector circuit are implemented in the processor core.

19. The circuit of claim 17, wherein the fault injection circuit is configured to: Select the first correction value from multiple correction values; and An XOR operation is performed on the first correction value and the first error correction value, wherein the output of the XOR operation is the second error correction value.

20. The circuit of claim 17, wherein the information signal is a set of all zeros, and wherein the second error correction value corresponds to a specific bit of the information signal that has been flipped.

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