Integrated multi-port IO-linked master transceiver and adaptive DIO design

Abstract

The invention relates to a multi-port IO linked master transceiver and adaptive DIO design. A system includes a microcontroller unit (MCU) and a plurality of reconfigurable devices connected to the MCU in a daisy chain arrangement via a serial peripheral interface (SPI) protocol. Each reconfigurable device includes control circuitry configured to operate in a digital input / output (DIO) mode and an IO link mode, digital logic for switching the DIO control circuitry between the DIO mode and the IO link mode, an output driver connected between an output of the control circuitry and a respective output pin of a plurality of pin sets, the input filter is connected between the input of the control circuit arrangement and the corresponding input pin of the plurality of pin sets, and the SPI interface is used for communicating with the MCU and other reconfigurable devices in the daisy chain, and the digital control facilitates communication between the SPI interface and the control circuit arrangement.

Description

Technical Field

[0001] This disclosure generally relates to industrial automation and control systems, and more specifically to reconfigurable integrated circuit systems that combine I / O link master functionality with digital input / output (DIO) capabilities. Background Technology

[0002] I / O links are standardized serial point-to-point communication protocols used in industrial automation to connect sensors and actuators to controllers. I / O link masters act as interfaces between I / O link devices (sensors and actuators) and advanced fieldbuses or industrial Ethernet. They manage communication with connected I / O link devices, enabling data exchange, parameterization, and diagnostics.

[0003] Known I / O link master devices require additional components to support an 8-port master transceiver as well as external drivers. They lack the flexibility to support digital input / output (DIO) functionality. Existing solutions require eight separate transceiver chips to implement the 8-port output, which increases the number of external components needed to support each device and results in a large number of interfaces to each individual device.

[0004] Therefore, further development is needed. Summary of the Invention

[0005] The system disclosed herein includes a microcontroller unit (MCU) and multiple reconfigurable devices daisy-chained to the MCU via a Serial Peripheral Interface (SPI) protocol. Each reconfigurable device has: digital input / output (DIO) control circuitry for operation in DIO mode and I / O link mode; input / output link (I / O link) logic circuitry for providing and reading data from the DIO control circuitry in I / O link mode; digital logic for switching between modes; an output driver connected between the output of the DIO control circuitry and the output pin of the pin set; an input filter connected between the input of the DIO control circuitry and the input pin of the pin set; and an SPI interface for communication with the MCU and other devices. The digital logic facilitates communication between the SPI interface and the DIO control circuitry and the I / O link logic circuitry.

[0006] Each pin set may have a power supply pin (L+), a communication / qualified input pin (C / Qi), a communication / qualified output pin (C / Qo), and additional input / output pins (I / Q).

[0007] In IO link mode, each pin set can be configured as an IO link channel.

[0008] In DIO mode, the C / Qi and I / Q pins can be configured as digital input channels, while the L+ and C / Qo pins can be configured as digital output channels.

[0009] The digital output channels can be configured to all be high-side outputs.

[0010] Alternatively, the digital output channel can be configured as a combination of high-side output and low-side output.

[0011] Each reconfigurable device's SPI interface can have a Serial Data Input (SDI) pin, a Serial Data Output (SDO) pin, a Chip Select (CS) pin, and a Clock (CLK) pin.

[0012] The MCU MOSI pin can be connected to the first device's SDI pin, its CS pin can be connected to all device CS pins, and its CLK pin can be connected to all device CLK pins. Each device's SDO pin can be connected to the next device's SDI pin, and the last device's SDO pin is connected to the MCU MISO pin.

[0013] Each reconfigurable device in a daisy-chain arrangement can be individually addressed and configured by the MCU via an SPI interface.

[0014] This document also discloses an operating system approach that includes configuring each device mode, providing data between I / O link logic and DIO control circuitry in I / O link mode, controlling digital I / O in DIO mode, switching modes, driving outputs, filtering inputs, and facilitating communication via an SPI interface.

[0015] This method may include configuring each pin set using L+, C / Qi, C / Qo, and I / Q pins. In I / O link mode, each pin set can be configured as an I / O link channel. In DIO mode, the C / Qi and I / Q pins can be configured as digital inputs, while the L+ and C / Qo pins can be configured as digital outputs. The digital output channels can be configured as all high-side outputs, or a combination of high-side and low-side outputs. The SPI interface can be configured with SDI, SDO, CS, and CLK pins.

[0016] The method may include connecting the MCU MOSI pin to the first device SDI pin, connecting the MCU CS and CLK pins to the corresponding pins of all devices, and connecting each device SDO pin to the next device SDI pin, wherein the last device SDO pin is connected to the MCU MISO pin.

[0017] This method may include individually addressing and configuring each device in the daisy-chain arrangement via an SPI interface. Attached Figure Description

[0018] Figure 1 This is a block diagram of a system including daisy-chained reconfigurable DIO / IO linked devices disclosed in this article. Detailed Implementation

[0019] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined herein can be applied to embodiments and applications beyond those described above without departing from the spirit and scope of this disclosure. The invention is not intended to be limited to the illustrated embodiments, but rather to be accorded the broadest scope consistent with the principles and features disclosed or suggested herein.

[0020] This paper discloses an integrated chip solution for Industrial Internet of Things (IIoT) and automation systems. To this end, Figure 1 The system shown is 100, which includes a microcontroller unit (MCU) 110 connected in a daisy chain to a plurality of reconfigurable digital input / output (DIO) / IO link devices 120(1) to 120(n) via the Serial Peripheral Interface (SPI) protocol, where n represents the total number of devices in the system.

[0021] The MCU110 includes a Main Sub-Input Output (MOSI) pin, a Chip Select pin (CS) pin, a Clock pin (CLK) pin, and a Main Sub-Output Output (MISO) pin.

[0022] Each DIO / IO link device, such as device 120(1), is an integrated circuit capable of operating in either DIO mode or IO link mode. Device 120(1) includes a digital logic block 129 containing a DIO control 123 and an IO link logic block 122 that can operate in both IO link mode and DIO mode. The digital logic block 129 manages the switching between DIO and IO link modes, while the SPI interface 121 manages communication with other devices 120(1), ..., 120(n) in the daisy chain.

[0023] The SPI interface 121 is connected via a data connection to the DIO control 123 and the I / O link logic 122 within the digital logic block 129. Additionally, a data connection exists between the I / O link logic 122 and the DIO control 123, allowing seamless coordination between the two operating modes.

[0024] DIO control 123 is connected to four pin sets 128a, ..., 128d via output driver 126 and input filter 127. The pins of pin sets 128a, ..., 128d, which are used as inputs, provide their inputs to DIO control 123 via input filter 127, while the pins of pin sets 128a, ..., 128d receive their output signals from DIO control 123 via output driver 126.

[0025] Although device 120(1) is described as having four pin sets 128a, ..., 128d, it should be understood that the design is scalable and can accommodate any number of pin sets required by the application. For example, the device can be expanded to include additional sets such as 128e, 128f, etc., each providing configurable I / O pins for the additional set. This scalability allows for greater flexibility in system design, enabling the device to be adapted to applications requiring a higher number of I / O channels without fundamentally altering its architecture. The DIO control 123 and I / O link logic 122 will then manage and configure these additional pin sets in the same manner as the four sets described, thus maintaining the device's ability to switch between DIO and I / O link modes on all available pin sets. This applies to each of these devices 120(1), ..., 120(n).

[0026] When devices 120(1), ..., 120(n) switch to IO link mode, IO link logic 122 handles IO link protocol communication and works with DIO control 123 to configure four pin sets 128a, ..., 128d as four IO link pin sets, each set including a power supply pin L+, a communication / qualification input pin C / Qi, a communication / qualification output pin C / Qo, and an additional input / output pin I / Q. Therefore, for example, in IO link mode:

[0027] The pin set 128a configured by DIO control 123 includes pin L+ (1), pin C / Qi (1), pin C / Qo (1) and pin I / Q (1);

[0028] The pin set 128b configured by DIO control 123 includes pin L+ (2), pin C / Qi (2), pin C / Qo (2) and pin I / Q (2);

[0029] The pin set 128c configured by DIO control 123 includes pin L+ (3), pin C / Qi (3), pin C / Qo (3), and pin I / Q (3); and

[0030] The pin set 128d configured by DIO control 123 includes pin L+ (4), pin C / Qi (4), pin C / Qo (4) and pin I / Q (4).

[0031] When devices 120(1), ..., 120(n) switch to DIO mode, DIO control 123 handles DIO communication, configuring four sets of pins 128a, ..., 128d as eight sets of digital input channels and eight sets of digital output channels. This configuration can be implemented in two ways: either all eight digital output channels act as high-side outputs, or four high-side outputs and four low-side outputs.

[0032] If the four pin sets 128a, ..., 128d are considered as four I / O link pin sets (but configured as DIO pins), each pin including an L+ pin, a C / Qi pin, a C / Qo pin, and an I / Q pin, then for eight digital input channels, the C / Qi pin will be used as the digital input for channels 1 to 4, and the I / Q pin will be used as the digital input for channels 5 to 8. For eight digital output channels, the L+ pin will be used as the digital output for channels 1 to 4, and the C / Qo pin will be used as the digital output for channels 5 to 8. Here, the digital output channels can be configured using all eight channels as high-side outputs (using the L+ and C / Qo pins), or using four high-side outputs (using the L+ pin) and four low-side outputs (using the C / Qo pin). This flexibility allows for adaptation to various industrial control scenarios. Therefore, for example, in DIO mode:

[0033] The pin set 128a configured by DIO control 123 includes pin DO(1), pin DI(1), pin DO(2) and pin DI(2);

[0034] The pin set 128b configured by DIO control 123 includes pin DO(3), pin DI(3), pin DO(4) and pin DI(4);

[0035] The pin set 128c configured by DIO control 123 includes pin DO(5), pin DI(5), pin DO(6), and pin DI(6); and

[0036] The pin set 128d configured by DIO control 123 includes pin DO (7), pin DI (7), pin DO (8) and pin DI (8).

[0037] Output driver 126 and input filter 127 help ensure that the electrical characteristics of the output and input signals meet the requirements of both IO links and DIO protocols (depending on the operating mode), including voltage levels and current capacity. For example, in DIO mode, output driver 126 can handle up to 500mA of current per channel at frequencies up to and exceeding 250kHz, making it suitable for directly driving a variety of industrial loads and compliant with the IEC 61131-2 standard for programmable controllers, thus providing compatibility with a wide range of industrial automation systems.

[0038] The SPI interface 121 includes SDI (Serial Data Input), SDO (Serial Data Output), CS (Chip Select), and CLK (Clock) pins. Devices 120(1), ..., 120(n) are connected to each other in a daisy chain arrangement, wherein the MOSI pin of MCU110 is connected to the SDI pin of the SPI interface 121 of device 120(1), the CS pin of MCU110 is connected to the CS pin of the SPI interface 121 of device 120(1), ..., 120(n), and the CLK pin of MCU110 is connected to the CLK pin of the SPI interface 121 of device 120(1), ..., 120(n). Due to the daisy chain arrangement, the SDO pin of the SPI interface 121 of device 120(1) is connected to the SDI pin of the SPI interface of the next device in the chain, which in turn connects its SDO pin to the SDI pin of the SPI interface of the next device in the chain, and the SDO pin of the SPI interface of the last device in the chain is connected to the MISO pin of MCU110.

[0039] Device 120(1) also includes a monitoring, protection, and fault alarm block 131 connected between the SPI interface 121 and the digital logic block 129. This block 131 provides several key functions to enhance the reliability and safety of the system. It continuously monitors the device's operating conditions, including voltage levels, current consumption, and temperature. The protection aspect of block 131 implements safety measures to prevent potential hazards such as overcurrent, overvoltage, and overtemperature conditions, automatically activating protection measures when necessary. Additionally, the fault alarm function allows block 131 to detect various fault conditions via the SPI interface 121 and report them to the MCU 110, enabling rapid response to any problems that may arise during operation.

[0040] The daisy-chain configuration of devices 120(1)..., 120(n) offers several advantages. It allows for efficient use of the MCU110's resources, as multiple devices can be controlled from a single set of SPI pins. This configuration also makes the system easily expandable; additional devices can be added to the chain without requiring additional pins on the MCU110. Daisy-chaining is particularly beneficial in applications such as remote I / O modules, where multiple I / O points can be distributed over considerable distances. In fact, each device 120(1)..., 120(n) in the chain can be individually addressed and configured by the MCU110 via the SPI interface. This allows for dynamic reconfiguration of the system, with some devices set to I / O link mode while others operate in DIO mode, providing a highly flexible I / O solution for complex industrial automation scenarios.

[0041] By integrating primary I / O linking functionality and reconfigurable digital I / O capabilities into a single general-purpose device, System 100 represents an advancement in industrial automation technology. The System 100 design offers substantial benefits over traditional approaches that rely on separate ICs for I / O linking and digital I / O functions.

[0042] Advantages include reduced system complexity, fewer components, fewer pins, lower cost, and enhanced flexibility. By consolidating multiple functions into a single device and enabling easy scalability through daisy-chaining, System 100 provides a powerful and adaptable tool for a wide range of industrial applications.

[0043] In practice, System 100 is particularly valuable in I / O link master systems, as well as in digital I / O or remote I / O modules and hubs. In I / O link master systems, System 100 can replace many single-channel and dual-channel ICs. In digital I / O or remote I / O modules and hubs, System 100's reconfigurable nature adapts to different I / O requirements. The combination of mode flexibility, scalability, and integrated functionality makes System 100 particularly valuable for a wide range of industrial automation scenarios, from basic machine control to complex distributed I / O systems. As a result, manufacturers gain access to an efficient and versatile tool that can significantly simplify their automation processes and adapt to evolving industrial needs.

[0044] Finally, it is obvious that modifications and changes can be made to the content described and shown herein without departing from the scope of this disclosure.

[0045] Although this disclosure has been described with a limited number of embodiments, those skilled in the art who benefit from it will envision other embodiments without departing from the scope of the disclosure. Furthermore, those skilled in the art will envision embodiments representing various combinations of the embodiments disclosed herein made in various ways.

Claims

1. A system comprising: Microcontroller unit (MCU); as well as Multiple reconfigurable devices are daisy-chained to the MCU via the Serial Peripheral Interface (SPI) protocol, each reconfigurable device comprising: A digital input / output (DIO) control circuit device is configured to operate in both digital input / output (DIO) mode and I / O link mode; An input / output link (IO-link) logic circuit device is configured to provide data to and read data from the DIO control circuit device when the DIO control circuit device operates in the IO-link mode. Digital logic for switching the DIO control circuitry between the DIO mode and the IO link mode; An output driver is connected between the output of the DIO control circuit device and the corresponding output pin of the plurality of pin sets; An input filter is connected between the input of the DIO control circuit device and the corresponding input pin of the plurality of pin sets; and An SPI interface for communicating with the MCU and other reconfigurable devices in the daisy-chain arrangement, wherein the digital logic facilitates communication between the SPI interface and the DIO control circuitry, and wherein the digital logic facilitates communication between the SPI interface and the I / O link logic circuitry.

2. The system of claim 1, wherein each of the plurality of pin sets comprises: Power supply pin L+; Communication / Qualified Input Pin C / Qi; Communication / Quality Output Pin C / Qo; as well as Additional input / output pins I / Q.

3. The system of claim 2, wherein in the IO link mode, each pin set is configured as an IO link channel.

4. The system of claim 2, wherein in the DIO mode: The C / Qi pins and I / Q pins of the plurality of pin sets are configured as digital input channels; and The L+ pin and the C / Qo pin of the plurality of pin sets are configured as digital output channels.

5. The system of claim 4, wherein the digital output channels can be configured to all be high-side outputs.

6. The system of claim 4, wherein the digital output channel can be configured as a combination of high-side output and low-side output.

7. The system of claim 1, wherein the SPI interface of each reconfigurable device comprises: Serial data input SDI pin; Serial data output SDO pin; Select the CS pin for the chip; as well as Clock CLK pin.

8. The system according to claim 7, wherein: The MOSI pin of the MCU is connected to the SDI pin of the first reconfigurable device in the daisy chain arrangement; The CS pin of the MCU is connected to the CS pin of all reconfigurable devices; The CLK pin of the MCU is connected to the CLK pin of all reconfigurable devices; as well as The SDO pin of each reconfigurable device is connected to the SDI pin of the next reconfigurable device in the daisy chain arrangement, wherein the SDO pin of the last reconfigurable device is connected to the MISO pin of the MCU.

9. The system of claim 1, wherein each reconfigurable device in the daisy-chain arrangement can be individually addressed and configured by the MCU via the SPI interface.

10. A method of operating an operating system, the system comprising a microcontroller unit (MCU) and a plurality of reconfigurable devices connected to the MCU in a daisy-chain arrangement via a Serial Peripheral Interface (SPI) protocol, the method comprising: Configure each reconfigurable device to operate in digital input / output (DIO) mode or I / O link mode; For each reconfigurable device operating in the said IO link mode: providing data to and reading data from the DIO control circuitry via the IO link logic circuitry; For each reconfigurable device operating in the DIO mode: digital inputs and outputs are controlled via the DIO control circuitry; The DIO control circuit device uses digital logic to switch between the DIO mode and the IO link mode; The output from the DIO control circuit device is driven to the corresponding output pin of the plurality of pin sets via the output driver; The inputs to the DIO control circuit device from the respective input pins of the plurality of pin sets are filtered by the input filter; as well as The digital logic facilitates communication between the SPI interface and the DIO control circuitry, as well as between the SPI interface and the I / O link logic circuitry.

11. The method of claim 10, further comprising: Configure each of the plurality of pin sets to include: a power supply pin L+; a communication / qualification input pin C / Qi; a communication / qualification output pin C / Qo; and an additional input / output pin I / Q.

12. The method of claim 11, further comprising: In the IO link mode, each pin set is configured as an IO link channel.

13. The method of claim 11, further comprising: In the DIO mode: the C / Qi pins and the I / Q pins of the plurality of pin sets are configured as digital input channels; And configure the L+ pin and the C / Qo pin in the plurality of pin sets as digital output channels.

14. The method of claim 13, further comprising: Configure the digital output channels to be either all high-side outputs or a combination of high-side and low-side outputs.

15. The method of claim 10, further comprising: Configure the SPI interface of each reconfigurable device to include: a serial data input (SDI) pin; a serial data output (SDO) pin; a chip select (CS) pin; and a clock (CLK) pin.

16. The method of claim 15, further comprising: Connect the MOSI pin of the MCU to the SDI pin of the first reconfigurable device in the daisy chain arrangement; connect the CS pin of the MCU to the CS pin of all reconfigurable devices; connect the CLK pin of the MCU to the CLK pin of all reconfigurable devices; and connect the SDO pin of each reconfigurable device to the SDI pin of the next reconfigurable device in the daisy chain arrangement, wherein the SDO pin of the last reconfigurable device is connected to the MISO pin of the MCU.

17. The method of claim 10, further comprising: Each reconfigurable device in the daisy-chain arrangement is individually addressed and configured by the MCU via the SPI interface.

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