Servers and server clusters

Abstract

This application discloses a server and a server cluster, relating to the technical field of servers. The server includes: a power supply module, a main board, and a sideband power board. The power supply module is connected to the sideband power board through a power transfer board, and the sideband power board is connected to the main board. The power supply module includes a server power supply board, and the server power supply board is connected to an acceleration unit. The sideband power board includes a power supply area and a signal transfer area. A first conversion module is provided in the power supply area, and the sideband power board processes and outputs the received initial signal through the signal transfer area. Thus, through modular design, each module in this server achieves flexible interconnection and management through standardized interfaces and logical signals, and can achieve the technical effects of improving the reusability and configuration flexibility of the server, reducing the cost of circuit boards and transmission losses, improving power supply efficiency and system reliability, and meeting the diverse requirements of different artificial intelligence application scenarios.

Description

Technical Field

[0001] This application relates to the field of server technology, and more particularly to a server and a server cluster. Background Technology

[0002] Against the backdrop of rapid development of artificial intelligence technology and accelerated iteration of large models, artificial intelligence applications have placed higher demands on server computing power. Currently, the improvement of computing power still relies on the "stack card" mode, that is, interconnecting a large number of computing cards through a bus. This poses a new challenge to the ability of server nodes to adapt to different customers and application models.

[0003] In related technologies, server design is carried out through non-modular motherboard design. However, this method has problems such as low motherboard reusability, inconsistent board material specifications, poor adaptability, high cost and insufficient flexibility. Summary of the Invention

[0004] This application provides servers and server clusters to at least address the problem of low motherboard reuse in related technologies.

[0005] This application provides a server, including: a power supply module, a motherboard, and a sideband power board. The power supply module is connected to the sideband power board via a power adapter board, and the sideband power board is connected to the motherboard. The power supply module includes a server power supply board, which is connected to an acceleration unit. The sideband power board includes a power supply area and a signal conversion area. The power supply area is provided with a first conversion module for converting the node current output by the power adapter board into a target current to power the motherboard. The sideband power board processes and outputs the received initial signal through the signal conversion area.

[0006] This application also provides a server cluster, including: a plurality of servers as described above; and a cluster resource scheduler, which is connected to the plurality of servers respectively.

[0007] This application utilizes a modular design, dividing the server into independent functional modules such as a power supply module, motherboard, sideband power board, and input / output power supply board. These modules are flexibly interconnected and managed through standardized interfaces and logic signals. Simultaneously, the power supply architecture is optimized, and an independent server power supply board is integrated, supporting multiple power supplies in parallel to meet redundancy requirements. Power adapter boards and conversion modules ensure precise voltage adaptation. The signal transfer area and signal manager on the sideband power board logically process and flexibly transfer various management signals. This significantly improves server reusability and configuration flexibility, reduces board costs and transmission losses, enhances power supply efficiency and system reliability, and meets the diverse needs of different artificial intelligence application scenarios. It also solves the problem of low motherboard reusability in related technologies. Attached Figure Description

[0008] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This application provides a schematic diagram of a server connection as an embodiment of the present application.

[0010] Figure 2 This is a connection diagram of a power supply module according to a specific embodiment of this application;

[0011] Figure 3 This is a schematic diagram showing the connection between the input / output power supply board and the electronic component module in a specific embodiment of this application;

[0012] Figure 4 This is a schematic diagram illustrating the communication connection between the motherboard, acceleration unit, and sideband power board in a specific embodiment of this application.

[0013] Figure 5 This is a schematic diagram of the communication connection between the motherboard and the fan unit according to a specific embodiment of this application;

[0014] Figure 6 This is a schematic diagram of the communication connection between the motherboard and the electronic component module according to a specific embodiment of this application;

[0015] Figure 7 This is a schematic diagram of the connection between the server power supply board and the power adapter board according to a specific embodiment of this application;

[0016] Figure 8 This is a pin diagram of a multi-channel input / output connector according to a specific embodiment of this application;

[0017] Figure 9 This is a schematic diagram showing the connection between the sideband power board and the mainboard in a specific embodiment of this application;

[0018] Figure 10 This is a schematic diagram showing a first signal manager and a sixth signal connector on a sideband power board according to a specific embodiment of this application;

[0019] Figure 11 This is a schematic diagram showing the communication connection between the sideband power board and the input / output power board via a seventh signal connector in a specific embodiment of this application.

[0020] Figure 12 This is a schematic diagram of an input / output power supply board with a second conversion module according to a specific embodiment of this application;

[0021] Figure 13 This is a schematic diagram showing the connection between the management board, the first ear-mounted board, and the second ear-mounted board according to a specific embodiment of this application.

[0022] Figure 14 This is a schematic diagram of the modular architecture of a server according to a specific embodiment of this application;

[0023] Figure 15 This is a schematic diagram of the connector topology of a server power supply module according to a specific embodiment of this application;

[0024] Figure 16 This is a schematic diagram of the DC power supply board and the server power supply in a specific embodiment of this application.

[0025] Figure 17 This is a schematic diagram of the structure of a sideband power board according to a specific embodiment of this application;

[0026] Figure 18 This is a schematic diagram of the structure of an electronic component module according to a specific embodiment of this application;

[0027] Figure 19 This is a schematic diagram of the input / output power supply board according to a specific embodiment of this application;

[0028] Figure 20 This is a clock and signal connection topology diagram of a motherboard according to a specific embodiment of this application;

[0029] Figure 21 This is a reset and signal connection topology diagram of a motherboard according to a specific embodiment of this application;

[0030] Figure 22 This is an integrated circuit bus connection topology diagram of a motherboard according to a specific embodiment of this application;

[0031] Figure 23 This is a network controller sideband interface connection topology diagram of a motherboard according to a specific embodiment of this application;

[0032] Figure 24 This is a schematic diagram of a 54V power supply topology according to a specific embodiment of this application;

[0033] Figure 25 This is a block diagram illustrating a server cluster provided in an embodiment of this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0035] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0036] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] In the current era of rapid development in artificial intelligence, large-scale models are evolving at an astounding pace, with rapid iterations placing higher demands on server computing power. However, all breakthroughs in computing power to date have relied on the relatively traditional method of stacking computing cards. In data centers, thousands or even tens of thousands of computing cards are interconnected through various buses. This presents new challenges for traditional AI server processor nodes, requiring adaptation to different processor platforms to meet the diverse needs of different clients and AI application models.

[0038] In related technologies, server design utilizes a non-modular motherboard design; however, the compute node architecture of this method has several problems:

[0039] 1) The non-modular design of the motherboard results in all the power supplies, external interfaces and board shapes being bizarre and almost unusable, making it difficult to meet different customer needs.

[0040] 2) Due to the different design dimensions of the circuit boards, the materials used also differ. This can lead to production delays or stagnant materials when facing urgent needs because it is impossible to obtain enough materials.

[0041] 3) The power supply design for the motherboard as a whole and the input / output modules is placed on the motherboard. As the server speed increases, the cost of the board material here also increases. Using high-specification board material will lead to an increase in the overall cost.

[0042] 4) Different focuses on artificial intelligence will lead to different topologies in the overall architecture. Adjusting non-modular motherboards requires significant modifications to the internal wiring, resulting in a large amount of repetitive work for layout.

[0043] 5) Currently, the computing nodes are powered independently, which will cause the power supply of the computing nodes to occupy space in the chassis, resulting in the GPU (Graphics Processing Unit) nodes not being able to meet the N+N power redundancy requirements.

[0044] To address at least one of the aforementioned technical problems, this application proposes a server that employs a modular design, dividing the server into independent functional modules such as a power supply module, motherboard, sideband power board, and input / output power supply board. Each module achieves flexible interconnection and management through standardized interfaces and logic signals. Simultaneously, the power supply architecture is optimized and an independent server power supply board is integrated, supporting multiple power supplies in parallel to meet redundancy requirements. Combined with a power adapter board and conversion module, precise voltage adaptation is achieved. The signal transfer area and signal manager on the sideband power board logically process and flexibly transfer various management signals. This significantly improves server reusability and configuration flexibility, reduces board costs and transmission losses, enhances power supply efficiency and system reliability, and meets the diverse needs of different artificial intelligence application scenarios. It also solves the problem of low motherboard reusability in related technologies.

[0045] The server and server cluster of the present application embodiments are described in detail below with reference to the accompanying drawings.

[0046] like Figure 1 As shown, the server 100 in this embodiment includes a power supply module 10, a motherboard 20, and a sideband power board 30. The power supply module 10 is connected to the sideband power board 30 via a power adapter board 40, and the sideband power board 30 is connected to the motherboard 20. The power supply module 10 includes a server power supply board 12, which is connected to an acceleration unit G1. The sideband power board 30 includes a power supply area and a signal conversion area. The power supply area is provided with a first conversion module M1, which is used to convert the node current output by the power adapter board 40 into a target current to power the motherboard 20. The sideband power board 30 processes and outputs the received initial signal through the signal conversion area.

[0047] Specifically, the power supply module 10, as the overall power source for the server, uses the power adapter board 40 to transfer and distribute power, ensuring centralized control of power supply and laying the foundation for the modular disassembly of the server 100. One end of the power adapter board 40 connects to the power supply module 10 to obtain power, and the other end connects to the sideband power board 30, transmitting the original node current to the sideband power board 30 while providing a stable input for current conversion. The sideband power board 30 is an intermediate component; on one hand, it establishes a power supply connection with the power adapter board 40 to receive node current; on the other hand, it connects to the motherboard 20, completing current conversion to power the motherboard 20, and simultaneously handling signal interaction between the motherboard 20 and other components. The acceleration unit G1 connects directly to the server power supply board 12 in the power supply module 10, ensuring a stable and efficient power supply for the computing components without the need for the power adapter board 40, thus meeting the high power consumption requirements of large-scale artificial intelligence models.

[0048] The sideband power board 30 integrates power conversion and signal processing by dividing the power supply area into a power supply area and a signal conversion area. This design directly addresses the problems of material waste and difficulty in board modification caused by the integration of power supply and signal functions in traditional motherboards. The first conversion module M1 in the power supply area converts the node current output by the power conversion board 40 into the target current. The signal conversion area is responsible for signal processing and output. It can receive the initial signal from the motherboard 20 and perform logical processing, conversion, or forwarding according to the system design requirements.

[0049] It should be noted that the acceleration unit G1 described in the above embodiments may include one or more of the following: a graphics processor, a data processing unit, a high-speed switching chip, a field-programmable gate array, an application-specific integrated circuit, and a memory acceleration unit. The first conversion module M1 may be a power supply brick.

[0050] Compared to the poor reusability issues caused by the non-modular motherboard in related technologies, this application's embodiment separates the power conversion function from the motherboard to the sideband power board. The motherboard retains only the core computing functions, eliminating the need for design modifications due to changes in power demand or signal configuration adjustments, thus achieving motherboard reuse across multiple platforms and configuration scenarios. Regarding the insufficient configuration flexibility caused by chaotic signal management, this application's embodiment centrally processes initial signals through the signal transfer area of ​​the sideband power board, enabling the server to flexibly adapt to different acceleration unit topology configurations and meet the diverse combination requirements of computing components for artificial intelligence servers.

[0051] Therefore, this embodiment adopts a modular design, dividing the server into independent functional modules such as a power supply module, motherboard, sideband power board, and input / output power supply board. Each module achieves flexible interconnection and management through standardized interfaces and logic signals. At the same time, the power supply architecture is optimized and an independent server power supply board is integrated, which can support multiple power supplies in parallel to meet redundancy requirements. With the help of power adapter boards and conversion modules, precise voltage adaptation is achieved. Through the signal transfer area and signal manager of the sideband power board, various management signals are logically processed and flexibly transferred. This can achieve the technical effects of greatly improving server reusability and configuration flexibility, reducing board costs and transmission losses, improving power supply efficiency and system reliability, and meeting the diverse needs of different artificial intelligence application scenarios. It can solve the problems of low motherboard reusability and insufficient configuration flexibility in related technologies.

[0052] In some embodiments of this application, such as Figure 2 As shown, the power supply module 10 also includes a power supply 11. The server power supply board 12 is connected to the power supply 11 and the power adapter board 40 respectively. The server power supply board 12 is connected to the acceleration unit G1 through the first power supply connector C1 and the server power supply board 12 is connected to the fan module 50 through the second power supply connector C2.

[0053] Specifically, power supply 11 is the power input source and can adopt a 54V output design. Compared with traditional 12V power supplies, it can directly power the fan module 50, improving heat dissipation performance, while reducing the current requirements of the boards and connectors and reducing transmission losses. The server power supply board 12 is the core of power distribution, undertaking the dual responsibilities of centralized power supply and status monitoring. It integrates the power from power supply 11 and distributes it to various components of the server through different paths, changing the irregular design problem caused by the direct integration of power supply interfaces on the traditional motherboard, and realizing the modular separation of power supply and motherboard.

[0054] The server power supply board 12 is connected to both the power supply 11 and the power adapter board 40, receiving power from the power supply and transmitting the centralized power to the power adapter board 40. The server power supply board 12 is connected to the acceleration unit G1 via the first power connector C1, ensuring a stable and efficient power supply to the acceleration unit G1 to meet the high power consumption requirements of large-scale artificial intelligence models, while simplifying the power supply chain and reducing potential failure points. The server power supply board 12 is connected to the fan module 50 via the second power connector C2, providing not only power but also transmitting signals such as fan speed control and status feedback, achieving integrated power supply and management, and solving the problem of poor coordination caused by the separation of traditional fan power supply and management. The first power connector C1 can be a PWR CON FOR GPU (Power Connector For GPU), and the second power connector C2 can be a FAN BOARD CONN (fan board connector). The first power connector C1 and the second power connector C2 can be located on the server power supply board 12.

[0055] The power supply module in this embodiment consists of a power supply and a server power supply board, realizing centralized integration and modular management of power supply. This avoids the layout chaos caused by traditional decentralized power supply. The server power supply board establishes targeted connections with the power supply, power adapter board, acceleration unit, and fan module, ensuring the stability and independence of power supply for each component, while also achieving coordinated and unified power supply and signal transmission. The fan module obtains integrated power supply and signal transmission support through the second power supply connector, enabling the fan's operating status to be precisely matched with the system operating conditions, optimizing the heat dissipation effect, and thus ensuring the overall stability and durability of the server's operation.

[0056] In some embodiments of this application, such as Figure 3 As shown, the server 100 also includes an input / output power supply board 60 and an electronic component module 70, wherein the input / output power supply board 60 is connected to the power adapter board 40 and the electronic component module 70, respectively.

[0057] Specifically, the input / output power supply board 60 is an independent power supply board designed for the electronic component module 70. Addressing the issues of irregularly shaped boards and poor reusability caused by traditional motherboards integrating power supplies for electronic components, the input / output power supply board 60 receives power from the power adapter board 40, providing precise and stable power to the electronic component module 70. This electronic component module 70 can be positioned at the front of the server, avoiding the need to modify the motherboard 20 due to changes in electronic component configurations. The electronic component module 70 is a replaceable module, enabling flexible combination and replacement of different components through standardized installation and power supply interfaces.

[0058] The input / output power supply board 60 is connected to the power adapter board 40, obtaining power directly from the power adapter board 40 without needing to go through the motherboard 20 or the sideband power board 30. The power adapter board 40 acts as a power distribution hub, transmitting power to the sideband power board 30 for use by the motherboard 20, and to the input / output power supply board 60 for use by the electronic component module 70. This achieves physical isolation between the motherboard power supply and the electronic component power supply, avoiding the waste of high-cost motherboard materials using low-speed power supply signals.

[0059] The input / output power supply board 60 is connected to the electronic component module 70, providing a power supply channel for each component in the electronic component module 70. This ensures that each electronic component receives a matching power supply, while avoiding power supply interference between components and improving system stability.

[0060] This embodiment achieves the separation and independence of power supply for electronic components from the motherboard by adding an input / output power supply board and electronic component modules. This avoids the need to modify the motherboard due to changes in electronic component configuration, improves motherboard reusability and system configuration flexibility. The targeted connection between the input / output power supply board, power adapter board, and electronic component modules ensures the stability and independence of power supply for electronic components, and allows the addition, removal, or replacement of electronic components without relying on motherboard adjustments. It can flexibly adapt to the component ratio requirements of different application scenarios. The overall architecture further improves the modular design, decoupling the easily changeable function of electronic power supply to a dedicated board, reducing system modification costs and maintenance difficulty. At the same time, it allows the motherboard to focus on core computing functions, optimizes motherboard design complexity and cost, and improves the reliability and adaptability of the entire machine.

[0061] In some embodiments of this application, such as Figure 4 As shown, the motherboard 20 is connected to the acceleration unit G1 via the first signal connector S1, and the motherboard 20 is connected to the sideband power board 30 via the second signal connector S2.

[0062] Specifically, the first signal connector S1 is used for communication between the motherboard 20 and the acceleration unit G1, focusing on high-speed data transmission requirements. Its function is to realize instruction interaction, data transmission, and status feedback between the motherboard 20 and the acceleration unit G1, ensuring that the acceleration unit G1 can accurately respond to the control commands of the motherboard 20, while simultaneously feeding back its own operating status to the motherboard 20 in real time, providing a basis for server computing power scheduling. The second signal connector S2 is used for communication between the motherboard 20 and the sideband power board 30, focusing on management signal interaction requirements. Its function is to receive various control signals and configuration signals issued by the motherboard 20, while transmitting feedback signals processed by the sideband power board 30, realizing collaborative work between the two and avoiding confusion between management signals and high-speed data signals.

[0063] The motherboard 20 communicates with the acceleration unit G1 via the first signal connector S1, reducing intermediate transfer links, lowering signal transmission delay and attenuation, ensuring data transmission efficiency when the acceleration unit G1 outputs high computing power, and meeting the server's adaptation requirements for high computing power scenarios. The motherboard 20 communicates with the sideband power board 30 via the second signal connector S2, centrally transmitting management signals related to power supply control and signal processing. This allows the sideband power board 30 to receive control commands from the motherboard 20 in a timely manner, adjust functions such as power conversion and signal processing, and simultaneously feed back the processing results to the motherboard 20, forming a closed-loop management system.

[0064] The first signal connector S1 can be an MCIO (Multi-Channel I / O Connector) connector, and the second signal connector S2 can be a SW MISC (Switch Miscellaneous) connector, a MISC FOR SW (Miscellaneous For Switch) connector, etc. The first signal connector S1 and the second signal connector S2 can be mounted on the motherboard 20.

[0065] This embodiment separates high-speed data signals and low-speed management signals through different connectors for transmission, avoiding interference between signals and improving the stability and reliability of signal transmission. It solves the problems of transmission errors and increased latency caused by traditional mixed signal transmission. The design of two signal connectors means that when the motherboard, acceleration unit, and sideband power board are upgraded or their configurations are adjusted, there is no need to modify the signal interfaces of other modules. Only the compatibility between themselves and their corresponding connectors needs to be ensured. This greatly improves the independent reusability of each module and the configuration flexibility of the whole machine. Moreover, the signal link is clearly divided. When a communication failure occurs, the link and module where the failure occurred can be quickly located, reducing the difficulty of troubleshooting and maintenance costs, and improving the maintainability of the server.

[0066] In some embodiments of this application, such as Figure 5 As shown, the motherboard 20 is connected to the fan module 50 via the third signal connector S3. The motherboard 20 obtains the first management signal from the fan module 50 via the third signal connector S3 and sends the first management signal to the sideband power board 30 via the second signal connector S2. The sideband power board 30 is used to process and output the first management signal.

[0067] Specifically, the third signal connector S3 is the interface for signal interaction between the motherboard 20 and the fan module 50. The third signal connector S3 can be an OTHER MISC connector and can be set on the motherboard 20. The third signal is the signal on the motherboard 20 that manages the fan node, including WDT (Watchdog Timer), I2C (Inter-Integrated Circuit) signal, fan board power-on enable signal, etc. The responsibility of the third signal connector S3 is to receive these fan management signals and realize the motherboard 20 to obtain the status of the fan module 50 and issue commands.

[0068] The fan module 50 includes a fan and related control components. It is the core execution unit for server heat dissipation. The fan module 50 needs to dynamically adjust its speed according to the server's power consumption and temperature status. Its status feedback and control command transmission depend on signal interaction with the motherboard 20 and the side power board 30.

[0069] The motherboard 20 obtains the first management signal from the fan module 50 through the third signal connector S3. This signal is a fan status signal, such as speed feedback, fault alarm, and temperature monitoring signal. As the core of temperature acquisition and heat dissipation execution, the fan module 50 outputs the first management signal, which provides a key basis for adjusting the server's heat dissipation strategy. The motherboard 20 obtains these signals in real time through the third signal connector S3 to ensure accurate control over the fan's operating status.

[0070] After the motherboard 20 receives the first management signal, it forwards it to the sideband power board 30 via the second signal connector S2. The sideband power board 30 performs logical analysis, filtering, and conversion on the first management signal. For example, when the motherboard 20 is in standby mode, the sideband power board 30 can adjust the fan speed to a low-power mode based on the temperature data in the first management signal. When the motherboard 20 is in operation and the load increases, it can trigger the fan speed to increase, achieving a dynamic balance between heat dissipation and power consumption.

[0071] After processing the first management signal, the sideband power board 30 outputs control commands, such as speed adjustment signals and power-on enable signals, and feeds them back to the fan module 50 through the corresponding signal channels, driving the fan module 50 to perform the corresponding operations. At the same time, the sideband power board 30 transmits the processing results back to the main board through the second signal connector S2, forming a closed-loop management of status acquisition, signal processing, command execution, and result feedback, ensuring that the main board 20 can monitor the fan's operating status in real time and respond promptly to abnormal situations.

[0072] This embodiment achieves signal interaction between the motherboard and the fan module through a third signal connector. The second signal connector, in conjunction with the third signal connector, transmits the first management signal to the sideband power board for centralized processing. This physically isolates the fan management signal from other system signals, avoiding signal interference and improving the stability and reliability of signal transmission. The logic processing design of the sideband power board for the first management signal allows the fan operating state to be dynamically adjusted according to system conditions, optimizing heat dissipation and ensuring stable server operation under different loads. By separating the fan management signal processing function from the motherboard, there is no need to modify the motherboard design due to adjustments in heat dissipation strategies or replacement of fan modules. This improves the reusability of the motherboard and the configuration flexibility of the system, while simplifying the system troubleshooting process and reducing maintenance costs.

[0073] In some embodiments of this application, such as Figure 6 As shown, the motherboard 20 is communicatively connected to the electronic component module 70 through the fourth signal connector S4. The motherboard 20 obtains the second management signal from the electronic component module 70 through the fourth signal connector S4 and sends the second management signal to the sideband power board 30 through the second signal connector S2. The sideband power board 30 is used to process and output the second management signal.

[0074] Specifically, the fourth signal connector S4 is the interface for signal interaction between the motherboard 20 and the electronic component module 70. Examples include the I2C connector connecting the hard drive backplane, the I2C connector connecting the PAD CARD (function expansion board), the motherboard's temperature sensor connector, and the IO MISC (Input / Output Miscellaneous) connector. The fourth signal includes VGA (Video Graphics Array) signals, UART (Universal Asynchronous Receiver / Transmitter) signals, light signals, NCSI (Network Controller Sideband Interface) signals, and OCP (Open Compute Project) button signals. The responsibility of the fourth signal connector S4 is to receive these electronic component-related signals, enabling the motherboard 20 to acquire the status of the electronic components and issue commands, while simultaneously preventing cable crossings within the computing node. The fourth signal connector S4 can be located on the motherboard 20.

[0075] Electronic Component Module 70 includes replaceable components such as an RDMA (Remote Direct Memory Access) network card, an NVME (Non-Volatile Memory Express) hard drive, an OCP network card, and a DPU (Data Processing Unit). It is the core module for the AI ​​server to achieve data interaction and expand its functions. Electronic Component Module 70 is designed as a replaceable module; the network card and the OCP-type DPU can be replaced to meet different customer configuration requirements. Its status feedback and configuration recognition signals interact with the motherboard and sideband power board through channels, ensuring configuration flexibility and system stability.

[0076] The motherboard 20 obtains the second management signal from the electronic component module 70 through the fourth signal connector S4. This signal is the status signal of the electronic component module 70, such as the network card working status, hard disk read / write status, DPU configuration information, and power supply feedback signal. As a key unit for server external interaction, the second management signal output by the electronic component module 70 provides crucial information for resource scheduling and configuration adaptation. The motherboard 20 obtains these signals in real time through the fourth signal connector S4 to ensure accurate control over the operating status of the electronic component module 70.

[0077] After the motherboard 20 obtains the second management signal, it forwards it to the sideband power board 30 through the second signal connector S2. The sideband power board 30 receives the second management signal and performs logic analysis, filtering and conversion. For example, when the customer changes the DPU model or adjusts the network card configuration, the sideband power board 30 can process the configuration identification information in the second management signal and adapt to the corresponding power supply logic and data transmission protocol without modifying the design of the motherboard 20. For the fault alarm signal of the electronic component module 70, the sideband power board 30 can quickly forward it to the motherboard 20 to trigger the alarm mechanism.

[0078] After processing the second management signal, the sideband power board 30 outputs control commands, such as component power-on enable and speed adjustment signals, and feeds them back to the electronic component module 70 through the corresponding signal channel, driving the electronic component module 70 to perform the corresponding operations. At the same time, the sideband power board 30 transmits the processing results back to the main board 20 through the second signal connector S2, forming a closed-loop management system. This ensures that the main board 20 can monitor the operating status of the electronic component module 70 in real time and respond promptly to configuration changes or malfunctions.

[0079] This embodiment achieves signal interaction between the motherboard and electronic component modules through a fourth signal connector. In conjunction with the second signal connector, the second management signal is transmitted to the sideband power board for centralized processing. This effectively isolates the electronic component management signal from other system signals, avoiding signal interference and improving the stability and reliability of signal transmission. The logic processing design of the sideband power board for the second management signal allows configuration changes and status monitoring of electronic components to be adapted to different component ratios without relying on motherboard modifications. This significantly improves the system's configuration flexibility and motherboard reusability. The clear division of labor in the signal links simplifies the troubleshooting process for electronic component-related faults, reduces system maintenance costs, and allows the motherboard to focus on core computing functions, optimizing motherboard design complexity and further improving the stability and adaptability of server operation.

[0080] In some embodiments of this application, such as Figure 7 As shown, the server power supply board 12 and the power adapter board 40 are connected by a first blind mating connector B1 and a first guide structure blind mating A1. The first blind mating connector B1 includes a computing node blind mating connector B11 and a fifth signal connector S5.

[0081] Specifically, the first blind-mating connector B1 is a component that enables blind-mating connection between the server power supply board 12 and the power adapter board 40. The first blind-mating connector B1's function is to achieve reliable power and signal connection without precise alignment through an orthogonal mating design, adapting to the assembly requirements of the server's drawer-type structure. The first blind-mating connector B1 can be a computing node blind-mating connector, miscellaneous connector, etc. The first guide structure blind-mating A1 is a guiding auxiliary mechanism in the blind-mating design, used to guide the first blind-mating connector B1 to precise alignment during the blind-mating process, avoiding misalignment, jamming, or damage during insertion and removal. Mechanical guidance ensures smooth and stable blind-mating, improving assembly efficiency and connection reliability. The first blind-mating connector B1 and the first guide structure blind-mating A1 can be mounted on the server power supply board 12.

[0082] The compute node blind-mating connector B11 is a power transmission sub-component of the first blind-mating connector B1, used to transmit 54V high-voltage power. Its design meets the current-carrying requirements of a 54V power supply architecture, adopts a universal blind-mating power connector specification, and meets the overall 300A current-carrying requirement of the server, avoiding the high cost of custom copper busbars required for 12V power supply architectures. The fifth signal connector S5 is a signal transmission sub-component of the first blind-mating connector B1, used to transmit power status monitoring signals, including a total of forty signals such as AC_OK (AC power normal signal), PWR_OK (power output normal signal), ALERT (alarm signal), and PRSNT (present signal). The fifth signal connector S5 is the transmission channel for these signals, enabling status monitoring of 40 pairs of power supplies on the power adapter board.

[0083] The server power supply board 12 and the power adapter board 40 achieve orthogonal blind mating through the first blind mating connector B1, that is, the connection direction of the two is perpendicular insertion and removal, in order to adapt to the spatial layout of the server chassis, so that the computing node can be directly inserted into the chassis like a drawer, without the need for additional cable adjustment or interface alignment, simplifying the assembly process and improving maintenance convenience.

[0084] Through the computing node blind-mating connector B11 in the first blind-mating connector B1, the server power supply board 12 transmits the centralized 54V DC power to the power adapter board 40. Through the fifth signal connector S5 in the first blind-mating connector B1, the power adapter board 40 obtains power status information from the server power supply board 12. The fifth signal connector S5 serves as a signal channel, physically isolating low-speed monitoring signals from high-voltage power supply signals to avoid signal interference and ensure the accuracy of power status monitoring.

[0085] This embodiment achieves blind-mating connection between the server power supply board and the power adapter board through the cooperation of the first blind-mating connector and the first guiding structure. Assembly can be completed without precise alignment, which greatly improves the convenience of installation and maintenance. The first blind-mating connector is split into a computing node blind-mating connector and a fifth signal connector, which realizes physical isolation between power transmission and signal transmission, avoids mutual interference between the two, and improves power supply stability and signal transmission reliability. The blind-mating design is compatible with the modular architecture of the server, so that the replacement of the power adapter board and the server power supply board does not require modification of other modules, which improves component reusability and system configuration flexibility. The fifth signal connector provides a channel for power status monitoring, which helps the power adapter board to obtain and feedback the working status of multiple power supplies in real time, providing data support for system power supply redundancy protection and further enhancing the reliability of server operation.

[0086] In some embodiments of this application, there are multiple power supplies 11 connected in parallel. The multiple power supplies are connected to the server power supply board 12 after being connected in parallel. The power adapter board 40 is used to obtain the status information of the multiple power supplies through the fifth signal connector S5 and monitor the multiple power supplies according to the status information.

[0087] Specifically, there can be multiple power supplies 11, connected in parallel to the server power supply board 12. The purpose is to integrate all the server's power supplies onto a single board, achieving N+N power redundancy. This ensures that even if some power supplies fail, the server can still maintain stable power supply through the redundant power supplies, meeting the server's high power consumption and high reliability requirements. For example, with ten 3.2KW 54V power supplies connected in parallel, the system can supply a maximum of 32KW, sufficient to meet the high power consumption requirements of a 16-GPU server.

[0088] After acquiring the status information of multiple power supplies through the fifth signal connector S5, the power adapter board 40 monitors these power supplies in real time according to preset rules. For example, when an abnormal AC_OK or PWR_OK signal of a power supply is detected, the faulty power supply can be quickly identified and fed back to the main board, triggering an alarm mechanism. Simultaneously, due to the parallel power supply design, the system power supply is unaffected by the faulty power supply, ensuring business continuity. Furthermore, by monitoring the PRSNT signal, the power adapter board can identify whether a power supply is present, providing a basis for system resource scheduling and maintenance. The fifth signal connector S5 can be a miscellaneous connector and can be installed on the power adapter board 40.

[0089] It should be noted that the parallel connection between multiple power supplies described in this embodiment can be achieved by connecting the power input ports of multiple power supplies to an external power supply, and connecting the power output ports of multiple power supplies to the server power supply board 12, thereby realizing the parallel connection between multiple power supplies. Furthermore, the purpose of connecting multiple power supplies to the server power supply board 12 is to design all the power supplies of the entire server onto a single board, which can achieve N+N power supply redundancy. This ensures that even if some power supplies fail, the server can still maintain a stable power supply through the redundant power supplies, meeting the server's high power consumption and high reliability requirements.

[0090] This embodiment improves the system's power supply capacity and redundancy by configuring multiple power supplies in parallel, ensuring stable power supply even when some power supplies fail. This significantly enhances the server's operational reliability under high load scenarios. The power adapter board acquires the status information of multiple power supplies in real time through the fifth signal connector, enabling precise monitoring of the power supply's operating status. This facilitates timely detection and response to power supply anomalies, reducing the risk of system downtime. This design, which combines centralized monitoring with redundant power supply, optimizes the allocation efficiency of power resources and simplifies the power supply maintenance process. It allows the server to better adapt to the application requirements of high power consumption and high reliability, while also improving the overall maintainability and stability of the system.

[0091] In some embodiments of this application, the first signal connector S1 and the second signal connector S2 include multiple pins, wherein the multiple pins are defined according to a preset pin design strategy.

[0092] Specifically, the first signal connector S1 can adopt an MCIO (Multi-Channel I / O Connector) connector, designed according to fixed pin definitions. After the pin definitions of the first signal connector S1 are standardized, it can be compatible with acceleration units G1 of different specifications and platforms without modifying the motherboard interface design. The first signal connector S1 includes multiple pins, which are defined according to a preset pin design strategy. Here, we take the use of an MCIO connector and standard pin definitions as an example for explanation.

[0093] like Figure 8The diagram shows the pinout of a multi-channel input / output connector. The Peripheral Component Interconnect (PCIe) pin is a high-speed signal connecting to a PCIe (PCI Express) device or a PCIe switch chip. The Reference Clock signal (PCIe CLK) pin is the reference clock signal for the PCIe high-speed signal. The Reset signal (PERST0 / 1) pin is a reset signal connecting to a PCIe device or a PCIe SW (PCI Express Switch) chip. The Wake signal (WAKE) pin is a wake-up signal that allows the device to wake up the host. The Throttle pin is used for system hot-triggering, causing the device to downclock. The Server Message Block (S-motherboard) pin is used to access the Server Message Block (S-motherboard_PEHP) device. The Hot-plug signal (S-motherboard_PEHP) pin is used for hot-plugging PCIe devices. The Universal Serial Bus (USB 2.0) pin is for OAM (Orbital Angular Bus). The GPU's management signals are in the form of Momentum (or orbital angular momentum). The warning signal (ALERT pin) is a system warning signal, and the device model (MCIO ID pin) is used to distinguish the current PCIe device model.

[0094] The second signal connector S2 can be either a SW MISC (Switch Miscellaneous) connector or an OTHER MISC connector. Standardized pin definitions ensure stable and reliable signal interaction between the motherboard and the sideband power board, preventing logic processing errors caused by inconsistent signal definitions. The pre-defined pin design strategy is based on functional classification and fixed allocation, dividing the connector's multiple pins according to signal type, with each pin corresponding to a unique signal transmission function.

[0095] Taking the second signal connector S2, which uses the SW MISC connector and standard pin definitions, as an example, the SW MISC connector includes the following signals: STBY_EN is the STBY (Standby) power enable signal on the GPU node; MAIN_EN is the MAIN (master) power enable signal on the GPU node; STBY_PG is the STBY power-on completion signal on the GPU node; MAIN_PG is the master power-on completion signal on the GPU node; S motherboard is the slave device connected to the GPU node via the S motherboard bus; UART is the CPLD (Complex Programmable Logic Device) serial port on the SW (Switch) board; UARTFOR SW (Universal Asynchronous Receiver / Transmitter for Switch) is the serial port signal of the SW chip within the GPU node; SW_FW_TYPE (Switch FirmwareType) is the firmware information that identifies which configuration the SW should load; SKU_ID[3:0] (StockKeeping Unit Identifier) [3:0], 4-bit inventory unit identifier) ​​identifies the current SW chip configuration and supplier. ACS (Access Control Services) is used to set the GPU access link. When this signal is enabled, GPU access to GPU uses the CPU (Central Processing Unit) interconnect bus. When ACS is disabled, GPU access to GPU uses the PCIE link between PCIE SW chips. LEAKAGE is the leakage detection signal in liquid cooling configuration. SW_CLK_EN (Switch Clock Enable) is the enable signal for non-same-source clocks. RSVD is the reserved GPIO (General Purpose Input / Output) for connecting the motherboard and GPU node switch board. Motherboard_Type [2:0] is a signal to distinguish the motherboard type.

[0096] In addition, the preset pin design strategy can be set by those skilled in the art according to the actual situation, and no specific restrictions are imposed here.

[0097] This embodiment defines multiple pins of the first and second signal connectors separately through a preset pin design strategy, realizing clear division and standardization of pin functions. This avoids transmission failures caused by mixing or misconnecting different signals, improves the accuracy and stability of signal transmission, and the standardized pin definition makes the first and second signal connectors form a unified interface standard. This allows the motherboard to interface with the acceleration unit and sideband power board without modifying the interface design due to changes in component specifications or configurations, greatly improving the independent reusability of each module and the configuration flexibility of the whole machine.

[0098] In some embodiments of this application, such as Figure 9 As shown, the side power board 30 and the main board 20 are connected by a second blind-mating connector B2 and a second guide structure blind-mating A2. The second blind-mating connector B2 includes a high-density connector B21.

[0099] Specifically, the second blind-mating connector B2 is a blind-mating interface adapted for signal transmission between the motherboard 20 and the side power board 30. Its function is to achieve reliable connection of various signal types between the motherboard 20 and the side power board 30 through an orthogonal mating design, without requiring precise alignment, thus meeting the assembly and maintenance needs of the server's drawer-type structure. The second guide structure blind mating A2 is an auxiliary guiding mechanism in the blind-mating design, used to guide the second blind-mating connector B2 to precise alignment during the blind mating process. The high-density connector B21 is a core signal transmission sub-component of the second blind-mating connector B2, used to carry high-density signals between the motherboard 20 and the side power board 30. These high-density signals include dozens of management signals and high-speed feedback signals. The second blind-mating connector B2 and the second guide structure blind mating A2 can be located on the side power board 30.

[0100] The sideband power board 30 and the main board 20 are orthogonally blind-mating via the second blind-mating connector B2, meaning their connection direction is perpendicular. The high-density connector B21, as the core of the second blind-mating connector B2, undertakes various signal transmission tasks processed by the sideband power board 30. Its high-density pin design ensures parallel transmission of multiple signal types, avoiding signal confusion or delay.

[0101] During blind mating, the second guide structure blind mating A2 contacts the second blind mating connector B2 first, and guides the side power board and the main board to be precisely aligned through a preset mechanical guide path, ensuring that each set of signal pins can be accurately connected, improving connection reliability and component lifespan.

[0102] This embodiment achieves blind mating connection between the sideband power board and the motherboard through the cooperation of the second blind mating connector and the second guide structure. Assembly can be completed without precise alignment, which improves the convenience of server installation and maintenance. The high-density connector in the second blind mating connector can meet the parallel transmission requirements of high-density signals between the motherboard and the sideband power board, avoid signal congestion or interference, and improve the stability and integrity of signal transmission.

[0103] In some embodiments of this application, such as Figure 10 As shown, the sideband power board 30 is provided with a first signal manager D1 and a sixth signal connector S6. The sideband power board 30 receives the third management signal from the motherboard 20 through the sixth signal connector S6, analyzes and processes the third management signal through the first signal manager D1 to obtain the target signal, and sends the target signal to the motherboard through the high-density connector.

[0104] Specifically, the first signal manager D1 is the core component of the sideband power board 30 for signal analysis, processing and conversion. It can be a CPLD (Complex Programmable Logic Device). The responsibility of the first signal manager D1 is to receive the third management signals sent by the motherboard 20, and to analyze, enhance or convert them through preset logic to adapt to different configuration requirements and avoid the need to modify the motherboard 20 due to changes in signal processing requirements.

[0105] The sixth signal connector S6 is the interface for transmitting third management signals between the sideband power board 30 and the main board 20. It can use a miscellaneous connector on the switchable daughter board. The sixth signal connector S6 receives various signals related to the management of the acceleration unit G1 issued by the main board 20, ensuring the independence and stability of signal transmission.

[0106] The third management signal can be the SW MISC signal, including STBY_EN (GPU node standby power enable signal), MAIN_EN (GPU node main power enable signal), SW motherboard (bus signal), UART (CPLD serial port signal), SW_FW_TYPE (SW firmware configuration identification signal), SKU_ID [3:0] (SW chip configuration identification signal), etc. These signals are the key basis for the motherboard 20 to manage and configure the GPU nodes.

[0107] The motherboard 20 sends the third management signal to the sideband power board 30 via the sixth signal connector S6. During signal transmission, the signal relies on the channel of the sixth signal connector S6 to avoid confusion with other signals. The first signal manager D1 receives the third management signal and analyzes and processes it according to preset logic. For example, if the signal provided by the motherboard only supports connecting one layer of GPU nodes, the CPLD can double the signal to support two layers of GPU nodes. Signals only needed for configuration identification are directly forwarded to the corresponding module. Signals requiring adaptation to different SW chips are flexibly configured through logic adjustments to achieve flexible GPU access link configuration. The resulting target signal meets the current system configuration requirements without requiring modifications to the motherboard design.

[0108] The first signal manager D1 feeds back the processed target signal to the motherboard 20 via the high-density connector B21. The high-density pin design of the high-density connector B21 ensures parallel transmission of multiple types of target signals. For example, it synchronously transmits processed GPU node power-on completion signals and SW chip initialization status signals back to the motherboard, forming a closed-loop management system. Simultaneously, the blind-mating characteristic of the high-density connector ensures that the signal feedback process is synchronized with the blind-mating connection of the sideband power board and the motherboard, without affecting assembly efficiency.

[0109] This embodiment receives the third management signal from the motherboard through the sixth signal connector, analyzes and processes it with the first signal manager to generate the target signal, and feeds it back to the motherboard through the high-density connector. This achieves precise processing and efficient transmission of the third management signal, avoiding the adaptation problems that may occur with direct signal transmission. The centralized processing design of the first signal manager means that the adaptation and adjustment of the third management signal does not require modification of the motherboard. Different system configuration requirements can be met simply by adjusting the processing logic of the signal manager, which greatly improves the system's configuration flexibility and motherboard reusability. The signal processing function is separated from the motherboard to the side power board, reducing the complexity of the motherboard design and allowing the motherboard to focus on core computing functions, thereby improving the system's maintainability and operational reliability.

[0110] In some embodiments of this application, the sixth signal connector S6 is provided with a spare signal pin, which is used for communication connection between the second signal manager and the first signal manager D1 on the motherboard 20.

[0111] Specifically, the spare signal pin is an additional signal transmission pin on the sixth signal connector S6, serving as a backup communication channel. For example, when the sixth signal connector S6 uses a switch miscellaneous connector, it enables direct communication between the motherboard 20 and the signal manager of the sideband power board 30 without GPIO, ensuring redundancy and scalability of signal interaction. For instance, when the motherboard 20 needs to issue a new GPU node configuration command to the sideband power board 30, or when the sideband power board 30 needs to report a signal processing anomaly alarm to the motherboard 20, there is no need to modify the hardware interface design of the motherboard 20 or the sideband power board 30; the new communication requirements can be met simply by expanding the registers of the spare signal pin.

[0112] The second signal manager is the core component of signal management on the motherboard 20 side. It can be a CPLD, responsible for issuing management signals, receiving feedback signals, and establishing communication with the first signal manager D1 through the spare signal pin to ensure signal coordination between the motherboard 20 and the side power board 30.

[0113] The spare signal pin directly enables communication between the second signal manager D2 on the motherboard 20 and the first signal manager D1 on the side power board 30. This connection can use the SGPIO (Serial Universal Input / Output) bus protocol, which is suitable for the transmission requirements of low-speed management signals. It can realize the serial transmission of multiple signals in a single pin or a group of pins, saving pin resources while ensuring communication stability. Furthermore, the communication of the spare signal pin and the main signal transmission of the sixth signal connector S6 complement each other, ensuring the integrity and reliability of signal interaction and preventing the failure to transmit critical information due to main channel occupancy or failure.

[0114] This embodiment establishes a communication channel between the motherboard's second signal manager and the sideband power board's first signal manager by setting a spare signal pin on the sixth signal connector. This compensates for the lack of a communication interface, improves the redundancy and flexibility of signal interaction, and allows the spare signal pin to meet new communication needs without modifying the hardware interface. It does not require changes to the interface design of the motherboard or sideband power board, and information transmission can be completed simply by expanding the registers, reducing modification costs and R&D workload.

[0115] In some embodiments of this application, such as Figure 11 As shown, the sideband power board 30 is provided with a seventh signal connector S7. The sideband power board 30 is communicatively connected to the input / output power supply board 60 through the seventh signal connector S7. The sideband power board 30 obtains the power supply logic information of the input / output power supply board 60 through the seventh signal connector S7, and processes and outputs the power supply logic information.

[0116] Specifically, the seventh signal connector S7 is the interface for signal interaction between the sideband power board 30 and the input / output power supply board 60. It can be a MISC FOR IO connector. The function of the seventh signal connector S7 is to receive the power supply logic information of the input / output power supply board 60 and transmit the control signals processed by the sideband power board 30 to ensure that the two work together.

[0117] The input / output power supply board 60 is used to power the electronic component module 70. Its power supply logic needs to be dynamically adjusted according to the configuration of the electronic components, therefore it needs to interact with the sideband power supply board 30. The power supply logic information refers to the power-on enable signal of the input / output power supply board 60, the power consumption and temperature data of the power supply module, and the power supply status signals of the components.

[0118] The input / output power supply board 60 transmits its power supply logic information to the sideband power supply board 30 via the seventh signal connector S7. After receiving the power supply logic information, the sideband power supply board 30 performs centralized analysis and processing by the first signal manager D1 on the board. For example, it adjusts the power-on enable sequence based on the configuration of electronic components (such as whether a DPU is inserted, the number of hard drives), ensuring that components power on in an orderly manner according to the PCIe specification. Alternatively, it determines whether the power supply load is balanced based on the power consumption and temperature data of the power supply blocks. If a power supply block has an excessively high load, it can trigger adjustment logic to prevent overload damage. After processing the power supply logic information, the sideband power supply board 30 outputs control commands via the seventh signal connector S7 to drive the input / output power supply board 60 to perform corresponding operations.

[0119] This embodiment establishes a communication channel between the sideband power board and the input / output power supply board through the seventh signal connector, realizing independent transmission and centralized processing of power supply logic information. This avoids interference caused by mixed transmission with other signals, improves the stability and accuracy of signal transmission, and this centralized management mode allows the power supply status of electronic components to be monitored in real time. This facilitates timely detection of overload, abnormal power supply and other problems and rapid response, reduces the risk of power supply failure and improves the reliability of power supply to electronic components.

[0120] In some embodiments of this application, such as Figure 12 As shown, the input / output power supply board 60 is provided with a second conversion module M2, which is used to convert the node current output by the power adapter board 40 into the target component current, so as to supply power to at least one component in the electronic component module 70.

[0121] Specifically, the second conversion module M2 is the core component on the input / output power supply board 60 for voltage conversion. It can be a power supply brick. When the system uses a 54V power supply architecture, the second conversion module M2 needs to convert 54V to 12V to power the electronic components and provide them with a suitable operating voltage.

[0122] After the input / output power supply board 60 obtains 54V node current through the power adapter board 40, the second conversion module M2 converts it into 12V target component current. The converted target component current is used to power at least one component in the electronic component module 70, including RDMA network cards, NVME hard drives, OCP network cards, DPU devices, etc., all of which obtain power through the target component current.

[0123] The power supply of the second conversion module M2 works in tandem with the logic control of the sideband power board 30. The sideband power board 30 sends a power-on enable signal to the input / output power supply board 60 through the seventh signal connector S7. The second conversion module M2 only starts voltage conversion and outputs the target component current after receiving the enable signal, ensuring that the electronic components are powered on according to the preset timing, avoiding component damage caused by instantaneous current surges. At the same time, it works with the sideband power board to realize real-time monitoring of the power supply status.

[0124] This embodiment converts the node current output by the power adapter board into the target component current adapted to the electronic components through the second conversion module on the input / output power supply board. This achieves independent and customized power supply for electronic components, avoiding the voltage compatibility limitations caused by relying on the motherboard power supply. The target component current can accurately match the power supply requirements of different electronic components, improving the compatibility and reliability of the power supply for electronic components. This modular power supply design allows the power supply adjustment of electronic components to be adapted to new or replaced components without modifying the motherboard. This improves the system configuration flexibility and scalability.

[0125] In some embodiments of this application, the input / output power supply board 60 is provided with a component power supply connector and a fuse. One end of the fuse is connected to the second conversion module M2, and the other end of the fuse is connected to the component power supply connector.

[0126] Specifically, the component power supply connector is the interface through which the input / output power supply board 60 supplies power to electronic components. It can use connectors such as HD PWR (Hard Disk Power), DPU PWR (Data Processing Unit Power), SLOT PWR (Slot Power), PCIE PWR (PCI Express Power), and M.2 PWR (M.2 Power). The responsibility of the component power supply connector is to provide a precise power supply interface for electronic components such as RDMA network cards, NVMe hard drives, OCP network cards, DPUs, and M.2 devices, ensuring the targeted and reliable transmission of power.

[0127] The fuse is an overcurrent protection component connected in series between the second conversion module M2 and the component power supply connector. It can be an electronic fuse. Its function is to monitor the power supply current in real time and automatically cut off the power supply when the current exceeds the preset threshold, so as to avoid power supply failure or component damage caused by component short circuit or overload.

[0128] The second conversion module M2 converts the 54V to 12V target component current. The current first flows through a fuse, then is transmitted to the corresponding electronic component via the component power supply connector. The fuse has a preset current threshold matched to the power consumption of the corresponding component and monitors the current flow in real time. When an electronic component experiences a short circuit, overload, or other abnormal condition causing the current to exceed the limit, the fuse quickly disconnects the power supply link to prevent excessive current from damaging the component or affecting the normal operation of other power supply links. The component power supply connector is designed according to the power supply interface specifications of different electronic components, such as an HD PWR connector for hard drives and a DPUPWR connector for DPUs.

[0129] This embodiment achieves precise power transmission and overcurrent protection for electronic components through the series design of fuses and component power supply connectors. The fuses can quickly disconnect the power supply link when the current exceeds the limit, avoiding equipment damage or power supply failure caused by component short circuits or overloads, and greatly improving the safety and reliability of power supply for electronic components.

[0130] In some embodiments of this application, a first bus is connected to the third signal connector S3 and the sixth signal connector S6, wherein the first bus includes the remaining circuit bus after access wiring to the bus devices on the motherboard 20.

[0131] Specifically, the first bus is the redundant bus resource that is not occupied after the motherboard 20 has completed the access wiring of its own fixed bus devices (such as CPU VR, sensors, FRU, etc.). The responsibility of the first bus is to realize the reuse of redundant resources through signal connectors and provide a channel for extended signal transmission.

[0132] When the motherboard 20 accesses and routes its own bus devices, it allocates bus resources according to the principle of priority for fixed devices. After the connection of fixed devices is completed, the unused bus becomes the first bus. The first bus is connected to the third signal connector S3 and the sixth signal connector S6 respectively, realizing dual reuse. On the one hand, through the third signal connector S3, the first bus can transmit the extended management signals of the fan module, supplementing the transmission of core management signals; on the other hand, through the sixth signal connector S6, the first bus can transmit the configuration extension signals of the GPU node, without the need for additional bus routing on the motherboard.

[0133] This embodiment fully utilizes the idle bus resources after the motherboard accesses the bus device by connecting the first bus to the third and sixth signal connectors, thus avoiding the waste of bus resources and improving resource utilization.

[0134] In some embodiments of this application, the motherboard 20 is provided with an expansion module, wherein the expansion module includes at least one network card interface, and the network card interface includes a network controller sideband interface.

[0135] Specifically, the expansion module includes at least one network card interface, supporting the insertion of various network cards. It is a hardware module on the motherboard 20 used to adapt to the insertion of various network cards. The expansion module's responsibility is to meet diverse customer network configuration needs by using a standardized interface to ensure compatibility with different types and specifications of network cards. The expansion module includes a network controller sideband interface, which connects standard OCP network cards or PCIe form factor DPUs. It serves as a communication channel between the network card and the motherboard 20, ensuring stable network signal transmission and supporting plug-and-play functionality for different network cards. The various network cards include RDMA network cards, OCP network cards, and PCIe network cards.

[0136] The network interface design follows a unified standard. Whether it's an RDMA, OCP, or PCIe network card, all interfaces with expansion modules via standardized interfaces, allowing for replacement of different network cards without modifying the motherboard hardware design. The network controller's sideband interface provides a communication channel for the network cards, ensuring independent transmission of network management and data signals. The expansion module supports the simultaneous insertion of multiple network cards of different types, and each network card operates independently without affecting the others.

[0137] The expansion module of this embodiment includes at least one network card interface, which can support the insertion of multiple network cards. Combined with the network controller sideband interface, it greatly improves the flexibility and compatibility of server network configuration. It can adapt to different types and specifications of network cards without modifying the core design of the motherboard, meeting the network needs of the server in different application scenarios and improving the server's scenario adaptability.

[0138] In some embodiments of this application, by Figure 13 As shown, the server also includes: a management board 80, a first ear-mount card E1 and a second ear-mount card E2, wherein the management board 80 is vertically connected to the motherboard 20 via a vertical connector V1, and the first ear-mount card E1 and the second ear-mount card E2 are respectively connected to the fourth signal connector S4.

[0139] Specifically, the management board 80 is the core management component of the server, responsible for overall system status monitoring, command issuance, and signal interaction. It can utilize a V-DCSCM module, which saves significantly more space compared to the original horizontal DCSCM architecture. The management board 80's role is to interface with the motherboard 20 via the vertical connector V1, achieving efficient management while saving space.

[0140] The vertical connector V1 is an interface component that enables the vertical connection between the management board 80 and the motherboard 20. The design of the vertical connector V1 is adapted to the vertical installation method, ensuring stable signal and power transmission between the management board 80 and the motherboard 20, while also meeting the space layout requirements of the server chassis.

[0141] The first ear-mount board E1 and the second ear-mount board E2 are auxiliary boards used to enhance the connection stability of the fourth signal connector S4. The function of the ear-mount board is to fix the fourth signal connector S4, reduce poor signal contact during insertion and removal, and at the same time help to organize the signal cables of electronic components.

[0142] The management board 80 is vertically installed to the motherboard 20 via the vertical connector V1, with the connection direction being perpendicular. Compared to the traditional horizontal installation method, this connection method can significantly save internal server space, especially suitable for the drawer-style structure of 16-GPU servers, allowing more core components to be accommodated inside the chassis and increasing the computing density per unit space. At the same time, the standardized interface design of the vertical connector ensures stable power and management signal transmission between the management board and the motherboard, avoiding signal attenuation caused by the installation method.

[0143] The first ear-mount plate E1 and the second ear-mount plate E2 are respectively connected to the fourth signal connector S4, fixing and reinforcing the connector from both sides. The ear-mount plates reduce the shaking of the connector during insertion, removal, and transportation through mechanical fixation, avoiding poor contact of the signal pins. At the same time, the ear-mount plates can help organize the cable routing, further preventing cross-interference between electronic components and cables from other modules.

[0144] In this embodiment, the management board is vertically connected to the motherboard via a vertical connector, which significantly saves internal server space compared to the traditional horizontal installation method, improves component integration and computing density per unit space, and adapts to the compact layout requirements of servers. The connection design between the first and second mounting tabs and the fourth signal connector effectively strengthens the installation stability of the connector, reduces poor signal contact caused by plugging or unplugging or vibration, and ensures the reliability of the second management signal transmission of electronic components.

[0145] In some embodiments of this application, the power supply module 10 and the fan module 50 are respectively disposed on one side of the server 100 chassis, wherein one side of the power supply module 10 and one side of the fan module 50 respectively abut against the rear panel of the server chassis, the power adapter board 40 is disposed adjacent to the other side of the power supply module 10, and the side power board 30 is adjacent to the other side of the fan module 50.

[0146] Specifically, both the power supply module 10 and the fan module 50 are positioned on one side of the server chassis rear panel, forming a centralized rear layout. This avoids the modules occupying front or middle space, reserving ample installation space for the electronic component module 70 and the motherboard 20, thus improving component integration within a given space. The power adapter board 40 is positioned adjacent to the other side of the power supply module 10, specifically between the power supply module 10 and the side power board 30. This close-proximity layout shortens the 54V high-voltage power supply link, reducing voltage loss and heat generation during transmission.

[0147] The sideband power board 30 is located on the other side of the fan module 50, between the fan module 50 and the motherboard 20. The airflow generated by the fan module 50 can flow directly through the sideband power board 30, effectively removing the heat generated during voltage conversion and signal processing. At the same time, the proximity of the sideband power board 30 to the motherboard 20 shortens the signal transmission link, reduces signal attenuation, and ensures stable transmission of management and data signals.

[0148] This embodiment centrally positions the power supply module and fan module on one side of the server chassis, abutting against the rear panel. The power adapter board and side power board are respectively positioned adjacent to the power supply module and the fan module on the other side, achieving a compact arrangement of core modules. This significantly improves the utilization of internal server space and reserves more installation space for electronic component modules, motherboards, etc. The design of the power adapter board adjacent to the power supply module shortens the power supply link, reduces power loss during power transmission, and improves power supply efficiency. The layout of the side power board adjacent to the fan module allows the cooling airflow to directly act on the side power board and surrounding core components, avoiding local overheating and improving the uniformity and reliability of overall heat dissipation.

[0149] In some embodiments of this application, the server 100 further includes: an air guide, one side of which abuts against the other side of the server housing, and the other side of which is adjacent to the power adapter board 40, wherein one side of the server housing and the other side of the server housing are perpendicular to each other; the air guide has openings at both ends, one end of which is connected to the air inlet of the power supply module 10, wherein the opening at one end of the air guide is larger than the opening at the other end of the air guide.

[0150] Specifically, the air guide is an airflow guiding component designed for the power supply module 10. Its function is to guide external cold air into the power supply module 10 in a directional manner, avoiding interference with the airflow of the fan module 50. The air guide is a hollow structure with openings at both ends, and one end is larger than the other, which can increase the airflow speed and air pressure entering the power supply module, ensuring that the cold air can fully cover all power supplies, solving the problem of uneven heat dissipation caused by airflow dispersion in traditional heat dissipation. At the same time, one side of the air guide abuts against the other side of the server chassis, and the other side is adjacent to the power adapter board. Its installation position avoids the core computing area and signal transmission links, avoiding interference with other modules. One end of the air guide is connected to the air inlet of the power supply module 10, and the other end faces the outside of the server, forming an independent airflow channel. This can prevent the airflow of the fan module and the airflow of the power supply module from affecting each other, prevent hot airflow from flowing back to the air inlet of the power supply module, and ensure that the power supply module always draws in low-temperature cold air.

[0151] This embodiment constructs an independent air duct for the power supply module by setting an air guide with openings at both ends, one of which is larger than the other. This effectively avoids backflow problems caused by mutual interference between the airflow of the fan module and the airflow of the power supply module, improving the air intake efficiency and heat dissipation effect of the power supply module. The layout of the air guide with one side abutting against the server chassis and the other side adjacent to the power adapter board does not occupy the core computing area space, and can guide the flow of cool air to the power supply module in a directional manner, ensuring uniform heat dissipation of all components of the power supply module.

[0152] Furthermore, the server also includes an air guide plate that abuts against the front panel of the server chassis, and the air guide plate is equipped with multiple rotatable blades.

[0153] Specifically, the server also includes an air deflector, which abuts against the front panel of the server chassis. Located at the airflow channel node between the electronic component area and the motherboard, the air deflector receives external cool air and guides it towards the internal core components (such as the processor and GPU), filling the airflow gap between the electronic component area and the core computing area, and preventing cool air from dispersing and escaping at the front. Multiple rotatable blades on the air deflector are angle-adjustable, allowing the blade angle to be adjusted according to the server's load scenario, changing the airflow direction and airflow distribution. For example, when the GPU is under full load, the blade opening in the corresponding area is increased to increase the supply of cool air to the core computing area; when the electronic network card and hard drive power consumption is high, the blades are adjusted to guide towards the electronic component area, improving local heat dissipation efficiency and achieving dynamic adaptation of heat dissipation on demand.

[0154] This embodiment allows for adjusting the angle of the rotatable blades of the air guide vane to control the air intake angle of the server enclosure. This enables more flexible spatial layout of multiple servers when configuring a server cluster. A suitable air intake angle within a room housing multiple servers can significantly improve the heat dissipation efficiency of the server cluster.

[0155] As a specific embodiment of this application, the modular architecture of the server is as follows: Figure 14 As shown, the top area of ​​the diagram includes a fan module, a sideband power board, and a power supply module. The fan module may include a fan board and multiple fans, each of which can be connected to the fan board. The power supply module may include multiple power supplies and a server power supply board. The fans are server cooling components used to cool the core hardware of the motherboard. The fan board is a circuit board integrating fan interfaces and control circuitry, centrally managing the fan power supply and speed adjustment. The sideband power board is a circuit board that independently powers the sideband communication / management module, ensuring that management functions are not affected by fluctuations in the main power supply. The power supply module supplies power to the server, responsible for converting external AC power to the voltage required by the hardware (e.g., to 54V). The server power supply board can be a circuit board carrying multiple power supplies and is the physical installation and circuit carrier of the main power supply.

[0156] The area on the left side of the diagram includes a power adapter board and multiple expansion power connectors K1. The power adapter board is a circuit board used to convert power interface types and distribute power. The expansion power connectors provide power interfaces for expansion hardware (such as PCIe cards and additional modules).

[0157] The expansion power connector K1 in the central area of ​​the diagram can power expansion hardware in different locations. The first signal connector S1 is a high-speed expansion connector used for communication with the acceleration unit. The second signal connector is a high-speed switching chip miscellaneous wire connector, serving as a signal interface for connecting to the high-speed switching chip and responsible for forwarding high-speed data within the motherboard. The Complex Programmable Logic Device K2, or CPLD, is a programmable logic control chip used to implement hardware logic control of the motherboard. The vertical connector can be used to connect the management board, which is a vertically laid-out management function circuit board, typically integrating a BMC (Baseboard Management Controller), responsible for remote monitoring, fault diagnosis, and other management functions of the server. The third signal connector is a miscellaneous signal connector used to connect non-core, scattered signal interfaces on the motherboard (such as sensor signals, indicator light signals). The battery is a backup battery powering the motherboard's power-down protection module or real-time clock, ensuring that critical data is not lost and the clock is not interrupted after a power outage. The trusted computing module integrates a trusted computing chip module, used to implement security functions such as server authentication, data encryption, and secure boot. The processor 1 power chip is a power management chip that provides stable power to processor 1. The processor 0 power chip is a power management chip that provides stable power to processor 0. Processor 1 is one of the core computing hardware components of the server, responsible for data processing and task handling. Processor 0 is another core computing hardware component of the server, working in conjunction with processor 1 to achieve multi-core / multi-processor operations.

[0158] The fourth signal connector in the lower part of the diagram can be the centralized signal / power connection area for the front-window user interface, connecting to the front mounting bracket of the server and simultaneously powering this area. This area does not have a screen; it only provides input / output interfaces. The input / output power supply board can be a circuit board that provides separate power to the electronic component modules, ensuring stable power to the front interface. There can be multiple fourth signal connectors, and the electronic component modules can include electronic components within the front-window component area.

[0159] The front panel area is the hardware mounting area on the front of the server chassis. This area includes electronic component modules such as the front panel interface and mounting brackets. The first mounting bracket is a physical fixing component on the left side of the server chassis, used to install the server into the rack. The second mounting bracket is a physical fixing component on the right side of the server chassis.

[0160] The connector topology diagram of the server power supply / functional modules is as follows: Figure 15 As shown in the diagram, the power supply unit connector is the interface for connecting the server power supply (PSU), responsible for inputting power from the server power supply to this circuit board, and is the main power input for the entire module. The first power supply connector provides power to acceleration units (such as GPUs), meeting the high power consumption requirements of the acceleration units and ensuring their stable operation. The current sharing plate is a device that implements current sharing, used to evenly distribute the current from multiple power inputs, avoiding excessive load on a single power supply and improving the stability and reliability of the power supply system. The complex programmable logic device is a programmable hardware logic control chip, responsible for managing the signal logic and timing control of each connector in this module. The second power supply connector can be an interface for connecting the fan board, used to transmit the fan's power supply and control signals, enabling unified management of the fans. The power supply connector is a general-purpose power output interface, providing power to other non-specific hardware within the module. The miscellaneous wire connector is used to connect interfaces for scattered, non-core signals, responsible for transmitting these miscellaneous signals. Specifically, the first power supply connector can be a graphics processor power supply connector, and the second power supply connector can be a fan board connector.

[0161] A diagram illustrating the connection between the DC power supply board and the server power supply is shown below. Figure 16As shown in the diagram, the motherboard power connector is the interface that provides power input to the motherboard, responsible for transmitting power from the external power supply to the motherboard; it is the motherboard's power entry point. The logic control miscellaneous wire connector is used to transmit scattered logic control signals, connecting the motherboard's logic control module with other components, responsible for transmitting non-core but necessary signals such as control commands and status feedback. The compute node blind-mating connector is a blind-mating interface for compute nodes, enabling signal / power connection between the compute node and the motherboard, facilitating quick plugging and unplugging and maintenance of the compute node. The first guide structure is a physical positioning structure that assists in connector plugging and unplugging, guiding components to accurately align during connection, avoiding incorrect plugging or interface damage, and improving the convenience and reliability of plugging and unplugging. The fifth signal connector is a blind-mating interface for the back-end bus (the bus used for back-end data transmission within the server, such as the communication bus for storage and expansion devices), enabling quick connection between back-end bus-related components (such as storage modules and expansion cards) and the motherboard; it also supports blind plugging, facilitating quick maintenance and replacement of components. The fifth signal connector can be a back-end bus blind-mating connector.

[0162] The structured block diagram of the sideband power board is as follows: Figure 17 As shown in the diagram, the rear window miscellaneous connector is located in the server's rear window area as a scattered signal interface, responsible for transmitting non-core signals of the rear window components. The seventh signal connector provides power to the front window user interface and controls the logic signals of the front window interface. The sixth signal connector connects to the control signal interface of the switching chip, responsible for transmitting control commands to the switching chip and managing it. The motherboard power supply connector provides power input to the motherboard; multiple connectors arranged in parallel can distribute the power load and ensure stable power supply to the core components of the motherboard. The second guide structure is a physical positioning structure that assists in component insertion and removal, guiding components to accurately align, avoiding incorrect insertion or interface damage, and improving the convenience of assembly / maintenance. The high-density connector is an interface integrating a large number of signal / power pins, used to transmit high-bandwidth, multi-channel signals, improving the space utilization and transmission efficiency of the interface. The first signal manager is a programmable hardware logic control chip responsible for managing the signal logic and timing coordination of the components in the diagram. The programming connector is used as an interface for programming and updating chips (such as CPLDs and BIOS (Basic Input / Output System) chips), supporting the writing or upgrading of firmware programs to the chip. The 54V power supply module outputs 54V. The sideband power supply board connector connects to the interface of the sideband power supply board, responsible for transmitting power from the sideband power supply board to this module, ensuring independent power supply for the sideband management function. The sixth signal connector can be a switching chip line control connector, the seventh signal connector can be a front-window user interface input / output power supply logic control connector, and the first signal manager can be a complex programmable logic device (CPLD).

[0163] The structural block diagram of the electronic component module is as follows: Figure 18 As shown in the diagram, the electronic component module can be located on the front window. Multiple hard drives are the server's storage components, used for persistent data storage. Multiple network interface cards (NICs) are responsible for communication between the server and the external network, enabling data transmission and reception, network protocol processing, supporting multi-link redundancy and load balancing, and improving network communication stability and bandwidth. The user interface panel is the interactive interface panel on the front of the server, typically including a power button, reset button, status indicator lights, and a USB (Universal Serial Bus) interface, used by users for local operation and status monitoring of the server. The data processing unit is responsible for offloading network and storage data processing tasks from the server, improving the computing efficiency of the main processor. Open Compute Project (OCP) form factor NICs are NICs conforming to the Open Compute Project standard. Compared to traditional NICs, their size and interfaces are more suitable for OCP architecture servers, facilitating modular replacement and expansion.

[0164] The structural block diagram of the input / output power supply board is as follows: Figure 19 As shown in the diagram, the front window user interface input / output power connector is the interface that provides power to the front window user interface and is the power input point for the front window area. The front window user interface input / output power logic control connector provides power to the front window user interface and controls the signal logic of the front window interface. The power management chip is responsible for voltage regulation and current distribution, providing stable and compatible power to the hardware within the module. The fuse is an electronic overcurrent protection device that automatically cuts off the circuit to prevent hardware damage when an overcurrent fault occurs in the connected component. The fuse can be an electronic fuse. Multiple component power supply connectors may include hard drive backplane power supply connectors, network card slot power supply connectors, data processing unit body power supply connectors, form data processing unit body power supply connectors, network card power supply connectors, and hard drive power supply connectors. Among them, the hard drive backplane power supply connector connects to the power supply interface of the hard drive backplane, providing power to the hard drive on the hard drive backplane and ensuring the stable operation of the hard drive. The network card slot power supply connector is the interface that provides power to the network card slot, ensuring that the network card inserted into the network card slot receives a stable power supply. The power connector for the data processing unit provides power to the data processing unit itself, meeting the high power consumption requirements of the DPU. The power connector for the form factor data processing unit provides power to data processing units of a specific form factor, adapting to the power requirements of that form factor component. The network interface card (NIC) power connector provides power to OCP form factor NICs, adapting to the power specifications of standard OCP NICs. The hard drive power connector provides power to the hard drive, adapting to the power requirements of the hard drive.

[0165] The motherboard's clock and signal connection topology is as follows: Figure 20As shown in the diagram, the clock generator produces the reference clock signal required for the server hardware to operate. Processor 0 is one of the core computing hardware components of the server, responsible for data processing and task scheduling. The data communication interface (G PORT) is the G-type port of processor 0, typically used for high-speed data communication. The processor communication interface (P PORT) is the P-type port of processor 0, generally used for inter-processor communication or connecting core components. Processor 1 is another core computing hardware component of the server, working in conjunction with processor 0 to achieve multi-core / multi-processor operations. The clock buffer is a device that buffers, amplifies, and replicates the reference clock signal output by the clock generator, splitting one clock signal into multiple paths to ensure clock synchronization for multiple peripherals (such as GPUs and network cards) while preventing signal attenuation. The multi-chip input / output interface (MCIOX8, Multi-Chip Input / Output×8) refers to an 8-channel multi-chip input / output interface, a high-speed serial bus interface used for high-speed data transmission between the processor, switching chip, and peripherals. The multiple sets of multi-chip input / output interfaces in the diagram represent multiple 8-channel high-speed links. Graphics Processing Unit (GPU) node 0 is the server's first GPU computing node, integrating multiple GPUs and related components, responsible for acceleration tasks such as graphics rendering and parallel computing. Switch chip 0 is a high-speed switch chip within GPU node 0, responsible for data forwarding and communication scheduling among the node's internal components. The GPU is used for acceleration tasks such as parallel computing and training. The network interface card (NIC) is responsible for data communication between GPU node 0 and the external network. Switch chip 1 is another high-speed switch chip within GPU node 0, working with Switch chip 0 to improve the node's internal communication bandwidth and redundancy. GPU node 1 is the server's second GPU computing node.

[0166] Figure 20 The dashed lines indicate support for non-homogeneous clocks, while the solid lines indicate support for homogeneous clocks. When the system needs high-speed interconnection across nodes, because the multi-chip I / O interfaces have fixed pinouts, a clock can be drawn from any of these interfaces to connect to the clock buffer chip of the GPU node. This provides a reference clock for an entire layer of PCIe devices, thus largely avoiding the problem of excessively long cross-node clocks. It can support two layers of GPU nodes, connected from the multi-chip I / O interfaces in the motherboard system. Simultaneously, because all clocks are homogeneous with the CPU, the front-panel connections to hard drives, network cards, and DPUs can directly use the clock or add a clock buffer to the hard drive backplane to obtain a clock homogeneous with the CPU.

[0167] The motherboard's reset and signal connection topology diagram is as follows: Figure 21As shown in the figure, the PCIe reset signal is issued by CPU0 and CPU1 respectively, sent to the complex programmable logic device on the motherboard, and then passed through to each multi-chip input / output interface. In this way, each PCIe device has a unified reset signal, ensuring that all reset timings are consistent when the system starts normally.

[0168] The motherboard's integrated circuit bus (I2C) connection topology is as follows: Figure 22 As shown in the diagram, the Baseboard Management Controller (BMC) is the core of the server's remote management, responsible for monitoring hardware status, remote control, fault diagnosis, and other functions. It communicates with various components via the I2C bus. Integrated Circuit Bus 1 to Integrated Circuit Bus 16 are the BMC's 16 I2C communication interfaces, each connecting to a different hardware module. A multiplexer is used to expand one I2C bus into multiple I2C interfaces. The 8-channel expansion interface (I2CHEADER 8) is an 8-channel I2C expansion interface; the multiplexer expands Integrated Circuit Bus 1 into 8 I2C interfaces for connecting more devices. The Trusted Platform Module (TPM) is used for server security authentication and data encryption; the DUMP module saves operational data in case of system failure for easy fault analysis; the Top-of-Rack Switch Module (TSOM) is responsible for the server's network switching; simultaneously, Integrated Circuit Bus 2 also connects to Processor 0 and Processor 1, allowing the BMC to monitor processor status. The multiplexer (MUX) is an I2C multiplexer; it connects Processor 0 and Processor 1 for I2C communication between the BMC and the dual processors. The BMC communicates with the Complex Programmable Logic Device (CPLD) on the motherboard via integrated circuit bus 4 to control the motherboard logic. The System Control Module (SCM CPLD) is the Complex Programmable Logic Device of the System Control Module; sensors are used to collect hardware status data; Field Replaceable Units (FRUs) are accessed by the BMC via integrated circuit bus 5, which reads FRU information (such as part model and serial number) to manage hardware assets. The Multi-Chip Input / Output Interface (MCIO (X8) 24) is a 24-channel, 8-way multi-chip input / output interface; the BMC manages the status of these high-speed interfaces via integrated circuit bus 6. The processor's voltage regulator (VR) is monitored and adjusted by the BMC via integrated circuit bus 7. Other miscellaneous connectors are OTHER MISCCONN; there are 10 power supply units (PSUs), and the BMC monitors their power status via integrated circuit bus 8. There are 5 fan boards. The BMC controls the fan speed and monitors the fan status through integrated circuit bus 9. The switching chips (miscellaneous switching modules) are miscellaneous functional modules that are connected to the switching chips via I2C interfaces. The BMC manages the status and configuration of the switching chips through these interfaces.

[0169] The system's I2C signals are arranged according to Figure 22The topology is used for routing to access all fixed I2C devices on the motherboard. A daisy-chain routing method is used to ensure that addresses do not overlap. If this is unavoidable, a multiplexer is used to split the I2C bus into multiple devices. After connecting the fixed access devices, the remaining I2C bus is connected to the switch miscellaneous connector and other miscellaneous connectors. In this way, all the I2C buses of the motherboard are brought out and connected using cables along the power board. Therefore, depending on the configuration requirements of the system, only modifications need to be made to the power board or different configurations can be connected using cables with multiple splits, without modifying the motherboard.

[0170] The motherboard's Network Controller Sideband Interface (NCSI) connection topology diagram is as follows: Figure 23 As shown in the figure, the NCSI signals on the Baseboard Management Controller (BMC) side include the following types: Network Controller Sideband Interface_Reference Clock Signal is the NCSI reference clock signal output by the BMC and transmitted to the clock buffer. Network Controller Sideband Interface_Carrier Detection Signal (NCSI_CRS_DV) is the NCSI carrier detection signal, used to identify whether valid data exists in the NCSI link. Network Controller Sideband Interface_Transmit Enable Signal (NCSI_TXEN) is the transmit enable signal, controlling the BMC to transmit NCSI data externally. Network Controller Sideband Interface_Transmit Data Channel 0 (NCSI_TXD0) is the NCSI transmit data channel 0, used to transmit the 0th channel of transmitted data. Network Controller Sideband Interface_Transmit Data Channel 1 (NCSI_TXD1) is the NCSI transmit data channel 1, used to transmit the 1st channel of transmitted data. Network Controller Sideband Interface_Receive Data Channel 0 (NCSI_RXD0) is the NCSI receive data channel 0, used to receive the 0th channel of data transmitted externally. Network Controller Sideband Interface_Receive Data Channel 1 (NCSI_RXD1) is the NCSI Receive Data Channel 1, used to receive the first channel of data transmitted from the outside.

[0171] The clock buffer output signals include the following types: The Network Controller Sideband Interface_50MHz Clock Signal (NCSI_CLK_50M) is the 50MHz NCSI clock signal output by the clock buffer, providing a synchronization clock for the NCSI link. The Open Compute Project (OCP) side NCSI signals after multiplexer (MUX) switching include the following types: The Sideband Interface Area (OCPSIDEBAND) is the sideband interface area of ​​the Open Compute Project form factor module, used to connect OCP standard hardware. The Network Controller Sideband Interface_Open Compute Project_50MHz Clock Signal (NCSI_OCP_CLK_50M) is the 50MHz NCSI clock signal for the OCP module. The Network Controller Sideband Interface_Open Compute Project_Transmit Enable Signal (NCSI_OCP_TXEN) is the NCSI transmit enable signal for the OCP module. The Network Controller Sideband Interface_Open Compute Project_Transmit Data Channel 0 (NCSI_OCP_TXD0) is the NCSI transmit data channel 0 for the OCP module. The Network Controller Sideband Interface_Open Computing Project_Transmit Data Channel 1 (NCSI_OCP_TXD1) is the NCSI transmit data channel 1 that interfaces with the OCP module. The Network Controller Sideband Interface_Open Computing Project_Receive Data Channel 0 (NCSI_OCP_RXD0) is the NCSI receive data channel 0 that interfaces with the OCP module. The Network Controller Sideband Interface_Open Computing Project_Receive Data Channel 1 (NCSI_OCP_RXD1) is the NCSI receive data channel 1 that interfaces with the OCP module.

[0172] The NCSI signals on the RISER side after multiplexing (MUX) switching include the following types: NCSI HEADER is the NCSI extension interface used to connect the NCSI extension card. NCSI_RISER_CLK_50M is the 50MHz NCSI clock signal for the NCSI extension card. NCSI_RISER_TXEN is the NCSI transmit enable signal for the NCSI extension card. NCSI_RISER_TXD0 is the NCSI transmit data channel 0 for the NCSI extension card. NCSI_RISER_TXD1 is the NCSI transmit data channel 1 for the NCSI extension card. Network Controller Sideband Interface_Extension Card_Receive Data Channel 0 (NCSI_RISER_RXD0) is the NCSI Receive Data Channel 0 that interfaces with the NCSI Extension Card. Network Controller Sideband Interface_Extension Card_Receive Data Channel 1 (NCSI_RISER_RXD1) is the NCSI Receive Data Channel 1 that interfaces with the NCSI Extension Card.

[0173] The NCSI interface designed for external use on motherboards is generally used for two purposes: connecting a standard OCP network card and connecting a PCIe DPU. Since the installation positions of the two modules are different and the corresponding soldering boards are also different, they are placed nearby according to the front window correspondence. This way, even if there are configuration changes, the motherboard will not need to be modified due to NCSI link issues.

[0174] Based on the various motherboard design schemes mentioned above, the current architecture can also support a variety of topologies and communication management, such as fully interconnected non-blocking mesh topology, ring interconnected topology, and ring interconnected dual uplink topology.

[0175] 54V power supply topology as follows Figure 24As shown in the diagram, the power supply module is responsible for distributing power from the main power supply to each module. The power supply module can contain 10 power supply units and is the main power source for the server, converting external AC power into the voltage required by the server hardware. The 54V output voltage from the power supply module is the initial high-voltage power for this power supply link, used for long-distance, low-loss transmission. Multiple acceleration nodes (e.g., GPUs) receive 54V power to meet their high power consumption requirements. The power adapter board is the DC voltage adapter board for the processor node, responsible for receiving 54V and transferring / distributing it to subsequent modules. The sideband power board is a circuit board that independently powers the sideband functional modules, receiving the 54V voltage output from the processor node's DC adapter board. The power brick is a miniaturized power module that converts 54V to 12V. The expansion power connector has 5 expansion power interfaces, receiving 12V to provide power to the expansion hardware. The motherboard receives 12V power through the expansion power connector. The front-side user interface input / output power connector supplies power to the server's front-side user interface, receiving 54V from the processor node's DC-DC converter board. The voltage regulator further regulates and distributes the 12V voltage. The power rail is a stable voltage output channel, providing regulated voltage. The network interface card / hard drive / data processing unit (DPU) of the server receives power through the power rail.

[0176] Replacing the 12V power supply topology with a 54V power supply reduces the current requirements of system boards and connectors. For example, if the total power consumption is 16000W, using a 12V power supply architecture would require a total system current of over 1300A. This necessitates a very thick copper busbar and custom bus bars and current-carrying plates for the power supply module design. Compute nodes require a bus bar with a current draw of over 170A. When using 54V power supply, the overall system current is 300A. It can use a universal blind-mating power connector, and the current of the computing node will be reduced to less than 40A. Therefore, it can reduce transmission loss and improve power supply efficiency in long link transmission. Taking the total power consumption of the system as 16000W as an example, under the same architecture, the transmission loss of the 54V system can be reduced by 200W-300W compared with the 12V system. In a product life cycle of 5 years, with industrial power supply at 0.7 yuan / kWh, the cost of a single machine can be reduced by 13,140 yuan. Taking a data center with a 10,000-card cluster as an example, the electricity cost can be reduced by 8.2 million yuan in one life cycle.

[0177] Therefore, the server proposed in this embodiment has the following technical advantages:

[0178] (1) Modular architecture design. The computing node is divided into independent modules such as core computing area, power supply area, and IO area. Each module communicates through a fixed interface, supporting multi-platform and multi-speed compatibility. Modules can be replaced to adapt to different configurations without modifying the motherboard, improving the reusability of the board and reducing R&D and modification costs.

[0179] (2) Power supply efficiency and reliability. A 54V power supply architecture is adopted to replace the traditional 12V, which reduces the system current requirement and transmission loss. With the centralized power supply design, N+N power supply redundancy can be achieved, which improves the power supply stability in high power consumption scenarios. The input and output power supply boards are independently powered, which avoids the waste of expensive motherboard materials and further optimizes the power supply cost.

[0180] (3) Signal interaction optimization. Standardized MCIO pin definitions and fixed signal topology reduce signal interference; the first bus multiplexing design and spare signal pin configuration reserve channels for functional expansion, allowing new communication requirements to be added without modifying the hardware, thus improving the flexibility and redundancy of signal interaction.

[0181] (4) Flexibility in configuration. The expansion module supports plug-and-play functionality for various devices such as RDMA network cards, OCP network cards, and DPUs, and the front window components can be flexibly replaced in different proportions; it supports various topologies such as full interconnection and ring interconnection, adapting to different scenario requirements such as large model training and distributed computing.

[0182] (5) Heat dissipation and space utilization. The whole machine fan wall is equipped with an independent air duct design to solve the fan backflow problem; the core module is centrally located at the rear and blind plug design saves chassis space, increases the computing density per unit space, and simplifies the assembly and maintenance process.

[0183] Therefore, the server proposed in this embodiment adopts a modular design, dividing the server into independent functional modules such as a power supply module, motherboard, sideband power board, and input / output power supply board. Each module achieves flexible interconnection and management through standardized interfaces and logic signals. At the same time, the power supply architecture is optimized and an independent server power supply board is integrated, supporting multiple power supplies in parallel to meet redundancy requirements. With the help of power adapter boards and conversion modules, precise voltage adaptation is achieved. Through the signal transfer area and signal manager of the sideband power board, various management signals are logically processed and flexibly transferred. This can achieve the technical effects of significantly improving server reusability and configuration flexibility, reducing board costs and transmission losses, improving power supply efficiency and system reliability, and meeting the diverse needs of different artificial intelligence application scenarios. It can solve the problem of low motherboard reusability in related technologies.

[0184] Embodiments of this application also provide a server cluster, such as Figure 25As shown, the server cluster 1000 includes: multiple servers 100 as described above; and a cluster resource scheduler 200, which is connected to each of the multiple servers. The cluster resource scheduler 200 is the core control unit of the cluster. Its core responsibility is to uniformly monitor, allocate, and schedule the hardware resources of all servers in the cluster, including CPU, GPU, memory, storage, and network bandwidth, to ensure that resources are allocated on demand and load balanced, while coordinating multiple servers to complete collaborative computing tasks.

[0185] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for specific applications, but such implementations should not be considered beyond the scope of this application.

[0186] The foregoing has provided a detailed description of a server and its implementation. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of these embodiments are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. A server, characterized in that, include: The system comprises a power supply module, a motherboard, and a sideband power supply board. The power supply module is connected to the sideband power supply board via a power adapter board. The sideband power supply board is connected to the motherboard. The power supply module includes a server power supply board, which is connected to the acceleration unit. The motherboard is communicatively connected to both a fan module and an electronic component module. The sideband power board includes a power supply area and a signal conversion area. The power supply area includes a first conversion module for converting the node current output by the power conversion board into a target current to power the motherboard. The sideband power board processes and outputs initial signals received by the motherboard through the signal conversion area. These initial signals include a first management signal from the fan module and a second management signal from the electronic component module. The motherboard is connected to the sideband power board via a second signal connector, the motherboard is connected to the fan module via a third signal connector, and the motherboard is connected to the electronic component module via a fourth signal connector.

2. The server according to claim 1, characterized in that, The power supply module also includes a power supply, and the server power supply board is connected to the power supply and the power adapter board respectively. The server power supply board is connected to the acceleration unit through a first power supply connector and to the fan module through a second power supply connector.

3. The server according to claim 2, characterized in that, Also includes: An input / output power supply board, wherein the input / output power supply board is connected to the power adapter board and the electronic component module, respectively.

4. The server according to claim 3, characterized in that, The motherboard is communicatively connected to the acceleration unit via a first signal connector.

5. The server according to claim 4, characterized in that, The server power supply board and the power adapter board are connected by a first blind-mating connector and a first guide structure. The first blind-mating connector includes a computing node blind-mating connector and a fifth signal connector.

6. The server according to claim 5, characterized in that, The power supply comprises multiple power supplies connected in parallel, and these power supplies are then connected to the server power supply board. The power adapter board is used to acquire status information of multiple power supplies through the fifth signal connector and monitor the multiple power supplies based on the status information.

7. The server according to claim 4, characterized in that, The first signal connector and the second signal connector each include a plurality of pins, wherein the plurality of pins are defined according to a preset pin design strategy.

8. The server according to claim 4, characterized in that, The side power board and the main board are connected by a second blind-mating connector and a second guide structure, wherein the second blind-mating connector includes a high-density connector.

9. The server according to claim 8, characterized in that, The sideband power board is provided with a first signal manager and a sixth signal connector. The sideband power board receives the third management signal from the motherboard through the sixth signal connector, analyzes and processes the third management signal through the first signal manager to obtain the target signal, and sends the target signal to the motherboard through the high-density connector.

10. The server according to claim 9, characterized in that, The sixth signal connector is provided with a spare signal pin, which is used for communication connection between the second signal manager and the first signal manager on the motherboard.

11. The server according to claim 3, characterized in that, The sideband power board is provided with a seventh signal connector, wherein the sideband power board is communicatively connected to the input / output power supply board through the seventh signal connector, the sideband power board obtains the power supply logic information of the input / output power supply board through the seventh signal connector, and processes and outputs the power supply logic information.

12. The server according to claim 3, characterized in that, The input / output power supply board is provided with a second conversion module, which is used to convert the node current output by the power adapter board into the target component current, so as to supply power to at least one component in the electronic component module.

13. The server according to claim 12, characterized in that, The input / output power supply board is equipped with a component power supply connector and a fuse. One end of the fuse is connected to the second conversion module, and the other end of the fuse is connected to the component power supply connector.

14. The server according to claim 9, characterized in that, The third signal connector and the sixth signal connector are connected to a first bus, wherein the first bus includes the remaining circuit bus after access wiring to the bus devices on the motherboard.

15. The server according to claim 1, characterized in that, The motherboard is provided with an expansion module, wherein the expansion module includes at least one network card interface, and the network card interface includes a network controller sideband interface.

16. The server according to claim 4, characterized in that, Also includes: The system includes a management board, a first ear-mount board, and a second ear-mount board. The management board is vertically connected to the motherboard via a vertical connector, and the first ear-mount board and the second ear-mount board are respectively connected to the fourth signal connector.

17. The server according to claim 3, characterized in that, The power supply module and the fan module are respectively located on one side of the server chassis. The side of the power supply module and the side of the fan module are respectively abutted against the rear panel of the server chassis. The power adapter board is located adjacent to the other side of the power supply module, and the side power board is located adjacent to the other side of the fan module.

18. The server according to claim 17, characterized in that, Also includes: An air guide is provided, one side of which abuts against the other side of the server chassis, and the other side of the air guide is adjacent to the power adapter board, wherein one side of the server chassis and the other side of the server chassis are perpendicular to each other; The air guide has openings at both ends, and one end of the air guide is connected to the air inlet of the power supply module. The opening at one end of the air guide is larger than the opening at the other end of the air guide.

19. A server cluster, characterized in that, include: Multiple servers as described in any one of claims 1-18; A cluster resource scheduler, which is connected to multiple of the servers respectively.

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