Neural network implementation method and device based on memory

Abstract

The invention discloses a memory-based neural network implementation method and device, and the method comprises the steps: firstly obtaining a preset memory array comprising a plurality of connected memories, and storing preset neuron parameters in each memory; then, determining a connection relationship between the neurons according to a preset connection mode; and the logic circuit corresponding to each memory is utilized to execute the logic functions of the stored preset neuron parameters, including weight processing, deviation adjustment, activation function application and the like. And finally, in combination with preset neuron parameters, neuron connection relationships and logic functions, constructing a target neuron network. According to the design, the network structure is simplified, the calculation efficiency and the energy efficiency are improved, and a new effective way is provided for the implementation of the neural network.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, and more specifically, to a method and apparatus for implementing a memory-based neural network. Background Technology

[0002] With the rapid development of artificial intelligence technology, neural networks, as a core component, are attracting increasing attention from researchers. Traditional methods for implementing neural networks often rely on high-performance computing devices; however, this approach has limitations in terms of energy efficiency, computational efficiency, and scalability. Summary of the Invention

[0003] The purpose of this invention is to provide a method and apparatus for implementing a memory-based neural network.

[0004] In a first aspect, embodiments of the present invention provide a memory-based neural network implementation method, comprising:

[0005] Obtain a preset memory array, the preset memory array comprising multiple memories connected according to a preset connection method;

[0006] Based on the preset neuron parameters stored in each of the memories;

[0007] The neuronal connection relationship is determined based on the preset connection method;

[0008] The logic function of each memory is executed based on the logic circuit corresponding to each memory, which executes the preset neuron parameters corresponding to each memory.

[0009] Based on the preset neuron parameters, neuron connectivity, and logical functions, a target neuron network is constructed.

[0010] In one possible implementation, the logical function of executing the preset neuron parameters corresponding to each memory based on the logic circuit corresponding to each memory includes:

[0011] The logical functions of the preset neuron parameters corresponding to each memory are executed based on the lookup table corresponding to each memory.

[0012] In one possible implementation, the input and output of the lookup table are N bits, and the lookup table implements N / 4 bits of neuron functionality.

[0013] In one possible implementation, the preset connection method is a sparse connection method, which means that each neuron is connected to only a portion of other neurons.

[0014] In one possible implementation, each of the memories stores preset neuron parameters including weights, biases, and activation functions, which are integrated into a single logic unit for processing.

[0015] In one possible implementation, the single logic unit represents all the results under the combined effect of the weights, biases, and activation functions through a truth table, wherein the truth table lists all input combinations and their corresponding outputs.

[0016] In one possible implementation, the method further includes:

[0017] The output activation is directly driven by the input data by looking up the predefined weights, biases, and activation functions stored in the truth table or lookup table.

[0018] In one possible implementation, the predefined weights, biases, and activation functions retain their original, unquantized values.

[0019] In one possible implementation, the logic circuits corresponding to each memory in the preset memory array are configured to perform integrated logic functions including weight processing, bias adjustment, and activation function application to realize the function of the neuron.

[0020] Secondly, embodiments of the present invention provide a memory-based neural network implementation device, comprising:

[0021] An acquisition module is used to acquire a preset memory array, the preset memory array including multiple memories connected according to a preset connection method; based on the preset neuron parameters stored in each memory; determine the neuron connection relationship based on the preset connection method; and execute the logical function corresponding to the preset neuron parameters of each memory based on the logic circuit corresponding to each memory.

[0022] The implementation module is used to construct the target neural network based on the preset neuron parameters, neuron connection relationships, and the logical functions.

[0023] Compared to existing technologies, the beneficial effects provided by this invention include: The invention employs a memory-based neural network implementation method and apparatus, comprising: first, acquiring a preset memory array containing multiple connected memories, each memory storing preset neuron parameters; then, determining the connection relationships between neurons according to a preset connection method; utilizing the logic circuits corresponding to each memory to execute the logical functions of the stored preset neuron parameters, including weight processing, bias adjustment, and activation function application; finally, combining the preset neuron parameters, neuron connection relationships, and logical functions to construct the target neural network. This design simplifies the network structure, improves computational efficiency and energy efficiency, and provides a new and effective approach for realizing neural networks. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as limiting the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A flowchart illustrating the steps of a memory-based neural network implementation method provided in an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of a memory-based neural network provided in an embodiment of the present invention;

[0027] Figure 3 A schematic diagram of another structure for implementing a neural network using a memory, as provided in an embodiment of the present invention;

[0028] Figure 4 A schematic diagram of neural network compaction provided in an embodiment of the present invention;

[0029] Figure 5 A schematic diagram illustrating the compactification of a neural network based on memory logic circuits, provided for an embodiment of the present invention;

[0030] Figure 6 A schematic block diagram of the structure of a memory-based neural network implementation device provided in an embodiment of the present invention;

[0031] Figure 7 A schematic block diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0033] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0034] In order to solve the technical problems mentioned in the background art Figure 1 This is a flowchart illustrating the memory-based neural network implementation method provided in this embodiment. The memory-based neural network implementation method will be described in detail below.

[0035] Step S201: Obtain a preset memory array, wherein the preset memory array includes multiple memories connected in a preset connection method;

[0036] Step S202, based on the preset neuron parameters stored in each of the memories;

[0037] Step S203: Determine the neuron connection relationship based on the preset connection method;

[0038] Step S204: Execute the logical function of the preset neuron parameters corresponding to each memory based on the logic circuit corresponding to each memory;

[0039] Step S205: Based on the preset neuron parameters, neuron connection relationships, and logical functions, construct the target neuron network.

[0040] In this embodiment of the invention, exemplarily, the server first acquires a preset memory array from a dedicated hardware device or module. This array consists of 1024 SRAM (Static Random Access Memory) cells, each capable of storing a certain amount of data. These SRAM cells are physically or logically connected according to a specific preset connection method (e.g., a grid connection). After acquiring the memory array, the server begins writing preset neuron parameters into each SRAM cell. For example, a certain SRAM cell stores the weight parameters of a neuron, which are obtained during training and optimized for a specific recognition or classification task. Another SRAM cell may store the bias parameters of the neuron, which are used to adjust the neuron's activation threshold. The server determines the connection relationships between neurons based on the preset connection methods of the SRAM cells in the memory array. For example, if SRAM cell A is directly connected to SRAM cells B and C, this means that there is a direct connection relationship between the neurons they represent. This connection relationship defines the information transmission path in the neural network. Each SRAM cell is associated with a specific logic circuit, which is responsible for performing the logical functions associated with that SRAM cell (i.e., neuron). For example, after the server reads the weights and biases from the SRAM cells, it calculates the neuron's output using the corresponding logic circuitry. This logic circuitry might include an adder to calculate the sum of the weighted inputs and a comparator to determine if the sum exceeds the neuron's activation threshold. After completing the aforementioned steps, the server has acquired all the necessary neuron parameters, determined the connections between neurons, and can execute the neurons' logical functions through the logic circuitry. At this point, the server integrates these elements to construct a complete target neural network. This network can be used to perform various machine learning tasks, such as image recognition, speech recognition, or natural language processing. The server can evaluate the network's performance by inputting data into the network and observing its output, and can further optimize and adjust it as needed.

[0041] In this embodiment of the invention, the aforementioned step S204 can be implemented through the following examples.

[0042] The logical functions of the preset neuron parameters corresponding to each memory are executed based on the lookup table corresponding to each memory.

[0043] In this embodiment of the invention, for example, when constructing a memory-based neural network, the server associates a specific look-up table (LUT) with each SRAM cell (memory). This look-up table is essentially a data structure that pre-computes and stores all possible input combinations and their corresponding outputs. For instance, assuming an SRAM cell stores the weights and biases of a neuron, the associated look-up table might contain all possible weighted inputs of that neuron (i.e., the sum of the products of the weights and the input signal plus the bias) and their corresponding activation function outputs. This look-up table is pre-computed and stored before the training or usage phase. When the server needs to calculate the output of the neuron, it no longer performs real-time weighted summation and activation function calculation, but directly looks up the corresponding output value in the look-up table based on the current input data. This method significantly reduces the amount of real-time computation and improves the computation speed of the neural network. Specifically, if the input of a neuron is a 3-bit number, then the look-up table will contain all eight possible input combinations (000 to 111) and their corresponding output values. When the server receives a specific 3-bit input, it only needs to find the row corresponding to that input in the lookup table and then directly read the output value stored in that row. In this way, the server can efficiently utilize each SRAM cell in the memory array and their respective lookup tables to execute the logical functions of preset neuron parameters, thereby achieving fast and accurate neural network operations.

[0044] In this embodiment of the invention, the input and output of the lookup table are N bits, and the lookup table implements N / 4 bits of neuron functionality.

[0045] In this embodiment of the invention, exemplaryly, during the construction of a memory-based neural network on a server, each lookup table associated with an SRAM cell is designed with specific input and output bit widths. In this example, the input and output of the lookup table are set to N bits, for example, N = 16 bits. The lookup table can accept a 16-bit input and output a 16-bit output. However, the lookup table actually implements N / 4 bits, or 4 bits, of neuronal functionality. Specifically, although the input and output interface of the lookup table is 16 bits, the internal logic may only focus on 4 bits of these 16 bits and execute the corresponding neuronal logic function, such as the calculation of the activation function, based on the value of these 4 bits. The remaining bits may be used for other purposes, such as control signals, error detection, etc., or may not directly participate in the current neuronal computation. For example, if the high 4 bits of the 16 bits of the lookup table input represent the weighted input value of the neuron (this value has been quantized to a 4-bit range in some way), then the lookup table will look up the corresponding 4-bit output based on the value of these 4 bits, which may be the value processed by the activation function. When constructing such a lookup table, the server pre-calculates the outputs corresponding to all possible 4-bit input values ​​and stores these input-output pairs in the lookup table. When neuron computation is needed, the server reads the relevant weights and biases from the SRAM cells, calculates the 4-bit weighted input based on the input data, and then directly finds the corresponding output value through the lookup table. The advantage of this approach is that it can significantly reduce the size and complexity of the lookup table while maintaining a certain level of accuracy, thereby improving the computational efficiency of the neural network. Moreover, by rationally designing the inputs and outputs of the lookup table, more complex neuron functions and more efficient data processing can be achieved.

[0046] In this embodiment of the invention, the preset connection method is a sparse connection method, which means that each neuron is connected to only a portion of other neurons.

[0047] In this embodiment of the invention, for example, when the server constructs a memory-based neural network, it employs a special connection method—sparse connection. This connection method means that each neuron in the network is not connected to all other neurons, but only to a subset of them. Specifically, suppose the server constructs a network containing 100 neurons. In a traditional fully connected network, each neuron is connected to 99 other neurons, forming a large number of connections. However, in a sparse connection network, each neuron may only be connected to 10 or 20 other neurons. For example, neuron A may only be connected to neurons B, C, D, E, F, G, H, I, J, and K, and not to any other neurons. This connection method significantly reduces the number of connections in the network, thereby simplifying the network's complexity and reducing computational costs. When determining this sparse connection method, the server considers factors such as training data, network performance requirements, and hardware resources. In this way, the server can construct a neural network that is both efficient and economical to meet specific application needs. In practice, the server may use specific algorithms to determine which neurons should be connected to ensure optimal network performance and efficiency. This sparse connection method not only helps reduce computation but also improves the network's generalization ability and avoids problems such as overfitting.

[0048] In this embodiment of the invention, each memory stores preset neuron parameters including weights, biases, and activation functions, which are integrated into a single logic unit for processing.

[0049] In this embodiment of the invention, for example, during the process of building a memory-based neural network on the server, each SRAM unit (memory) stores not only the weights and bias parameters of the neuron, but also the activation function information associated with that neuron. This design makes each SRAM unit a fully functional logical unit capable of independently completing the neuron's computational tasks. Specifically, suppose an SRAM unit stores the weight parameters, bias parameters, and ReLU (Rectified Linear Unit) activation function information of a neuron. When the server needs to obtain the output from this neuron, it first reads the weights and bias parameters stored in the SRAM unit, and then calculates the weighted input based on the input data. Next, the server processes the weighted input using the activation function information stored in the SRAM unit. In this example, the server uses the ReLU function, which converts all negative values ​​to 0 while keeping positive values ​​unchanged. This processing is completed in the logic circuit corresponding to the SRAM unit, and is therefore very efficient. In this way, each SRAM unit becomes an independent, fully functional neuron processing unit. The server only needs to connect these units according to a preset connection method to build a powerful neural network. This design not only improves the computational efficiency of neural networks but also makes network expansion and maintenance easier. Servers can increase or decrease the number of SRAM cells as needed, thus flexibly adjusting the network's size and complexity. Furthermore, since each SRAM cell contains complete neuron processing logic, troubleshooting and repairing the server become simpler and more straightforward.

[0050] In this embodiment of the invention, the single logical unit represents all the results under the combined action of the weights, biases, and activation functions through a truth table, wherein the truth table lists all input combinations and their corresponding outputs. In this embodiment, for example, in the server, each memory (such as an SRAM unit) is treated as a single logical unit, storing the neuron's weights, biases, and activation functions. To process this information more efficiently, the server uses a truth table to pre-calculate and store all possible input combinations and their corresponding outputs. For example, assuming the weights and biases of a neuron are determined, and the activation function is the ReLU function, the server creates a truth table for this neuron, listing all possible input values ​​(in this scenario, it can be assumed that the inputs are binary, i.e., 0 or 1, for simplicity) and their outputs under the combined action of the weights, biases, and activation functions. Specifically, the truth table can be referenced in Table 1:

[0051] Table 1

[0052]

[0053] In this truth table, the server lists all possible inputs (0 and 1 in this simple example) and computes the output for each input given weights, biases, and activation functions. During actual runtime, the server only needs to look up this truth table to directly obtain the neuron's output, without performing complex calculations each time. This method significantly improves the computational efficiency of neural networks, especially when processing large amounts of data. By pre-compiling and storing all possible results, the server can quickly look up and provide results during real-time processing, reducing computational latency and improving overall performance. Of course, in practical applications, neuron inputs may not be just binary, but more complex numerical values ​​or vectors. In this case, the server may employ more complex data structures and algorithms to create and use the truth table to accommodate different input and output requirements. However, overall, using a truth table to represent all results under the combined effect of weights, biases, and activation functions is an effective way to improve the computational efficiency of neural networks.

[0054] In this embodiment of the invention, the following implementation methods are also provided.

[0055] The output activation is directly driven by the input data by looking up the predefined weights, biases, and activation functions stored in the truth table or lookup table.

[0056] In this embodiment of the invention, for example, when the server runs the neural network, when input data arrives at a neuron, the server directly drives the output activation using the truth table or lookup table corresponding to that neuron. This process skips the traditional steps of weight multiplication, bias addition, and activation function calculation, thereby significantly improving processing speed.

[0057] Specifically, suppose there is a neuron whose truth table has already been built based on predefined weights, biases, and activation functions (such as ReLU). When the server receives specific input data, such as the binary number "1011", it will convert this input data into the corresponding index in the truth table.

[0058] The server then directly looks up the output activation value corresponding to this index in the truth table. Since the truth table has been pre-computed and stored for all possible input combinations and their corresponding output activation values, the server can obtain the result immediately without performing any real-time computation.

[0059] The advantage of this approach is that it completely eliminates the overhead of multiplication, addition, and activation function operations in traditional neuronal computation, resulting in faster response times for neural networks. For applications requiring real-time response or processing of large amounts of data, this method can significantly improve system performance and efficiency.

[0060] For example, in image recognition tasks, when a server receives an image to be recognized, it can use the value of each pixel in the image as input data and quickly obtain the output activation value of each neuron by looking up a truth table or lookup table. In this way, the server can complete the entire image recognition process in a short time and provide real-time feedback to the user.

[0061] In this embodiment of the invention, the predefined weights, biases, and activation functions retain their original, unquantized values.

[0062] In this embodiment of the invention, an exemplary neural network implemented in a server has predefined weights, biases, and activation functions as key parameters stored in a truth table or lookup table. These parameters retain their original, unquantized values ​​during storage and computation, meaning they exist in a high-precision, unapproximated or unsimplified form.

[0063] Specifically, suppose a neuron in the server has a specific set of weights and biases, which may be floating-point numbers with high precision. For example, the original value of a weight might be 0.7654321, and the original value of a bias might be -0.1234567. These original values ​​are used directly in the construction of the truth table or lookup table without any form of quantization or approximation.

[0064] When the server looks up the corresponding output activation in a truth table or lookup table based on the input data, it uses these unquantized raw values ​​for computation. This ensures that the output of the neural network has the highest possible precision and accuracy, because no information is lost during the quantization process.

[0065] Maintaining the original values ​​of parameters is particularly important for applications requiring high-precision calculations. For example, in the financial field, tiny numerical differences can lead to significant fluctuations in funds. Therefore, when processing financial data, servers must ensure that the parameters of the neural network maintain their original precision.

[0066] In summary, by maintaining the original values ​​of predefined weights, biases, and activation functions, the server can ensure that the output of the neural network has the highest accuracy and reliability, thereby meeting the needs of various high-precision application scenarios.

[0067] In this embodiment of the invention, the logic circuit corresponding to each memory in the preset memory array is configured to perform integrated logic functions including weight processing, bias adjustment and activation function application to realize the function of the neuron.

[0068] In this embodiment of the invention, for example, within a server, a pre-defined memory array is a core component of the neural network. This array consists of multiple memories, each equipped with dedicated logic circuitry. These logic circuits are carefully designed and configured to perform a series of complex logical functions, thereby enabling the function of the neurons.

[0069] Specifically, when input data arrives at a memory location, the corresponding logic circuit first performs weighting processing. This means that it weights the input data according to the weight values ​​stored in the memory. For example, if the input data is a vector [x1,x2,x3], and the stored weights are [w1,w2,w3], then the logic circuit will calculate x1*w1 + x2*w2 + x3*w3.

[0070] Next, the logic circuit performs bias adjustment. It adds the previously calculated weighted sum to the bias value stored in memory, resulting in an adjusted value. This step ensures that the neuron's output can account for a variety of possible input scenarios, rather than being limited to a specific dataset.

[0071] Finally, the logic circuit applies an activation function. The purpose of the activation function is to map the adjusted value to a specific output range to ensure that the neuron's output is reasonable and meaningful. Common activation functions include ReLU and Sigmoid. In this step, the logic circuit performs the appropriate mapping operation on the adjusted value based on the activation function type stored in memory.

[0072] In this way, each memory and its corresponding logic circuit can independently perform the functions of a neuron, including weight processing, bias adjustment, and activation function application. This enables the server to efficiently process large amounts of input data and quickly generate accurate output results. Furthermore, because each memory operates independently, the server can easily scale its neural network to accommodate more complex computational needs.

[0073] To more clearly describe the solutions provided in the embodiments of this application, a more complete implementation method is provided below.

[0074] Please refer to the following: Figure 2 and Figure 3 , Figure 2 and Figure 3 This is a schematic diagram of the structure of a memory-based neural network provided in an embodiment of the present invention.

[0075] A complete neural network was constructed using memory-based logic circuits composed of memory arrays.

[0076] Neuron function is represented by a memory-based logic circuit.

[0077] This logic is implemented in the LUT (Look Up Table) of the FPGA.

[0078] A maximum of N / 4 neuron functions can be implemented in an N-bit input-output LUT.

[0079] Due to structural constraints, a fully connected neural network (FC) is impossible to implement.

[0080] Weights, biases, and activation functions are integrated.

[0081] Data and computations can be represented using truth tables (the truth table consists of weights, biases, and the results of activation functions).

[0082] The input data can directly drive the output activation.

[0083] Weights and biases do not need to be quantized.

[0084] By using memory-based logic circuits to construct the neural network, the need for high-speed computation and power-intensive logic circuits is eliminated. Neurons can function simply by accessing data in memory, achieving low power consumption and low cost.

[0085] Please refer to the following: Figure 4 and Figure 5 , Figure 4 A schematic diagram of neural network compaction provided in an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the compactification of a neural network based on memory logic circuits, as provided in an embodiment of the present invention. It can be seen that the original method of sparsifying the neural network involved pruning a fully associative network, removing parameters and neurons that do not affect accuracy. However, for the fully associative construction of a neural network, using a memory-based logic circuit array is highly suitable.

[0086] Please refer to the following: Figure 6 , Figure 6 A schematic block diagram of a memory-based neural network implementation device 110 provided in an embodiment of the present invention includes:

[0087] The acquisition module 1101 is used to acquire a preset memory array, the preset memory array including multiple memories connected according to a preset connection method; based on the preset neuron parameters stored in each memory; determine the neuron connection relationship based on the preset connection method; and execute the logical function corresponding to the preset neuron parameters of each memory based on the logic circuit corresponding to each memory.

[0088] The implementation module 1102 is used to construct the target neural network based on the preset neuron parameters, neuron connection relationships and the logical functions.

[0089] It should be noted that the implementation principle of the aforementioned memory-based neural network implementation device 110 can refer to the implementation principle of the aforementioned memory-based neural network implementation method, and will not be repeated here. It should be understood that the division of the various modules in the above device is merely a logical functional division; in actual implementation, they can be fully or partially integrated into a single physical entity, or physically separated. Furthermore, these modules can all be implemented in software through processing element calls; they can all be implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. For example, the memory-based neural network implementation device 110 can be a separately established processing element, or it can be integrated into a chip within the aforementioned device. Alternatively, it can be stored as program code in the memory of the aforementioned device, and called and executed by a processing element of the aforementioned device. The implementation of other modules is similar. Furthermore, these modules can be fully or partially integrated together, or implemented independently. The processing element described here can be an integrated circuit with signal processing capabilities. During implementation, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0090] For example, these modules can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs). As another example, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together to implement a system-on-a-chip (SOC).

[0091] This invention provides a computer device 100, which includes a processor and a non-volatile memory storing computer instructions. When the computer instructions are executed by the processor, the computer device 100 executes the aforementioned memory-based neural network implementation device 110. Figure 7 As shown, Figure 7 This is a structural block diagram of a computer device 100 provided in an embodiment of the present invention. The computer device 100 includes a memory-based neural network implementation device 110, a memory 111, a processor 112, and a communication unit 113.

[0092] To enable data transmission or interaction, the memory 111, processor 112, and communication unit 113 are electrically connected to each other directly or indirectly. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The memory-based neural network implementation device 110 includes at least one software function module that can be stored in the memory 111 or embedded in the operating system (OS) of the computer device 100 in the form of software or firmware. The processor 112 is used to execute the memory-based neural network implementation device 110 stored in the memory 111, such as the software function module and computer program included in the memory-based neural network implementation device 110.

[0093] This invention provides a readable storage medium, which includes a computer program. When the computer program runs, it controls the computer device where the readable storage medium is located to execute the aforementioned memory-based neural network implementation method.

[0094] For illustrative purposes, the foregoing description has been made with reference to specific embodiments. However, the foregoing illustrative discussions are not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Numerous modifications and variations are possible in accordance with the foregoing teachings. These embodiments were chosen and described in order to best illustrate the principles of the present disclosure and its practical application, thereby enabling those skilled in the art to best utilize the disclosure and to employ various embodiments with different modifications to suit a particular intended application.

Claims

1. A memory-based neural network implementation method, characterized in that, include: Obtain a preset memory array, the preset memory array comprising multiple memories connected according to a preset connection method; Based on the preset neuron parameters stored in each of the memories; The neuronal connection relationship is determined based on the preset connection method; The logic function of each memory is executed based on the logic circuit corresponding to each memory, which executes the preset neuron parameters corresponding to each memory. Based on the preset neuron parameters, neuron connectivity, and logical functions, a target neuron network is constructed.

2. The method according to claim 1, characterized in that, The logical function of executing the preset neuron parameters corresponding to each memory based on the logic circuit corresponding to each memory includes: The logical functions of the preset neuron parameters corresponding to each memory are executed based on the lookup table corresponding to each memory.

3. The method according to claim 2, characterized in that, The lookup table has N bits as input and output, and it implements N / 4 bits of neuron functionality.

4. The method according to claim 1, characterized in that, The preset connection method is a sparse connection method, which means that each neuron is connected to only a portion of other neurons.

5. The method according to claim 1, characterized in that, Each of the memories stores preset neuron parameters including weights, biases, and activation functions, which are integrated into a single logical unit for processing.

6. The method according to claim 5, characterized in that, The single logic unit uses a truth table to represent all the results under the combined effect of the weights, biases, and activation functions. The truth table lists all the input combinations and their corresponding outputs.

7. The method according to claim 6, characterized in that, The method further includes: The output activation is directly driven by the input data by looking up the predefined weights, biases, and activation functions stored in the truth table or lookup table.

8. The method according to claim 7, characterized in that, The predefined weights, biases, and activation functions retain their original, unquantized values.

9. The method according to claim 1, characterized in that, The logic circuits corresponding to each memory in the preset memory array are configured to perform integrated logic functions including weight processing, bias adjustment, and activation function application to realize the function of the neuron.

10. A memory-based neural network implementation device, characterized in that, include: An acquisition module is used to acquire a preset memory array, wherein the preset memory array includes multiple memories connected in a preset connection method; Based on the preset neuron parameters stored in each of the memories; The neuron connection relationship is determined based on the preset connection method; the logical function corresponding to the preset neuron parameters of each memory is executed based on the logic circuit corresponding to each memory. The implementation module is used to construct the target neural network based on the preset neuron parameters, neuron connection relationships, and the logical functions.

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