Pixel driving circuit and display panel

Abstract

The invention provides a pixel driving circuit and a display panel, and the pixel driving circuit comprises a third transistor, a sixth transistor, a third capacitor, and a first power voltage line. The third transistor and the sixth transistor are double-gate transistors; the first electrode of the third capacitor is connected to the midpoint of the third transistor and the midpoint of the sixth transistor, and the second electrode is connected to a first power supply voltage line. The display panel can reduce grid electric leakage of the driving transistor, reduce the low-frequency splash screen phenomenon of the display panel and improve the user experience.

Description

Technical Field

[0001] This invention relates to the field of display panel circuitry, and more specifically, to a pixel driving circuit and a display panel. Background Technology

[0002] Compared to traditional OLED display panels, AMOLED (Active-Matrix Organic Light-Emitting Diode) display panels offer advantages such as a wide color gamut, low power consumption, and thinness, thus attracting increasing attention from display technology developers. An AMOLED display panel comprises a pixel array and pixel driving circuitry that controls the pixel array. The light-emitting pixels in the pixel array emit light under the combined action of the pixel driving circuitry, scanning driving circuitry, and light-emitting driving circuitry.

[0003] In related technologies, during the display of a frame, the gate of the driving transistor in the pixel driving circuit of the AMOLED display panel has a voltage difference with the adjacent devices, resulting in continuous leakage between the gate and the adjacent devices. This leakage leads to changes in the brightness of the display panel, which can cause screen flickering at low refresh rates, affecting the user experience.

[0004] It should be noted that the information in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present invention provides a pixel driving circuit and a display panel to at least solve the screen flickering problem of the above-mentioned display panel.

[0006] One aspect of this invention provides a pixel driving circuit, comprising:

[0007] The first transistor has its first terminal connected to a data signal line, its second terminal connected to a fourth node, and its gate connected to a first scan signal line.

[0008] The second transistor has its first terminal connected to the first node, its second terminal connected to the third node, and its gate connected to the second node;

[0009] The third transistor has its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the second scan signal line; wherein, the third transistor is a dual-gate transistor.

[0010] The fourth transistor has its first terminal connected to the first power supply voltage line, its second terminal connected to the first node, and its gate connected to the first light-emitting signal line.

[0011] The fifth transistor has its first terminal connected to the third node and its gate connected to the second light-emitting signal line;

[0012] The sixth transistor has its first terminal connected to the second node, its second terminal connected to the first initial voltage line, and its gate connected to the third scan signal line; wherein, the sixth transistor is a dual-gate transistor.

[0013] The seventh transistor has its first terminal connected to the second initial voltage line, its second terminal connected to the second terminal of the fifth transistor, and its gate connected to the fourth scan signal line;

[0014] The eighth transistor has its first terminal connected to the first node, its second terminal connected to the third initial voltage line, and its gate connected to the fourth scan signal line.

[0015] The ninth transistor has its first terminal connected to the fourth node, its second terminal connected to the fourth initial voltage line, and its gate connected to the second scan signal line;

[0016] The second capacitor has its first terminal connected to the fourth node and its second terminal connected to the second node.

[0017] The third capacitor has its first terminal connected to the midpoint of the third transistor and the midpoint of the sixth transistor, and its second terminal connected to the first power supply voltage line.

[0018] A light-emitting diode, wherein the first terminal of the light-emitting diode is connected to the second terminal of the fifth transistor, and the second terminal is connected to the second power supply voltage line.

[0019] In some embodiments, the pixel driving circuit further includes:

[0020] A first capacitor, wherein the first terminal of the first capacitor is connected to the fourth node, and the second terminal is connected to the first power supply voltage line.

[0021] In some embodiments, the first transistor and the ninth transistor are dual-gate transistors; the first transistor to the ninth transistor are all P-type MOS transistors.

[0022] In some embodiments, within one frame time, the first scan signal line, the second scan signal line, the third scan signal line, and the fourth scan signal line respectively provide the pixel driving circuit with a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal of the same frequency.

[0023] In some embodiments, within one frame, the duration of the low potential of the second scan signal is greater than that of the first scan signal, the third scan signal, and the fourth scan signal.

[0024] In some embodiments, within one frame time, the first light-emitting signal line and the second light-emitting signal line respectively provide the pixel driving circuit with a first light-emitting signal and a second light-emitting signal of the same frequency.

[0025] In some embodiments, within a frame time, the high-potential period of the first luminous signal is included within the high-potential period of the second luminous signal.

[0026] In some embodiments, within one frame time, the low-potential period of the fourth scanning signal is included within the high-potential period of the first luminous signal;

[0027] Within one frame, the low-potential periods of the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are all included within the high-potential period of the second light-emitting signal.

[0028] In some embodiments, the first scanning signal and the first light emission signal have the same frequency.

[0029] Another aspect of the present invention provides a display panel including the pixel driving circuit described above.

[0030] The pixel driving circuit and display panel of the present invention reduce leakage current at the second node, reduce potential changes at the second node, and reduce brightness changes at the display panel by connecting the midpoint of the third transistor and the midpoint of the sixth transistor together and adding a third capacitor between them and the first power supply voltage line, thereby reducing low-frequency flickering of the display panel and improving user experience.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0033] Figure 1 This is a brightness curve of a display panel with a refresh rate of 60Hz for related technologies;

[0034] Figure 2 yes Figure 1 Brightness curve of the display panel at a refresh rate of 30Hz;

[0035] Figure 3 yes Figure 1 A graph showing the gate potential curve of the driving transistor when the refresh rate of the display panel is 30Hz.

[0036] Figure 4 This is a schematic diagram of the overall circuit structure of a display panel according to an embodiment of the present invention;

[0037] Figure 5 yes Figure 4 Circuit diagram of the mid-pixel driving circuit;

[0038] Figure 6 yes Figure 5 Waveform diagram of the mid-pixel driving circuit during operation;

[0039] Figure 7 yes Figure 6 A schematic diagram of the working state of the pixel driving circuit in stage t1;

[0040] Figure 8 yes Figure 6 A schematic diagram of the working state of the pixel driving circuit in the t2 stage;

[0041] Figure 9 yes Figure 6 A schematic diagram of the working state of the pixel driving circuit in the t3 stage;

[0042] Figure 10 yes Figure 6 A schematic diagram of the working state of the pixel driving circuit in the t4 stage.

[0043] Figure 11 yes Figure 4 Potential curves at the midpoint of the second node and the third transistor;

[0044] Figure 12 This is a schematic diagram of a display panel according to an embodiment of the present invention.

[0045] Figure label:

[0046] 11-pixel driving circuit

[0047] T1 First Transistor

[0048] T2 second transistor

[0049] T3 Third Transistor

[0050] T4 fourth transistor

[0051] T5 fifth transistor

[0052] T6 sixth transistor

[0053] T7 Seventh Transistor

[0054] T8 Eighth Transistor

[0055] T9 Ninth Transistor

[0056] C1 First capacitor

[0057] C2, the second capacitor

[0058] C3 Third capacitor

[0059] D Light Emitting Diode

[0060] N1 First Node

[0061] N2 Second Node

[0062] N3 Third Node

[0063] N4 Fourth Node

[0064] SN1 First Scan Signal Line

[0065] SN2 Second Scan Signal Line

[0066] SN3 Third Scan Signal Line

[0067] SN4 Fourth Scan Signal Line

[0068] EM1 First Light-Emitting Signal Line

[0069] EM2 Second Light-Emitting Signal Line

[0070] Data signal line

[0071] ELVDD First power supply voltage line

[0072] ELVSS Second Power Supply Voltage Line

[0073] Vint1 First Initial Voltage Line

[0074] Vint2 Second Initial Voltage Line

[0075] Vint3 Third Initial Voltage Line

[0076] Vint4 Fourth Initial Voltage Line

[0077] 10 Display Panel Detailed Implementation

[0078] To make the technical problems solved by the present invention, the technical solutions adopted, and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0079] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, modules, apparatuses, steps, etc., can be employed. In other instances, well-known modules, methods, apparatuses, implementations, steps, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0080] like Figure 1 and Figure 2 As shown, in related technologies, the brightness of a display panel changes by ΔLV. (nit) within one frame. The brightness increases by ΔLV. when switching between adjacent frames, resulting in a brightness jump. When the display panel's refresh rate is high (e.g., 60Hz), this brightness jump is not noticeable to the human eye. However, when the display panel's refresh rate is low (e.g., 30Hz), this brightness jump is more noticeable to the human eye, resulting in screen flickering.

[0081] like Figure 3 As shown, specifically, the brightness variation of the aforementioned display panel is caused by gate leakage of the driving transistor in the pixel driving circuit. During the display of one frame, due to the voltage difference between the gate of the driving transistor and adjacent devices, a continuous leakage phenomenon occurs between the gate and adjacent devices, causing the potential to drop by ΔV. When switching between adjacent frames, the potential increases by ΔV, resulting in a brightness jump. This potential change of ΔV caused by gate leakage leads to a change in the display panel's brightness ΔLV. At low refresh rates, this brightness variation can cause screen flickering, affecting the user experience.

[0082] Through meticulous and in-depth research, the inventors of this invention have provided a solution to the problems existing in the prior art. This invention provides a pixel driving circuit and a display panel. The pixel driving circuit includes: a third transistor, a sixth transistor, a third capacitor, and a first power supply voltage line; both the third and sixth transistors are dual-gate transistors; the first terminal of the third capacitor is connected to the midpoint of both the third and sixth transistors, and the second terminal is connected to the first power supply voltage line. This invention can reduce gate leakage current of the driving transistors, reduce low-frequency screen flicker in the display panel, and improve the user experience.

[0083] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0084] like Figure 4 As shown, the overall circuit of the display panel of the present invention includes: a scanning driving circuit, a light-emitting driving circuit, a data driver, a timing controller, and a pixel driving circuit 11. Figure 4 The area within the dashed line is the display area, and the area outside the dashed line is the non-display area. The scan driving circuit, light-emitting driving circuit, data driver, and timing controller are all located in the non-display area, while the pixel driving circuit 11 is located in the display area.

[0085] Specifically, the scan driving circuit leads out multiple scan signal lines SN and connects them to the pixel driving circuit 11 to provide scan signals to the pixel driving circuit 11. The light-emitting driving circuit leads out multiple light-emitting signal lines EM and connects them to the pixel driving circuit 11 to provide light-emitting signals to the pixel driving circuit 11. The data driver leads out multiple data signal lines Data and connects them to the pixel driving circuit 11 to provide data signals to the pixel driving circuit 11. The display panel includes multiple pixel driving circuits 11 arranged in an array. Under the combined action of the scan signals, light-emitting signals, and data signals, the pixel driving circuit 11 controls the light-emitting state of the light-emitting pixels.

[0086] like Figure 5 As shown, one aspect of the present invention provides a pixel driving circuit 11, which is a 9T3C circuit, that is, a circuit containing 9 transistors and 3 capacitors.

[0087] Specifically, the first transistor T1 has its first terminal connected to the data signal line Data, its second terminal connected to the fourth node N4, and its gate connected to the first scan signal line SN1. The second transistor T2 has its first terminal connected to the first node N1, its second terminal connected to the third node N3, and its gate connected to the second node N2. The third transistor T3 has its first terminal connected to the second node N2, its second terminal connected to the third node N3, and its gate connected to the second scan signal line SN2. The fourth transistor T4 has its first terminal connected to the first power supply voltage line ELVDD, its second terminal connected to the first node N1, and its gate connected to the first light emission signal line EM1. The fifth transistor T5 has its first terminal connected to the third node N3, and its gate connected to the second light emission signal line EM2. The sixth transistor T6 has its first terminal connected to the second node N2, its second terminal connected to the first initial voltage line Vint1, and its gate connected to the third scan signal line SN3. The seventh transistor T7 has its first terminal connected to the second initial voltage line Vint2, its second terminal connected to the second terminal of the fifth transistor T5, and its gate connected to the fourth scan signal line SN4. The eighth transistor T8 has its first terminal connected to the first node N1, its second terminal connected to the third initial voltage line Vint3, and its gate connected to the fourth scan signal line SN4. The ninth transistor T9 has its first terminal connected to the fourth node N4, its second terminal connected to the fourth initial voltage line Vint4, and its gate connected to the second scan signal line SN2. The first capacitor C1 has its first terminal connected to the fourth node N4, and its second terminal connected to the first power supply voltage line ELVDD. The second capacitor C2 has its first terminal connected to the fourth node N4, and its second terminal connected to the second node N2. The first terminal of the light-emitting diode D is connected to the second terminal of the fifth transistor T5, and its second terminal is connected to the second power supply voltage line ELVSS.

[0088] Furthermore, both the third transistor T3 and the sixth transistor T6 are dual-gate transistors. The first terminal of the third capacitor C3 is connected to the midpoint of the third transistor T3 and the midpoint of the sixth transistor T6, respectively, and the second terminal is connected to the first power supply voltage line ELVDD. By connecting the midpoints of the third transistor T3 and the sixth transistor T6 together and adding a third capacitor C3 between them and the first power supply voltage line ELVDD, this application can reduce the drain-source voltage difference VDS between the third transistor T3 and the sixth transistor T6, thereby reducing the leakage current of the third transistor T3 and the sixth transistor T6. At the same time, it can also reduce the voltage difference between the second node N2 (i.e., the gate of the driving transistor of the pixel driving circuit 11 in this embodiment) and the midpoints of the third transistor T3 and the sixth transistor T6, thereby reducing the leakage current from the second node N2 to the first initial voltage line Vint1 and the third node N3, reducing the potential change of the second node N2, reducing the brightness change of the display panel, and thus reducing the low-frequency flicker phenomenon of the display panel and improving the user experience.

[0089] In some embodiments, in addition to the third transistor T3 and the sixth transistor T6, the first transistor T1 and the ninth transistor T9 are also dual-gate transistors. In the pixel driving circuit 11, the use of dual-gate transistors in the above-mentioned transistors has several major advantages over ordinary single-gate transistors: higher driving capability, as dual-gate transistors have two gates and can simultaneously control one channel, providing higher driving current and thus improving the response speed of the pixel driving circuit 11; better control characteristics, as the dual-gate structure can better control the switching of current, thereby reducing leakage current and improving switching speed and efficiency; and lower power consumption, as the structure of the dual-gate transistor allows it to more effectively prevent leakage current in the off state, thereby reducing the static power consumption of the pixel driving circuit 11.

[0090] In some embodiments, the first transistor T1 to the ninth transistor T9 are all P-type MOSFETs. A P-type MOSFET, also called a PMOS transistor, is short for Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The control terminal of a PMOS transistor is the gate, its first terminal is the source, and its second terminal is the drain, or vice versa. The on-state level of a PMOS transistor is low, and its off-state level is high. In other embodiments, those skilled in the art will readily recognize that the pixel driving circuit 11 provided by this invention can be easily modified to use only N-type MOSFETs or hybrid CMOS transistors. It should be noted that the high and low voltage levels during transistor on- and off-state operations described below are based on PMOS transistors; when other appropriate transistor types are selected according to design requirements, their on- and off-state high and low voltage levels will also change accordingly.

[0091] In some embodiments, the light-emitting diode D can be an OLED (Organic Light Emitting Diode) or an AMOLED. The first electrode of the light-emitting diode D is the anode, and the second electrode is the cathode. In addition, the first power supply voltage line ELVDD provides a positive power supply voltage to the pixel driving circuit 11, and the second power supply voltage line ELVSS provides a negative power supply voltage to the pixel driving circuit 11, but this is not a limitation.

[0092] In some embodiments, the first initial voltage line Vint1, the second initial voltage line Vint2, the third initial voltage line Vint3, and the fourth initial voltage line Vint4 provide a first initial voltage, a second initial voltage, a third initial voltage, and a fourth initial voltage to the pixel driving circuit 11, respectively. Furthermore, the first initial voltage, the second initial voltage, the third initial voltage, and the fourth initial voltage are constant. Moreover, the first initial voltage, the second initial voltage, the third initial voltage, and the fourth initial voltage can be selected by the pixel driving circuit 11 to meet different display requirements; this invention does not impose limitations in this regard. Specifically, the first initial voltage and the second initial voltage can be low potentials, and the third initial voltage and the fourth initial voltage can be high potentials.

[0093] like Figure 6 As shown, in some embodiments, within one frame, the first scan signal line SN1, the second scan signal line SN2, the third scan signal line SN3, and the fourth scan signal line SN4 provide the pixel driving circuit 11 with first scan signals, second scan signals, third scan signals, and fourth scan signals of the same frequency, respectively. Furthermore, within the same period, each of the first scan signal, second scan signal, third scan signal, and fourth scan signal has only one low-level period, and the four low-level periods do not overlap. In addition, the four low levels, in chronological order, belong to the third scan signal, second scan signal, first scan signal, and fourth scan signal, respectively.

[0094] Continue to refer to Figure 6 In some embodiments, within one frame, the duration of the low level of the second scan signal is longer than that of the first, third, and fourth scan signals. The low-level durations of the first, third, and fourth scan signals are the same. Specifically, the period of low level of the second scan signal can be the compensation phase of the pixel driving circuit 11. The above setting can make the compensation effect of the pixel driving circuit 11 on the second transistor T2, i.e., the driving transistor, better.

[0095] Continue to refer to Figure 6 In some embodiments, within one frame time, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 respectively provide the pixel driving circuit 11 with a first light-emitting signal and a second light-emitting signal of the same frequency.

[0096] Continue to refer to Figure 6 In some embodiments, within one frame of a picture, the high-potential period of the first light-emitting signal is included in the high-potential period of the second light-emitting signal.

[0097] Continue to refer to Figure 6 In some embodiments, within one frame time, the low-potential period of the fourth scan signal is included in the high-potential period of the first light emission signal;

[0098] Continue to refer to Figure 6 Within one frame, the low-potential periods of the first, second, third, and fourth scan signals are all included within the high-potential period of the second light-emitting signal.

[0099] Continue to refer to Figure 6 In some embodiments, the first scanning signal and the first light-emitting signal have the same frequency. Specifically, the first scanning signal, the second scanning signal, the third scanning signal, and the fourth scanning signal have only one low-level period within one frame, and the first light-emitting signal and the second light-emitting signal also have only one high-level period.

[0100] Specifically, the pixel driving circuit 11 can operate at a low frequency, where low frequency means an operating frequency less than 60Hz, but the minimum operating frequency is 1Hz, though not limited to this. Figure 6 This can be a timing diagram of the pixel driving circuit 11 of the present invention operating at a frequency of 30Hz, with black insertion and one emission per frame.

[0101] Continue to refer to Figure 6 In this embodiment, the operation of the pixel driving circuit 11 is divided into four stages, t1 to t4, within one frame of the displayed image. During these four stages, the light-emitting diode D in the pixel driving circuit 11 completes one cycle from black insertion to light emission. The following section combines... Figure 6 waveform diagram and Figure 5 The circuit diagram is used to analyze the relationship between the input / output and light emission of the pixel driving circuit 11 in the above four processes:

[0102] like Figure 6 and Figure 7 As shown, in stage t1, the third scan signal line SN3 and the first light-emitting signal line EM1 are input at a low level, while the first scan signal line SN1, the second scan signal line SN2, the fourth scan signal line SN4, and the second light-emitting signal line EM2 are input at a high level. The first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off, while the fourth transistor T4 and the sixth transistor T6 are turned on. In this stage, the first initial voltage line Vint1 writes a low potential to the second node N2 through the sixth transistor T6. Since the second node N2 is also the gate of the second transistor T2, and the second transistor T2 is also the driving transistor that directly drives the light-emitting diode D to emit light, this stage can be considered the reset stage of the pixel driving circuit 11. The first initial voltage line Vint1 writes a low potential to the second node N2 to reset the second transistor T2. Furthermore, in this stage, since the fifth transistor T5 is turned off, the light-emitting diode D does not emit light.

[0103] like Figure 6 and Figure 8 As shown, in stage t2, the second scan signal line SN2 and the first light-emitting signal line EM1 are input at a low level, while the first scan signal line SN1, the third scan signal line SN3, the fourth scan signal line SN4, and the second light-emitting signal line EM2 are input at a high level. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off, while the third transistor T3, the fourth transistor T4, and the ninth transistor T9 are turned on. In this stage, the fourth initial voltage line Vint4 writes a high potential to the fourth node N4 through the ninth transistor T9, and the first power supply voltage line ELVDD writes a high potential to the first node N1 through the fourth transistor T4. At this time, the potential of the second node N2 is the potential of the first power supply voltage line ELVDD plus the threshold voltage VTH of the second transistor T2, i.e., V... N2 =ELVDD+VTH. Furthermore, in this stage, since the fifth transistor T5 is turned off, the light-emitting diode D does not emit light. Specifically, this stage can be the compensation stage of the pixel driving circuit 11. By setting the low potential period of the second scan signal line SN2 to be longer than the low potential periods of the first scan signal line SN1, the third scan signal line SN3, and the fourth scan signal line SN4, the compensation effect of the pixel driving circuit 11 for the second transistor T2, i.e., the driving transistor, can be improved.

[0104] like Figure 6 and Figure 9 As shown, in stage t3, the first scan signal line SN1 and the first light-emitting signal line EM1 are input at a low level, while the second scan signal line SN2, the third scan signal line SN3, the fourth scan signal line SN4, and the second light-emitting signal line EM2 are input at a high level. The third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off, while the first transistor T1 and the fourth transistor T4 are turned on. In this stage, the data signal line Data writes a potential to the fourth node N4 through the first transistor T1. The potential of the fourth node N4 changes from the high potential of the fourth initial voltage line Vint4 in stage t2 to the potential of the data signal line Data, i.e., V. N4 =V Data The potential change of N4 is Data - Vint4. At this time, due to the presence of the second capacitor C2, the potential of the second node N2 is the potential at stage t2 plus the potential change of the fourth node N4, which is V. N2 =ELVDD+VTH+V Data -Vint4. Furthermore, in this stage, since the fifth transistor T5 is turned off, the LED D does not emit light.

[0105] like Figure 6 and Figure 10 As shown, in stage t4, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are input at a low level, while the first scan signal line SN1, the second scan signal line SN2, the third scan signal line SN3, and the fourth scan signal line SN4 are input at a high level. The first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on. In this stage, due to the presence of the second capacitor C2, the potential of the second node N2 remains the same as in the previous stage, i.e., V. N2 =ELVDD+VTH+V Data -Vint4. Furthermore, in this stage, since the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on, current flows from the first power supply voltage line ELVDD through the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the light-emitting diode D, reaching the second power supply voltage line ELVSS, thus causing the light-emitting diode D to emit light. Specifically, the current I flowing through the second transistor T2... T2 =K(VGS-VTH) 2 =K(V) N2 -ELVDD-VTH) 2 =K(ELVDD+VTH+V) Data -Vint4-ELVDD-VTH) 2 =K(V) Data -Vint4) 2 , where K is the current calculation coefficient of the second transistor T2.

[0106] like Figure 11 As shown, the three curves in stage t3, from top to bottom, represent: the potential change curve at the midpoint of the third transistor T3 in the related art, the potential change curve at the midpoint of the third transistor T3 in this invention, and the potential change curve of the second node N2 in this invention. Wherein, ΔV1 is the voltage difference between the midpoint of the second node N2 and the third transistor T3 in the related art, and ΔV2 is the voltage difference between the midpoint of the second node N2 and the third transistor T3 in this invention.

[0107] It should be noted that by connecting the midpoint of the third transistor T3 and the midpoint of the sixth transistor T6 together, and adding a third capacitor C3 between them and the first power supply voltage line ELVDD, the potentials of the midpoints of the third transistor T3 and the sixth transistor T6 are the same. This reduces the drain-source voltage difference VDS between the third transistor T3 and the sixth transistor T6, thereby reducing the leakage current of the third transistor T3 and the sixth transistor T6. In other words, it reduces the voltage difference between the second node N2 (i.e., the gate of the driving transistor of the pixel driving circuit 11 in this embodiment) and the midpoints of the third transistor T3 and the sixth transistor T6 (i.e., ΔV2 < ΔV1), thereby reducing the leakage current from the second node N2 to the first initial voltage line Vint1 and the third node N3.

[0108] Furthermore, because this application reduces leakage current from the second node N2 to the first initial voltage line Vint1 and the third node N3, it reduces the brightness variation of the display panel caused by the potential change of the second node N2 (driving transistor gate). Therefore, this invention can reduce screen flicker caused by brightness changes during low-frequency display, thus improving the user experience.

[0109] like Figure 12 As shown, based on the same inventive concept, another aspect of the present invention provides a display panel 10, including the pixel driving circuit 11 described above. This display panel 10 can be applied to any product or component with display function, such as mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, and navigators. Specific implementations of this display panel 10 can be found in the embodiments of the pixel driving circuit 11 described above; repeated technical solutions and effects will not be repeated here.

[0110] In summary, the pixel driving circuit and display panel of the present invention reduce leakage current at the second node, reduce potential changes at the second node, and reduce brightness changes at the display panel by connecting the midpoint of the third transistor and the midpoint of the sixth transistor together and adding a third capacitor between them and the first power supply voltage line, thereby reducing low-frequency flickering of the display panel and improving user experience.

[0111] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A pixel driving circuit, characterized in that, include: The first transistor has its first terminal connected to a data signal line, its second terminal connected to a fourth node, and its gate connected to a first scan signal line. The second transistor has its first terminal connected to the first node, its second terminal connected to the third node, and its gate connected to the second node; The third transistor has its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the second scan signal line; wherein, the third transistor is a dual-gate transistor. The fourth transistor has its first terminal connected to the first power supply voltage line, its second terminal connected to the first node, and its gate connected to the first light-emitting signal line. The fifth transistor has its first terminal connected to the third node and its gate connected to the second light-emitting signal line; The sixth transistor has its first terminal connected to the second node, its second terminal connected to the first initial voltage line, and its gate connected to the third scan signal line; wherein, the sixth transistor is a dual-gate transistor. The seventh transistor has its first terminal connected to the second initial voltage line, its second terminal connected to the second terminal of the fifth transistor, and its gate connected to the fourth scan signal line; The eighth transistor has its first terminal connected to the first node, its second terminal connected to the third initial voltage line, and its gate connected to the fourth scan signal line. The ninth transistor has its first terminal connected to the fourth node, its second terminal connected to the fourth initial voltage line, and its gate connected to the second scan signal line; The second capacitor has its first terminal connected to the fourth node and its second terminal connected to the second node. The third capacitor has its first terminal connected to the midpoint of the third transistor and the midpoint of the sixth transistor, and its second terminal connected to the first power supply voltage line. A light-emitting diode, wherein the first terminal of the light-emitting diode is connected to the second terminal of the fifth transistor, and the second terminal is connected to the second power supply voltage line.

2. The pixel driving circuit according to claim 1, characterized in that, Also includes: A first capacitor, wherein the first terminal of the first capacitor is connected to the fourth node, and the second terminal is connected to the first power supply voltage line.

3. The pixel driving circuit according to claim 1, characterized in that, The first transistor and the ninth transistor are dual-gate transistors; all of the first transistor to the ninth transistor are P-type MOS transistors.

4. The pixel driving circuit according to claim 1, characterized in that, Within one frame, the first scan signal line, the second scan signal line, the third scan signal line, and the fourth scan signal line respectively provide the pixel driving circuit with a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal of the same frequency.

5. The pixel driving circuit according to claim 4, characterized in that, Within one frame, the duration of the low potential of the second scan signal is greater than that of the first scan signal, the third scan signal, and the fourth scan signal.

6. The pixel driving circuit according to claim 4, characterized in that, Within one frame, the first light-emitting signal line and the second light-emitting signal line respectively provide the pixel driving circuit with a first light-emitting signal and a second light-emitting signal of the same frequency.

7. The pixel driving circuit according to claim 6, characterized in that, Within one frame, the high-potential period of the first luminous signal is included within the high-potential period of the second luminous signal.

8. The pixel driving circuit according to claim 6, characterized in that, Within one frame, the low-potential period of the fourth scanning signal is included within the high-potential period of the first luminous signal; Within one frame, the low-potential periods of the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are all included within the high-potential period of the second light-emitting signal.

9. The pixel driving circuit according to claim 6, characterized in that, The first scanning signal and the first light emission signal have the same frequency.

10. A display panel, characterized in that, Includes the pixel driving circuit according to any one of claims 1 to 9.

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