Memory storage device and reading method thereof
By introducing a combination of signed and selected memory cells into the memory cell array, the controller circuit simultaneously reads and judges the memory cells, solving the problem of memory cell read failure and improving the reliability and stability of reading.
Patent Information
- Application Number
- CN202510148944.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-20
- Filing Date
- 2025-02-11
- Publication Date
- 2026-03-03
AI Technical Summary
In existing technologies, storage cells are susceptible to power noise and power degradation during the reading process, leading to read failures.
The controller circuit uses a combination of signing and selection storage units. It reads both the signing and selection storage units simultaneously, and after the signing storage unit is successfully read, the selection storage unit is also considered successfully read.
This improves the accuracy of reading from storage units, reduces the impact of power noise and power degradation on reading results, and ensures the reliability of data reading.
Smart Images
Figure CN121600981A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an electronic device and its operating method, and more particularly to a memory storage device and its reading method. Background Technology
[0002] Taking flash memory as an example, when the controller circuit reads the memory cell array, it first reads one memory cell. Only after successfully reading that memory cell does it begin reading other memory cells. However, this reading method may result in the initial memory cell being successfully read, but subsequent readings of other memory cells may fail due to power noise and power degradation. Summary of the Invention
[0003] This invention provides a memory storage device and a method for reading the same, which can accurately read the storage unit.
[0004] The present invention provides a memory storage device, comprising a storage cell array and a controller circuit. The storage cell array includes signature cells and option cells. The controller circuit is coupled to the storage cell array. The controller circuit is used to simultaneously read the signature cells and option cells. When a signature cell read is successful, the controller circuit determines that the read of the option cell is successful.
[0005] The reading method of the memory storage device of the present invention includes: applying a word line signal to a word line to simultaneously read a signed storage unit and a selected storage unit, wherein the signed storage unit and the selected storage unit are located on the word line; determining whether the signed storage unit has been read successfully; and when the signed storage unit has been read successfully, determining that the selected storage unit has also been read successfully. Attached Figure Description
[0006] Figure 1 A block diagram of a memory storage device according to an embodiment of the present invention is shown;
[0007] Figure 2 A block diagram illustrating another embodiment of the memory storage device of the present invention;
[0008] Figure 3A Show Figure 2 A schematic diagram of the storage cell array in the embodiment;
[0009] Figure 3B A schematic diagram of a storage cell array according to another embodiment of the present invention is shown;
[0010] Figure 4 A schematic diagram showing the waveforms of word line signals and address signals according to an embodiment of the present invention is provided.
[0011] Figure 5 A flowchart illustrating the steps of a method for reading a memory storage device according to an embodiment of the present invention is shown.
[0012] Figure 6 A waveform diagram of word line signals and address signals according to another embodiment of the present invention is shown;
[0013] Figure 7 A flowchart illustrating the steps of a method for reading a memory storage device according to another embodiment of the present invention is shown. Detailed Implementation
[0014] Taking flash memory as an example, Figure 1 The power-on sequence of the memory storage device 100 is described below. First, the power-up detection circuit 110 detects the power supply VCC and outputs a power-up signal PU accordingly. The power-up signal PU is used to activate the bandgap reference circuit 120, causing it to generate a reference voltage VREF for the charge pump circuit 130 and the regulator circuit 140. The charge pump circuit 130 generates a high voltage signal VH based on the reference voltage VREF. Next, the regulator circuit 140 generates a voltage signal RVPP based on the reference voltage VREF and the high voltage signal VH. The voltage signal RVPP can be provided to the word line decoder circuit as an operating voltage.
[0015] refer to Figure 2 and Figure 3A The memory storage device 200 includes a memory cell array 210, a controller circuit 220, a bit switch circuit 230, a word line decoder circuit 240, a sense amplifier circuit 250, and a comparator circuit 260. The controller circuit 220 is coupled to the memory cell array 210.
[0016] The memory cell array 210 includes a plurality of signed memory cells 212 and a plurality of select memory cells 214. Taking the word line WL0 as an example, the memory cell group 211_0 corresponding to the same address signal Y[0] includes N memory cells, among which M memory cells are signed memory cells 212 and N-M memory cells are select memory cells 214. Here, M and N are positive integers, and M < N. In one embodiment, the memory cell group 211_0 includes 32 memory cells, among which 4 memory cells are signed memory cells and 28 memory cells are select memory cells. Alternatively, in another embodiment, the memory cell group 211_0 includes 32 memory cells, among which 8 memory cells are signed memory cells and 24 memory cells are select memory cells. The memory cell groups 211_1, 211_2, and 211_3 corresponding to the address signals Y[1], Y[2], and Y[3] can be类推. The quantities of the above-mentioned memory cells and address signals are not used to limit the present invention. The signed memory cells 212 are used to store specific data, for example. These specific data must be read during the power-on startup process. Generally, during the execution of the power-on startup read operation, applying an appropriate read voltage can ensure correct data reading.
[0017] Therefore, when the word line WL0 is enabled, the signed memory cells 212 and the select memory cells 214 selected by the address signals Y[0] to Y[3] can be read simultaneously. Similarly, when the remaining word lines WL1 to WLk are enabled, the signed memory cells 212 and the select memory cells 214 selected by the address signals Y[0] to Y[3] are also read simultaneously. The quantity of the above-mentioned word lines is not used to limit the present invention.
[0018] The word line decoder circuit 240 is coupled to the memory cell array 210 through a plurality of word lines WL0 to WLk. The word line decoder circuit 240 is used to output a plurality of word line signals WL[0] to WL[k] to enable the corresponding word lines WL0 to WLk respectively. The controller circuit 220 can control the word line decoder circuit 240 to output word line signals to apply the word line signals to the corresponding word lines. The memory storage device 200 can generate a voltage signal RVPP for the word line decoder circuit 240 as an operating voltage by using, for example, Figure 1 the power-on startup process. The bit switch circuit 230 is coupled to the memory cell array 210 through bit lines BL. The controller circuit 220 is used to output address signals Y[0] to Y[3] to select the memory cells to be read.
[0019] Figure 3A The layout manner of the memory cell array 210 of Figure 3B , Figure 3BThe layout of another memory cell array 310 is shown. The memory cell array 310 includes memory cell groups 311_0, 311_1, 311_2, and 311_3 corresponding to address signals Y[0], Y[1], Y[2], and Y[3]. Each memory cell group includes multiple signing memory cells 312 and selection memory cells 314. Figure 3B In this context, the memory cell group on each word line does not correspond to the same address signal. For example, the memory cell group 311_0 on word line WL0 corresponds to the address signal Y[0], and the memory cell group 311_1 on word line WL1 corresponds to the address signal Y[1].
[0020] In this embodiment, when word line WL0 is enabled, the signature storage unit 312 and the selection storage unit 314 selected by the address signal Y[0] are read simultaneously. When word line WL1 is enabled, the signature storage unit 312 and the selection storage unit 314 selected by the address signal Y[1] are also read simultaneously. The reading situation corresponding to other word lines being enabled can be deduced in the same way.
[0021] Figure 3A and Figure 3B The layout of the memory cell arrays 210 and 310 is for illustrative purposes only and is not intended to limit the invention. The distribution of the memory cell group in the memory cell array can be as follows: Figure 3A and Figure 3B Any combination of these, meaning each word line can have one or more memory cell groups. Figure 3A and Figure 3B The layout of the storage cell arrays 210 and 310 are only two possible exemplary embodiments.
[0022] about Figure 1 and Figure 2 The hardware structure of the components includes a controller circuit 220 that can be a processor with computing capabilities. Alternatively, the controller circuit 220 can be designed using a hardware description language (HDL) or any other digital circuit design method familiar to those skilled in the art, and can be a hardware circuit implemented using a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC). Furthermore, sufficient teaching, advice, and implementation instructions can be obtained regarding the hardware structure of the word-line decoder circuit 240, the sense amplifier circuit 250, and the comparator circuit 260 based on general knowledge in the art.
[0023] In addition, Figure 3A and Figure 3B The number of word lines, bit lines, memory cells, and memory cell groups is for illustrative purposes only and is not intended to limit the invention.
[0024] refer to Figures 2 to 4 During the power-on reading period, the controller circuit 220 simultaneously reads the data D1 and D2 of the signature storage unit 212 and the signature storage unit 214 located on the same word line until the signature storage unit 212 is successfully read.
[0025] Specifically, during the power-on reading period, the controller circuit 220 reads the data D1 from the signature storage unit 212, which is sensed by the sense amplifier circuit 250. Then, the comparator circuit 260 determines whether the read data D1 is correct. If the read data D1 is correct, it means that the signature storage unit 212 has been read successfully. Conversely, if the read data D1 is incorrect, it means that the signature storage unit 212 has failed to be read.
[0026] exist Figure 4 In the middle, the word line decoder circuit 240 outputs word line signals WL[0] and WL[1] to turn on word lines WL0 and WL1. The remaining word line signals can be deduced similarly. Word line turn-on means that the word line signal applied to the word line is during the enable period, such as during a high or low level. Figure 4 In the middle, the high level period of word line signals WL[0] and WL[1] is the enable period.
[0027] by Figure 3A Taking the first word line WL0 as an example, the signing storage unit 212 and the selection storage unit 214 are located on the first word line WL0. The controller circuit 220 is used to apply the first word line signal WL[0] to the first word line WL0 to read the data D1 and D2 of the signing storage unit 212 and the selection storage unit 214 simultaneously multiple times until the signing storage unit 212 has been read successfully.
[0028] The first word line signal WL[0] includes multiple enable periods T1. The duration of each enable period T1 is the same. During each enable period T1, the controller circuit 220 outputs address signals Y[0]~Y[n] sequentially to read data D1 and D2 located on the first word line WL0 in the read signature storage unit 212 and the selection storage unit 214. Furthermore, in Figure 4 In the above, the address signals Y[0] to Y[n] have the same width, where n is an integer greater than 0.
[0029] In this embodiment, the controller circuit 220 toggles the first word line signal WL[0] multiple times to read data, indicating that when the signing memory unit 212 fails to read, the first word line signal WL[0] will be re-enabled. That is, the multiple enable periods T1 of the first word line signal WL[0] are discontinuous; between each read, the first word line WL[0] is not conducting. Figure 4 In this process, the controller circuit 220 simultaneously performs a first read 410_1 on the signature storage unit 212 and the selection storage unit 214 on the first word line WL0. If either signature storage unit 212 fails to read, the controller circuit 220 will re-enable the first word line signal WL[0] and read the signature storage unit 212 and the selection storage unit 214 on the first word line WL0 again. Then, in the m-th read 410_m, the controller circuit 220 determines that the signature storage unit 212 has been read successfully, where m is an integer greater than 1. In this read, when the signature storage unit 212 is read successfully, the controller circuit 220 will also determine that the read of the selection storage unit 214 has been successfully completed. That is, the controller circuit 220 considers the data D2 read from the selection storage unit 214 to be correct.
[0030] Next, when the signature storage unit 212 located on the first word line WL0 is read, the controller circuit 220 applies the second word line signal WL[1] to the second word line WL1 to read the data D1 and D2 of the signature storage unit 212 and the selection storage unit 214 located on the second word line WL1. The controller circuit 220 can read the storage units of other word lines in the same way.
[0031] refer to Figures 2 to 5 The memory storage device reading method of this embodiment is at least suitable for Figure 2 The present invention includes a memory storage device 200, but is not limited thereto.
[0032] Taking the memory storage device 200 as an example, in step S100, the controller circuit 220 applies a first word line signal WL[0] to the first word line WL0 to simultaneously read data D1 and D2 from the signing storage unit 212 and the selection storage unit 214. In step S110, the controller circuit 220 determines whether the signing storage unit 212 has been read successfully. If the read data D1 is correct, it indicates that the signing storage unit 212 has been read successfully, and the reading method will execute step S120. In step S120, the controller circuit 220 also determines that the reading of the selection storage unit 214 has been successful, indicating that the data D2 read from the selection storage unit 214 is considered correct.
[0033] Conversely, if the read data D1 is incorrect, it indicates that the signing storage unit 212 has failed to read, and the reading method will return to step S100. In step S130, the controller circuit 220 switches the first word line signal WL[0] to return to step S100 and read the data D1 and D2 of the signing storage unit 212 and the selection storage unit 214 simultaneously again until the signing storage unit 212 is successfully read.
[0034] Furthermore, the method for reading the memory storage device in this embodiment of the invention can be provided by... Figures 1 to 4 Sufficient teaching, suggestions and implementation instructions are provided in the description of the embodiments, and therefore will not be repeated.
[0035] Figure 6 A schematic diagram of the waveforms of the word line signal and the address signal according to another embodiment of the present invention is shown. (See reference) Figure 2 , Figure 3A and Figure 6 ,exist Figure 6 In the middle, the word line decoder circuit 240 outputs word line signals WL[0] and WL[1] to turn on word lines WL0 and WL1. The remaining word line signals can be deduced similarly. Word line turn-on means that the word line signal applied to the word line is during the enable period, such as during a high or low level. Figure 6 In the middle, the high level period of word line signals WL[0] and WL[1] is the enable period.
[0036] by Figure 3A Taking the first word line WL0 as an example, the signing storage unit 212 and the selection storage unit 214 are located on the first word line WL0. The controller circuit 220 applies the first word line signal WL[0] to the first word line WL0 so that during the enable period T2, it can simultaneously read the data D1 and D2 of the signing storage unit 212_1 and the selection storage unit 214_1 multiple times until the signing storage unit 212 is successfully read.
[0037] In this embodiment, the controller circuit 220 reads the first word line WL0 multiple times (610_1, 610_m). During the m-th read, the controller circuit 220 determines that the signature storage unit 212 has been successfully read. Between each read, the first word line signal WL0 remains in the enabled state and does not switch. That is, the single enabled period T2 of the first word line signal WL[0] is continuous, and between each read, the first word line WL0 will not be restarted but will remain in the on state.
[0038] Next, when the signature storage unit 212 located on the first word line WL0 is successfully read, the controller circuit 220 applies the second word line signal WL[1] to the second word line WL1 to read the data D1 and D2 of the signature storage unit 212 and the selection storage unit 214, until the signature storage unit 212 located on the second word line WL1 is successfully read. Between each read, the second word line signal WL[1] remains enabled and does not switch. The controller circuit 220 reads the storage units of other word lines in the same manner.
[0039] exist Figure 6 In this embodiment, since the word line signal is kept enabled without switching between reads, the power of the voltage signal RVPP is saved. Furthermore, because power noise and power drop are reduced, reading from the memory cell is easier.
[0040] Please refer to Figure 2 , Figure 3A , Figure 6 and Figure 7 The memory storage device reading method of this embodiment is at least suitable for Figure 2 The present invention is not limited to the memory storage device 200. Taking the memory storage device 200 as an example, steps S200, S210, and S220 are similar to those of memory storage device 200. Figure 5 The embodiment is as follows. However, in this embodiment, the word line signals WL[0] and WL[1] remain enabled between each read.
[0041] Furthermore, the method for reading the memory storage device in this embodiment of the invention can be provided by... Figures 1 to 3A and Figure 6 Sufficient teaching, suggestions and implementation instructions are provided in the description of the embodiments, and therefore will not be repeated.
[0042] In summary, in the embodiments of the present invention, the controller circuit can simultaneously read the signature storage unit and the selection storage unit until the signature storage unit is successfully read. When the signature storage unit is successfully read, the controller circuit also determines that the read of the selection storage unit is successful. In this way, the controller circuit can correctly read the selection storage unit, reducing the impact of power noise and power degradation on the read results. In addition, the controller circuit can switch the word line signal and perform reading during its enabled state, or the controller circuit can keep the word line signal enabled and perform multiple reads without switching the word line signal.
[0043] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.
Claims
1. A memory storage device, characterized in that, include: A storage cell array, comprising signed storage cells and selected storage cells; as well as A controller circuit is coupled to the storage cell array and is used to simultaneously read the signing storage cell and the selection storage cell, wherein when the signing storage cell is read successfully, the controller circuit determines that the reading of the selection storage cell is successful.
2. The memory storage device according to claim 1, characterized in that, The signature storage unit and the selection storage unit are located on the same word line. The controller circuit is used to apply a word line signal to the word line to read the signature storage unit and the selection storage unit simultaneously.
3. The memory storage device according to claim 2, characterized in that, The controller circuit reads the signature storage unit and the selection storage unit simultaneously multiple times until the signature storage unit is successfully read.
4. The memory storage device according to claim 2, characterized in that, The word line signal includes multiple enable periods, during which the controller circuit simultaneously reads the signature storage unit and the selection storage unit.
5. The memory storage device according to claim 4, characterized in that, The duration of the plurality of enable periods of the word line signal is the same.
6. The memory storage device according to claim 2, characterized in that, The word line signal includes a single enable period during which the controller circuit simultaneously reads the signature memory unit and the selection memory unit.
7. The memory storage device according to claim 1, characterized in that, The controller circuit reads both the signature storage unit and the selection storage unit simultaneously during power-on reading.
8. A method for reading from a memory storage device, characterized in that, The memory storage device includes a storage cell array, and the storage cell array includes a signing storage cell and a selection storage cell. The method for reading the memory storage device includes: A word line signal is applied to the word line to simultaneously read the signature storage unit and the selection storage unit, wherein the signature storage unit and the selection storage unit are located on the word line; Determine whether the signature storage unit has been read successfully; and When the signed storage unit is successfully read, the selected storage unit is also determined to be successfully read.
9. The method for reading a memory storage device according to claim 8, characterized in that, Also includes: If the signing storage unit fails to be read, both the signing storage unit and the selected storage unit are read again until the signing storage unit is successfully read.
10. The method for reading a memory storage device according to claim 8, characterized in that, The word line signal includes multiple enable periods, during which the signature storage unit and the selection storage unit are read simultaneously.
11. The method for reading a memory storage device according to claim 10, characterized in that, The duration of the plurality of enable periods of the word line signal is the same.
12. The method for reading a memory storage device according to claim 8, characterized in that, The word line signal includes a single enable period during which the signature storage unit and the selection storage unit are read simultaneously.