Processing unit for table lookup memory

Abstract

A processing unit for a memory for table lookup is described herein. A plurality of elements (e.g., output values) of a lookup table LUT may be sequentially prefetched from a respective column of memory cells indicated by each of the vector values stored in a location of a register of the processing unit. Each of the vector values may be shifted by a position among the positions of the register such that an end position of the register is available to store a respective one of the prefetched output values.

Description

Technical Field

[0001] This disclosure generally relates to memory, and more specifically, to a processing unit of memory for table lookup. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and includes NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), etc.

[0003] Memory is also used as a volatile and non-volatile data storage device for a wide range of electronic applications. Non-volatile memory can be used in, for example, personal computers, memory sticks, digital cameras, cellular phones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged in arrays, which are used in memory devices. Summary of the Invention

[0004] On one hand, this disclosure provides a method for table lookup, comprising: prefetching data values ​​corresponding to a first plurality of elements of a lookup table (LUT) from a first column memory cell, wherein the first column is indicated by a first vector value of a plurality of vector values ​​stored in a plurality of locations (332-0, ..., 332-31) of a register (232; 332); shifting each of the plurality of vector values ​​stored in the register toward a first location (332-0) of the plurality of locations by one position so that a second location (332-31) of the plurality of locations is unoccupied; and storing one of the first plurality of elements indicated by the first vector value in the second location of the register.

[0005] On the other hand, this disclosure further provides an apparatus for table lookup, comprising: a memory cell array (130); and a processing unit (102) including registers (232; 332) and coupled to the array, the processing unit being configured to perform a table lookup operation: sequentially prefetching a plurality of output values ​​of a lookup table (LUT) from corresponding columns of the memory cells of the array, wherein the corresponding columns are indicated by corresponding vector values ​​of a plurality of vector values ​​stored in a first location of the register; after each prefetch of the corresponding columns of the memory cells, shifting the plurality of vector values ​​stored in the plurality of locations (332-0, ..., 332-31) of the register one position toward the first location so that a second location (332-31) of the register is unoccupied; and storing a corresponding output value of the plurality of output values ​​indicated by the corresponding vector values ​​of the plurality of vector values ​​in the second location of the register.

[0006] On the other hand, this disclosure further provides an apparatus for table lookup, comprising: a memory cell array (130); and a processing unit (102) coupled to the memory cell array and comprising: a shift register (232; 332); and a multiplexer (234) coupled to the shift register; wherein the processing unit is configured to: prefetch a first plurality of output values ​​of a lookup table (LUT) from a first column of memory cells of the array, wherein the first column is indicated by a first portion of bits of a first vector value of a plurality of vector values ​​stored in a plurality of locations (332-0, ..., 332-31) of the shift register; shift each of the plurality of vector values ​​of the shift register toward an initial location (332-0) of the plurality of locations by one position so that an end location (332-31) of the plurality of locations is unoccupied; and input a second portion of bits of the first vector value to the multiplexer, wherein the multiplexer is configured to select one of the first plurality of prefetched output values ​​based on the second portion of bits of the first vector value. Attached Figure Description

[0007] Figure 1 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of a processing unit for table lookup according to several embodiments of the present disclosure.

[0009] Figure 3 Examples of shifting data values ​​in a vector register in association with a table lookup operation according to several embodiments of this disclosure are described.

[0010] Figure 4Example flowcharts illustrating a method for performing a table lookup operation using a processing unit with memory, according to several embodiments of the present disclosure.

[0011] Figure 5 An example machine describing a computer system is a set of instructions that can be executed within the computer system to cause the machine to perform any or more of the methods discussed herein. Detailed Implementation

[0012] This disclosure includes processing units for table lookup. An example method may include prefetching data values ​​corresponding to a plurality of elements from a column of memory cells. The column may be indicated by a first vector value of a plurality of vector values ​​stored in a plurality of locations in a register. The method may further include shifting each of the plurality of vector values ​​stored in the register one position toward the first location of the plurality of locations so that a second location of the plurality of locations is unoccupied. The method may further include storing one of the plurality of elements indicated by the first vector value in the second location of the register.

[0013] Perceptrons are fundamental computational components used to implement a wide range of artificial intelligence (AI) and machine learning algorithms. As used in this paper, artificial intelligence (AI) refers to the ability of a device to improve itself through “learning” (e.g., by storing patterns and / or instances that can be used to take action at a later time). Machine learning (which can be a subset of AI) refers to algorithms that can learn from data and make predictions or decisions based on that data.

[0014] A perceptron consists of a weight vector and an input vector. The perceptron computes the inner product of these vectors and then applies a nonlinear function, called the activation function, to the resulting sum. Activation functions can range from simple shearing functions to more complex functions, such as exponential or polynomial expansions. Implementing these more complex functions is often costly because they require larger die area for the hardware circuitry and can significantly impact overall performance due to increased computational load and power consumption. However, activation functions can be simplified by using lookup tables (LUTs) to describe them. As used herein, the term "lookup table" or "LUT" refers to a data structure that maps input values ​​to corresponding (e.g., pre-computed) output values. LUTs are designed for fast retrieval and are often used to optimize performance by replacing runtime computations with pre-computed results, thereby minimizing hardware complexity and improving performance.

[0015] Embodiments of this disclosure describe a hardware circuitry that can be implemented as part of an AI accelerator architecture to provide fast retrieval of output values ​​from a LUT. This hardware circuitry is characterized by a relatively simple design compared to hardware circuitry used in previous methods for performing table lookup operations. The hardware circuitry can be implemented per unit of a memory cell array, such as a bank of memory cells. Therefore, this hardware implementation can be replicated across each bank of memory in the accelerator. The architecture allows for parallel execution of the lookup function, which not only improves system efficiency but also significantly enhances its overall performance by reducing latency and improving throughput.

[0016] The figures in this document follow a numbering convention, where the first one or a few digits correspond to the figure number and the remaining digits identify elements or components within the figure. Similar elements or components between different figures can be identified by using similar digits. For example, 102 could refer to... Figure 1 Component "02" in the text, and similar components in Figure 2 The symbol can be labeled 202. Similar elements within the diagram can be referenced using hyphens and additional numbers or letters. Such similar elements can be generally referenced without hyphens and additional numbers or letters. For example, Figure 1 Elements 105-1, 105-2, ..., 105-N in the figures can be collectively referred to as 105. As used herein, the indicator “N”, particularly with respect to reference numerals in the figures, indicates that several specific features may be included. It should be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate a particular embodiment of the invention and should not be considered as intended to be limiting.

[0017] Figure 1 This is a block diagram of a device in the form of a computing system 100 including a memory device 120, according to several embodiments of the present disclosure. As used herein, the memory device 120, a plurality of memory banks 130 (also referred to as memory array 130), the host 110, and / or the PU may also be individually considered as a “device”.

[0018] In this example, system 100 includes a host 110 coupled to memory device 120 via interface 156. Computing system 100 may be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or device with Internet of Things (IoT) capabilities, as well as various other types of systems. Host 110 may include several processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) capable of accessing memory 120. System 100 may include a separate integrated circuit, or both host 110 and memory device 120 may be on the same integrated circuit. For example, host 110 may be a system controller for a memory system including multiple memory devices 120, wherein system controller 110 provides access to the respective memory devices 120 via another processing resource, such as a central processing unit (CPU).

[0019] exist Figure 1 In the example shown, host 110 is responsible for executing the operating system (OS) and / or various applications that can be loaded onto it (e.g., from memory device 120 via controller 140). Host 110 can provide access commands and / or safe mode initialization commands to the memory device via interface 156.

[0020] For clarity, system 100 has been simplified to focus on features particularly relevant to this disclosure. For example, memory array 130 may be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and / or NOR flash array. Array 130 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digital lines or data lines).

[0021] Memory device 120 includes an address circuitry system to latch address signals provided via interface 156. For example, interface 156 may include a physical interface employing a suitable protocol (e.g., a data bus, address bus, and command bus, or a combined data / address / command bus). This protocol may be custom or proprietary, or interface 156 may employ a standardized protocol, such as PCIe, Gen-Z, CCIX, or similar. Address signals are received and decoded by row decoder 146 and column decoder 152 to access memory array 130. Data can be read from memory array 130 by using a sensing circuitry system to sense changes in voltage and / or current on a sensing line. For example, the sensing circuitry system may include a sensing amplifier that can read and latch a page (e.g., a row) of data from memory array 130. I / O circuitry systems can be used for bidirectional data communication with host 110 via interface 156. Read / write circuitry systems are used to write data to or read data from memory array 130.

[0022] Controller 140 decodes signals provided by host 110. These signals may include chip enable signals, write enable signals, and address latch signals for controlling operations performed on memory array 130 (including data read, data write, and data erase operations). In various embodiments, controller 140 is responsible for executing instructions from host 110. Controller 140 may include a state machine, sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination of the three.

[0023] In various examples, controller 140 may receive signals provided by host 110, including signals requesting that operation be performed by PU 102. As used herein, PU 102 may include hardware, firmware, and / or software for performing operations using data provided by memory array 130 and / or host 110, such operations as, for example, multiplication and table lookup operations.

[0024] In various instances, an error correction code (ECC) circuitry 103 may be coupled to a column decoder 152. The ECC circuitry 103 may receive data from a memory array 130. The ECC circuitry 103 may perform error correction operations to correct errors in the data sensed from the memory array 130. A push-pull (PU) 102 may be coupled to the ECC circuitry 102. The PU 102 may perform various operations on the data received from the ECC circuitry 103. The PU 102 may provide an output to a data path 104. The data path 104 may provide data to an interface 156. In various instances, the data path 104 may include input / output (I / O lines) and / or receivers and / or drivers. As used herein, a receiver may include circuitry configured to receive signals. A driver may describe circuitry used to drive signals across one or more lines. Although... Figure 1 The description focuses on a single decoder (e.g., row and column decoders 146, 156), ECC circuitry 103, and PU 102, but the embodiments are not limited thereto. For example, the memory device 120 may comprise multiple layers, such as layers 105-1, ..., 105-N (collectively referred to as layers 105), where each layer 105 includes a memory bank 130, a decoder (e.g., row and column decoders 146, 156), ECC circuitry 103, and PU 102. In other words, the memory device 120 may include multiple memory banks, decoders, ECC circuitry, and PUs.

[0025] Each PU 102 may contain one or more registers (e.g. Figure 2 The registers 232 and / or MUX (e.g., as described in the document) Figure 2 The MUX 231 described herein can be used in conjunction with other functions to perform table lookup operations. Registers can initially be loaded with vector values, which can be used as input values ​​to the corresponding output values ​​of LUTs (stored in one or more memory banks 130). One or more LUTs can be stored in array 130. Using vector values, PU 102 can sequentially load corresponding output values ​​into registers in a manner where the vector values ​​stored in the registers are eventually replaced by the corresponding output values.

[0026] In some embodiments, multiple table lookup operations can be performed in parallel by PU 102 (e.g., using LUTs stored in multiple storage banks 130 respectively). For example, one PU 102 can perform a table lookup operation using data corresponding to a LUT stored in storage bank 130 of layer 105-1, while another PU 102 performs another table lookup operation using data corresponding to a LUT stored in storage bank 130 of layer 105-N. Figure 2 and 3 Further details about the table lookup process.

[0027] Figure 2Processing unit 202 for table lookup according to several embodiments of this disclosure (e.g.) Figure 1 A block diagram of PU 102. (See attached diagram.) Figure 1 As described and illustrated, PU 202 may be located on the memory device side (e.g., on...). Figure 1 (as described in the document on the memory device 120); thereby allowing the memory device 120 to perform the operations described herein using PU 202.

[0028] PU 202 may include multiplexers (MUX) 231, 234, 236, 238, shift register 232, multiply-accumulate (MAC) unit 233, and arithmetic function unit (AFU) 235. Although a single MAC unit 233 is shown, PU 202 may include multiple MAC units. PU 202 may receive data via an input data bus (e.g., including a receiver and / or driver), which may be 256 bits wide, but embodiments are not limited thereto. The input data bus may couple PU 202 to a memory device (e.g., ...). Figure 1 The memory device 120 described herein contains one or more memory banks (e.g., memory devices 120) Figure 1 The storage 130 described herein) and / or the host computer coupled to the memory device (e.g., Figure 1 The host 110 described in the document.

[0029] A table lookup operation can be initiated by loading (e.g., storing) a vector (alternatively referred to as a "vector value") into vector register 232. The vector can be received from a memory bank of a memory device (e.g., a DRAM array) and / or a host coupled to the memory device. While embodiments are not limited thereto, the vector initially loaded into vector register 232 may consist of thirty-two groups, each with 8 bits, for a total of 256 bits. The thirty-two 8-bit vectors may be provided as a single 256-bit data block via an input data bus. The vector may contain the value to be "looked up". The vector may serve as input to a table lookup operation. The vector can be used to produce output values, as described below.

[0030] Register 232 may represent multiple registers. For example, register 232 may consist of thirty-two 8-bit registers. Although embodiments are not limited to this, register 232 may be a shift register that can shift data values ​​(e.g., vector values ​​or output values ​​of a LUT) stored in corresponding "positions" of shift register 232 one position in a specific direction. For example, thirty-two 8-bit registers provide thirty-two "positions" in which thirty-two vectors can be stored respectively, and the vectors can be shifted one position in each iteration.

[0031] After the vector is loaded into register 232, it can be (e.g., by...) Figure 1The controller 140 shown activates a row memory cell (controlled by the row decoder 146) that stores data corresponding to the LUT. For example, the data corresponding to the LUT may contain several (e.g., pre-computed) output values ​​(alternatively referred to as "elements," "lookup table elements," or "LUT elements") that can be mapped to input values. Figure 2 In the illustrated example, the vector loaded into register 232 can be used as the “input value” of a LUT that can be mapped (e.g., matched) to the output value of the LUT.

[0032] Each vector can be used to indicate, retrieve, and further load (e.g., store) one of the LUT elements into vector register 232. For example, each vector stored in vector register 232 can be used to select a specific column memory cell, which may correspond to a column of the LUT and a specific element within said column memory cell. For example, the first portion of the bits in each vector (e.g. Figure 2 The “SR[0][5:7]” shown can be used to select a specific column of the activated row. Therefore, the data corresponding to the selected column (e.g., 32 elements) can be prefetched onto the data bus (e.g., the “input data bus” coupled to PU 202) and provided (presented) to MUX 231.

[0033] Once the elements have been prefetched and presented on the data bus, vector register 232 can "discard" the vector used to prefetch the elements corresponding to the selected column. For example, vector register 232, which can be used as a shift register, can shift the position of the stored vector toward a first position (e.g., ...). Figure 3 The location described in the document is 332-0, and is alternatively referred to as the "initial location"). This will be previously stored in the second location (e.g., Figure 3 The vector at position 332-1 is shifted to the first position, while the last position (e.g., the 32nd position, alternatively referred to as the "end position") is "cleared" so that it can be used for subsequent data.

[0034] The second part of the bits of each vector (e.g.) Figure 2 The “SR[0][0:4]” shown can be used as a “control signal” for the MUX 231. The second part of the bit can be used to select an element from the prefetch elements. For example, the second part of the bit provided to the MUX 231 can cause the MUX 231 to select and output one of the prefetch elements, as indicated by the second part of the bit. The selected element output from the MUX 231 can be loaded (e.g., stored) into the “last position” of the shift register 232, which becomes available because the vector is discarded.

[0035] In several embodiments, the second portion of a bit may be presented to MUX 231 to prefetch the corresponding column while the first portion of the bit is presented to the corresponding row decoder (e.g., row decoder 146). As used herein, the term "substantially" means that a feature does not need to be absolute, but is close enough to achieve the advantages of the feature. For example, "substantially simultaneous" is not limited to operations or events that are performed absolutely simultaneously and may include timing that is desired to be simultaneous but may not be precisely simultaneous due to manufacturing limitations.

[0036] Alternatively, the vector stored in register 232 can be "rotated," where it was previously stored in the first position (e.g., Figure 3 The vector at position 332-0 described can be shifted to the last position (e.g., Figure 3 (Positions 332-31 are described). In this example, the last position of the vector previously stored in the first position can be overwritten with a selected element output from MUX 231.

[0037] Consider an example where a LUT with 256 elements (each element being 1 byte in size, thus making the total size of the lookup table 256 bytes) is stored in an array (e.g., Figure 1 The instances are located in at least a portion of a row of memory cells (e.g., a row of memory cells with a size of 2KB) and above 8 columns (each column storing 32 elements) of the described memory bank 130. Register 232 is initially loaded with thirty-two vectors, each vector consisting of 8 bits. In the first iteration, the first vector ( Figure 3 The three bits of “SR[0]” shown Figure 2 The shown SR[0][5:7]) can be used (e.g., to indicate) to prefetch elements from one of the eight columns provided to the MUX 231, and the first vector ( Figure 3 The five bits of “SR[0]” shown Figure 2 The “SR[0][0:4]” shown can be used to indicate one of the 32 elements of the selected column so that the indicated element is eventually loaded into register 232.

[0038] Each iteration of discarding a vector and loading the corresponding element into register 232 can be repeated until every vector initially loaded into vector register 232 is exhausted (e.g., replaced by an element). For example, if vector register 232 initially contains 32 vectors, then the iteration can be repeated thirty-two times to discard and exhaust thirty-two vectors and fill register 232 with the thirty-two elements of the LUT. Figure 3 Further details of this iterative process will be provided.

[0039] PU 202 further includes logic unit 237. For example... Figure 2As shown, logic unit 237 includes a multiply-accumulate (MAC) unit 233 and an arithmetic function unit 235. However, embodiments are not limited to a specific type of unit, circuit, etc., that may be included as part of logic unit 237. In some embodiments, PU 202 may not include a logic unit (e.g., logic unit 237), such that the output from vector register 232 can be sent out (e.g., via MUX 234) without being processed at the logic unit.

[0040] Each MAC unit 233 may contain a multiplier and an accumulator (also called an accumulator register). Each of the MAC units 233 may receive operands "A" and "B" (in...). Figure 2 The data values ​​(displayed as "OP A" and "OP B" respectively) are used as corresponding inputs. For example, operand "A" can be received from MUX 236, and MUX 236 can selectively provide one of its inputs (e.g., received from memory bank 130 or AFU 235 of memory device 120) to MAC 233. Furthermore, for example, operand "B" can be received from MUX 234, and MUX 234 can selectively provide one of its inputs (e.g., a vector, LUT element, etc. received from register 232) to MAC 233.

[0041] Each corresponding MAC unit 233's multiplier and accumulator can perform multiple multiplication operations and multiple accumulation operations (collectively referred to as MAC operations) using the data values ​​received from operands "A" and "B". The output of each corresponding multiplier can be provided to different corresponding accumulators. Each accumulator can sum the corresponding output of the multiplier with the previous output of the multiplier.

[0042] AFU 235 can perform various arithmetic operations using inputs received from MAC unit 233 as corresponding operands for arithmetic operations. While embodiments are not limited to this, AFU 235 can be a logic unit (e.g., a rectified linear unit, ReLU, e.g., f(x) = |x|)) that performs a nonlinear mapping from input values ​​to output values. The mapping can be reconfigured at runtime when the lookup table is written to the memory array by the host. As an example, an AFU 235 performing a nonlinear mapping enables the handling of complex computational tasks (that go beyond traditional linear arithmetic operations), such as those required in machine learning and signal processing.

[0043] In some embodiments, MAC unit 233 may be able to handle larger amounts of data (24-bit MAC unit) compared to AFU 235 (e.g., 8-bit AFU). To achieve the same level of precision between MAC unit 233 and AFU 235, MAC unit 233 may be implemented using a shift function that allows MAC unit 233 to selectively provide a portion (e.g., 8 bits) of its 24-bit data to AFU 235.

[0044] Logic unit 237 can perform a variety of operations, ranging from relatively complex operations to simple tasks, such as reading data values ​​(e.g., vectors, LUT elements, etc.) stored in register 232. For example, logic unit 237 can be used to execute activation functions associated with artificial neural networks (ANNs), such as thresholding functions, sign functions, sigmoid functions, or linear functions, but embodiments are not limited thereto.

[0045] In another example, reading a data value from register 232 might involve providing a data value of "1" as operand "A" to MAC unit 233, and providing a LUT element (or vector) as operand "B" to MAC unit 233. The multiplication performed by MAC unit 233 using these two operands produces an output equal to the input LUT element (as the result of multiplying the value corresponding to the input LUT element by the value "1"). The output from MAC unit 233 (which corresponds to the input LUT element) can be transmitted via MUX 238 (e.g., to the host). For example, the outputs from AFU 235 and MAC 233 can be provided as corresponding inputs to MUX 238, which can then transmit the data via MUX 238. Figure 2 The demonstrated "output data bus" selectively transmits one of its inputs to the host (e.g., Figure 1 The host shown is 110.

[0046] Figure 3 Examples of shifting processes in a vector register associated with a table lookup operation according to several embodiments of this disclosure are provided. Figure 3 The thirty-two positions shown (e.g., positions 332-0, ..., 332-31) can be stored in registers (e.g. Figure 2 The data values ​​in register 232 shown can be shifted in a specific direction at these positions. More specifically, the thirty-two positions 332-0, ..., 332-31 can represent thirty-two registers (e.g., 8-bit registers). Although Figure 3 Explain the shift register (e.g.) Figure 2 The shift register 232 described has thirty-two positions, but the embodiment is not limited to a specific number of positions where the data value stored in the shift register can be shifted.

[0047] At position 342-1, shift register 232 initially loads vectors (e.g., ..., 332-31) into positions 332-0, ..., 332-31 respectively. Figure 3 The vectors shown are "1" to "32". (As combined...) Figure 2 As described, the bits of each vector are used to identify one of the LUT elements that will be mapped to the corresponding vector. At 342-2, assuming LUT element "1" is mapped to vector "1", then vectors "1" through "32" are shifted one position toward position 332-0 such that vector "1" is discarded from shift register 232, and the last position 332-31 becomes "empty" to finally load element "1". Similarly, at 342-3, assuming LUT element "2" is mapped to vector "2", vectors "2" through "32" and LUT element "1" are shifted one position toward position 332-0 such that vector "2" is discarded from shift register 232, and the last position 332-31 again becomes "empty" to finally load LUT element "2".

[0048] The process of discarding a vector from shift register 232 and loading the corresponding LUT element (e.g., mapped to the discarded vector) into shift register 232 can be repeated iteratively several times until all vectors "1" through "32" are exhausted (e.g., discarded). For example, to exhaust thirty-two vectors (e.g., vectors "1" through "32"), the process can be repeated iteratively thirty-two times. More specifically, at the 31st iteration (as shown at 342-31), since the vector "31" previously stored at position 332-0 is exhausted, the last position 332-31 is loaded with LUT element "31". Furthermore, in the 32nd iteration (as shown at 342-32), since the vector "32" previously stored at position 332-0 is exhausted, the last position 332-31 is loaded with LUT element "32", and at the end of the 32nd iteration, position 332-0 is now loaded with LUT element "1". Due to the thirty-two iterations, the thirty-two positions 332-0, ..., 332-31 of shift register 232 are loaded with thirty-two LUT elements "1" to "32", such as Figure 3 As shown.

[0049] Figure 4 This is a flowchart of an example method 480 for performing a table lookup operation using a processing unit with memory, according to some embodiments of the present disclosure. The method may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, by or using Figure 1The memory device 120 of the illustrated computing system 100 is used to execute the method. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0050] At position 482, data values ​​corresponding to the first plurality of elements can be prefetched from the first column memory cell (e.g., in response to receiving a command to perform a table lookup operation). The first column is stored in a register (e.g., Figure 2 and 3 The multiple locations of the registers 232 and 332 shown (e.g.) Figure 3 Multiple vector values ​​(e.g., positions 332-1, ..., 332-32) described in the text Figure 3 The first vector value of the vectors shown ("vector 1" to "vector 32") (e.g.) Figure 3 The “vector 1” shown indicates this. For example, the first plurality of elements to be prefetched can be represented by the first part of the bits of the corresponding data value ( Figure 2 The “SR[0][5:7]” instruction is shown.

[0051] The first plurality of elements may each correspond to the output value of a lookup table (LUT). In some embodiments, a row of memory cells configured to store data corresponding to the LUT may be activated before the data values ​​corresponding to the first plurality of elements are prefetched from the first column of memory cells.

[0052] At position 484, each of the multiple vector values ​​stored in registers 232 and 332 can be oriented toward the first of a plurality of positions (e.g., Figure 3 The position described in 332-1) is shifted by one position to make the second position (e.g.) of a plurality of positions. Figure 3 Positions 332-31 described are not occupied. At 486, one of the first plurality of elements indicated by the first vector value (e.g., Figure 3 The shown "element 1" is stored in the second positions 332-31 of registers 232 and 332. For example, one of the first plurality of elements stored in registers 232 and 332 can be obtained from the second part of the bits of the first vector value ( Figure 2 The “SR[0][0:4]” instruction is shown.

[0053] After storing one of the first plurality of elements in the second positions 332-31 of registers 232 and 332, a second plurality of elements can be prefetched from the second column memory cell. The second column can be the same as the first column (where the second plurality of elements are similar to the first plurality of elements) or a different column (where the second plurality of elements may be different from the first plurality of elements). This second column consists of the second vector value from the plurality of vector values ​​stored in the first positions 332-1 of registers 232 and 332. Figure 2 The “vector 2” shown indicates this. In this example, each of the multiple vector values ​​stored in registers 232, 332 can be shifted one position toward the first position 332-1 so that the second position 332-31 of the multiple positions is not occupied. Furthermore, one of the second multiple elements indicated by the second vector value (e.g., Figure 3 The “element 2” shown can be stored in the second position 332-31 of registers 232 and 332.

[0054] Figure 5 The computer system 590 is described as an example machine, within which a set of instructions can be executed to cause the machine to perform any or more of the methods discussed herein. In some embodiments, the computer system 590 may correspond to a host system (e.g., Figure 1 The host 110 includes, is coupled to, or utilizes a memory device (e.g., Figure 1 The memory device 120), or can be used to execute a PU (e.g., Figure 1 The operation of PU 102). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0055] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be considered as encompassing any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0056] The example computer system 590 includes a processing device 591, a main memory 593 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static memory 597 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 598, which can communicate with each other via a bus 596.

[0057] Processing device 591 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or several processors implementing combinations of instruction sets. Processing device 591 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 591 is configured to execute instructions 592 for performing the operations and steps discussed herein. Computer system 590 may further include a network interface device 594 for communication via network 595.

[0058] Data storage system 598 may include machine-readable storage medium 599 (also referred to as computer-readable medium) storing one or more sets of instructions 592 or software embodying any or more of the methods or functions described herein. Instructions 592 may also reside wholly or at least partially in main memory 593 and / or processing device 591 during execution by computer system 590, which also constitute machine-readable storage medium.

[0059] In one embodiment, instruction 592 includes implementing the corresponding Figure 1 The functional instructions of PU 102. Although the machine-readable storage medium 599 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0060] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of this disclosure. It should be understood that the above description has been carried out in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon review of the above description, combinations of the above embodiments and other embodiments not explicitly described herein. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined with reference to the appended claims, together with the full scope of the equivalents granted therein.

[0061] In the foregoing detailed embodiments, various features are grouped together in a single embodiment for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than expressly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention exists in fewer than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is an independent, separate embodiment.

Claims

1. A method for table lookup, comprising: Prefetch data values ​​corresponding to the first plurality of elements of the lookup table LUT from the first column memory cell, wherein the first column is stored in register (232); The first vector value among multiple vector values ​​at multiple positions (332-0, ..., 332-31) of 332 indicates; Each of the plurality of vector values ​​stored in the register is shifted one position toward the first position (332-0) of the plurality of positions so that the second position (332-31) of the plurality of positions is not occupied; and One of the first plurality of elements indicated by the first vector value is stored in the second location of the register.

2. The method according to claim 1, further comprising: The first plurality of elements are prefetched from the first column memory cell as indicated by the first portion of the plurality of bits of the first vector value; and Store one of the first plurality of elements indicated by the second portion of the plurality of bits of the first vector value.

3. The method according to any one of claims 1 to 2, further comprising, after storing one of the first plurality of elements in the second location of the register: A second plurality of elements of the lookup table are prefetched from a second column of memory cells, wherein the second column is indicated by a second vector value among the plurality of vector values ​​stored in the first location of the register; Shift each of the plurality of vector values ​​stored in the register one position toward the first position so that the second position among the plurality of positions is not occupied; and One of the second plurality of elements indicated by the second vector value is stored in the second location of the register.

4. The method according to any one of claims 1 to 2, wherein: The first plurality of elements respectively correspond to the output values ​​of the LUT; and The method further includes activating a row memory cell configured to store data corresponding to the LUT before prefetching the data values ​​corresponding to the first plurality of elements from the first column memory cell.

5. A device for table lookup, comprising: Memory cell array (130); and The processing unit (102) includes a register (232); 332) and coupled to the array, the processing unit is configured to perform a table lookup operation: Multiple output values ​​of a lookup table (LUT) are sequentially prefetched from corresponding columns of memory cells in the array, wherein the corresponding columns are indicated by corresponding vector values ​​from multiple vector values ​​stored in a first location of the register; After each prefetch of the corresponding column of the memory cell, the plurality of vector values ​​stored in the plurality of locations (332-0, ..., 332-31) of the register are shifted one position toward the first location so that the second location (332-31) of the register is not occupied; and The corresponding output value, which is indicated by the corresponding vector value among the plurality of vector values, is stored in the second location of the register.

6. The device according to claim 5, wherein: The processing unit further includes a multiplexer (236), wherein the plurality of prefetched output values ​​are received as corresponding inputs into the multiplexer; and The multiplexer is configured to: The corresponding output value among the plurality of prefetched output values ​​is selected based on one or more bits of the corresponding vector value among the plurality of vector values ​​and output to the register.

7. The device according to claim 5, wherein: The processing unit is a first processing unit (102) and the memory cell array is a first memory cell array (130); and The device further includes a second memory cell array (130) and a second processing unit (102) coupled to the second array; in: The first processing unit is configured to perform a first table lookup operation; and The second processing unit is configured to perform a second table lookup operation simultaneously with the first table lookup operation performed by the first processing unit.

8. The device of claim 5, wherein the first position is the initial position (332-0) among the plurality of positions of the register.

9. The device of claim 5, wherein the second position is the end position (332-31) of the plurality of positions of the register.

10. The device according to any one of claims 5 to 9, wherein each vector value used to indicate the respective column and output value is discarded from the register due to each shift following the respective prefetch of the plurality of output values ​​of the respective column in the memory cell.

11. The device according to any one of claims 5 to 9, wherein each of the plurality of vector values ​​comprises: Several first digits, which are used to indicate the corresponding column of the memory cell of the array; and Several second bits are used to indicate the corresponding output value among the plurality of output values.

12. An apparatus for table lookup, comprising: Memory cell array (130); and Processing unit (102), coupled to the memory cell array and comprising: Shift registers (232; 332); and A multiplexer (234) coupled to the shift register; The processing unit is configured to: The first plurality of output values ​​of the lookup table LUT are prefetched from the first column memory cells of the array, wherein the first column is indicated by the first portion of the bits of the first vector value of a plurality of vector values ​​stored in a plurality of locations (332-0, ..., 332-31) of the shift register respectively; Each of the plurality of vector values ​​stored in the shift register is shifted one position toward the initial position (332-0) of the plurality of positions so that the end position (332-31) of the plurality of positions is not occupied; and A second portion of the bits of the first vector value is input to the multiplexer, wherein the multiplexer is configured to select one of the first plurality of prefetch output values ​​based on the second portion of the bits of the first vector value.

13. The device of claim 12, wherein the second vector value of the plurality of vector values ​​is stored in the initial position as the plurality of vector values ​​are shifted toward the initial position.

14. The apparatus of claim 12, wherein the processing unit is further configured to: Prefetch a second plurality of output values ​​of the LUT from the second column memory cells of the array, wherein the second column is indicated by the first portion of the bits of the second vector value among the plurality of vector values; Each of the data values ​​corresponding to the plurality of vector values ​​stored in the shift register is shifted one position toward the initial position among the plurality of positions so that the end position among the plurality of positions is not occupied; and A second portion of the bits of the second vector value is input to the multiplexer, wherein the multiplexer is configured to select one of the second plurality of prefetch output values ​​based on the second portion of the bits of the second vector.

15. The device according to claim 14, wherein: One of the first plurality of prefetched output values ​​indicated by the first vector value is the first output value; and The first output value is shifted one position from the end position to the first position (332-30) among the plurality of positions.

16. The apparatus according to claim 15, wherein: One of the second plurality of prefetched output values ​​selected by the second vector value is the second output value, and the second output value is stored in the end position of the shift register in response to selection by the multiplexer; and The third vector value among the plurality of vector values ​​is stored in the initial position because the plurality of vector values ​​have shifted toward the initial position.

17. The apparatus of claim 16, wherein the processing unit is further configured to: The third plurality of output values ​​of the LUT are prefetched from the third column memory cells of the array, wherein the third column is indicated by the first portion of the bits of the third vector value among the plurality of vector values; Each of the data values ​​corresponding to the plurality of vector values ​​stored in the shift register is shifted one position toward the initial position among the plurality of positions so that the end position among the plurality of positions is not occupied; and A second portion of the bits of the third vector value is input to the multiplexer, wherein the multiplexer is configured to select one of the third plurality of prefetch output values ​​based on the second portion of the bits of the third vector value.

18. The device according to claim 17, wherein, Following the prefetching of the third plurality of output values ​​as indicated by the third vector value: The first output value is shifted one position from the first position to the second position (332-29) among the plurality of positions; and The second output value is shifted one position from the end position to the first position among the plurality of positions.

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