Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device may include: a column switch electrically connecting a global bit line to a bit line or electrically disconnecting the global bit line from the bit line; a row switch electrically connecting the global word line to the word line or electrically disconnecting the global word line from the word line; and a memory cell electrically connected between the bit line and the word line. During a write operation, one or both of a degree of conduction of the column switch and a degree of conduction of the row switch may be changed.

Description

[0001] Cross-references to related applications This application claims priority to Korean Patent Application No. 10-2024-0114539, filed on August 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to integrated circuit technology, and more specifically, to semiconductor devices and methods of operating semiconductor devices. Background Technology

[0003] In recent years, with the miniaturization, low power consumption, high performance, and diversification of electronic devices, there has been a demand for semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices. These semiconductor devices can be broadly classified into volatile memory devices and non-volatile memory devices. Volatile memory devices retain data only when powered, while non-volatile memory devices retain data even when no power is supplied.

[0004] Among non-volatile memory devices, NAND flash memory is representative. Next-generation memory under development includes ferroelectric RAM (random access memory) (FRAM), magnetic RAM (MRAM), phase change RAM (PRAM), polymer RAM (PoRAM), and resistive RAM (ReRAM). Summary of the Invention

[0005] In one embodiment, a semiconductor device may include: one or more column switches that electrically connect global bit lines to bit lines / electrically disconnect global bit lines from bit lines; one or more row switches that electrically connect global word lines to word lines / electrically disconnect global word lines from word lines; and memory cells electrically connected between the bit lines and word lines, wherein, during a write operation, the conduction level of at least one of the column switches and row switches can be changed.

[0006] In one embodiment, a method of operating a semiconductor device may include: a first connection step of electrically connecting a global bit line to a target bit line during a write operation; a second connection step of electrically connecting a global word line to a target word line during a write operation; a direction determination step of determining the direction of current to be supplied to a memory cell connected between the bit line and the word line; and a current amount adjustment step of adjusting the amount of current flowing in the direction determined in the direction determination step.

[0007] In one embodiment, a semiconductor device may include: a memory cell for storing data; at least one first transistor that electrically connects a bit line to the memory cell / electrically disconnects a bit line from the memory cell; and at least one second transistor that electrically connects a word line to the memory cell / electrically disconnects a word line from the memory cell, wherein, during a write operation, the voltage level applied to the gate of at least one of the first and second transistors may change based on the data. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a diagram illustrating a first write operation of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3 This is a diagram illustrating a second write operation of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4 , Figure 5 and Figure 6 This is a diagram illustrating data storage operations of a memory cell for a write operation of a semiconductor device according to embodiments of the present disclosure.

[0012] Figure 7 This is a diagram illustrating the readout operation of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0013] Various embodiments are intended to provide a semiconductor device capable of writing and reading memory cells at multilevels and a method of operating the semiconductor device.

[0014] Because memory cells can be written and read at multiple levels, the data storage capacity of semiconductor devices can be increased without changing the manufacturing process.

[0015] Some embodiments of this disclosure will now be described with reference to the accompanying drawings. As used herein (including the claims), a list of items beginning with phrases such as “at least one of…”, “one or more of…”, or “one or two of…” indicates an inclusive list, such that, for example, a list of “at least one of A and B” and a list of “one or two of A and B” both indicate A, or B, or AB (i.e., A and B). Furthermore, the term “a” or “an” entity refers to one or more of that entity. For example, the terms “a” or “an,” “one or more,” and “at least one” are used interchangeably herein.

[0016] Figure 1 This is a diagram illustrating the configuration of a semiconductor device 100 according to an embodiment of the present disclosure.

[0017] A semiconductor device 100 according to an embodiment of the present disclosure includes a memory cell MC connected between a bit line BL and a word line WL. For ease of description, an example of a memory cell MC connected between one bit line BL and one word line WL is used, but embodiments of the present disclosure are not limited to this configuration. For example, Figure 1 The semiconductor device 100 shown includes a selectable bit line BL from a plurality of bit lines (not shown), a selected word line WL from a plurality of word lines (not shown), and a memory cell MC connected between the selectable bit line BL and the selected word line WL. Here, a plurality of memory cells (not shown) may be connected between the plurality of bit lines and the plurality of word lines, and the memory cell MC connected between the selectable bit line BL and the selected word line WL is a memory cell MC selected from the plurality of memory cells.

[0018] Reference Figure 1 A semiconductor device 100 according to an embodiment of the present disclosure includes a first column switch (e.g., a global column switch) GYS, a second column switch (e.g., a local column switch) LYS, a first row switch (e.g., a global row switch) GXS, a second row switch (e.g., a local row switch) LXS, and a memory cell MC. The semiconductor device 100 according to an embodiment of the present disclosure may further include a first write voltage generation circuit 10, a second write voltage generation circuit 20, and a sensing circuit 30 capable of driving bit lines BL and word lines WL to store data in the memory cell MC or to sense the stored data. For example, the first write voltage generation circuit 10 and the second write voltage generation circuit 20 can drive bit lines BL and word lines WL to store data in the memory cell MC, while the sensing circuit 30 can drive bit lines BL and word lines WL to sense the stored data.

[0019] In one embodiment, the global column switch GYS is turned on or off based on the global column address signal GY_a. When the global column switch GYS is on, it electrically connects the global bit line GBL to the local column switch LYS. The degree of on / off state of the global column switch GYS is determined based on the voltage level of the global column address signal GY_a. When the global column switch GYS is off, it electrically disconnects the global bit line GBL from the local column switch LYS.

[0020] For example, the global column switch GYS includes a first transistor T1.

[0021] In one embodiment, the first transistor T1 includes: a control terminal (e.g., a gate), to which a global column address signal GY_a is input; and a first terminal (e.g., a drain) and a second terminal (e.g., a source), with a global bit line GBL and a local column switch LYS connected to the first and second terminals, respectively. For example, the first transistor T1 is a P-type transistor. As the voltage level of the global column address signal GY_a decreases, the conduction level of the first transistor T1 increases. As the conduction level increases, the first transistor T1 allows a large amount of current to flow. In other words, as the voltage level of the global column address signal GY_a decreases, the conduction level of the first transistor T1 increases and the on-resistance of the first transistor T1 decreases, thereby increasing the amount of current flowing through the first transistor T1. On the other hand, as the voltage level of the global column address signal GY_a increases, the conduction level of the first transistor T1 decreases. As the conduction level decreases, the first transistor T1 allows a small amount of current to flow.

[0022] In one embodiment, the local column switch LYS is turned on or off based on the local column address signal LY_a. When the local column switch LYS is on, it electrically connects the global column switch GYS to the bit line BL. The degree of on / off state of the local column switch LYS is determined by the voltage level of the local column address signal LY_a. When the local column switch LYS is off, it electrically disconnects the global column switch GYS from the bit line BL.

[0023] For example, the local column switch LYS includes a second transistor T2.

[0024] In one embodiment, the second transistor T2 includes: a control terminal (e.g., a gate), to which a local column address signal LY_a is input; and a first terminal (e.g., a drain) and a second terminal (e.g., a source), with a global column switch GYS and a bit line BL connected to the first and second terminals, respectively. For example, the second transistor T2 is a P-type transistor. As the voltage level of the local column address signal LY_a decreases, the conduction level of the second transistor T2 increases. Furthermore, with the increased conduction level, the second transistor T2 allows a large amount of current to flow. Conversely, as the voltage level of the local column address signal LY_a increases, the conduction level of the second transistor T2 decreases. Furthermore, with the decreased conduction level, the second transistor T2 allows a small amount of current to flow.

[0025] In one embodiment, the memory cell MC is connected between the bit line BL and the word line WL. The memory cell MC is connected to the local column switch LYS via the bit line BL. The memory cell MC is connected to the local row switch LXS via the word line WL. The memory cell MC is a memory cell with bidirectional current characteristics. For example, the threshold voltage level of the memory cell MC is determined based on the direction of the current flowing through the memory cell MC during a write operation. The threshold voltage level of the memory cell MC differs when current flows through the memory cell MC in a first direction compared to when current flows through the memory cell MC in a second direction. The first direction and the second direction are different from each other. For example, the memory cell MC is a variable resistor memory cell.

[0026] In one embodiment, the storage cell MC comprises a chalcogenide material. The storage cell MC is a storage unit that stores data by causing a phase transition in the chalcogenide material according to changes in the direction and magnitude of the applied current.

[0027] In one embodiment, a local row switch LXS is turned on or off based on a local row address signal LX_a. When the local row switch LXS is on, it electrically connects the word line WL to the global row switch GXS. The degree of on / off state of the local row switch LXS is determined by the voltage level of the local row address signal LX_a. Conversely, when the local row switch LXS is off, it electrically disconnects the word line WL from the global row switch GXS.

[0028] For example, the local row switch LXS includes a third transistor T3.

[0029] In one embodiment, the third transistor T3 has: a control terminal (e.g., gate) to which a local row address signal LX_a is input; and a first terminal (e.g., drain) and a second terminal (e.g., source), with a word line WL and a global row switch GXS connected to the first and second terminals, respectively. For example, the third transistor T3 is an N-type transistor. As the voltage level of the local row address signal LX_a increases, the conduction level of the third transistor T3 increases. Furthermore, with the increased conduction level, the third transistor T3 allows a large amount of current to flow. On the other hand, as the voltage level of the local row address signal LX_a decreases, the conduction level of the third transistor T3 decreases. Furthermore, with the decreased conduction level, the third transistor T3 allows a small amount of current to flow.

[0030] In one embodiment, the global row switch GXS is turned on or off based on the global row address signal GX_a. When the global row switch GXS is on, it electrically connects the local row switch LXS to the global word line GWL. The degree of on / off state of the global row switch GXS is determined by the voltage level of the global row address signal GX_a. Conversely, when the global row switch GXS is off, it electrically disconnects the local row switch LXS from the global word line GWL.

[0031] For example, the global row switch GXS includes a fourth transistor T4.

[0032] In one embodiment, the fourth transistor T4 has: a control terminal (e.g., gate) to which a global row address signal GX_a is input; and a first terminal (e.g., drain) and a second terminal (e.g., source), with a local row switch LXS and a global word line GWL connected to the first and second terminals, respectively. For example, the fourth transistor T4 is an N-type transistor. As the voltage level of the global row address signal GX_a increases, the conduction level of the fourth transistor T4 increases. Furthermore, as the conduction level increases, the fourth transistor T4 allows a large amount of current to flow. On the other hand, as the voltage level of the global row address signal GX_a decreases, the conduction level of the fourth transistor T4 decreases.

[0033] Furthermore, as the conduction level decreases, the fourth transistor T4 allows a small amount of current to pass through. Although it has been used Figure 1 As an example, a semiconductor device 100 according to an embodiment of the present disclosure is described, wherein it is assumed that the first transistor T1 and the second transistor T2 are P-type transistors, and the third transistor T3 and the fourth transistor T4 are N-type transistors; however, the embodiments of the present disclosure are not limited thereto. In some embodiments, the first transistor T1 and the second transistor T2 may be N-type transistors, while the third transistor T3 and the fourth transistor T4 may be P-type transistors. In some embodiments, the first to fourth transistors T1, T2, T3 and T4 may all be either P-type transistors or N-type transistors.

[0034] In one embodiment, during a write operation, a first write voltage generation circuit 10 and a second write voltage generation circuit 20 provide write voltages with different levels to the global bit line GBL and the global word line GWL, respectively. For example, the first write voltage generation circuit 10 generates a higher voltage level write voltage compared to the second write voltage generation circuit 20. The first write voltage generation circuit 10 also generates a lower voltage level write voltage compared to the second write voltage generation circuit 20. As an example, when the first write voltage generation circuit 10 generates a positive voltage during a write operation and provides this positive voltage as the write voltage to the global bit line GBL, the second write voltage generation circuit 20 generates a negative voltage and provides this negative voltage as the write voltage to the global word line GWL. Furthermore, when the first write voltage generation circuit 10 generates a negative voltage during a write operation and provides this negative voltage to the global bit line GBL, the second write voltage generation circuit 20 generates a positive voltage and provides this positive voltage to the global word line GWL.

[0035] In one embodiment, the sensing circuit 30 is configured to sense the memory cell MC during a read operation. For example, the sensing circuit 30 senses the amount of current flowing through the memory cell MC during a read operation and outputs the data stored in the memory cell MC. As an example, the sensing circuit 30 is connected to the global word line GWL and is configured to sense the amount of current flowing from the bit line BL through the memory cell MC to the global word line GWL during a read operation. In this case, the sensing circuit 30 is configured to generate a voltage corresponding to the amount of current flowing through the memory cell MC, compare the level of the generated voltage with the level of a reference voltage, and determine the data stored in the memory cell MC.

[0036] Figure 2 This is a diagram illustrating a first write operation of a semiconductor device according to an embodiment of the present disclosure. Figure 2 The diagram illustrates a memory cell MC selected via address signals when a semiconductor device contains multiple memory cells. The address signals include column address signals and row address signals. The column address signals include a first column address signal (e.g., a global column address signal GY_a) and a second column address signal (e.g., a local column address signal LY_a), while the row address signals include a first row address signal (e.g., a global row address signal GX_a) and a second row address signal (e.g., a local row address signal LX_a).

[0037] Reference Figure 2 The first write operation is to write to the memory cell MC by providing a first-direction current FWD_I to the memory cell MC selected by the address signal.

[0038] For example, the selected memory cell MC is electrically connected to the global bit line GBL via the bit line BL, and via the global column switch GYS and the local column switch LYS, which are activated according to the global column address signal GY_a and the local column address signal LY_a. Furthermore, the selected memory cell MC is electrically connected to the global word line GWL via the word line WL, and via the global row switch GXS and the local row switch LXS, which are activated according to the global row address signal GX_a and the local row address signal LX_a. Hereinafter, for ease of description, the selected memory cell MC will be referred to as memory cell MC.

[0039] In one embodiment, during the first write operation, the global bit line GBL receives a higher voltage level compared to the global word line GWL.

[0040] Therefore, during the first write operation, a first-direction current FWD_I flows through the memory cell MC via the global bit line GBL, global column switch GYS, local column switch LYS, and bit line BL to the word line WL, local row switch LXS, global row switch GXS, and global word line GWL. In other words, during the first write operation, the first-direction current FWD_I flows sequentially through the global bit line GBL, global column switch GYS, local column switch LYS, bit line BL, memory cell MC, word line WL, local row switch LXS, global row switch GXS, and global word line GWL. That is, during the first write operation, the first-direction current FWD_I flows from the bit line BL through the memory cell MC to the word line WL.

[0041] Figure 3 This is a diagram illustrating a second write operation of a semiconductor device according to an embodiment of the present disclosure. Figure 2 similar, Figure 3 The diagram illustrates a memory cell MC selected via address signals when a semiconductor device contains multiple memory cells. The address signals include column address signals and row address signals. Furthermore, the column address signals include a global column address signal GY_a and a local column address signal LY_a, while the row address signals include a global row address signal GX_a and a local row address signal LX_a.

[0042] Reference Figure 3 The second write operation is performed by providing a second-direction current RVS_I to the memory cell MC selected by the address signal to write to the memory cell MC.

[0043] For example, the selected memory cell MC is electrically connected to the global bit line GBL via the bit line BL, and via the global column switch GYS and the local column switch LYS, which are activated according to the global column address signal GY_a and the local column address signal LY_a. Furthermore, the selected memory cell MC is electrically connected to the global word line GWL via the word line WL, and via the global row switch GXS and the local row switch LXS, which are activated according to the global row address signal GX_a and the local row address signal LX_a. Hereinafter, for ease of description, the selected memory cell MC will be referred to as memory cell MC.

[0044] In one embodiment, during the second write operation, the global bit line GBL receives a voltage with a lower level than the global word line GWL.

[0045] Therefore, during the second write operation, a second-direction current RVS_I flows through the memory cell MC via the global word line GWL, global row switch GXS, local row switch LXS, and word line WL to the bit line BL, local column switch LYS, global column switch GYS, and global bit line GBL. In other words, during the second write operation, the second-direction current RVS_I flows sequentially through the global word line GWL, global row switch GXS, local row switch LXS, word line WL, memory cell MC, bit line BL, local column switch LYS, global column switch GYS, and global bit line GBL. That is, during the second write operation, the second-direction current RVS_I flows from the word line WL through the memory cell MC to the bit line BL.

[0046] Figure 4 , Figure 5 and Figure 6 This is a diagram illustrating data storage operations of a memory cell for a write operation of a semiconductor device according to embodiments of the present disclosure.

[0047] Figure 4 Used to illustrate according to Figure 2 and Figure 3 The states of the memory cell MC and the voltage levels of the address signals for the first and second write operations are shown.

[0048] In one embodiment, when the first directional current FWD_I flows through the memory cell MC during the first write operation, the memory cell MC is in a first state (e.g., entering the first state). Furthermore, when the second directional current RVS_I flows through the memory cell MC during the second write operation, the memory cell MC is in a second state (e.g., entering the second state). The first state and the second state are different from each other.

[0049] For example, refer to Figure 4 When the first directional current FWD_I flows through the memory cell MC, the memory cell MC enters the set state SET. On the other hand, when the second directional current RVS_I flows through the memory cell MC, the memory cell MC enters the reset state RST. The set state SET is a state in which the threshold voltage level of the memory cell MC is lower than that of the reset state RST. Therefore, when different voltage levels are supplied to the bit line BL and the word line WL during a read operation, and the voltage difference between the two ends of the memory cell MC is equal to the level of the read voltage Vread, the memory cell MC in the set state SET is turned on, allowing current to flow, while the memory cell MC in the reset state RST is turned off, resulting in virtually no current flow.

[0050] As an example, during a read operation, a higher voltage is applied to the bit line BL compared to the word line WL, and current flows via the bit line BL, the memory cell MC, and the word line WL to the global word line GWL. In other words, during a read operation, current flows sequentially through the bit line BL, the memory cell MC, the word line WL, and the global word line GWL. In this case, the sensing circuit 30 connected to the global word line GWL senses the amount of current that varies depending on whether the memory cell MC is on, and determines the data stored in the memory cell MC. Figure 4 In one embodiment, it is determined that the memory cell MC in the set state SET stores data with a first value (e.g., 0), while the memory cell MC in the reset state RST stores data with a second value (e.g., 1).

[0051] In this way, during the first and second write operations, the voltage level (ADD Voltage) of the address signals that enable the global column switch GYS, local column switch LYS, global row switch GXS, and local row switch LXS remains unchanged. That is, during the first and second write operations, the voltage level (ADD Voltage) of the address signals that enable the global column switch GYS, local column switch LYS, global row switch GXS, and local row switch LXS is maintained at a constant level. For example, the global column switch GYS and local column switch LYS, composed of P-type transistors, are enabled by the global column address signal GY_a and the local column address signal LY_a, which have a first voltage level. Similarly, the global row switch GXS and local row switch LXS, composed of N-type transistors, are enabled by the global row address signal GX_a and the local row address signal LX_a, which have a second voltage level. Furthermore, since the first and second voltage levels for enabling different types of switches remain essentially constant, the degree of activation of each switch also remains essentially constant.

[0052] Figure 5 This diagram illustrates a write operation that causes the memory cell MC to have a first set state SET1 or a second set state SET2 (e.g., changing the memory cell MC to the first set state SET1 or the second set state SET2) through a first write operation. In this case, when the first directional current FWD_I is as... Figure 2 When the flow is as shown, the state of the storage cell MC is in the set state SET (for example, it becomes the set state SET), but the set state SET changes according to the amount of the first direction current FWD_I.

[0053] Reference Figure 5The state of the memory cell MC changes to either a first set state SET1 or a second set state SET2 based on the amount of the first directional current FWD_I. For example, the threshold voltage level of the memory cell MC in the first set state SET1 is different from the threshold voltage level of the memory cell MC in the second set state SET2. More specifically, for example, the threshold voltage level of the memory cell MC in the first set state SET1 is lower than the threshold voltage level of the memory cell MC in the second set state SET2. In this case, the amount of the first directional current FWD_I used to change the memory cell MC to the first set state SET1 is less than the amount of the first directional current FWD_I used to change the memory cell MC to the second set state SET2. That is, during the first write operation, the amount of the first directional current FWD_I flowing through the memory cell MC in the first set state SET1 is less than the amount of the first directional current FWD_I flowing through the memory cell MC in the second set state SET2.

[0054] Therefore, the semiconductor device according to an embodiment of the present disclosure can change the amount of the first directional current FWD_I during a first write operation by changing the voltage level ADD Voltage of the address signal provided to at least one of the global column switch GYS, the local column switch LYS, the global row switch GXS, and the local row switch LXS, so as to change the state of the memory cell MC to a first set state SET1 or a second set state SET2.

[0055] For example, in order to change the state of the memory cell MC to either the first set state SET1 or the second set state SET2, the voltage level ADD Voltage of the address signal provided to one or both of the global row switch GXS and the local row switch LXS, which are composed of N-type transistors, is changed.

[0056] In one embodiment, the higher the voltage level of the signal supplied to the gate of the N-type transistor, the greater the current flow allowed through the N-type transistor. Conversely, the lower the voltage level of the signal supplied to the gate of the N-type transistor, the smaller the current flow allowed through the N-type transistor.

[0057] Therefore, during the first write operation, the amount of the first-direction current FWD_I flowing through the memory cell MC changes according to the voltage level of the address signal provided to one or both of the global row switch GXS and the local row switch LXS.

[0058] For example, the following describes the operation of controlling the voltage level of the local row address signal LX_a provided to the local row switch LXS so as to change the state of the memory cell MC to a first set state SET1 or a second set state SET2 during a first write operation. When the state of the memory cell MC changes to the first set state SET1, a local row address signal LX_a with a lower voltage level is provided to the local row switch LXS compared to when the state of the memory cell MC changes to the second set state SET2. On the other hand, when the state of the memory cell MC changes to the second set state SET2, a local row address signal LX_a with a higher voltage level is provided to the local row switch LXS compared to when the state of the memory cell MC changes to the first set state SET1.

[0059] although Figure 5 Not shown, but in order to change the state of the memory cell MC to the first set state SET1 or the second set state SET2, the voltage level ADD Voltage of the address signal provided to one or both of the global column switch GYS and the local column switch LYS composed of P-type transistors is changed.

[0060] The lower the voltage level of the signal supplied to the gate of a P-type transistor, the larger the current flow allowed through it. Conversely, the higher the voltage level of the signal supplied to the gate of a P-type transistor, the smaller the current flow allowed through it.

[0061] Therefore, during the first write operation, the amount of the first-direction current FWD_I flowing through the memory cell MC changes according to the voltage level of the address signal provided to one or both of the global column switch GYS and the local column switch LYS.

[0062] For example, the operation of controlling the voltage level of the local column address signal LY_a provided to the local column switch LYS is described below so as to change the state of the memory cell MC to a first set state SET1 or a second set state SET2 during a first write operation. When the state of the memory cell MC changes to the first set state SET1, the local column address signal LY_a with a higher voltage level is provided to the local column switch LYS compared to when the state of the memory cell MC changes to the second set state SET2. On the other hand, when the state of the memory cell MC changes to the second set state SET2, the local column address signal LY_a with a lower voltage level is provided to the local column switch LYS compared to when the state of the memory cell MC changes to the first set state SET1.

[0063] Figure 6This diagram illustrates a write operation that causes the memory cell MC to have a first reset state RST1 or a second reset state RST2 (e.g., changing the memory cell MC to the first reset state RST1 or the second reset state RST2) by using a second write operation. In this case, when the second directional current RVS_I... Figure 3 When the flow is as shown, the state of the storage cell MC is in the reset state RST (for example, it becomes the reset state RST), but the reset state RST changes according to the amount of the second directional current RVS_I.

[0064] Reference Figure 6 The state of the memory cell MC is changed to either a first reset state RST1 or a second reset state RST2 based on the amount of the second directional current RSV_I. For example, the threshold voltage level of the memory cell MC in the first reset state RST1 is different from the threshold voltage level of the memory cell MC in the second reset state RST2. More specifically, for example, the threshold voltage level of the memory cell MC in the first reset state RST1 is lower than the threshold voltage level of the memory cell MC in the second reset state RST2. In this case, the amount of the second directional current RVS_I used to change the memory cell MC to the first reset state RST1 is less than the amount of the second directional current RVS_I used to change the memory cell MC to the second reset state RST2. That is, during the second write operation, the amount of the second directional current RVS_I flowing through the memory cell MC in the first reset state RST1 is less than the amount of the second directional current RVS_I flowing through the memory cell MC in the second reset state RST2.

[0065] Therefore, the semiconductor device according to embodiments of the present disclosure can change the amount of the second directional current RVS_I during the second write operation by changing the voltage level ADD Voltage of the address signal provided to at least one of the global column switch GYS, the local column switch LYS, the global row switch GXS, and the local row switch LXS, so as to change the state of the memory cell MC to a first reset state RST1 or a second reset state RST2.

[0066] For example, in order to change the state of the memory cell MC to the first reset state RST1 or the second reset state RST2, the voltage level ADD Voltage of the address signal provided to one or both of the global row switch GXS and the local row switch LXS, which are composed of N-type transistors, is changed.

[0067] In one embodiment, the higher the voltage level of the signal supplied to the gate of the N-type transistor, the greater the current flow allowed through the N-type transistor. Conversely, the lower the voltage level of the signal supplied to the gate of the N-type transistor, the smaller the current flow allowed through the N-type transistor.

[0068] Therefore, during the second write operation, the amount of the second-direction current RVS_I flowing through the memory cell MC changes according to the voltage level of the address signal provided to one or both of the global row switch GXS and the local row switch LXS.

[0069] For example, the operation of controlling the voltage level of the local row address signal LX_a provided to the local row switch LXS is described below so as to change the state of the memory cell MC to a first reset state RST1 or a second reset state RST2 during a second write operation. When the state of the memory cell MC changes to the first reset state RST1, a local row address signal LX_a with a lower voltage level is provided to the local row switch LXS compared to when the state of the memory cell MC changes to the second reset state RST2. On the other hand, when the state of the memory cell MC changes to the second reset state RST2, a local row address signal LX_a with a higher voltage level is provided to the local row switch LXS compared to when the state of the memory cell MC changes to the first reset state RST1.

[0070] Although Figure 6 Not shown, but in order to change the state of the memory cell MC to the first reset state RST1 or the second reset state RST2, the voltage level ADD Voltage of the address signal provided to one or both of the global column switch GYS and the local column switch LYS composed of P-type transistors is changed.

[0071] The lower the voltage level of the signal supplied to the gate of a P-type transistor, the larger the current flow allowed through it. Conversely, the higher the voltage level of the signal supplied to the gate of a P-type transistor, the smaller the current flow allowed through it.

[0072] Therefore, during the second write operation, the amount of the second-direction current RVS_I flowing through the memory cell MC changes according to the voltage level of the address signal provided to one or both of the global column switch GYS and the local column switch LYS.

[0073] For example, the following describes the operation of controlling the voltage level of the local column address signal LY_a provided to the local column switch LYS so as to change the state of the memory cell MC to either a first reset state RST1 or a second reset state RST2 during a second write operation. When the state of the memory cell MC changes to the first reset state RST1, the local column address signal LY_a with a higher voltage level is provided to the local column switch LYS compared to when the state of the memory cell MC changes to the second reset state RST2. On the other hand, when the state of the memory cell MC changes to the second reset state RST2, the local column address signal LY_a with a lower voltage level is provided to the local column switch LYS compared to when the state of the memory cell MC changes to the first reset state RST1.

[0074] As described above, the semiconductor device according to embodiments of the present disclosure can control the amount of current flowing through the memory cell MC during a write operation to change the state of the memory cell MC to a corresponding one of one or more reset states among a plurality of set states. In one embodiment, the memory cell MC is controlled according to a first directional current (e.g., Figure 2 The first directional current FWD_I in the middle is in multiple set states with different threshold voltage levels (e.g., Figure 5 The corresponding one of the first set state SET1 and the second set state SET2 in the control column (e.g., ...). The amount of the first direction current is controlled by the column switch (e.g., ... Figure 1 The conduction level of the global column switch GYS, or the local column switch LYS, or both, or the control row switch (e.g., Figure 1 The conduction level of the global row switch GXS, or the local row switch LXS, or both, is changed by controlling both. In one embodiment, the memory cell MC is adjusted based on the second directional current (e.g., Figure 3 The amount of the second directional current (RVS_I) in the middle is in multiple reset states with different threshold voltage levels (e.g., Figure 6 The corresponding one of the first reset state RST1 and the second reset state RST2 in the system. The amount of the second direction current is controlled by the column switch (e.g., Figure 1 The conduction level of the global column switch GYS, or the local column switch LYS, or both, or the control row switch (e.g., Figure 1 The conduction level of the global row switch GXS, or the local row switch LXS, or both, can be changed by controlling both. In this case, the semiconductor device according to embodiments of the present disclosure can change the voltage level of the address signal used to select the memory cell MC in order to control the amount of current flowing through the memory cell MC during a write operation.

[0075] Figure 7This is a diagram illustrating the readout operation of a semiconductor device according to an embodiment of the present disclosure. Figure 7 This is a diagram illustrating the operation of reading a memory cell that is in one of one or more reset states among multiple set states. In this case, the multiple set states include a first set state SET1 and a second set state SET2, and the multiple reset states include a first reset state RST1 and a second reset state RST2.

[0076] Reference Figure 7 The threshold voltage level of memory cell MC in the first set state SET1 is lower than the threshold voltage level of memory cell MC in the second set state SET2. The threshold voltage level of memory cell MC in the second set state SET2 is lower than the threshold voltage level of memory cell MC in the first reset state RST1. The threshold voltage level of memory cell MC in the first reset state RST1 is lower than the threshold voltage level of memory cell MC in the second reset state RST2.

[0077] In one embodiment, the level of the first read voltage Vread (1) is lower than the level of the second read voltage Vread (2). The level of the second read voltage Vread (2) is lower than the level of the third read voltage Vread (3). Furthermore, the level of the first read voltage Vread (1) is a voltage level corresponding to the threshold voltage level of the memory cell MC between the first set state SET1 and the second set state SET2. The level of the second read voltage Vread (2) is a voltage level corresponding to the threshold voltage level of the memory cell MC between the second set state SET2 and the first reset state RST1. The level of the third read voltage Vread (3) is a voltage level corresponding to the threshold voltage level of the memory cell MC between the first reset state RST1 and the second reset state RST2.

[0078] In one embodiment, the first, second, and third read voltages Vread(1), Vread(2), and Vread(3) are the voltage level differences applied to the two ends of the memory cell MC during a read operation. That is, the read operation is an operation that senses the current changing according to the on or off state of the memory cell MC by providing voltages of different levels to the bit line BL and the word line WL such that the voltage level difference between the two ends of the memory cell MC is one of the first to third read voltages Vread(1), Vread(2), and Vread(3). For example, the voltage level applied to the bit line BL during the read operation is higher than the voltage level applied to the word line WL. When voltages corresponding to the first to third read voltages Vread(1), Vread(2), and Vread(3) are provided to the two ends of the memory cell MC respectively during the read operation, the amount of current flowing from the bit line BL through the memory cell MC to the word line WL changes according to the on or off state of the memory cell MC. In this configuration, word line WL is connected to global word line GWL via local row switch LXS and global row switch GXS, thus electrically connecting word line WL to sensing circuit 30 connected to global word line GWL. Sensing circuit 30 senses the amount of current supplied through word line WL and global word line GWL during read operations to determine the state of memory cell MC.

[0079] More specifically, the read operation of the semiconductor device according to embodiments of the present disclosure is described below.

[0080] According to embodiments of the present disclosure, a read operation of a semiconductor device provides voltages of different levels to the two ends of a memory cell MC, such that the voltage level difference between the two ends of the memory cell MC sequentially corresponds to a first read voltage Vread (1), a second read voltage Vread (2), and a third read voltage Vread (3). In one embodiment, the semiconductor device according to embodiments of the present disclosure sequentially provides multiple read voltages (e.g., ...) to the memory cell MC during a read operation. Figure 7 The first, second, and third read voltages Vread(1), Vread(2), and Vread(3) are used to determine the state of the memory cell MC. Once the state of the memory cell MC is determined, the semiconductor device can stop sequentially providing read voltages. For example, the memory controller of the semiconductor device can sequentially provide multiple read voltages to the memory cell MC, or stop providing multiple read voltages to the memory cell.

[0081] First, voltages of different levels are supplied to the two ends of the memory cell MC, such that the voltage level difference between the two ends of the memory cell MC corresponds to the level of the first read voltage Vread (1). In this case, when the memory cell MC is in the first set state SET1, the memory cell MC is turned on, and a larger current is supplied to the global word line GWL through the memory cell MC via the word line WL compared to when the memory cell MC is turned off. The sensing circuit 30 connected to the global word line GWL compares the level of the voltage corresponding to the current flowing through the memory cell MC with the level of a reference voltage. When the voltage level corresponding to the current flowing through the memory cell MC is higher than the level of the reference voltage, the sensing circuit 30 determines that the memory cell MC is in the first set state SET1. When the memory cell MC is determined to be in the first set state SET1, the supply of the second read voltage Vread (2) and the third read voltage Vread (3) to the memory cell MC is stopped.

[0082] On the other hand, when the voltage level corresponding to the current flowing through the memory cell MC is lower than the level of the reference voltage, the sensing circuit 30 determines that the memory cell MC is not in the first set state SET1. Subsequently, voltages with different levels are supplied to the two ends of the memory cell MC, such that the voltage level difference between the two ends of the memory cell MC corresponds to the level of the second read voltage Vread (2). In this case, when the memory cell MC is in the second set state SET2, the memory cell MC is turned on, and a larger current is supplied to the global word line GWL through the memory cell MC via the word line WL compared to when the memory cell MC is turned off. The sensing circuit 30 connected to the global word line GWL compares the level of the voltage corresponding to the current flowing through the memory cell MC with the level of the reference voltage. When the voltage level corresponding to the current flowing through the memory cell MC is higher than the level of the reference voltage, the sensing circuit 30 determines that the memory cell MC is in the second set state SET2. When the memory cell MC is determined to be in the second set state SET2, the supply of the third read voltage Vread (3) to the memory cell MC is stopped.

[0083] Furthermore, when the voltage level corresponding to the current flowing through the memory cell MC is lower than the level of the reference voltage, the sensing circuit 30 determines that the memory cell MC is not in the second set state SET2. Subsequently, voltages with different levels are provided to the two ends of the memory cell MC, such that the voltage level difference between the two ends of the memory cell MC corresponds to the level of the third read voltage Vread (3). In this case, when the memory cell MC is in the first reset state RST1, the memory cell MC is turned on, and a larger current is supplied to the global word line GWL through the memory cell MC via the word line WL compared to when the memory cell MC is turned off. The sensing circuit 30 connected to the global word line GWL compares the level of the voltage corresponding to the current flowing through the memory cell MC with the level of the reference voltage. When the voltage level corresponding to the current flowing through the memory cell MC is higher than the level of the reference voltage, the sensing circuit 30 determines that the memory cell MC is in the first reset state RST1. With the third read voltage Vread (3) already provided, when the voltage level corresponding to the current flowing through the memory cell MC is lower than the level of the reference voltage, the sensing circuit 30 determines that the memory cell MC is in the second reset state RST2. The first set state SET1 indicates that the storage cell MC stores the decimal number 0. The second set state SET2 indicates that the storage cell MC stores the decimal number 1. The first reset state RST1 indicates that the storage cell MC stores the decimal number 2. The second reset state RST2 indicates that the storage cell MC stores the decimal number 3. In this case, the decimal number 0 corresponds to the combination of binary numbers 00, the decimal number 1 corresponds to the combination of binary numbers 01, the decimal number 2 corresponds to the combination of binary numbers 10, and the decimal number 3 corresponds to the combination of binary numbers 11. Therefore, the first set state SET1 indicates that the storage cell MC stores the combination of binary numbers 00. The second set state SET2 indicates that the storage cell MC stores the combination of binary numbers 01. The first reset state RST1 indicates that the storage cell MC stores the combination of binary numbers 10. The second reset state RST2 indicates that the storage cell MC stores the combination of binary numbers 11.

[0084] As described above, the read operation of the semiconductor device according to embodiments of the present disclosure can sequentially provide multiple read voltages to the two ends of the memory cell MC in an order of increasing read voltage from the lowest voltage level to the highest voltage level, so as to determine that the state of the memory cell is in a specific state among multiple set states and multiple reset states.

[0085] Although some embodiments of this disclosure have been described above with reference to the accompanying drawings, the embodiments of this disclosure are not limited to those described above. Those skilled in the art to which this disclosure pertains can make various substitutions, modifications, and changes to the embodiments without departing from the technical spirit of this disclosure as defined in the following claims.

Claims

1. A semiconductor device, comprising: A column switch that electrically connects the global bit line to the bit line or electrically disconnects the global bit line from the bit line; A line switch that electrically connects the global word line to the word line or electrically disconnects the global word line from the word line; as well as The storage cell is electrically connected between the bit line and the word line. During the write operation, one or both of the conduction levels of the column switches and the row switches are changed.

2. The semiconductor device according to claim 1, wherein, The column switch is turned on or off based on the column address signal, and The conduction level of the column switch changes according to the voltage level of the column address signal.

3. The semiconductor device according to claim 1, wherein, The column switch is a first column switch, and the device further includes a second column switch, which electrically connects the global bit line to the bit line or electrically disconnects the global bit line from the bit line. The first column switches and the second column switches are turned on or off based on the first column address signal and the second column address signal, and The conduction level of the first column switch changes according to the voltage level of the first column address signal, or the conduction level of the second column switch changes according to the voltage level of the second column address signal, or both.

4. The semiconductor device according to claim 1, wherein, The row switch is turned on or off based on the row address signal, and The conduction level of the row switch changes according to the voltage level of the row address signal.

5. The semiconductor device according to claim 1, wherein, The row switch is a first row switch, and the device further includes a second row switch, which electrically connects the global word line to the word line or electrically disconnects the global word line from the word line; The first row switch and the second row switch are turned on or off based on the first row address signal and the second row address signal; Wherein, the conduction degree of the first row switch changes according to the voltage level of the first row address signal, or the conduction degree of the second row switch changes according to the voltage level of the second row address signal, or both.

6. The semiconductor device according to claim 1, wherein, During the write operation, the memory cell is in a set state when a voltage with a higher level than that of the word line is supplied to the bit line and current flows in a first direction; During the write operation, the memory cell is in a reset state when a voltage with a lower level than that of the word line is supplied to the bit line and current flows in a second direction.

7. The semiconductor device according to claim 6, wherein, The storage cell is in one of a plurality of set states with different threshold voltage levels according to the amount of the first directional current, the amount of the first directional current being changed by controlling the conduction degree of the column switch, or the conduction degree of the row switch, or both.

8. The semiconductor device according to claim 6, wherein, The storage cell is in one of a plurality of reset states with different threshold voltage levels depending on the amount of the second directional current, the amount of which is changed by controlling the conduction degree of the column switch, or the conduction degree of the row switch, or both.

9. The semiconductor device according to claim 6, wherein, The device sequentially provides multiple read voltages with different voltage levels to the memory cell during a read operation to determine the state of the memory cell.

10. The semiconductor device according to claim 9, wherein, The device sequentially provides the plurality of read voltages to the memory cell in an order of increasing read voltage from the lowest read voltage level to the highest read voltage level.

11. The semiconductor device according to claim 10, wherein, When the state of the storage cell is determined, the device stops sequentially supplying the read voltage to the storage cell.

12. The semiconductor device according to claim 9, wherein, Each read voltage corresponds to the voltage level difference between the bit line and the word line.

13. The semiconductor device according to claim 9, further comprising: A sensing circuit, connected to the global word line, determines the state of the memory cell during the read operation based on the amount of current supplied from the global word line.

14. A method of operating a semiconductor device, comprising: During a write operation, the global bit line is electrically connected to the bit line; During the write operation, the global word line is electrically connected to the word line; Determine the direction of the current flowing through the memory cell, which is connected between the bit line and the word line; as well as Adjust the amount of the current flowing in a specific direction.

15. The operating method according to claim 14, wherein, Electrically connecting the global bit line to the bit line includes: Based on the column address signal, one or both of the first column switch and the second column switch connected between the global bit line and the bit line are turned on.

16. The operating method according to claim 15, wherein, Adjusting the amount of the current includes: The conduction level of the first column switch, or the conduction level of the second column switch, or both, can be adjusted by adjusting the voltage level of the column address signal.

17. The operating method according to claim 14, wherein, Electrically connecting the global word line to the word line includes: Based on the row address signal, one or both of the first row switch and the second row switch connected between the global word line and the word line are turned on.

18. The operating method according to claim 17, wherein, Adjusting the amount of the current includes: The conduction level of the first row switch, or the conduction level of the second row switch, or both, can be adjusted by adjusting the voltage level of the row address signal.

19. The operating method according to claim 14, wherein, The state of the storage unit is either set or reset depending on the direction of the determined current.

20. The operating method according to claim 19, wherein, The set states include multiple set states with different threshold voltage levels, and The state of the storage cell is in one of the plurality of set states depending on the amount of current.

21. The operating method according to claim 19, wherein, The reset states include multiple reset states with different threshold voltage levels, and The state of the storage unit is in one of the plurality of reset states depending on the amount of current.

22. The operating method according to claim 14, further comprising: During a read operation, multiple read voltages with different levels are sequentially supplied to the memory cell.

23. The operating method according to claim 22, wherein, The sequential provision of the plurality of read voltages includes: The read voltages are sequentially supplied to the memory cells in order of increasing read voltage from the lowest level to the highest level.

24. The operating method according to claim 22, wherein, Once the state of the memory cell is determined, the sequential supply of the plurality of read voltages is stopped.

25. A semiconductor device, comprising: Storage unit, which stores data; A first transistor electrically connects the global bit line to the bit line or electrically disconnects the global bit line from the bit line; as well as The second transistor electrically connects the global word line to the word line or electrically disconnects the global word line from the word line. The memory cell is electrically connected between the bit line and the word line, and During a write operation, the conduction level of the first transistor changes according to the voltage level applied to the gate of the first transistor, the conduction level of the second transistor changes according to the voltage level applied to the gate of the second transistor, or both.

26. The semiconductor device of claim 25, wherein, During the write operation, the memory cell is in a set state when a higher voltage is supplied to the bit line compared to the word line and current flows in a first direction. During the write operation, the memory cell is in a reset state when a voltage with a lower level than that of the word line is supplied to the bit line and current flows in a second direction.

27. The semiconductor device according to claim 26, wherein, The state of the memory cell is in one of a plurality of set states with different threshold voltage levels based on the amount of the first directional current, the amount of the first directional current being changed according to the voltage level applied to the gate of the first transistor, or the voltage level applied to the gate of the second transistor, or both.

28. The semiconductor device according to claim 26, wherein, The state of the memory cell is in one of a plurality of reset states with different threshold voltage levels based on the amount of the second directional current, the amount of the second directional current being changed according to the voltage level applied to the gate of the first transistor, or the voltage level applied to the gate of the second transistor, or both.

29. The semiconductor device according to claim 26, wherein, The device sequentially provides multiple read voltages with different voltage levels to the memory cell during a read operation to determine the state of the memory cell.

30. The semiconductor device according to claim 29, wherein, The device sequentially provides the plurality of read voltages to the memory cell in an increasing order, from the read voltage with the lowest voltage level to the read voltage with the highest voltage level.

31. The semiconductor device according to claim 30, wherein, When the state of the storage cell is determined, the device stops sequentially supplying the read voltage to the storage cell.

32. The semiconductor device according to claim 25, wherein, The storage unit is a variable resistance storage unit.

33. The semiconductor device according to claim 32, wherein, The variable resistance storage unit comprises a chalcogenide material.

34. The semiconductor device according to claim 33, wherein, The variable resistance storage unit stores data through the phase transition of the chalcogenide material.

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