Memory device for controlling slew rate and method thereof

Abstract

The invention provides a memory device for controlling slew rate and a method thereof. The memory device includes a memory array, a slew rate control circuit, and an output stage circuit. The memory array provides a data signal. The slew rate control circuit includes a plurality of pre-drivers. The slew rate control circuit obtains a ZQ calibration signal, and adjusts the driving force of each pre-driver in the slew rate control circuit according to the ZQ calibration signal. The pre-driver is to generate a driven enable signal based on the data signal. The output stage circuit generates a data voltage signal according to a driving enable signal and a data signal. A slew rate of the data voltage signal is adjusted based on a driving capability of the pre-driver.

Description

Technical Field

[0001] This invention relates to semiconductor memory technology, and more particularly to a semiconductor memory device and method for controlling and compensating slew rate (SR) using a ZQ calibration signal. Background Technology

[0002] The output stage circuitry of a double data rate memory device needs to meet industry specifications for both DC and AC. Since the component dimensions of the output stage circuitry are determined during the DC stage, the AC output of the output stage circuitry is controlled by a slew rate control circuit.

[0003] The output stage circuit itself is affected by variations in process, voltage, and temperature (PVT), resulting in variations in drive strength. Under certain conditions (e.g., high voltage, fast-fast (FF) corners based on corner analysis), the slew rate may be too high, potentially affecting EMI measurements on the system. Under other conditions (e.g., low voltage, slow-slow (SS) corners based on corner analysis), the slew rate may be too low, leading to a decrease in the effective data window.

[0004] In third-generation double data rate (DDR3) memory devices and subsequent generations of memory devices, although ZQ calibration has been used to reduce the variation in drive strength, the slew rate control circuit, which is based on adjusting the delay time, still incurs additional current consumption and is still affected by different P, V, T variations. Therefore, reducing the delay time variation of the slew rate control circuit is one of the urgent problems to be solved. Summary of the Invention

[0005] The present invention provides a memory device and method for controlling slew rate, which adjusts the driving capability of a pre-driver according to a ZQ calibration signal to compensate for the delay time of the output data voltage signal, thereby reducing the variation of the slew rate of the output signal in the delay time.

[0006] According to an embodiment of the present invention, the memory device includes a memory array, a slew rate control circuit, and an output stage circuit. The memory array provides a data signal. The slew rate control circuit is coupled to the memory array and includes a plurality of pre-drivers. The slew rate control circuit receives a ZQ calibration signal and adjusts the driving capability of each of the pre-drivers in the slew rate control circuit according to the ZQ calibration signal. The pre-drivers are used to generate a driven enable signal based on the data signal. The output stage circuit is coupled to the SR control circuit. The output stage circuit generates the data voltage signal according to the driven enable signal and the data signal. The slew rate of the data voltage signal is adjusted based on the driving capability of the pre-drivers.

[0007] According to an embodiment of the present invention, a method for controlling the slew rate is used to adjust the slew rate of a data voltage signal applied to a memory cell having different PVT characteristics. The method includes: obtaining a ZQ calibration signal for impedance compensation; adjusting the drive capability of a plurality of pre-drivers in a slew rate control circuit according to the ZQ calibration signal, wherein the pre-drivers are used to generate a drive enable signal based on a data signal provided by a memory array; and generating a data voltage signal by an output stage circuit according to the drive enable signal and the data signal, wherein the slew rate of the data voltage signal is adjusted based on the drive capability of the pre-drivers. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a memory device according to an embodiment of the present invention;

[0009] Figure 2 This is a circuit block diagram of the slew rate control circuit and the output stage circuit according to an embodiment of the present invention;

[0010] Figure 3 This is a flowchart illustrating a method for controlling the slewing rate according to an embodiment of the present invention. Detailed Implementation

[0011] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0012] Figure 1 This is a schematic diagram of a memory device 100 according to an embodiment of the present invention. Figure 1As shown, the memory device 100 includes a memory array 110, a slew rate (SR) control circuit 120, and an output stage circuit 130. In this embodiment, the memory device 100 may be a third-generation double data rate (DDR3) memory device, a fourth-generation double data rate (DDR4) memory device, or other memory devices with a ZQ calibration signal.

[0013] Memory array 110 includes one or more memory blocks, each memory block including multiple memory cells arranged in an array. Memory array 110 may be dynamic random access memory (DRAM), static random access memory (SRAM), or any other type of memory (including those that do not require refresh). Memory array 110 may include multiple channels of memory such as synchronous DRAM (SDRAM). SDRAM may be double data rate (DDR). The invention is not limited to the types of memory described above. In one embodiment, each memory array may be coupled to a corresponding output stage circuitry 130 via a memory controller (not shown). The memory array is used to provide a data signal 112. In this embodiment, the data signal 112 is read from memory array 110 and output as a data voltage signal 132 by output stage circuitry 130.

[0014] An SR control circuit 120 is coupled to a memory array 110 and an output stage circuit 130. The SR control circuit 120 receives a data signal 112 and a ZQ calibration signal 104. The SR control circuit 120 includes a plurality of pre-drivers 122. These pre-drivers 122 are used to generate a drive enable signal 124 based on the data signal 112. The SR control circuit 120 receives the ZQ calibration signal 104 and adjusts the drive capability of each of the pre-drivers in the SR control circuit 120 according to the ZQ calibration signal 104. An output stage circuit 130 is coupled to the SR control circuit 120 and the memory array 112. The output stage circuit 130 generates a data voltage signal 132 based on the drive enable signal 124 and the data signal 112. The slew rate of the data voltage signal 132 is adjusted based on the drive capability of the pre-drivers 122.

[0015] It should be noted that the ZQ calibration signal 104 is generally used to compensate for impedance variations in the output stage circuit 130 caused by PVT variations (also known as PVT characteristics). For example, the ZQ calibration signal 104 can be used to adjust the resistance values ​​of the pull-up and pull-down resistors (not shown) within the output stage circuit 130 based on the resistance value of the on-die termination (ODT) resistor during PVT variations. Therefore, the ZQ calibration signal 104 reflects the effects caused by PVT variations.

[0016] This embodiment adjusts the slew rate (also called output slew rate) of the data voltage signal 132 output by the output stage circuit 130 by means of the relationship between the ZQ calibration signal 104 and the driving capability of the pre-driver 122. Specifically, the SR control circuit 120 mainly adjusts the slew rate by delaying the output buffer in the output stage circuit 130 by a certain delay time before it is turned on. Therefore, when this delay time is affected by PVT variations, this embodiment utilizes the existing ZQ calibration signal in third-generation double data rate (DDR3) memory devices and subsequent generations of memory devices to strengthen or weaken the signal strength of the output buffer in the output stage circuit 130 under different PVT characteristics, thereby shortening or increasing the circuit delay time and compensating for the slew rate variation. Furthermore, since this embodiment uses changing the driving capability in the pre-driver to change the delay time and thus compensate for the slew rate variation, rather than adjusting the component parameters on the resistor-capacitor (RC) delay circuit inside the control circuit, no additional current consumption is generated, resulting in greater power saving.

[0017] In this embodiment, the ZQ calibration signal 104 may have N+1 bits. For example, the ZQ calibration signal 104 may also be referred to as the ZQ calibration code ZQC. <n:0>N is a positive integer. In this embodiment, the slew rate compensation is based on a predetermined relationship between the ZQ calibration signal and the driving capability of the pre-driver. In practical applications, considering that the number of bits in the ZQ calibration signal 104 may be large, resulting in more precise impedance calibration, the SR control circuit 120 in this embodiment uses the signals other than the least significant bit (LSB) in the ZQ calibration signal 104 as the adjusted ZQ calibration signal (e.g., the adjusted ZQ calibration signal ZQC). <n:1>This adjusts the driving capability of each pre-driver 122 in the SR control circuit 120. This approach also reduces the increase in chip area caused by the total size of the transistors in the pre-drivers being too large due to overly fine differentiation of driving capabilities. Figure 2 The lieutenant general adjusted the ZQ calibration signal ZQC. <n:1>Presented via the adjusted ZQ calibration signal ZQSC.

[0018] In this embodiment, the SR control circuit 120 includes a pre-driver 122 and a resistor-capacitor (RC) delay circuit. The dimensions of the transistors in the pre-driver 122, the dimensions of the RC delay circuit, and the ZQ calibration signal ZQC are also considered. <n:1>The relationship between these relationships can be determined based on experimental or computer simulation results and can be implemented in the SR control circuit 120 using lookup tables or corresponding logic circuits. For example, based on the fast-fast (FF) and slow-slow (SS) corners determined by boundary angle analysis, the required drive capability of the output stage circuit 130 at these two corners is used as the result, and the result is calibrated by the ZQ calibration signal ZQC. <n:1>Corresponding to the gear changes of the pre-driver, the change value of each gear of the driving capability in the pre-driver is adjusted, thereby adjusting the delay time of the delayed-on output stage circuit 130 to achieve slew rate compensation.

[0019] Figure 2 This is a circuit block diagram of the slew rate control circuit 120 and the output stage circuit 130 according to an embodiment of the present invention. The slew rate control circuit of this embodiment includes at least one enable signal path, and the output stage circuit 130 includes at least one output buffer. The number of enable signal paths and output buffers are the same. Figure 2 As shown, the SR control circuit 120 includes three enable signal paths PE1~PE3, and the output stage circuit 130 includes three output buffers 134-1~134-3. Each enable signal path PE1~PE3 receives the data voltage signal 112 and provides corresponding multiple driver-enabled signals EN1~EN3. This embodiment will... Figure 2 The driver enable signals EN1~EN3 are used as Figure 1 The drive enable signal is 124.

[0020] The output stage circuit 130 includes multiple output buffers (e.g., three output buffers 134-1 to 134-3). Output buffers 134-1 to 134-3 receive corresponding driver enable signals EN1 to EN3 to generate multiple sub-data voltage signals, and these sub-data voltage signals serve as data voltage signals 132.

[0021] Each data transfer path includes a first pre-driver and a second pre-driver connected in series. For example, Figure 2 Data transmission path PE1 includes a first pre-driver 122-11 and a second pre-driver 122-12 connected in series; data transmission path PE2 includes a first pre-driver 122-21 and a second pre-driver 122-22 connected in series; data transmission path PE3 includes a first pre-driver 122-31 and a second pre-driver 122-32 connected in series. The circuit structures of the first pre-drivers 122-11~122-31 and the second pre-drivers 122-12~122-32 are the same.

[0022] The circuit structure of each predriver in the SR control circuit 120 is illustrated here using the first predriver 122-11 as an example. The first predriver 122-11 includes an input terminal INN, an output terminal OUTN, multiple first-type transistors (e.g., N-type transistors) MN1~MNN, a first switching circuit SWC1, multiple second-type transistors (e.g., P-type transistors) MP1~MPN, and a second switching circuit SWC2.

[0023] The control terminal (e.g., gate terminal) of the first-type transistors MN1~MNN is coupled to the input terminal INN. The first terminal (e.g., drain terminal) of the first-type transistors MN1~MNN is coupled to the output terminal OUTN. The dimensions of the first-type transistors MN1~MNN are different. In this embodiment, the dimensions of the first-type transistors MN1~MNN can be designed as 1:2:4…:n, where n is a positive integer. The control terminal of the first switching circuit SWC1 is coupled to the adjusted ZQ calibration signal ZQSC. The first terminal of the first switching circuit SWC1 is coupled to the reference voltage terminal (e.g., ground terminal). The second terminal of the first switching circuit SWC1 is coupled to the second terminal (e.g., source terminal) of the first-type transistors MN1~MNN.

[0024] The first terminal (e.g., the drain terminal) of the second-type transistors MP1~MPN is coupled to the output terminal OUTN. The dimensions of the second-type transistors MP1~MPN are different. In this embodiment, the dimensions of the second-type transistors MP1~MPN can be designed as 1:2:4…:n, where n is a positive integer. The control terminal of the second switching circuit SWC2 is coupled to the inverted and adjusted ZQ calibration signal ZQSN. The first terminal of the second switching circuit SWC2 is coupled to the operating voltage terminal. The second terminal of the second switching circuit SWC2 is coupled to the second terminal (e.g., the source terminal) of the second-type transistors MP1~MPN.

[0025] Figure 2 The slew rate control circuit 120 selectively turns on the first transistors MN1 to MNN in the first pre-driver 122-11 to the reference voltage terminal using an adjusted ZQ calibration signal ZQSC. That is, the first switching circuit SWC1 selectively turns on one or a combination of the first transistors MN1 to MNN according to the adjusted ZQ calibration signal ZQSC. For example, one, two, or N of the first transistors MN1 to MNN can be selectively turned on. A first predetermined relationship exists between the adjusted ZQ calibration signal ZQSC and the dimensions of the first transistors MN1 to MNN. This first predetermined relationship can be generated experimentally or through computer simulation.

[0026] Figure 2 The slew rate control circuit 120 also selectively turns on the second transistors MP1 to MPN in the first pre-driver 122-11 to the operating voltage terminal using the inverted adjusted ZQ calibration signal ZQSN, thereby changing the driving capability of the first pre-driver 122-11 and thus changing the delay time of the driver enable signal EN1. In other words, the second switching circuit SWC2 selectively turns on one or a combination of the second transistors MP1 to MPN according to the inverted adjusted ZQ calibration signal ZQSN. For example, one, two, or N of the second transistors MP1 to MPN can be selectively turned on. A second predetermined relationship exists between the inverted adjusted ZQ calibration signal ZQSN and the dimensions of the second transistors MP1 to MPN. This second predetermined relationship can be generated experimentally or through computer simulation.

[0027] Based on the PVT characteristics, the boundary angle analysis of the components of the memory device 100 can be classified into features such as typical-typical (TT) corners, FF corners, and SS corners. Due to the variation of PVT, each corner has different variations in delay time, impedance, drive capability, etc. In this embodiment, the ZQ calibration signal 104 is input to the output stage 130 to compensate for the impedance difference caused by PVT variation, and the ZQ calibration signal 104 is also input to the SR calibration circuit 120 to adjust the delay time used to enable the output stage circuit 130. For example, in one embodiment, using the existing ZQ calibration signal in a third-generation double data rate (DDR3) memory device, when the drive capability of the pre-driver is increased under different P, V, T corners, the signal strength of the driver enable signals EN1~EN3 provided to the output stage circuit is strengthened to shorten the circuit delay time; on the other hand, when the drive capability of the pre-driver is reduced, the signal strength of the driver enable signals EN1~EN3 provided to the output stage circuit is weakened to increase the circuit delay time. Furthermore, this embodiment can calibrate the slew rate of the memory device.

[0028] In this embodiment, the data transmission path may further include a resistor-capacitor delay circuit. For example, data transmission path PE2 includes a resistor-capacitor delay circuit RC1, and data transmission path PE3 includes a resistor-capacitor delay circuit RC2. The output terminal of the first pre-driver 122-21 is coupled to the input terminal of the second pre-driver 122-22 through the resistor-capacitor delay circuit RC1. The output terminal of the first pre-driver 122-31 is coupled to the input terminal of the second pre-driver 122-32 through the resistor-capacitor delay circuit RC2. The resistor-capacitor delay circuit RC1 includes a resistor R1 and a capacitor C1. The resistor-capacitor delay circuit RC2 includes a resistor R2 and a capacitor C2.

[0029] In this embodiment, the variations in the FF and SS corners can be adjusted based on actual testing or computer simulation results. For example, the ZQ calibration signal may include the delay time of the transistors in the output stage circuit (or memory cell) with SS or FF corner characteristics. The delay time obtained by this ZQ calibration signal is compared with the drive capability (e.g., transistor size) in the pre-driver to determine whether to increase or decrease the delay time of the output stage circuit 130 by adjusting the drive capability.

[0030] In one embodiment, the delay time can be adjusted by increasing or decreasing it in levels. Each level can be set according to hardware capabilities, for example, with a delay time in nanoseconds (ns), microseconds (μs), or picoseconds (ps). In other embodiments, a predetermined threshold can be set based on the characteristics of the TT corner, thereby reducing the difference in slew rate output by output stages with different corner characteristics.

[0031] Table 1 illustrates the changes in the slew rate (e.g., V / ns) of the data voltage signal before and after compensation by the SR control circuit 120 for different corners (e.g., TT, SS, FF corners). For example, by increasing the delay time of the SR control circuit 120 from 166 ps to 172 ps to adjust the slew rate, the slew rate of the output stage circuit with TT corner characteristics is reduced from 3.25 V / ns to 3.11 V / ns. Similarly, by increasing the delay time of the SR control circuit 120 from 216 ps to 150 ps to adjust the slew rate, the slew rate of the output stage circuit with SS corner characteristics is increased from 2.37 V / ns to 3.28 V / ns. By increasing the delay time of the SR control circuit 120 from 108 ps to 161 ps to adjust the slew rate, the slew rate of the output stage circuit with FF corner characteristics is reduced from 4.87 V / ns to 3.25 V / ns. Consequently, the variation in slew rate decreased from 2.5 V / ns to 0.17 V / ns. It should be noted that the values ​​shown in Table 1 are for illustrative purposes only and are not intended to limit the invention or its embodiments.

[0032]

[0033] Table 1

[0034] Figure 3 This is a flowchart illustrating a method for controlling the slewing rate according to an embodiment of the present invention. Figure 3 The method can be applied to Figure 1 and Figure 2 The aforementioned memory device 100. (Refer to...) Figure 1 and Figure 3 In step S310, the SR control circuit 120 receives the ZQ calibration signal 104 for impedance compensation. In step S320, the SR control circuit 120 adjusts the driving capability of each of the plurality of pre-drivers 122 in the SR control circuit 120 according to the ZQ calibration signal 104. The pre-drivers 122 generate a driven enable signal 124 based on the data signal 112 provided by the drive memory array 110. In step S330, the output stage circuit 130 generates a data voltage signal 132 according to the driven enable signal 124 and the data signal 112. The slew rate of the data voltage signal 132 is adjusted based on the driving capability of the pre-drivers 122.

[0035] In summary, the memory device and method for controlling slew rate described in this invention adjust the driving capability of each pre-driver accordingly based on the ZQ calibration signal in the memory device to change the delay time of the data signal, thereby compensating for the slew rate of the data voltage signal. The predetermined relationship between the driving capability of the pre-driver and the ZQ calibration signal can be generated experimentally or through computer simulation, and the driving capability can be adjusted accordingly by adjusting the size of the transistors turned on in the pre-driver. In other words, this invention can adjust the slew rate of the data voltage signal generated by output stage circuits with different PVT characteristics according to the ZQ calibration signal, thereby reducing the variation in the delay time of the data voltage signal caused by the PVT characteristics.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory device, characterized in that, include: A memory array used to provide data signals; A slew rate control circuit, coupled to the memory array and including a plurality of pre-drivers, wherein the slew rate control circuit receives a ZQ calibration signal and adjusts the driving capability of each of the pre-drivers in the slew rate control circuit according to the ZQ calibration signal, wherein the pre-drivers are used to generate a driven enable signal based on the data signal. as well as An output stage circuit, coupled to the slew rate control circuit, wherein the output stage circuit generates a data voltage signal based on the drive enable signal and the data signal. The slew rate of the data voltage signal is adjusted based on the driving capability of the pre-driver.

2. The memory device according to claim 1, characterized in that, The slew rate control circuit adjusts the driving capability of each of the pre-drivers in the slew rate control circuit based on the other signals in the ZQ calibration signal except for the least significant bit as the adjusted ZQ calibration signal.

3. The memory device according to claim 2, characterized in that, The slew rate control circuit includes at least one enable signal path, each enable signal path receiving the data voltage signal and providing corresponding multiple driven sub-enable signals, wherein the multiple driven sub-enable signals serve as the driven enable signal. Each data transmission path includes a first pre-driver and a second pre-driver connected in series. The first pre-driver and the second pre-driver have the same circuit structure, and the pre-driver includes the first pre-driver and the second pre-driver.

4. The memory device according to claim 3, characterized in that, The circuit structure of the first pre-driver and the second pre-driver includes: Input terminal; Output terminal; A plurality of first-type transistors, wherein the control terminal of the first-type transistor is coupled to the input terminal, and the first terminal of the first-type transistor is coupled to the output terminal, wherein the first-type transistors are of different sizes; A first switching circuit, the control terminal of which is coupled to the adjusted ZQ calibration signal, the first terminal of the first switching circuit is coupled to the reference voltage terminal, and the second terminal of the first switching circuit is coupled to the second terminal of the first type transistor. A plurality of second-type transistors, wherein the control terminal of each second-type transistor is coupled to the input terminal, and the first terminal of each second-type transistor is coupled to the output terminal, wherein the dimensions of the second-type transistors are different; and The second switching circuit has its control terminal coupled to the inverted adjusted ZQ calibration signal, its first terminal coupled to the operating voltage terminal, and its second terminal coupled to the second terminal of the second type transistor.

5. The memory device according to claim 4, characterized in that, The first switching circuit selectively turns on one or a combination of the first type of transistors according to the adjusted ZQ calibration signal, wherein the adjusted ZQ calibration signal and the size of the first type of transistor have a first predetermined relationship. Furthermore, the second switching circuit selectively turns on one or a combination of the second type transistors according to the inverted adjusted ZQ calibration signal, and the inverted adjusted ZQ calibration signal has a second predetermined relationship with the size of the second type transistor.

6. The memory device according to claim 3, characterized in that, Each data transmission path also includes a resistor-capacitor delay circuit, and the output of the first pre-driver is coupled to the input of the second pre-driver through the resistor-capacitor delay circuit.

7. The memory device according to claim 3, characterized in that, The output stage circuit includes multiple output buffers, each output buffer receiving a corresponding driver enable signal to generate multiple sub-data voltage signals, and the sub-data voltage signals serve as the data voltage signals.

8. The memory device according to claim 7, characterized in that, The slew rate control circuit adjusts the slew rate of the sub-data voltage signal generated by the output buffer by changing the driving capability of each of the pre-drivers to alter the delay time of the driven sub-enable signal.

9. The memory device according to claim 1, characterized in that, The output stage circuit has the fast-fast angle and slow-slow angle characteristics of PVT.

10. A method for controlling the slewing rate, characterized in that, The method is used to adjust the slew rate of a data voltage signal applied to a memory cell with different PVT characteristics, and the method includes: Receives the ZQ calibration signal used for impedance compensation; The driving capability of each of the multiple pre-drivers in the slew rate control circuit is adjusted according to the ZQ calibration signal, wherein the pre-drivers generate a drive enable signal based on data signals provided by the drive memory array; and A data voltage signal is generated by an output stage circuit based on the driven enable signal and the data signal, wherein the slew rate of the data voltage signal is adjusted based on the driving capability of the pre-driver.

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