Memory device performing memory access operation and repair operation

Abstract

The invention relates to a memory device performing memory access operations and repair operations. A memory device includes a memory chip disposed over a base chip. The base chip includes a cache memory configured to store a first access address and first access data when a failure occurs in the first access data during a first memory access operation; the repair control circuit is configured to perform a cache write operation and a cache read operation on the cache memory when a second access address received in a second memory access operation is the same as an address stored in the cache memory, and a processor configured to perform a core write operation and a core read operation on the memory chip when the second access address is different from the address stored in the cache memory.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0110096, filed on August 16, 2024. Technical Field

[0003] Some embodiments of this disclosure relate to memory devices that analyze information about data faults in memory access operations to perform repair operations. Background Technology

[0004] Recently, stacked memory systems (such as high-bandwidth memory (HBM)) have gained widespread application due to their superior bandwidth. Unlike traditional memory systems that use parallel data buses, stacked memory systems consist of a base chip and multiple slices of chips interconnected via through-silicon vias (TSVs). The stacked memory device includes a physical interface (e.g., a physical layer, or PHY) for communicating with the processor. The PHY needs to be designed to ensure high-speed data transfer and efficient communication. Summary of the Invention

[0005] This disclosure provides a memory device including a memory chip disposed on a base chip, wherein the base chip may include a cache memory and a repair control circuit. The cache memory is configured to store a first access address and the first access data when a fault occurs in the first access data during a first memory access operation. The repair control circuit is configured to perform a cache write operation and a cache read operation on the cache memory when the second access address received in a second memory access operation is the same as the address stored in the cache memory, and is configured to perform a core write operation and a core read operation on the memory chip when the second access address is different from the address stored in the cache memory.

[0006] Furthermore, this disclosure may provide a memory device including a memory chip disposed on a base chip, wherein the base chip may include a memory circuit and a repair control circuit, the memory circuit being configured to store an access address when a fault occurs in the accessed data during a memory access operation; the repair control circuit being configured to check the access address stored in the memory circuit at a set time to determine whether to perform a repair operation.

[0007] Furthermore, this disclosure can provide a method for performing memory access operations by a memory chip, comprising: when a fault occurs in the first access data during a first memory access operation, generating fault occurrence information by a memory controller; based on the fault occurrence information, storing the first access address and the first access data received during the first memory access operation in a cache memory by a repair control circuit; and when the memory controller receives a memory request, a second access address, and the second access data, performing a cache write operation or a core write operation by the repair control circuit.

[0008] Furthermore, this disclosure may provide a method for performing a repair operation, comprising: when a fault occurs in the accessed data during a memory access operation, generating fault occurrence information by a memory controller; based on the fault occurrence information, storing the access address and accessed data received during a first memory access operation in a cache memory by a repair control circuit; and checking the address stored in the cache memory at a set time to determine whether to perform a repair operation. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a flowchart illustrating an operation based on a fault occurring in the access data during a memory access operation of a memory device according to an embodiment of the present disclosure.

[0011] Figure 3 This is a flowchart illustrating a storage operation and a load operation performed in a memory access operation of a memory device according to an embodiment of the present disclosure.

[0012] Figure 4 This is a flowchart illustrating the operation of checking whether to perform a repair according to an embodiment of the present disclosure and the operation of performing the repair, both of which are performed periodically in the memory device.

[0013] Figure 5 This is a flowchart illustrating a soft post-packaging repair operation performed in a memory device according to an embodiment of the present disclosure.

[0014] Figure 6 This is a flowchart illustrating a data copying operation in a soft post-packaging repair operation performed in a memory device according to an embodiment of the present disclosure.

[0015] Figure 7 This is a flowchart illustrating a data copy-back operation in a soft post-packaging repair operation performed in a memory device according to an embodiment of the present disclosure.

[0016] Figure 8This is a block diagram illustrating a memory device according to another embodiment of the present disclosure.

[0017] Figure 9 This is a flowchart illustrating an operation based on a data failure occurring during a memory access operation of a memory device, according to another embodiment of the present disclosure.

[0018] Figure 10 This is a flowchart illustrating memory access operations of a memory device according to another embodiment of the present disclosure.

[0019] Figure 11 This is a block diagram illustrating a stacked memory system according to an embodiment of the present disclosure. Specific Implementation

[0020] In the following description of the embodiments, when a parameter is referred to as "predetermined," the value of the parameter can be determined in advance when the parameter is used in a process or algorithm. The value of the parameter can be determined at the start of the process or algorithm, or it can be determined during the period in which the process or algorithm is executed.

[0021] When one element is referred to as "connected" to another element, these elements can be directly connected or connected to one or more intermediate elements between the two elements. When two elements are referred to as "directly connected," there are no intermediate elements between the two elements. When one element is identified as being "on" or "above" another element, the two elements can be in direct contact with each other, or an intermediate element can be placed between the two elements. Terms such as "top," "above," "upper," "side," "horizontal," "column," "outermost," and other terms that suggest relative spatial relationships or orientations are used for ease of description or reference to the accompanying drawings only and are not intended for any other limiting purpose.

[0022] Various embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. These embodiments are for illustrative purposes only and are not intended to limit the scope of the disclosure.

[0023] Figure 1 This is a block diagram illustrating a memory device 10 according to an embodiment of the present disclosure. Figure 1 As shown, the memory device 10 may include a base chip 101 and a memory chip 103. The memory chip 103 may be disposed on top of the base chip 101. The memory chip 103 may include multiple sliced ​​chips (e.g., Figure 11 (313, 315, 317, and 319 in the example). Each of the plurality of slice chips can be via a via (e.g., ...). Figure 11 The 341) transmits signals and can be arranged in a stacked manner by being connected via micro-bumps, etc.

[0024] The base chip 101 may include a transceiver circuit (RX TX) 111, a serialization-parallelization circuit (SERDES) 112, a transmission control circuit (DTRCTR) 113, a memory controller (MC) 114, a repair control circuit (SPPR CTR) 115, a cache memory 116, an interface conversion circuit (IF CVT) 117, and a core control circuit (CORE CTR) 119.

[0025] Transceiver circuit 111 can receive write data WDATA, write valid signal WVALID, and transmission write clock signals WCK-t and WCK-c from the host for memory access operations. Write data WDATA may include a store request, a load request, an access address, and access data. Transceiver circuit 111 can receive read data RDATA, read valid signal RVALID, and transmission read clock signals RCK-t and RCK-c from serialization-parallelization circuit 112 via memory access operations, and can transmit read data RDATA, read valid signal RVALID, and transmission read clock signals RCK-t and RCK-c to an external device. The host can be one of a central processing unit (CPU), a graphics processing unit (GPU), or a neural processing unit (NPU). Memory access operations may include store operations that store data in memory chip 103 or cache memory 116 and load operations that output data stored in memory chip 103 or cache memory 116. Store operations may be performed based on store requests contained in write data WDATA, and load operations may be performed based on load requests contained in write data WDATA. When a storage operation is performed, the accessed data can be stored in at least one storage cell accessed by the access address in the storage cells included in the storage chip 103, or the accessed data can be stored in the region corresponding to the access address in the cache memory 116. When a load operation is performed, the data stored in at least one storage cell accessed by the access address in the storage cells included in the storage chip 103 can be output as accessed data, or the data stored in the region corresponding to the access address in the cache memory 116 can be output as accessed data.

[0026] When the write valid signal WVALID is activated synchronously with the transmission write clock signals WCK-t and WCK-c, the serialization-parallelization circuit 112 can transmit the memory request, access address, and access data contained in the write data WDATA to the memory controller 114 via the transmission control circuit 113. When the write valid signal WVALID is activated synchronously with the transmission write clock signals WCK-t and WCK-c, the serialization-parallelization circuit 112 can transmit the load request and access address contained in the write data WDATA to the memory controller 114 via the transmission control circuit 113. When a load operation is performed, the serialization-parallelization circuit 112 can generate read data RDATA, a read valid signal RVALID, and transmission read clock signals RCK-t and RCK-c based on the signals received from the memory controller 114 via the transmission control circuit 113, and can transmit the read data RDATA, the read valid signal RVALID, and the transmission read clock signals RCK-t and RCK-c to the transceiver circuit 111.

[0027] The storage controller 114 can control the transmission control circuit 113, the repair control circuit 115, and the interface conversion circuit 117 to perform memory access operations.

[0028] When a fault occurs in the accessed data during a memory access operation, the memory controller 114 can transmit fault information to the repair control circuit 115. The memory controller 114 may include error correction circuitry (not shown) to determine whether a fault has occurred in the accessed data during the memory access operation. The error correction circuitry may be implemented using Hamming codes or Reed-Solomon (RS) codes to detect the fault; however, this is merely an example, and the disclosure is not limited thereto. Upon receiving fault information from the memory controller 114, the repair control circuit 115 can receive the access address and accessed data from the memory controller 114 and can store the access address and accessed data in a cache memory 116. In the cache memory 116, the access address and accessed data can be stored in corresponding areas.

[0029] When the transmission control circuit 113 receives a storage request, access address, and access data for a storage operation, the storage controller 114 can transmit the access address to the repair control circuit 115. The repair control circuit 115 can check if the access address is the same as one of the addresses stored in the cache memory 116. When the access address is the same as one of the addresses stored in the cache memory 116, the repair control circuit 115 can receive the access data from the storage controller 114 and can perform a cache write operation, which stores the access data in the region of the cache memory 116 corresponding to the access address. When the access address is not the same as one of the addresses stored in the cache memory 116, the repair control circuit 115 can control the storage controller 114 to perform a core write operation. In the core write operation, the storage controller 114 can control the interface conversion circuit 117 so that the access data is stored in at least one storage cell accessed by the access address among the storage cells included in the storage chip 103.

[0030] When the access address and load request for a load operation are received via the transmission control circuit 113, the storage controller 114 can transmit the access address to the repair control circuit 115. The repair control circuit 115 can check whether the access address is the same as one of the addresses stored in the cache memory 116. When the access address is the same as one of the addresses stored in the cache memory 116, the repair control circuit 115 can control the cache memory 116 and the storage controller 114 to perform a cache read operation. In the cache read operation, the cache memory 116 can output the data stored in the region corresponding to the access address as access data, and the storage controller 114 can transmit the access data to the transmission control circuit 113. When the access address is not the same as one of the addresses stored in the cache memory 116, the repair control circuit 115 can control the storage controller 114 to perform a core read operation. During the core read operation, the storage controller 114 can control the interface conversion circuit 117 so that the data stored in at least one storage cell accessed by the access address in the storage cells included in the storage chip 103 is output as access data.

[0031] The repair control circuit 115 can check the access addresses stored in the cache memory 116 at set intervals to determine whether to perform a repair operation. The repair control circuit 115 may be equipped with a timer (not shown) for determining whether to perform a repair operation at the set intervals. The repair control circuit 115 can control the memory controller 114 such that a repair operation is performed when it is confirmed that a set number or more faults have occurred in memory cells connected to the same word line via access addresses. The memory controller 114 can perform the repair operation under the control of the repair control circuit 115. The repair operation performed in the memory controller 114 can be a soft-back-pack repair based on the access addresses stored in the cache memory 116, but it can also be performed as a hard-back-pack repair, depending on the embodiment. The memory controller 114 can receive information from the repair control circuit 115 about the word line requiring repair and can perform the repair operation on the memory cells connected to that word line. For example, the memory controller 114 can sequentially access memory cells connected to the word lines requiring repair operations based on the target address, to store the data stored in the memory cells in the cache memory 116, replace the word lines requiring repair operations with redundant word lines, and then copy the data stored in the memory cells in the cache memory 116 back to the memory cells connected to the replaced redundant word lines. The repair control circuit 115 can receive confirmation from the memory controller 114 that the repair operation has ended, and can delete the access address of the memory cell connected to the replaced word line based on the repair operation from the cache memory 116.

[0032] The interface conversion circuit 117 can, under the control of the memory controller 114, convert the interface of the control signals transmitted from the memory controller 114 during core write operations and core read operations, so as to transmit the control signals to the core control circuit 119.

[0033] The core control circuit 119 can perform a core write operation that stores the accessed data in at least one memory cell accessed by an access address in the memory cells included in the memory chip 103, or it can perform a core read operation that outputs the data stored in at least one memory cell accessed by an access address in the memory cells included in the memory chip 103 as accessed data, based on the control signal whose interface has been converted in the interface conversion circuit 117.

[0034] During a core write operation, the core control circuit 119 can store the accessed data received from the interface conversion circuit 117 into at least one memory cell accessed by an access address among the memory cells included in the memory chip 103. During a core read operation, the core control circuit 119 can output the data stored in at least one memory cell accessed by an access address among the memory cells included in the memory chip 103 to the interface conversion circuit 117.

[0035] When a fault occurs in the accessed data during a memory access operation, the memory device 10 configured as described above can store the access address and accessed data in the cache memory 116. Furthermore, when performing a memory access operation on a memory cell that has experienced a data fault, the memory device 10 can perform cache write and cache read operations on the access address and accessed data stored in the cache memory 116, thereby quickly executing the memory access operation. In addition, the memory device 10 can periodically check the access addresses stored in the cache memory 116 to proactively detect and respond to defects in the memory device to determine whether to perform a repair operation.

[0036] Figure 2 It shows based on Figure 1 A flowchart illustrating the operation of a data fault occurring during a memory access operation of the memory device 10 shown.

[0037] refer to Figure 1 and Figure 2 The following actions are performed when a data failure occurs during a memory access operation.

[0038] First, the memory device 10 can be in a standby state (S101). Second, while in the standby state (S101), the memory controller 114 can determine whether a fault has occurred in the accessed data during a memory access operation (S103).

[0039] Next, when a fault occurrence information is received from the storage controller 114, the repair control circuit 115 can receive the access address and access data from the storage controller 114 and store the access address and access data in the cache memory 116 (S105).

[0040] Figure 3 It is shown Figure 1 The flowchart shows the storage and load operations performed in the memory access operation of the memory device 10 shown.

[0041] Reference Figure 1 and Figure 3 Cache memory operations can be performed as follows.

[0042] In standby mode (S111), the memory controller 114 can determine whether to perform a memory access operation (S113). When the memory access operation is performed, the memory controller 114 can transmit the access address to the repair control circuit 115 through the transmission control circuit 113.

[0043] The repair control circuit 115 can check whether the access address is the same as one of the addresses stored in the cache memory 116 (S115).

[0044] When the access address matches one of the addresses stored in cache memory 116, the repair control circuit 115 can check whether the storage controller 114 has received a storage request for a storage operation from the storage controller 114 (S117). When the storage controller 114 receives a storage request, the repair control circuit 115 can receive access data from the storage controller 114 and can control the execution of a cache write operation to store the accessed data in the region of cache memory 116 corresponding to the access address (S118). Simultaneously, when the access address matches one of the addresses stored in cache memory 116 and the storage controller 114 has not yet received a storage request (but rather when a load request for a load operation has been received), the repair control circuit 115 can execute a cache read operation, which outputs the data stored in the region of cache memory 116 corresponding to the access address as access data (S119).

[0045] When the access address is not the same as one of the addresses stored in cache memory 116, the repair control circuit 115 can check whether the memory controller 114 has received a storage request from the memory controller 114 (S121). When the memory controller 114 receives a storage request, the repair control circuit 115 can control the memory controller 114 to perform a core write operation. In the core write operation, the memory controller 114 can control the interface conversion circuit 117 so that the access data is stored in at least one memory cell accessed by the access address among the memory cells included in the memory chip 103 (S122). Simultaneously, when the access address is not the same as one of the addresses stored in cache memory 116 and the memory controller 114 has not yet received a storage request (but rather when a load request for a load operation is received), the repair control circuit 115 can control the memory controller 114 to perform a core read operation. During the core read operation, the memory controller 114 can control the interface conversion circuit 117 so that the data stored in at least one memory cell accessed by the access address among the memory cells included in the memory chip 103 is output as access data (S123).

[0046] Figure 4 It is shown in Figure 1 The memory device 10 shown here periodically performs a check to determine whether a repair operation should be performed, and a flowchart of the repair operation.

[0047] refer to Figure 1 and Figure 4Check whether to perform a repair operation and perform the repair operation as follows.

[0048] First, in standby mode (S131), the repair control circuit 115 can determine whether a set time has elapsed (S133). When the set time has elapsed, the repair control circuit 115 can check all access addresses stored in the cache memory 116 (S135).

[0049] Next, the repair control circuit 115 can determine whether a repair operation is needed based on a check of the access addresses (S137). Based on the access addresses, the repair control circuit 115 can control the memory controller 114 such that a repair operation is performed when a fault is confirmed to have occurred in a set number or more memory cells connected to the same word line. The memory controller 114 can perform a soft-backpack repair operation based on the access addresses stored in the cache memory 116 (S138). The repair control circuit 115 can receive confirmation from the memory controller 114 that the repair operation has ended, and can delete the access addresses of the memory cells connected to the replaced word lines based on the soft-backpack repair operation from the cache memory 116 (S139).

[0050] Figure 5 It is shown in Figure 1 The flowchart shows the soft post-packaging repair operation performed in the memory device 10 shown.

[0051] refer to Figure 1 and Figure 5 The soft-re-encapsulation repair operation is performed as follows.

[0052] First, in standby mode (S141), the repair control circuit 115 determines whether a soft-back packaging repair operation is required (S143). When it is determined that a soft-back packaging repair operation is required, the storage controller 114 can be controlled by the repair control circuit 115 to execute the soft-back packaging repair operation. In the soft-back packaging repair operation, a data copy operation (S145), a faulty storage cell repair operation (S147), and a data copy-back operation (S149) can be executed sequentially. The data copy operation (S145) can be executed by storing the data stored in the storage cell requiring repair in the cache memory 116. The faulty storage cell repair operation (S147) can be executed by replacing the word line connected to the storage cell requiring repair with a redundant word line. Before the storage cell is connected to the redundant word line, the data copy-back operation (S149) can be executed by copying back the data stored in the cache memory 116 during the data copy operation S145.

[0053] Figure 6 This is a flowchart illustrating the data copying operation performed during the repair process.

[0054] refer to Figure 1 and Figure 6 Data copying operations can be performed as follows.

[0055] First, the memory controller 114 can initialize the target address TADD (S151). The initialized target address TADD can be set to the address of the first memory cell connected to the word line that needs to be repaired. The repair control circuit 115 can store the data of the memory cell accessed by the target address TADD initialized by the memory controller 114 in the cache memory 116 (S153).

[0056] Next, the memory controller 114 can sequentially count up the target address TADD (S155), and the repair control circuit 115 can store the data of the memory cell accessed by the target address TADD counted up by the memory controller 114 in the cache memory 116. Each time the target address TADD is counted up, the memory cell accessed by the counted target address TADD can change from the second memory cell connected to the word line requiring the repair operation to the last memory cell.

[0057] Next, the storage controller 114 can determine whether the counted target address TADD is greater than or equal to a predetermined size PS (S157). When the target address TADD is greater than or equal to the predetermined size PS, it means that the storage cell accessed by the counted target address TADD is the last storage cell connected to the word line requiring the repair operation. Therefore, when the counted target address TADD is greater than or equal to the predetermined size, the storage controller 114 can terminate the data copying operation and perform the faulty storage cell repair operation (S147).

[0058] Figure 7 This is a flowchart illustrating the data copy-back operation performed during the repair process.

[0059] refer to Figure 1 and Figure 7 The data copy-back operation can be performed as follows.

[0060] First, the memory controller 114 can initialize the target address TADD (S161). The initialized target address TADD can be set to the address of the first memory cell connected to the redundant word line replaced during the repair operation. The repair control circuit 115 can store the data stored in the cache memory 116 in the memory cell accessed through the target address TADD initialized by the memory controller 114. In this case, the data stored in the cache memory 116 can be set to the data stored in the first memory cell connected to the word line; however, this is only an example and the present disclosure is not limited thereto (S163).

[0061] Next, the memory controller 114 can sequentially count up the target data TADD, and the repair control circuit 115 can store the data stored in the cache memory 116 in the memory cell accessed by the target address TADD counted up by the memory controller 114. Whenever the target address TADD is counted up, the memory cell accessed by the counted target address TADD can change from the second memory cell connected to the redundant word line to the last memory cell, and the data stored in the cache memory 116 can also change from data stored in the second memory cell connected to the word line to data stored in the last memory cell; however, this is merely an example, and this disclosure is not limited thereto.

[0062] Next, the memory controller 114 can determine whether the counted target address TADD is greater than or equal to a predetermined size PS (S167). When the target address TADD is greater than or equal to the predetermined size PS, it means that the memory cell accessed by the upward-counted target address TADD is the last memory cell connected to the redundant word line. Therefore, when the upward-counted target address TADD is greater than or equal to the predetermined size PS, the memory controller 114 can end the data copy-back operation and control the memory device 10 to enter a standby state (S131).

[0063] Figure 8 This is a block diagram illustrating a memory device 20 according to another embodiment of the present disclosure. Figure 8 As shown, the memory device 20 may include a base chip 201 and a memory chip 203. The memory chip 203 may be disposed on the base chip 201. The memory chip 203 may include a plurality of memory chips 203. The plurality of memory chips 203 may be disposed via through-holes (e.g., Figure 11 341) are interconnected and can be set up in a stacked manner.

[0064] The base chip 201 may include a transceiver circuit (RX TX) 211, a serialization-parallelization circuit (SERDES) 212, a transmission control circuit (DTRCTR) 213, a memory controller (MC) 214, a repair control circuit (SPPR CTR) 215, a memory circuit 216, an interface conversion circuit (IF CVT) 217, and a core control circuit (CORE CTR) 219.

[0065] Transceiver circuit 211 can receive write data WDATA, write valid signal WVALID, and transmission write clock signals WCK-t and WCK-c applied from the host to perform memory access operations. Write data WDATA may include a store request, a load request, an access address, and access data. Transceiver circuit 211 can receive read data RDATA, read valid signal RVALID, and transmission read clock signals RCK-t and RCK-c from serialization-parallelization circuit 212 during memory access operations, and can transmit read data RDATA, read valid signal RVALID, and transmission read clock signals RCK-t and RCK-c to an external device. Memory access operations may include a store operation to store data in memory chip 203 and a load operation to output data stored in memory chip 203. Store operations can be performed using a store request included in write data WDATA, and load operations can be performed using a load request included in write data WDATA. When a store operation is performed, access data can be stored in at least one memory cell accessed by the access address among the memory cells included in memory chip 203. When a load operation is performed, the data stored in at least one memory cell accessed by the access address in the memory cells included in the memory chip 203 can be output as access data.

[0066] When the write valid signal WVALID is activated synchronously with the transmission write clock signals WCK-t and WCK-c, the serialization-parallelization circuit 212 can transmit the memory request, access address, and access data contained in the write data WDATA to the memory controller 214 via the transmission control circuit 213. When the write valid signal WVALID is activated synchronously with the transmission write clock signals WCK-t and WCK-c, the serialization-parallelization circuit 212 can transmit the load request and access address contained in the write data WDATA to the memory controller 214 via the transmission control circuit 213. When the load operation is executed, the serialization-parallelization circuit 212 can generate read data RDATA, a read valid signal RVALID, and transmission read clock signals RCK-t and RCK-c based on the signals received from the memory controller 214 via the transmission control circuit 213, and can transmit the read data RDATA, the read valid signal RVALID, and the transmission read clock signals RCK-t and RCK-c to the transceiver circuit 211.

[0067] The storage controller 214 can control the transmission control circuit 213, the repair control circuit 215 and the interface conversion circuit 217 to perform memory access operations.

[0068] When a fault occurs in the accessed data during a memory access operation, the memory controller 214 can transmit fault occurrence information to the repair control circuit 215. The memory controller 214 may include error correction circuitry (not shown) for determining whether a fault has occurred in the accessed data during the memory access operation. The error correction circuitry may be implemented using Hamming codes or Reed-Solomon (RS) codes to detect whether a fault has occurred; however, this is merely an example, and the disclosure is not limited thereto. When fault occurrence information is received from the memory controller 214, the repair control circuit 215 can receive the access address from the memory controller 214 to store the access address in the memory circuit 216. The memory circuit 216 may be implemented using an SRAM device; however, this is merely an example, and the disclosure is not limited thereto.

[0069] When the transmission control circuit 213 receives a storage request, access address, and access data for a storage operation, the storage controller 214 can transmit the access address to the repair control circuit 215. The repair control circuit 215 can check whether the access address is the same as one of the addresses stored in the storage circuit 216. When the access address is not the same as one of the addresses stored in the storage circuit 216, the repair control circuit 215 can control the storage controller 214 to perform a core write operation. In the core write operation, the storage controller 214 can store the accessed data in at least one storage cell among the storage cells included in the storage chip 203 that is accessed by the access address.

[0070] When the access address and load request for a load operation are received via the transmission control circuit 213, the storage controller 214 can transmit the access address to the repair control circuit 215. The repair control circuit 215 can check whether the access address is the same as one of the addresses stored in the storage circuit 216. When the access address is the same as one of the addresses stored in the storage circuit 216, the repair control circuit 215 can store the access address received from the storage controller 214 in the storage circuit 216. When the access address is not the same as one of the addresses stored in the storage circuit 216, the repair control circuit 215 can control the storage controller 214 to perform a core read operation. During the core read operation, the storage controller 214 can control the interface conversion circuit 217 so that data stored in at least one storage cell accessed by the access address in the storage cells included in the storage chip 203 is output as access data.

[0071] The repair control circuit 215 can check the access addresses stored in the storage circuit 216 at a set time to determine whether to perform a repair operation. The repair control circuit 215 may be equipped with a timer (not shown) to determine whether to perform a repair operation at the set time. When it is confirmed that a fault has occurred in multiple memory cells connected to the same word line via access addresses, and equal to or greater than a set number, the repair control circuit 215 can control the storage controller 214 to perform a repair operation. The storage controller 214 can perform the repair operation according to the control of the repair control circuit 215. The repair operation performed in the storage controller 214 can be a soft-back-package repair operation based on the access addresses stored in the storage circuit 216, but according to embodiments, the repair operation can also be performed as a hard-back-package repair operation, etc. The storage controller 214 can receive information from the repair control circuit 215 about the word line requiring repair, and can perform repair operations on the memory cells connected to that word line. For example, the memory controller 214 can sequentially access memory cells connected to the word lines requiring repair operations based on target addresses, to store the data stored in the memory cells in the memory circuit 216, replace the word lines requiring repair operations with redundant word lines, and then copy the data stored in the memory cells in the memory circuit 216 back to the memory cells connected to the replaced redundant word lines. The repair control circuit 215 can receive confirmation from the memory controller 214 that the repair operation has ended, and can delete the access addresses of the memory cells connected to the word lines replaced based on the repair operation from the memory circuit 216.

[0072] The interface conversion circuit 217 can, under the control of the storage controller 214, convert the interface of the control signals transmitted from the storage controller 214 to the core control circuit 219 during core write and core read operations.

[0073] The core control circuit 219 can perform a core write operation that stores the access data in at least one memory cell accessed by the access address in the memory cells included in the memory chip 203, or it can perform a core read operation that outputs the data stored in at least one memory cell accessed by the access address in the memory cells included in the memory chip 203 as access data, based on the control signal whose interface has been converted in the interface conversion circuit 217.

[0074] During a core write operation, the core control circuit 219 can store the accessed data received from the interface conversion circuit 217 into at least one memory cell accessed by an access address among the memory cells included in the memory chip 203. During a core read operation, the core control circuit 219 can output the data stored in at least one memory cell accessed by an access address among the memory cells included in the memory chip 203 to the interface conversion circuit 217.

[0075] When a fault occurs in the accessed data during a memory access operation, the memory device 20 configured as described above can store the access address in the storage circuit 216, and the memory device 20 can periodically check the access address stored in the storage circuit 216 to determine whether to perform a repair operation, thereby detecting defects in the memory device 20 in advance and responding to the defects.

[0076] Figure 9 It shows based on Figure 8 A flowchart of the operation of a data fault occurring during a memory access operation of the memory device 20 shown.

[0077] refer to Figure 8 and Figure 9 When a data failure occurs during a memory access operation, the operation is performed as follows.

[0078] First, in standby mode (S201), the storage controller 214 can determine whether a fault has occurred in the accessed data during a memory access operation (S203).

[0079] Next, when the repair control circuit 215 receives fault information from the storage controller 214, the repair control circuit 215 can receive the access address from the storage controller 214 and store the access address in the storage circuit 216 (S205).

[0080] Figure 10 It is shown Figure 8 A flowchart of memory access operations for the memory device 20 shown.

[0081] refer to Figure 8 and Figure 9The memory access operation is performed as follows.

[0082] In standby mode (S211), the memory controller 214 can determine whether to perform a memory access operation (S213). When not performing a memory access operation, the memory controller 214 can transmit the access address to the repair control circuit 215 through the transmission control circuit 213. The repair control circuit 215 can check whether the access address is the same as one of the addresses stored in the memory circuit 216 (S215). When the access address is not the same as one of the addresses stored in the memory circuit 216, the repair control circuit 215 can store the access address received from the memory controller 214 in the memory circuit 216 (S217).

[0083] Figure 11 This is a block diagram illustrating a stacked memory system 30 according to an embodiment of the present disclosure.

[0084] like Figure 11 As shown, the stacked memory system 30 may include a stacked memory device 301, a processor 303, an interposer 305, and a substrate 307.

[0085] An interposer layer 305 may be disposed on the substrate 307, and the stacked memory device 301 and the processor 303 may be disposed on the interposer layer 305. The interposer layer 305 can be used to electrically connect the substrate 307, the stacked memory device 301, and the processor 303 to each other. Since the spacing between the substrate 307, the stacked memory device 301, and the processor 303 is large, the substrate 307, the stacked memory device 301, and the processor 303 can be electrically connected using an interposer layer 305 including various formed wires.

[0086] Processor 303 may include processor interface circuitry (PPHY) 321. Processor 303 can apply write control signals, including commands and addresses for controlling various internal operations of the stacked memory device 301, to the stacked memory device 301 via processor interface circuitry 321, and can receive read control signals from the stacked memory device 301 via processor interface circuitry 321. The write control signals may include... Figure 1 and Figure 8 The diagram shows the write data WDATA, the write valid signal WVALID, and the transmit write clock signals WCK-t and WCK-c. Read control signals may include... Figure 1 and Figure 8 The data shown is read data RDATA, read valid signal RVALID, and transmit read clock signals RCK-t and RCK-c.

[0087] The stacked memory device 301 may include a base chip 311 and slice chips 314, 315, 317, and 319. The stacked memory device 301 can utilize... Figure 1 and Figure 8 This is achieved using the stacked memory device 20 shown.

[0088] Slice chips 314, 315, 317 and 319 can be stacked sequentially on top of base chip 311 and can receive various signals from base chip 311 through via 341.

[0089] The base chip 311 may include a core interface circuit (CPHY) 331 and an operation control circuit (OP CTR) 333. The core interface circuit 331 may be configured to communicate with the processor interface circuit 321 to transmit write control signals from the processor 303 to the operation control circuit 333, and to apply read control signals generated in the operation control circuit 333 to the processor 303.

[0090] For illustrative purposes, a limited number of possible embodiments of this teaching have been presented above. Those skilled in the art will recognize that various modifications, additions, and substitutions are possible. While this patent document contains numerous details, these details should not be construed as limiting the scope of this teaching or any potentially claimed protection, but rather as descriptions of features specific to particular embodiments. Certain features described in the context of individual embodiments in this patent document may also be implemented in combinations of individual embodiments. Conversely, multiple features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, or even initially claimed, in some cases one or more features may be removed from the claimed combination, and the claimed combination may involve sub-combinations or variations thereof.

Claims

1. A memory device, comprising: Memory chips are mounted on top of the base chip. The basic chip includes: A cache memory that stores a first access address and the first access data in the event of a fault in the first access data during a first memory access operation; and The control circuit is repaired such that: when the second access address received in the second memory access operation is the same as the address stored in the cache memory, a cache write operation and a cache read operation are performed on the cache memory; and when the second access address is not the same as the address stored in the cache memory, a core write operation and a core read operation are performed on the memory chip.

2. The memory device of claim 1, further comprising a memory controller, wherein during the first memory access operation, the memory controller: The first access address and the first access data are received through the transmission circuit. When a fault occurs in the first access data, the fault information is transmitted to the repair control circuit, and The first access address and the first access data are transmitted to the repair control circuit.

3. The memory device according to claim 2, wherein, When a storage request, the second access address, and the second access data are received by the transmission control circuit during the second memory access operation, the storage controller transmits the second access address and the second access data to the repair control circuit.

4. The memory device according to claim 3, wherein, When the second access address is the same as one of the addresses stored in the cache memory, the repair control circuit performs the cache write operation, which stores the second access address in the area of ​​the cache memory corresponding to the second access address.

5. The memory device according to claim 3, wherein, When the second access address is different from the address stored in the cache memory, the storage controller performs the core write operation, which stores the second access data in at least one storage cell among the storage cells included in the storage chip that was accessed by the second access address.

6. The memory device according to claim 2, wherein, When a load request and the second access address are received via the transmission control circuit during the second memory access operation, the memory controller transmits the second access address to the repair control circuit.

7. The memory device according to claim 6, wherein, When the second access address is the same as one of the addresses stored in the cache memory, the repair control circuit performs a cache read operation, which outputs data stored in the region corresponding to the second access address in the cache memory.

8. The memory device according to claim 6, wherein, When the second access address is different from the address stored in the cache memory, the memory controller performs a core read operation, which outputs data stored in at least one memory cell accessed by the access address among the memory cells included in the memory chip.

9. The memory device according to claim 1, wherein, The repair control circuit checks the access address stored in the cache memory at a set time to determine whether to perform a repair operation.

10. The memory device according to claim 9, wherein, The repair control circuit controls the storage controller such that when a fault is confirmed in one of a set number or more storage cells connected to the same word line based on the address stored in the cache memory, the repair operation is performed.

11. The memory device according to claim 10, wherein, When the repair operation is performed, the memory controller receives information from the repair control circuit about the word lines that require the repair operation, so as to perform the repair operation on the memory cells connected to the word lines.

12. The memory device according to claim 1, wherein, The storage controller: The memory cells connected to the word lines that require the repair operation are accessed sequentially to store the data stored in the memory cells in the cache memory. Replace the word lines that require the repair operation with redundant word lines; as well as The data stored in the cache memory is copied back to the storage cell connected to the redundant word line.

13. The memory device according to claim 12, wherein, The repair control circuit: Receive confirmation from the storage controller that the repair operation has been completed, and The address of the word line that was replaced based on the repair operation is deleted from the cache memory.

14. A memory device, comprising: Memory chips are mounted on top of the base chip. The basic chip includes: A storage circuit that stores the access address in the event of a fault in the accessed data during a memory access operation; and The repair control circuit checks the access address stored in the storage circuit at set times to determine whether to perform a repair operation.

15. The memory device of claim 14, further comprising a memory controller, wherein during the memory access operation, the memory controller: The access address and access data are received through the transmission circuit. When a fault occurs in the access data, the fault information is transmitted to the repair control circuit, and The access address is transmitted to the repair control circuit.

16. The memory device according to claim 15, wherein, The repair control circuit controls the memory controller such that when a fault is confirmed in one or more memory cells connected to the same word line, equal to or greater than a set number, based on the address stored in the memory circuit, the repair operation is performed.

17. The memory device according to claim 16, wherein, The storage controller receives information from the repair control circuit about the word line that requires the repair operation, and performs the repair operation on the storage cell connected to the word line when the repair operation is performed.

18. The memory device according to claim 14, wherein, The storage controller: The memory cells connected to the word lines that require the repair operation are accessed sequentially to store the data stored in the memory cells in the cache memory. Replace the word lines that require the repair operation with redundant word lines; as well as The data stored in the cache memory is copied back to the storage cell connected to the redundant word line.

19. The memory device according to claim 18, wherein, The repair control circuit: Receive confirmation from the storage controller that the repair operation has been completed, and The address of the word line that was replaced based on the repair operation is deleted from the storage circuit.

20. A method for performing a memory access operation by a memory chip, the method comprising: When a fault occurs in the first accessed data during the first memory access operation, the memory controller generates fault occurrence information; Based on the fault occurrence information, the repair control circuit stores the first access address and the first access data received during the first memory access operation in the cache memory; as well as When the storage controller receives a storage request, a second access address, and second access data, the repair control circuit performs a cache write operation or a core write operation.

21. The method according to claim 20, wherein, When the second access address is the same as one of the addresses stored in the cache memory, the repair control circuit performs the cache write operation, which stores the second access address in the area of ​​the cache memory corresponding to the second access address.

22. The method according to claim 20, wherein, When the second access address is different from the address stored in the cache memory, the storage controller performs the core write operation, which stores the second access data in at least one storage cell accessed by the second access address in the storage cells included in the storage chip.

23. The method of claim 20, further comprising: When the storage controller receives a load request and a third access address, the repair control circuit performs a cache read operation or a core read operation.

24. The method according to claim 23, wherein, When the third access address is the same as one of the addresses stored in the cache memory, the repair control circuit performs the cache read operation, which outputs the data in the region corresponding to the third access address stored in the cache memory as the third access data.

25. The method according to claim 23, wherein, When the third access address is different from the address stored in the cache memory, the memory controller performs the core read operation, which outputs the data in at least one memory cell accessed by the third access address among the memory cells included in the memory chip as the third access data.

26. A method for performing a repair operation, the method comprising: When a fault occurs in the accessed data during a memory access operation, the memory controller generates fault occurrence information; Based on the fault occurrence information, the repair control circuit stores the access address and the access data received during the memory access operation in the cache memory; as well as The address stored in the cache memory is checked at a set time to determine whether the repair operation should be performed.

27. The method of claim 26, further comprising: The repair control circuit controls the memory controller such that when a fault is confirmed in one of a set number or more memory cells connected to the same word line based on the address stored in the cache memory, the repair operation is performed.

28. The method of claim 27, further comprising: When the repair operation is performed, the memory controller receives information from the repair control circuit about the word line that requires the repair operation, and the memory controller performs the repair operation on the memory cell connected to the word line.

29. The method according to claim 28, wherein, The storage controller: The memory cells connected to the word lines that require the repair operation are accessed sequentially to store the data stored in the memory cells in the cache memory. Replace the word lines that require the repair operation with redundant word lines; as well as The data stored in the cache memory is copied back to the storage cell connected to the redundant word line.

30. The method according to claim 29, wherein, The repair control circuit: Receive confirmation from the storage controller that the repair operation has been completed, and The address of the word line that was replaced based on the repair operation is deleted from the cache memory.

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