Method for designing large-scale high-frame-frequency infrared focal plane reading circuit and reading circuit

Abstract

The invention discloses a method for designing a large-scale high-frame-frequency infrared focal plane readout circuit and the readout circuit, which are characterized in that odd and even column processing circuits are arranged in a side-by-side manner, so that the layout space of the column processing circuits is doubled in the transverse direction, and the realization of small pixel spacing design is facilitated. Meanwhile, for high-power-consumption large current generated by a high-speed operational amplifier, the arrangement of odd and even sides is beneficial to the layout of a power supply and a ground wire, and the IR Drop adverse effect generated by the large current on a power supply network is dispersed and weakened. Therefore, the problem that the frame frequency is too low due to the fact that an existing conventional large-array-scale reading circuit is too long in signal reading time in some high-speed target scenes is effectively solved.

Description

Technical Field

[0001] This invention relates to the field of infrared focal plane readout circuit technology, and in particular to a method for designing a large-scale high-frame-rate infrared focal plane readout circuit and a readout circuit. Background Technology

[0002] Infrared focal plane array detectors (FFPs) are core components of infrared detection technology. They detect the infrared radiation emitted by objects, and the integrated readout circuitry converts, amplifies, and processes the signal to acquire image information of the target and background. FFPs possess advantages such as low detection rate, strong anti-interference capability, high environmental adaptability, strong target recognition ability, and small size and light weight, making them widely used in deep space remote sensing, Earth resource exploration, weather monitoring and forecasting, and medical detection and diagnosis. In recent years, with the continuous development of infrared detector materials and device fabrication processes, the performance of various infrared systems has been rapidly improved, and their application areas have become increasingly broad, making them an irreplaceable and crucial technological tool in many fields of modern information society.

[0003] With the widespread application of high-speed dynamic scenarios (such as transient thermodynamic analysis), higher demands are placed on the frame rate performance of high-speed infrared imaging systems. High frame rate imaging (typically ≥1000fps) has the advantage of effectively capturing rapidly changing infrared radiation signals, enabling multi-frame imaging of targets within a short time and acquiring a large amount of target information. The realization of high frame rate imaging is highly dependent on the performance of the infrared detector readout circuit.

[0004] The frame rate of an infrared detector is approximately equal to the reciprocal of the readout time. To achieve a high frame rate, the readout time per frame must be as small as possible. The array size of a conventional readout circuit is negatively correlated with the readout time. A larger array size requires more pixels to be read, resulting in a longer readout time. Therefore, readout circuits with larger array sizes often have lower frame rates. Summary of the Invention

[0005] This invention provides a method and a readout circuit for designing a large-scale, high-frame-rate infrared focal plane readout circuit, in order to solve the problem that existing methods cannot quickly read large-scale array circuits.

[0006] This invention provides a method for designing a large-scale, high-frame-rate infrared focal plane readout circuit, comprising: An injection-level pixel module is set up for the infrared focal plane readout circuit, and the photocurrent of the infrared focal plane detector is converted into a voltage signal through the injection-level pixel module. The odd-numbered column processing circuit and the even-numbered column processing circuit of the column processing circuit are placed on both sides of the pixel array. Each column of pixels in the infrared focal plane readout circuit corresponds to a column processing circuit. That is, the output of each column of pixels in the pixel array is connected together to form a bus. The row selection switch controls the connection and disconnection of each row of pixels in a column with the column bus. During readout, the row selection switch is turned on row by row to complete the readout of a column of pixels. K output stage operational amplifiers are evenly distributed at the ends of the odd-numbered column processing circuits and the even-numbered column processing circuits to drive the data of the column processing circuits to be output to the off-chip in sequence. Each output stage operational amplifier is used to output the data of M / K column processing circuits near its position in sequence according to the timing control. The readout time of each row of pixel data is M / K master clock cycles.

[0007] Optionally, the injection-stage pixel module of the infrared focal plane readout circuit includes: adopting a preset input stage structure according to the magnitude and range of the input signal, equipping it with an integrating capacitor size that matches the signal, and adjusting the width-to-length ratio of the operational amplifier input pair, tail current source, and switch in the preset input stage structure according to simulation iterations, so that the detector current signal is injected into the integrating capacitor with the highest efficiency and converted into a suitable voltage signal.

[0008] Optionally, the preset input level structure is a CTIA input level structure, a DI input level structure, or a BDI input level structure.

[0009] Optionally, the column processing circuit adopts an OTA operational amplifier plus a ping-pong sample-and-hold structure.

[0010] Optionally, the output stage operational amplifier is a unity-gain buffer, and the output stage unity-gain buffer is designed by cascading a folded common-source cascode differential operational amplifier and a Class AB push-pull inverting operational amplifier.

[0011] Optionally, the number of unity-gain buffers is determined according to the number of counts of the column counter, and the signals of several column processing circuits within the location range of the unity-gain buffers are driven to be output to the off-chip.

[0012] Optionally, based on the required frame rate f of the infrared focal plane readout circuit, its reciprocal, 1 / f, is the time required to complete the readout of one frame of signal. Each output channel of the infrared focal plane readout circuit completes the readout of one signal per clock cycle. Assuming the array size of the readout circuit is M*N and the number of output channels is K, and the unity-gain buffer of the readout circuit output stage completes the establishment of one signal at a maximum frequency of X, then 1 / f = M*N / K*X.

[0013] Optionally, the method further includes: completing the overall design and fabrication of the infrared focal plane readout circuit by controlling the timing generation circuit of the analog link.

[0014] In a second aspect, the present invention provides an infrared focal plane readout circuit designed using any of the methods described above, the infrared focal plane readout circuit comprising: The column processing circuit of the infrared focal plane readout circuit is divided into odd-numbered column processing circuit and even-numbered column processing circuit on both sides of the pixel array. Each column of pixels in the infrared focal plane readout circuit corresponds to a column processing circuit. That is, the output of each column of pixels in the pixel array is connected together to form a bus. The row selection switch controls the connection and disconnection of each row of pixels in a column with the column bus. During readout, the row selection switch is turned on row by row to complete the readout of a column of pixels. There are K output stage operational amplifiers, which are equally spaced at the ends of the odd-numbered column processing circuits and the even-numbered column processing circuits, so as to drive the data of the column processing circuits to be output to the off-chip in sequence. Each output stage operational amplifier is used to output the M / K column processing circuits near its position in sequence according to the timing control. The readout time of each row of pixel data is M / K main clock cycles.

[0015] Optionally, the output stage operational amplifier is a unity-gain buffer, and the output stage unity-gain buffer is designed by cascading a folded common-source cascode differential operational amplifier and a Class AB push-pull inverting operational amplifier.

[0016] The beneficial effects of this invention are as follows: This invention utilizes a side-by-side arrangement of odd and even column processing circuits, effectively doubling the horizontal layout space for the column processing circuits and facilitating the design of small pixel pitch. Simultaneously, the odd-even side-by-side arrangement benefits the power supply and ground line layout, dispersing and mitigating the adverse effects of IR drop caused by large currents on the power supply network, thus effectively solving the problem of excessively long signal readout times and low frame rates in certain high-speed target scenarios using existing conventional large-array readout circuits.

[0017] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the large-scale high frame rate infrared focal plane readout circuit structure provided in an embodiment of the present invention; Figure 2This is a schematic diagram of the pixel and column processing circuit layout provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the connection between the column processing circuit and the output stage provided in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the scope of the invention.

[0020] The frame rate of an infrared detector is approximately equal to the reciprocal of the readout time. To achieve a high frame rate, the readout time per frame must be as small as possible. Currently, the array size of conventional readout circuits is negatively correlated with readout time; a larger array size requires more pixels to be read, resulting in a longer readout time. Therefore, readout circuits with larger array sizes often have lower frame rates. To address this issue, this invention proposes a method for designing a large-scale, high-frame-rate infrared focal plane readout circuit. (See [link to relevant documentation]). Figure 1 and Figure 2 The method includes: Step 101: Set up the injection-level pixel module of the infrared focal plane readout circuit, and convert the photocurrent of the infrared focal plane detector into a voltage signal through the injection-level pixel module; Specifically, in this embodiment of the invention, a preset input stage structure is adopted based on the magnitude and range of the input signal. The size of the integrating capacitor is matched with the signal. The width-to-length ratio of the operational amplifier input pair, tail current source, and switch in the preset input stage structure is adjusted according to simulation iterations, so that the detector current signal is injected into the integrating capacitor with the highest efficiency and converted into a suitable voltage signal.

[0021] In this embodiment of the invention, the preset input level structure is a CTIA input level structure, a DI input level structure, or a BDI input level structure, etc. Those skilled in the art can set it arbitrarily, and this invention will not elaborate on it in detail.

[0022] It should be noted that the column processing circuit in this embodiment of the invention adopts an OTA operational amplifier plus a ping-pong sample-and-hold structure, see details below. Figure 3 .

[0023] Step 102: Place the odd-numbered column processing circuit and the even-numbered column processing circuit of the column processing circuit on both sides of the pixel array. Each column of pixels in the infrared focal plane readout circuit corresponds to a column processing circuit. That is, the output of each column of pixels in the pixel array is connected together to form a bus. The row selection switch controls the connection and disconnection of each row of pixels in a column with the column bus. When reading, the row selection switch is turned on row by row to complete the reading of a column of pixels. Step 103: K output stage operational amplifiers are evenly distributed at the ends of the odd-numbered column processing circuits and the even-numbered column processing circuits to drive the data of the column processing circuits to be output to the off-chip in sequence. Each output stage operational amplifier is used to output the data of M / K column processing circuits near its position in sequence according to the timing control. The readout time of each row of pixel data is M / K main clock cycles.

[0024] In other words, the embodiments of this invention, by arranging the odd and even column processing circuits side-by-side, double the layout space of the column processing circuits in the horizontal direction, which is beneficial for achieving small pixel pitch design. Simultaneously, for the high power consumption and large current generated by the high-speed operational amplifier, the odd-even side-by-side arrangement is beneficial for the layout of power supply and ground lines, dispersing and reducing the adverse effects of IR drop caused by large current on the power supply network. The output stage buffer of the cascaded structure of the folded cascode differential operational amplifier and the Class AB push-pull inverting operational amplifier can provide a slew rate of up to 75MV / s, complete signal establishment within 14ns, and the readout circuit can maintain a sampling position for more than 40% of the clock cycle at a readout rate of 40MHz.

[0025] Taking a pixel array of 2108×1024 pixels with a pixel pitch of 10 micrometers as an example, the odd and even column processing circuits are arranged above and below the pixel array, respectively. The width of the column processing circuit of a single pixel can be expanded to 20 micrometers. With 124 output stages, 124 channels can be output simultaneously. Each output channel is responsible for outputting the signals of the 17 column processing circuits below it. One line of data can be output every 17 clock cycles. The readout time of the entire frame of data is 17408 clock cycles. The theoretical limit of the readout circuit of such a large-scale array can reach 2297Hz.

[0026] In specific implementation, the output stage operational amplifier is configured as follows: based on the required frame rate f of the infrared focal plane readout circuit, its reciprocal is 1 / f, which is the time required to complete the readout of one frame of signal. Each output channel of the infrared focal plane readout circuit completes the readout of one signal per clock cycle. Assuming the readout circuit array size is M*N and the output stage operational amplifier is designed to be K, the readout circuit output stage unity gain buffer completes the establishment of one signal at a maximum frequency of X. Then 1 / f = M*N / K*X.

[0027] The following will combine Figures 1-3 The method described in the embodiments of the present invention will be explained and illustrated in detail through a specific example: This invention provides a large-scale infrared focal plane readout circuit suitable for high frame rate applications. This readout circuit can effectively solve the problem of excessively long signal readout time and low frame rate caused by conventional large-scale readout circuits in certain high-speed target scenarios.

[0028] Specifically, the method for designing an infrared focal plane readout circuit according to embodiments of the present invention includes: First, an injection-stage pixel module is designed to convert the detector photocurrent into a voltage signal. The injection-stage pixel module is connected to the photodiode array via indium pillars. Based on the detector's wavelength and the characteristics of the target being detected, a suitable injection-stage structure, such as CTIA, DI, or BDI, is selected to complete the integration of the detector photocurrent and voltage conversion.

[0029] Secondly, the design places the column processing circuits above and below the pixel array, respectively, for odd and even columns. The outputs of each column of pixels in the pixel array are connected together to form a bus, and row selection switches control the connection and disconnection of each row of pixels in a column to the column bus. During readout, the row selection switches are turned on row by row to complete the readout of one column of pixels. Each column of pixels corresponds to one column processing circuit, with the column processing circuits for odd columns located above the pixel array and the column processing circuits for even columns located below the pixel array. The column processing circuits employ an OTA operational amplifier with a ping-pong sample-and-hold structure.

[0030] The results of the column processing circuit are output by redesigning a unity-gain buffer with a high slew rate. Specifically, the method described in this embodiment of the invention uses a cascaded structure of a folded common-source cascode differential op-amp and a Class AB push-pull inverting op-amp to design an output stage unity-gain buffer, which is evenly distributed at the ends of the odd and even column processing circuits. The number of output stage buffers is determined according to the number of counts of the column counter, and is responsible for driving the signals of several column processing circuits within its position range to the off-chip.

[0031] Finally, a timing generation circuit for controlling the analog link was designed, the overall design was completed and the chip was fabricated; specifically, the embodiment of the present invention uses simple logic gate circuits and digital logic circuits such as counters and latches to design the integration reset and row selection and column selection related control timing.

[0032] Figure 1 This diagram illustrates a large-scale, high-frame-rate infrared focal plane array readout circuit. It includes an M-column, N-row pixel array. The pixel injection stage structure can be selected from DI, CTIA, BDI, etc., depending on the detector characteristics and target features. Column processing circuit arrays are distributed on the top and bottom sides of the pixel array, with odd-numbered columns on top and even-numbered columns on the bottom (these can be interchanged). Each column of pixels shares one column processing circuit. K output stage operational amplifiers are evenly spaced at the ends of the odd and even column processing circuit arrays. They are responsible for sequentially driving the data from the column processing circuits to off-chip outputs. Each output stage operational amplifier is responsible for the outputs of M / K column processing circuits near its location, outputting sequentially according to timing control. The readout time for each row of pixel data is M / K master clock cycles. The appropriate number of K can be designed based on the target frame rate of the readout circuit; a larger number of K results in a faster readout time and a higher frame rate.

[0033] Figure 2This diagram illustrates the layout of the pixel and column processing circuits. The output of each pixel in the first column is connected to the first column pixel output bus via a row selection switch. The switch can be a single-transistor NMOS / PMOS or a transmission gate. The output bus of the first column pixels connects upwards to the input of the first column processing circuit, and the output bus of the second column pixels connects downwards to the input of the second column processing circuit. Since the odd and even column processing circuits are distributed on both sides of the pixel array, assuming the pixel pitch is X, the traditional readout circuit design uses a column processing circuit with a width consistent with the pixel pitch of X. However, the column processing circuit width using this design can be increased to 2X, doubling the width compared to the traditional readout circuit, which is highly advantageous for small-pitch designs.

[0034] Figure 3 This is a schematic diagram showing the connection between the column-level processing circuit and the output stage. The output terminal of column operational amplifier 1 is shorted to the inverting input terminal to form a unity-gain buffer, which drives the pixel integral voltage to the column processing circuit for sampling and holding. Its positive input transistor is located in each pixel. When the row selection transistor in the pixel is turned on, the positive input transistor in the pixel and other parts located in the column processing circuit form a complete operational amplifier to realize the function. Switches 2 and 3 are identical in structure and are turned on complementaryly through timing control. In odd-numbered rows, switch 3 is on and switch 2 is off. The signal in the pixel is driven and sampled into column ping-pong sampling capacitor 7 and held, then sequentially selected by column selector 5 to output stage operational amplifier 8. In even-numbered rows, switch 2 is on and switch 3 is off. The signal in the pixel is driven and sampled into column ping-pong sampling capacitor 6 and held, then sequentially selected by column selector 4 to output stage operational amplifier 8. The output terminals of the column selectors of the M / K column processing circuits are connected to the positive input of output stage operational amplifier 8. The output stage operational amplifier adopts a cascaded structure of folded common-source common-gate and Class AB push-pull inverting operational amplifiers, achieving a slew rate of up to 78.5MV / s. Within the 1.8V voltage domain, the full-swing setup time for the signal is ≤14ns, and the readout frequency of the readout circuit can reach up to 40MHz. Transmission gate 9 implements channel selection, and the number of output channels can be controlled through additional digital logic.

[0035] Accordingly, embodiments of the present invention also provide an infrared focal plane readout circuit designed using the method described above, the infrared focal plane readout circuit comprising: The column processing circuit of the infrared focal plane readout circuit is divided into odd-numbered column processing circuit and even-numbered column processing circuit on both sides of the pixel array. Each column of pixels in the infrared focal plane readout circuit corresponds to a column processing circuit. That is, the output of each column of pixels in the pixel array is connected together to form a bus. The row selection switch controls the connection and disconnection of each row of pixels in a column with the column bus. During readout, the row selection switch is turned on row by row to complete the readout of a column of pixels. There are K output stage operational amplifiers, which are equally spaced at the ends of the odd-numbered column processing circuits and the even-numbered column processing circuits, so as to drive the data of the column processing circuits to be output to the off-chip in sequence. Each output stage operational amplifier is used to output the M / K column processing circuits near its position in sequence according to the timing control. The readout time of each row of pixel data is M / K main clock cycles.

[0036] In this embodiment of the invention, the output stage operational amplifier is a unity-gain buffer, and the output stage unity-gain buffer is designed by cascading a folded common-source cascode differential operational amplifier and a Class AB push-pull inverting operational amplifier.

[0037] Practice has proven that the infrared focal plane readout circuit structure of this invention improves the readout speed of the readout circuit and can still maintain a high readout frame rate when the array size increases. It has obvious advantages over the traditional structure and will have important applications in infrared imaging systems with large array and high frame rate requirements.

[0038] Although preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will recognize that various modifications, additions, and substitutions are possible, and therefore the scope of the invention should not be limited to the embodiments described above.

Claims

1. A method for designing a large-scale, high-frame-rate infrared focal plane readout circuit, characterized in that, include: An injection-level pixel module is set up for the infrared focal plane readout circuit, and the photocurrent of the infrared focal plane detector is converted into a voltage signal through the injection-level pixel module. The column processing circuits of the infrared focal plane readout circuit are divided into odd-numbered column processing circuits and even-numbered column processing circuits on both sides of the pixel array. Each column of pixels in the infrared focal plane readout circuit corresponds to a column processing circuit. That is, the outputs of each column of pixels in the pixel array are connected together to form a bus. The row selection switch controls the connection and disconnection of each row of pixels in a column with the column bus. K output stage operational amplifiers are evenly distributed at the ends of the odd-numbered column processing circuits and the even-numbered column processing circuits to drive the data of the column processing circuits to be output to the off-chip in sequence. Each output stage operational amplifier is used to output M / K column processing circuits near its position in sequence according to the timing control. The readout time of each row of pixel data is M / K master clock cycles.

2. The method according to claim 1, characterized in that, The injection-level pixel module of the infrared focal plane readout circuit includes: Based on the magnitude and range of the input signal, a preset input stage structure is adopted, equipped with an integrating capacitor size that matches the signal. The width-to-length ratio of the operational amplifier input pair, tail current source, and switch in the preset input stage structure is adjusted according to simulation iterations, so that the infrared focal plane detector current signal is injected into the integrating capacitor with the highest efficiency and converted into a suitable voltage signal.

3. The method according to claim 2, characterized in that, The preset input level structure is the CTIA input level structure, the DI input level structure, and the BDI input level structure.

4. The method according to claim 1, characterized in that, The column processing circuit uses an OTA operational amplifier with a ping-pong sample-and-hold structure.

5. The method according to claim 1, characterized in that, The output stage operational amplifier is a unity-gain buffer, and the unity-gain buffer is designed by cascading a folded common-source cascode differential operational amplifier and a Class AB push-pull inverting operational amplifier.

6. The method according to claim 5, characterized in that, The number of unity-gain buffers is determined by the number of counts of the column counter.

7. The method according to any one of claims 1-6, characterized in that, The required frame rate f of the infrared focal plane readout circuit is equal to the reciprocal 1 / f, which is the time required to read out one frame of signal. Each output channel of the infrared focal plane readout circuit completes the reading out of one signal per clock cycle. Assuming the readout circuit array size is M*N, the output stage operational amplifier is designed to be K, and the readout circuit output stage unity gain buffer completes the establishment of one signal at a maximum frequency of X, then 1 / f = M*N / K*X.

8. The method according to any one of claims 1-6, characterized in that, The method further includes: The overall design and fabrication of the infrared focal plane readout circuit were completed by controlling the timing generation circuit of the analog link.

9. An infrared focal plane readout circuit designed using the method described in any one of claims 1-7, characterized in that, The infrared focal plane readout circuit includes: The column processing circuit of the infrared focal plane readout circuit is divided into odd-numbered column processing circuit and even-numbered column processing circuit on both sides of the pixel array. Each column of pixels in the infrared focal plane readout circuit corresponds to a column processing circuit. That is, the output of each column of pixels in the pixel array is connected together to form a bus, and the connection and disconnection of each row of pixels in a column to the column bus is controlled by the row selection switch. There are K output stage operational amplifiers, and the output stage operational amplifiers are equally spaced at the ends of the odd-numbered column processing circuits and the even-numbered column processing circuits, so as to drive the data of the column processing circuits to be output to the off-chip in sequence. Each output stage operational amplifier is used to output the M / K column processing circuits near its position in sequence according to the timing control. The readout time of each row of pixel data is M / K main clock cycles.

10. The infrared focal plane readout circuit according to claim 8, characterized in that, The output stage operational amplifier is a unity-gain buffer, and the unity-gain buffer is designed by cascading a folded common-source cascode differential operational amplifier and a Class AB push-pull inverting operational amplifier.

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