Transceiver and electronic device including the same

Abstract

A transceiver and an electronic device including the same are provided. The transceiver includes a first mixer, a noise reduction circuit, a first amplifier, a second amplifier, and an input / output (I / O) port. The first mixer receives first data and a first clock signal, and generates a first signal to be transmitted to an external device based on the first data and the first clock signal. The noise reduction circuit provides a first clock signal to the first mixer. The first amplifier amplifies the first signal received from the first mixer. The second amplifier amplifies a second signal received from an external device. The I / O port is shared by the first amplifier and the second amplifier and is configured to output the amplified first signal and receive the second signal. The noise reduction circuit activates the first clock signal during an activation time interval of the first data and deactivates the first clock signal during a deactivation time interval of the first data.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0109300, filed on August 14, 2024, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] The example embodiments generally relate to semiconductor integrated circuits, and more specifically, to transceivers and semiconductor chips with low noise characteristics, and electronic devices including transceivers and / or semiconductor chips. Background Technology

[0003] As packaging costs increase, the size of radio frequency integrated circuits (RFICs) used in wireless mobile communications has become increasingly smaller. Furthermore, for RFICs used in wireless mobile communications, producing the desired output at low power is advantageous. Recently, with the evolution of mobile communications from third-generation (3G) to Long Term Evolution (LTE) and then to fifth-generation (5G), RFICs used in wireless mobile communications increasingly need to support modulation such as radio detection and ranging (RADAR), and their operating frequencies are also increasing. However, problems exist in the design of impedance matching networks for RFICs used in wireless mobile communications, as well as in the design of RFICs with low-noise characteristics. Summary of the Invention

[0004] At least one example embodiment of this disclosure provides a transceiver and semiconductor chip capable of having low noise characteristics by preventing signals from the transmitter from being transmitted to the receiver.

[0005] At least one example embodiment of this disclosure provides an electronic device including a transceiver and / or a semiconductor chip.

[0006] According to an example embodiment, a transceiver includes a first mixer, a noise reduction circuit, a first amplifier, a second amplifier, and an input / output (I / O) port. The first mixer receives first data and a first clock signal, and generates a first signal to be transmitted to an external device based on the first data and the first clock signal. The noise reduction circuit provides the first clock signal to the first mixer. The first amplifier amplifies the first signal received from the first mixer. The second amplifier amplifies a second signal received from an external device. The I / O port is shared by the first and second amplifiers and is configured to output the amplified first signal and receive the second signal. The noise reduction circuit activates the first clock signal during an activation period of the first data and deactivates the first clock signal during a deactivation period of the first data.

[0007] According to an example embodiment, a transceiver includes a first mixer, a first amplifier, a second amplifier, an input / output (I / O) port, a switching circuit, and a noise reduction circuit. The first mixer receives first data and a first clock signal, and generates a first signal to be transmitted to an external device based on the first data and the first clock signal. The first amplifier amplifies the first signal received from the first mixer. The second amplifier amplifies a second signal received from the external device. The I / O port is shared by the first and second amplifiers and is configured to output the amplified first signal and receive the second signal. The switching circuit is disposed between the first amplifier and the I / O port and is turned on and off based on a switching control signal. The noise reduction circuit provides the switching control signal to the switching circuit. The noise reduction circuit is configured to output the switching control signal to have an active state during an active time interval of the first data, and to output the switching control signal to have a deactivated state during a deactivated time interval of the first data.

[0008] According to an example embodiment, a semiconductor chip includes a processor and a transceiver. The processor generates first data to be sent to an external device. The transceiver receives the first data and operates based on the first data. The transceiver includes a first mixer, a noise reduction circuit, a first amplifier, a second amplifier, and input / output (I / O) ports. The first mixer generates a first signal based on the first data and a first clock signal. The noise reduction circuit provides the first clock signal to the first mixer. The first amplifier amplifies the first signal received from the first mixer. The second amplifier amplifies a second signal received from an external device. The I / O ports are shared by the first and second amplifiers and are configured to output the amplified first signal and receive the second signal. The noise reduction circuit activates the first clock signal during an activation time interval of the first data and deactivates the first clock signal during a deactivation time interval of the first data.

[0009] According to an example embodiment, a semiconductor chip includes a processor and a transceiver. The processor generates first data to be sent to an external device. The transceiver receives the first data and operates based on the first data. The transceiver includes a first mixer, a first amplifier, a second amplifier, an input / output (I / O) port, a switching circuit, and a noise reduction circuit. The first mixer generates a first signal based on the first data and a first clock signal. The first amplifier amplifies the first signal received from the first mixer. The second amplifier amplifies the second signal received from the external device. The I / O port is shared by the first and second amplifiers and is configured to output the amplified first signal and receive the second signal. The switching circuit is disposed between the first amplifier and the I / O port and is turned on and off based on a switching control signal. The noise reduction circuit provides the switching control signal to the switching circuit. The noise reduction circuit is configured to: control the switching control signal to be active during the active time interval of the first data and control the switching control signal to be inactive during the deactivation time interval of the first data.

[0010] According to an example embodiment, an electronic device includes an antenna, a processor, and a transceiver. The antenna transmits a first signal to an external device or receives a second signal from an external device. The processor generates first data corresponding to the first signal, generates an enable signal, and receives second data corresponding to the second signal. The enable signal is activated during an activation time interval of the first data and deactivated during a deactivation time interval of the first data. The transceiver generates the first signal based on the first data and the enable signal, and generates the second data based on the second signal. The transceiver includes a noise reduction circuit, a first mixer, a power amplifier, a low-noise amplifier, a second mixer, input / output (I / O) ports, and switching circuitry. The noise reduction circuit generates a first clock signal based on the enable signal and a second clock signal, and generates a switch control signal based on the enable signal. The first mixer generates the first signal based on the first data and the first clock signal. The power amplifier amplifies the first signal. The low-noise amplifier amplifies the second signal. The second mixer generates the second data based on the amplified second signal and the second clock signal. The I / O ports are shared by the first amplifier and the second amplifier and are connected to the antenna. The switching circuit is located between the first amplifier and the I / O port, and is turned on and off based on the switching control signal.

[0011] In transceivers, semiconductor chips, and electronic devices according to example embodiments, I / O ports may be shared by the transmitter and receiver, and noise reduction circuitry that generates a noise reduction control signal synchronously with first data may be included. For example, the noise reduction control signal may be generated based on an enable signal. For example, the noise reduction control signal and the enable signal may be activated (e.g., in an active state) during the activation time interval of the first data and deactivated (e.g., in an inactive state) during the deactivation time interval of the first data. For example, at least one of a mixer and a switching circuit included in the transmitter may be selectively turned on and off based on the enable signal. Therefore, noise from the transmitter can be efficiently prevented from being transmitted to the receiver, and the transceiver may have relatively improved or enhanced performance. Attached Figure Description

[0012] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 This is a block diagram illustrating a transceiver according to an example embodiment.

[0014] Figure 2 It is shown Figure 1 A block diagram of an example transceiver.

[0015] Figure 3 It is shown that it includes Figure 2 A block diagram of an example noise reduction circuit in a transceiver.

[0016] Figure 4 It is used to describe Figure 3 A diagram illustrating the operation of the noise reduction circuit.

[0017] Figure 5 It is shown that it includes Figure 2 A block diagram of an example noise reduction circuit in a transceiver.

[0018] Figure 6 It is shown Figure 1 A block diagram of an example transceiver.

[0019] Figure 7 It is shown Figure 1 A block diagram of an example transceiver.

[0020] Figure 8 It is shown Figure 1 A block diagram of an example transceiver.

[0021] Figure 9 It is shown that it includes Figure 8 A block diagram of an example noise reduction circuit in a transceiver.

[0022] Figure 10A and Figure 10B It is used to describe Figure 9 A diagram of the noise reduction circuit.

[0023] Figure 11 It is shown Figure 9 A diagram illustrating examples of buffer circuits and switching circuits.

[0024] Figure 12 , Figure 13 and Figure 14 It is used to describe according to the example embodiments Figure 9 A diagram illustrating the operation of the noise reduction circuit.

[0025] Figure 15 It is shown Figure 9 A diagram illustrating examples of buffer circuits and switching circuits.

[0026] Figure 16 It is shown Figure 1 A block diagram of an example transceiver.

[0027] Figure 17 It is shown Figure 1 A block diagram of an example transceiver.

[0028] Figure 18 It is shown that it includes Figure 17 A block diagram of an example noise reduction circuit in a transceiver.

[0029] Figure 19 This is a block diagram illustrating a semiconductor chip according to an example embodiment.

[0030] Figure 20 and Figure 21 This is a flowchart illustrating a method for sending data according to an example embodiment.

[0031] Figure 22 This is a block diagram illustrating an electronic device in a network environment according to an example embodiment. Detailed Implementation

[0032] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, the same reference numerals denote the same elements.

[0033] Ordinal numbers (such as "first," "second," "third," etc.) can simply be used as labels for specific elements, steps, etc., to distinguish them from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, terms referenced with a specific ordinal number (e.g., "first") in a particular claim may be described elsewhere in the specification or in other claims using a different ordinal number (e.g., "second").

[0034] This is described herein as a component that performs a specific function or step, configured to perform those functions or steps based on hardware (such as circuitry) and, in some cases, software included therein.

[0035] Figure 1 This is a block diagram illustrating a transceiver according to an example embodiment.

[0036] Reference Figure 1 The transceiver 10 includes a noise reduction circuit 20, a transmitter 30, a receiver 40, and an input / output (I / O) port PT.

[0037] In some example embodiments, transceiver 10 may be included in an electronic device (e.g., a communication device). For example, transceiver 10 may transmit signals to an external device (e.g., another electronic device and / or another transceiver), and / or receive signals from an external device.

[0038] In some example embodiments, transceiver 10 may be implemented as a single integrated circuit (IC). For example, the noise reduction circuitry 20, transmitter 30, receiver 40, and I / O port PT included in transceiver 10 may be included in a single semiconductor chip (or a single semiconductor package or module).

[0039] Transmitter 30 receives first data TDAT and generates and outputs a first signal (or transmit signal) by performing data processing and / or signal processing on the first data TDAT. For example, the first data TDAT may be provided from a processor located outside transceiver 10. For example, the first signal may be output externally to transceiver 10 and may be transmitted to other electronic devices and / or other transceivers. Transmitter 30 and / or the path including transmitter 30 may be referred to as a transmission path.

[0040] Receiver 40 receives a second signal (or a receive signal) and generates and outputs second data RDAT by performing signal processing and / or data processing on the second signal. For example, the second signal may be provided from another electronic device and / or another transceiver. For example, the second data RDAT may be output externally from transceiver 10 and may be sent to a processor. Receiver 40 and / or the path including receiver 40 may be referred to as a receive path.

[0041] The I / O port PT is connected to and shared by the transmitter 30 and the receiver 40. The I / O port PT can be connected to the antenna 50 located outside the transceiver 10, and can output a first signal or receive a second signal through the antenna 50.

[0042] In some example embodiments, transceiver 10 can operate in both a transmit mode and a receive mode. For example, in transmit mode, transmitter 30 can be enabled or activated to receive first data TDAT and generate and output a first signal, and receiver 40 can be disabled or deactivated at this time. For example, in receive mode, receiver 40 can be enabled or activated to receive a second signal and generate and output second data RDAT, and transmitter 30 can be disabled or deactivated at this time.

[0043] In some example embodiments, transceiver 10 may operate in an operating mode in which transmitter 30 and receiver 40 are enabled or activated together. For example, when transceiver 10 is included in an electronic device that supports radio detection and ranging (RADAR) functionality, transceiver 10 for RADAR functionality may operate with transmitter 30 and receiver 40 enabled substantially simultaneously or concurrently.

[0044] The noise reduction circuit 20 generates a noise reduction control signal NRCON. The noise reduction control signal NRCON can be provided to the transmitter 30, and the transmitter 30 can perform noise reduction operations based on the noise reduction control signal NRCON. For example, in an operating mode where the transmitter 30 and receiver 40 are both enabled, when the transmitter 30 generates and outputs a first signal based on the first data TDAT, noise generated by the transmitter 30 can be prevented from being transmitted to the receiver 40 via the I / O port PT based on the noise reduction control signal NRCON.

[0045] For example, the noise reduction circuit 20 may receive an enable signal EN and may generate a noise reduction control signal NRCON based on the enable signal EN. The enable signal EN may be provided synchronously with the first data TDAT. For example, the enable signal EN may be activated during the activation time interval of the first data TDAT (e.g., the time interval during which the first data TDAT is transmitted) and deactivated during the deactivation time interval of the first data TDAT (e.g., the time interval during which the first data TDAT is not transmitted). For example, since the enable signal EN is synchronized with the first data TDAT, it may be provided from the processor similarly to the first data TDAT.

[0046] The detailed configuration and operation of the noise reduction circuit 20 will be described later.

[0047] In transceiver architectures where I / O ports are shared by the transmitter and receiver, there is a potential issue where signals output from the transmitter are reflected and transmitted to the receiver. To prevent or mitigate the impact of such problems, schemes have been investigated to reduce the noise of the transmitter itself, to use additional external components (such as circulators), and / or to use additional techniques (such as self-interference cancellation (SIC)). However, when reducing the noise of the transmitter itself, the current consumption of the transmitter typically increases significantly, and it is difficult to achieve the target output power. Furthermore, when using additional external components and / or additional techniques, it is often difficult to ensure a wide bandwidth frequency.

[0048] In the transceiver 10 according to the example embodiment, the I / O port PT may be shared by the transmitter 30 and the receiver 40, and a noise reduction circuit 20 that generates a noise reduction control signal NRCON synchronously with the first data TDAT may be included. For example, the noise reduction control signal NRCON may be generated based on an enable signal EN. For example, the noise reduction control signal NRCON and the enable signal EN may be activated during the activation time interval of the first data TDAT (e.g., in an active or activated state) and deactivated during the deactivation time interval of the first data TDAT (e.g., in an inactive or deactivated state). For example, as will be referred to Figure 2 The mixer included in transmitter 30 can be selectively turned on and off based on the enable signal EN. For example, as will be referred to... Figure 8 The described switching circuitry included in transmitter 30 can be selectively turned on and off based on the enable signal EN. Therefore, noise from transmitter 30 can be efficiently prevented from being transmitted to receiver 40, and transceiver 10 can have relatively improved or enhanced performance.

[0049] Figure 2 It is shown Figure 1 A block diagram of an example transceiver.

[0050] Reference Figure 2 The transceiver 100 includes a noise reduction circuit 110, a first mixer 120, a first amplifier 130, a second amplifier 140, and an I / O port PT. The transceiver 100 may also include a second mixer 150.

[0051] The noise reduction circuit 110 and the I / O port PT can be respectively connected to Figure 1 The noise reduction circuit 20 corresponds to the I / O port PT. The first mixer 120 and the first amplifier 130 may be included. Figure 1 The transmitter 30. The second amplifier 140 and the second mixer 150 may be included. Figure 1 In receiver 40. For brevity, the following will be omitted. Figure 1 The description is repetitive or overlapping.

[0052] The noise reduction circuit 110 generates a first clock signal LO1 that is provided to the first mixer 120. For example, the noise reduction circuit 110 may activate the first clock signal LO1 during the activation time interval of the first data TDAT and may deactivate the first clock signal LO1 during the deactivation time interval of the first data TDAT. For example, the first clock signal LO1 may be included in... Figure 1 In the noise reduction control signal NRCON. For example, the noise reduction circuit 110 may receive an enable signal EN that is activated (e.g., in an active or active state) during the activation time interval of the first data TDAT and deactivated (e.g., in an inactive or deactivated state) during the deactivation time interval of the first data TDAT, and may generate a first clock signal LO1 based on the enable signal EN. Refer to Figure 3 and Figure 5 An example describing the noise reduction circuit 110.

[0053] The first mixer 120 receives first data TDAT and generates a first signal TS to be sent to an external device based on the first data TDAT and the first clock signal LO1. For example, the first mixer 120 may be a mixer for up-conversion. For example, the first mixer 120 may be a passive mixer.

[0054] The first amplifier 130 amplifies the first signal TS and generates the amplified first signal ATS. For example, the first amplifier 130 may be a power amplifier (PA).

[0055] The second amplifier 140 amplifies the second signal RS received from the external device and generates an amplified second signal ARS. For example, the second amplifier 140 may be a low-noise amplifier (LNA).

[0056] The second mixer 150 can generate second data RDAT based on the amplified second signal ARS and the second clock signal LO2. For example, the second mixer 150 can be a mixer for down-conversion.

[0057] The I / O port PT is shared by the first amplifier 130 and the second amplifier 140, and outputs the amplified first signal ATS or receives the second signal RS through the antenna 50.

[0058] In some example embodiments, the first clock signal LO1 generated based on the enable signal EN can be switched during the active time interval of the first data TDAT and can be deactivated during the deactivation time interval of the first data TDAT. Therefore, the first mixer 120 operating based on the first clock signal LO1 can be turned on and operate normally during the active time interval of the first data TDAT, and can be turned off and inactive during the deactivation time interval of the first data TDAT. (Refer to...) Figure 4Example describing the first data TDAT, the enable signal EN, and the first clock signal LO1.

[0059] Figure 3 It is shown that it includes Figure 2 A block diagram of an example noise reduction circuit in a transceiver.

[0060] Reference Figure 3 The noise reduction circuit 110a may include an AND gate 112. For ease of illustration, a first mixer 120 and a first amplifier 130 operating in conjunction with the noise reduction circuit 110a on the transmitter side are shown together.

[0061] AND gate 112 can generate the first clock signal LO1 by performing an AND operation on the enable signal EN and the second clock signal LO2.

[0062] In some example embodiments, the second clock signal LO2 can be switched at all times (or continuously) regardless of the enable signal EN. An AND operation can be performed on the enable signal EN and the second clock signal LO2, and thus a first clock signal LO1 can be generated that switches during the active time interval of the first data TDAT and is deactivated during the deactivation time interval of the first data TDAT.

[0063] However, the example embodiment is not limited thereto, and the noise reduction circuit 110a can be implemented with at least one of various structures for generating a first clock signal LO1 based on the enable signal EN, which is switched during the activation time interval of the first data TDAT and deactivated during the deactivation time interval of the first data TDAT.

[0064] Figure 4 It is used to describe Figure 3 A diagram illustrating the operation of the noise reduction circuit.

[0065] Reference Figure 3 and Figure 4 Examples of first data TDAT, enable signal EN, first clock signal LO1 and second clock signal LO2, and first signal TS according to an example embodiment are shown, and an example of first signal TSc according to a conventional scheme is also shown.

[0066] The first data TDAT may include an activation time interval T1 and a deactivation time interval T2. For example, the activation time interval T1 may be a time interval in which the voltage level of the first data TDAT is changed (e.g., a time interval in which the first data TDAT has a specific value). For example, the deactivation time interval T2 may be a time interval in which the voltage level of the first data TDAT is not changed and is maintained (e.g., a time interval in which the first data TDAT does not have a specific value (or a time interval in which no data value exists)).

[0067] The enable signal EN can be activated during the activation time interval T1 of the first data TDAT, and can be deactivated during the deactivation time interval T2 of the first data TDAT. For example, activation of the enable signal EN can indicate or suggest that the enable signal EN has a logic high level, and deactivation of the enable signal EN can indicate or suggest that the enable signal EN has a logic low level. However, the example embodiment is not limited thereto.

[0068] The second clock signal LO2 can be switched continuously during both the activation time interval T1 and the deactivation time interval T2 of the first data TDAT. For example, the switching of the second clock signal LO2 can indicate or indicate that the second clock signal LO2 alternately has a logic high level and a logic low level, for example, the voltage level of the second clock signal LO2 changes (or oscillates) regularly between a logic high level and a logic low level.

[0069] The first clock signal LO1 can be switched during the activation time interval T1 of the first data TDAT, and can be deactivated during the deactivation time interval T2 of the first data TDAT. For example, the switching of the first clock signal LO1 can indicate or indicate that the first clock signal LO1 alternately has a logic high level and a logic low level, and the deactivation of the first clock signal LO1 can indicate or indicate that the first clock signal LO1 has a logic low level.

[0070] According to the example embodiment, the first signal TS generated based on the first data TDAT and the first clock signal LO1 may have an up-converted waveform in which the first data TDAT and the first clock signal LO1 are mixed during the activation time interval T1 of the first data TDAT, and may have relatively small or low noise because the first clock signal LO1 is deactivated and the first mixer 120 is disconnected during the deactivation time interval T2 of the first data TDAT.

[0071] In contrast, because the second clock signal LO2 switches and the first mixer 120 is turned on even during the deactivation time interval T2 of the first data TDAT, the first signal TSc generated by the conventional scheme based on the first data TDAT and the second clock signal LO2 may have relatively large or high noise.

[0072] Regarding signal-to-noise ratio (SNR), noise from the input can be the most significant factor. Therefore, when no data or signal is present (e.g., during the deactivation time interval T2 of the first data TDAT), according to the example embodiment, the first clock signal LO1 can be used to disconnect the first mixer 120, thus shielding against noise transmitted to the receiver and reducing current consumption. For example, as... Figure 3As shown, the first mixer 120 can be selectively turned on and off by receiving an enable signal EN and using an AND gate 112, and such a configuration can be referred to as a switching AND gate type mixer.

[0073] Figure 5 It is shown that it includes Figure 2 A block diagram of an example noise reduction circuit in a transceiver. For brevity, [the following is omitted]. Figure 3 The description is repetitive or overlapping.

[0074] Reference Figure 5 The noise reduction circuit 110b may include an AND gate 112 and a buffer circuit 114.

[0075] Buffer circuit 114 can be disposed or located between AND gate 112 and the first mixer 120, and can generate a first clock signal LO1' based on the output of AND gate 112. The first clock signal LO1' can be ANDed with... Figure 3 The first clock signal LO1 is basically the same.

[0076] For example, buffer circuit 114 may include multiple inverters INV11 and INV12 connected in series. For ease of illustration, only two inverters INV11 and INV12 are shown, but the example embodiment is not limited thereto. Inverters INV11 and INV12 can be used as buffers for driving clock signals with high radio frequency (RF) frequencies.

[0077] However, the example embodiments are not limited thereto, and in addition to AND gate 112, the noise reduction circuit 110 may also include at least one of other components necessary for the operation of the transceiver or for the operation of the transceiver.

[0078] Figure 6 It is shown Figure 1 A block diagram of an example transceiver. For brevity, the symbols and symbols are omitted. Figure 2 The description is repetitive or overlapping.

[0079] Reference Figure 6 The transceiver 100a includes a noise reduction circuit 110, a first mixer 120, a first amplifier 130, a second amplifier 140, and an I / O port PT. The transceiver 100a may also include a second mixer 150, a transmit (TX) circuit 160, an output circuit 165, an input circuit 170, and a receive (RX) circuit 175.

[0080] The transmitting circuit 160 may be located at the front end of the first amplifier 130 and may generate a first signal TS based on the first data TDAT. For example, a first mixer 120 may be included in the transmitting circuit 160. For example, although not shown in detail, the transmitting circuit 160 may also include an analog filter, etc.

[0081] The output circuit 165 may be located at the rear end of the first amplifier 130 and may output the amplified first signal ATS. For example, although not shown in detail, the output circuit 165 may include an impedance matching circuit, a filter, etc.

[0082] The input circuit 170 may be located at the front end of the second amplifier 140 and may receive the second signal RS. For example, although not shown in detail, the input circuit 170 may include impedance matching circuitry, filters, etc.

[0083] The receiving circuit 175 may be located at the rear end of the second amplifier 140 and may generate second data RDAT based on the amplified second signal ARS. For example, a second mixer 150 may be included in the receiving circuit 175. For example, although not shown in detail, the receiving circuit 175 may also include analog filters, etc.

[0084] In some example embodiments, the transmitter and receiver (or transmit path and receive path) may be implemented to generate differential signals. In some example embodiments, the transmit circuit 160 and the output circuit 165 may include at least one current source, at least one resistor, at least one capacitor, at least one converter, a pre-power amplifier (PPA), etc.

[0085] Figure 7 It is shown Figure 1 A block diagram of an example transceiver. For brevity, the symbols and symbols are omitted. Figure 2 The description is repetitive or overlapping.

[0086] Reference Figure 7 The transceiver 101 includes a noise reduction circuit 111, a first mixer 120, a first amplifier 130, a second amplifier 140, and an I / O port PT. The transceiver 101 may also include a second mixer 150.

[0087] The noise reduction circuit 110 generates a first clock signal LO1 as the noise reduction control signal NRCON, and the first mixer 120 is turned on and off based on the first clock signal LO1. Figure 2 The examples are different. Figure 7 The noise reduction circuit 111 in the middle can generate a mixer on / off signal MOF as the noise reduction control signal NRCON, and Figure 7The first mixer 120 can be turned on and off based on a mixer on / off signal MOF and can operate based on a second clock signal LO2. For example, the mixer on / off signal MOF can be activated during the active time interval of the first data TDAT and deactivated during the deactivated time interval of the first data TDAT. For example, the noise reduction circuit 111 can generate the mixer on / off signal MOF based on an enable signal EN, and the waveform of the mixer on / off signal MOF can be similar to the waveform of the enable signal EN. For example, the first mixer 120 can be turned on during the active time interval of the mixer on / off signal MOF (e.g., a time interval with a logic high level) and turned off during the deactivated time interval of the mixer on / off signal MOF (e.g., a time interval with a logic low level).

[0088] Figure 8 It is shown Figure 1 A block diagram of an example transceiver.

[0089] Reference Figure 8 The transceiver 200 includes a noise reduction circuit 210, a first mixer 220, a first amplifier 230, a second amplifier 240, an I / O port PT, and a switching circuit 260. The transceiver 200 may also include a second mixer 250.

[0090] The noise reduction circuit 210 and the I / O port PT can be respectively connected to Figure 1 The noise reduction circuit 20 corresponds to the I / O port PT. The first mixer 220, the first amplifier 230, and the switching circuit 260 may be included. Figure 1 The transmitter 30. The second amplifier 240 and the second mixer 250 may be included. Figure 1 In receiver 40. For brevity, the following will be omitted. Figure 1 The description is repetitive or overlapping.

[0091] The noise reduction circuit 210 generates a switching control signal SCC that is provided to the switching circuit 260. For example, the noise reduction circuit 210 may activate (e.g., output) the switching control signal SCC during the activation time interval of the first data TDAT, and may deactivate (e.g., output) the switching control signal SCC during the deactivation time interval of the first data TDAT. For example, the switching control signal SCC may be included in... Figure 1 In the noise reduction control signal NRCON. For example, the noise reduction circuit 210 may receive an enable signal EN that is activated during the activation time interval of the first data TDAT and deactivated during the deactivation time interval of the first data TDAT, and may generate a switch control signal SCC based on the enable signal EN. Refer to Figure 9 , Figure 11 and Figure 15 An example describing the noise reduction circuit 210.

[0092] The first mixer 220 receives first data TDAT and generates a first signal TS to be sent to an external device based on the first data TDAT and the clock signal LO. For example, the first mixer 220 can be used with... Figure 2 The first mixer 120 is similar. For example, the clock signal LO can be... Figure 2 The first clock signal LO1 or Figure 7 The second clock signal LO2 is similar.

[0093] The first amplifier 230 amplifies the first signal TS and generates the amplified first signal ATS. For example, the first amplifier 230 can be used with... Figure 2 The first amplifier 130 is similar.

[0094] The second amplifier 240 amplifies the second signal RS received from the external device and generates an amplified second signal ARS. For example, the second amplifier 240 can be used with... Figure 2 The second amplifier 140 is similar.

[0095] The second mixer 250 can generate second data RDAT based on the amplified second signal ARS and the clock signal LO. For example, the second mixer 250 can be used with... Figure 2 The second mixer 150 is similar.

[0096] The I / O port PT is shared by the first amplifier 130 and the second amplifier 140, and outputs the amplified first signal ATS or receives the second signal RS through the antenna 50.

[0097] A switching circuit 260 is disposed or located between the first amplifier 230 and the I / O port PT, and is turned on and off based on a switching control signal SCC, and outputs a signal ATS' corresponding to the amplified first signal ATS. For example, the switching circuit 260 can be turned on in a transmit mode for sending the amplified first signal ATS to an external device, and can be turned off in a receive mode for receiving a second signal RS from an external device.

[0098] In some example embodiments, the switch control signal SCC generated based on the enable signal EN can be activated during the activation time interval of the first data TDAT and deactivated during the deactivation time interval of the first data TDAT. Therefore, the switch circuit 260, operating based on the switch control signal SCC, can be turned on (or closed) during the activation time interval of the first data TDAT and electrically connect the first amplifier 230 to the I / O port PT, and can be turned off (or open-circuited) during the deactivation time interval of the first data TDAT and block the electrical connection between the first amplifier 230 and the I / O port PT. Therefore, the switch circuit 260 can not be continuously turned on in transmit mode, but can instead be selectively turned on and off in transmit mode. (Refer to...) Figure 12 Example describing the first data TDAT, the enable signal EN, and the switch control signal SCC.

[0099] Figure 9 It is shown that it includes Figure 8 A block diagram of an example noise reduction circuit in a transceiver. Figure 10A and Figure 10B It is used to describe Figure 9 A diagram of the noise reduction circuit.

[0100] Reference Figure 9 , Figure 10A and Figure 10B The noise reduction circuit 210a may include a buffer circuit 212. For ease of illustration, a first mixer 220, a first amplifier 230, and a switching circuit 262 on the transmitter side that operate in conjunction with the noise reduction circuit 210a are shown together.

[0101] The buffer circuit 212 can generate a switch control signal SCC based on the enable signal EN, and can be implemented as an LPFC with low-pass filter characteristics. For example, the buffer circuit 212 may include multiple inverters INV connected in series. For example, the relationship between the frequency f and the transfer function H of the buffer circuit 212 can be as follows: Figure 10A The implementation shown is illustrated.

[0102] The switching circuit 262 can be implemented as a high-pass filter (HPFC). For example, the relationship between the frequency f and the transfer function H of the switching circuit 262 can be as follows: Figure 10B The implementation shown is illustrated.

[0103] Figure 11 It is shown Figure 9 A diagram illustrating examples of buffer circuits and switching circuits.

[0104] Reference Figure 11The buffer circuit 212a may include multiple inverters INV21 and INV22. For ease of illustration, only two inverters INV21 and INV22 located near the switching circuit 262a are shown, but the example embodiment is not limited thereto.

[0105] The inverter INV21 located closest to the switching circuit 262a may include transistors PT1 and NT1, as well as resistors HR11 and HR12.

[0106] Transistor PT1 can be connected between the power supply voltage and the first node N1 of the output switch control signal SCC. Transistor NT1 can be connected between the first node N1 and ground. The gates (or gate electrodes) of transistors PT1 and NT1 can be connected to the second node N2. For example, transistor PT1 can be a p-type metal-oxide-semiconductor (PMOS) transistor, and transistor NT1 can be an n-type metal-oxide-semiconductor (NMOS) transistor.

[0107] Resistor HR11 can be connected between the body of transistor PT1 and the power supply voltage. Resistor HR12 can be connected between the body of transistor NT1 and the ground voltage. The body separation structure of transistor PT1, where the body is separated from the power supply voltage, can be achieved by resistor HR11, and the body separation structure of transistor NT1, where the body is separated from the ground voltage, can be achieved by resistor HR12. Each of resistors HR11 and HR12 can be referred to as a choke resistor.

[0108] As described above, when inverters INV21 and INV22 are implemented in a separate body structure, buffer circuit 212a can have the characteristics of a low-pass filter (LPFC).

[0109] The inverter INV22, adjacent to inverter INV21, may have a structure substantially the same as that of inverter INV21. For example, inverter INV22 may include transistors PT2 and NT2, and resistors HR21 and HR22. Transistor PT2 may be connected between the power supply voltage and the second node N2. Transistor NT2 may be connected between the second node N2 and the ground voltage. The gates of transistors PT2 and NT2 may be connected to a third node N3 that receives the enable signal EN. Resistor HR21 may be connected between the body of transistor PT2 and the power supply voltage. Resistor HR22 may be connected between the body of transistor NT2 and the ground voltage.

[0110] Switching circuit 262a may include transistor NT3 and resistor (LR). Transistor NT3 may be connected between the output of first amplifier 230 and I / O port PT. Resistor LR may be connected between first node N1 and the gate of transistor NT3. Resistor LR may also be referred to as a choke resistor.

[0111] In some example embodiments, each of resistors HR11 and HR12 may have a relatively large resistance, and resistor LR may have a relatively small resistance. For example, the resistance of resistor HR11 and the resistance of resistor HR12 may be greater than a reference resistance, and the resistance of resistor LR may be less than a reference resistance. For example, resistors HR11 and HR12 may be implemented as high-Z choke resistors, and resistor LR may be implemented as a low-Z choke resistor.

[0112] As described above, when inverters INV21 and INV22 are implemented in a body-separated structure, and when the resistor LR connected to the gate of transistor NT3 is implemented as a low-Z choke resistor, the switching circuit 262a can have the characteristics of a high-pass filter, HPFC.

[0113] Conventionally, to minimize losses in transistors included in switching circuits, gain boosts are designed by connecting high-Z choke resistors with relatively large resistances to the transistor's gate, source, and body. However, there is a problem that makes it difficult to turn the transistor on and off because there is no frequency response when turning it on and off.

[0114] In the transceiver according to the example embodiment, a resistor LR, implemented as a low-Z choke resistor, can be used to facilitate the turn-on and turn-off of transistor NT3, thereby reducing the resistance of the choke resistor connected to the gate of transistor NT3. However, when the low-Z choke resistor LR is used, there may be a problem of performance degradation or deterioration of transistor NT3. To solve this problem, resistors HR11 and HR12, implemented as high-Z choke resistors, can be used and connected to the bodies of transistors PT1 and NT1 included in inverter INV21, which generates a switching control signal SCC for gate control of transistor NT3. Therefore, the high-Z choke is visible from the gate of transistor NT3 in AC direction, and simultaneously, the turn-on / turn-off operation of the gate of transistor NT3 can be normally performed using the switching control signal SCC.

[0115] However, the example embodiments are not limited thereto. For example, the buffer circuit 212a can be implemented using at least one of various structures to have the characteristics of a low-pass filter (LPFC), and the switching circuit 262a can be implemented using at least one of various structures to have the characteristics of a high-pass filter (HPFC).

[0116] Figure 12 , Figure 13 and Figure 14 It is used to describe Figure 9 A diagram illustrating the operation of the noise reduction circuit.

[0117] Reference Figure 9 and Figure 12This illustrates an example of first data TDAT, clock signal LO, enable signal EN, switch control signal SCC, amplified first signal ATS, and signal ATS' corresponding to the amplified first signal ATS, according to an example embodiment. For brevity, the symbols TDAT and ATS' are omitted. Figure 4 The description is repetitive or overlapping.

[0118] The first data TDAT may include the activation time interval T1 and the deactivation time interval T2.

[0119] The clock signal LO can switch between the activation time interval T1 and the deactivation time interval T2 of the first data TDAT.

[0120] The enable signal EN can be activated during the activation time interval T1 of the first data TDAT, and can be deactivated during the deactivation time interval T2 of the first data TDAT.

[0121] The switch control signal SCC can have a low-pass filtered waveform of the enable signal EN.

[0122] The amplified first signal ATS output from the first amplifier 230 may have an up-converted waveform in which the first data TDAT and the clock signal LO are mixed during the activation time interval T1 of the first data TDAT, and may have relatively large or high noise because the clock signal LO switches continuously during the deactivation time interval T2 of the first data TDAT and various noises appear inside the transmitter.

[0123] In contrast, the signal ATS' generated by the buffer circuit 212 with the characteristics of LPFC (low-pass filter) and the switching circuit 262 with the characteristics of HPFC (high-pass filter) and the signal corresponding to the amplified first signal ATS can have relatively small or low noise during the deactivation time interval T2 of the first data TDAT.

[0124] In the transceiver according to the example embodiment, the signal ATS' can be output through a switching circuit 262 with high-pass filter characteristics HPFC, and the buffer circuit 212 for driving the switching circuit 262 to turn on / off can have low-pass filter characteristics LPFC in the direction observed from the switching circuit 262. Furthermore, to facilitate turning the switching circuit 262 on and off, the resistance of the choke resistor LR connected to the gate of the transistor NT3 included in the switching circuit 262 should be reduced, and additionally, the path observed from the low-pass filter should have an AC response. Therefore, when there is no data or signal (e.g., during the deactivation time interval T2 of the first data TDAT), noise and leakage transmitted to the receiver side can be reduced. For example, as... Figure 11As shown, transistor NT3 can be implemented using a low-Z choke resistor LR, and inverters INV21 and INV22 can be implemented using high-Z choke resistors HR11 and HR12 in a body-separated structure. Such a configuration can be referred to as a low-Z choke switching RF switch with body boost inverters.

[0125] Reference Figure 13 and Figure 14 This illustrates the importance of the bulk separation structure of inverters INV21 and INV22. Figure 13 and Figure 14 In the diagram, the vertical axis represents voltage (V) (unit: volt (V)) and the horizontal axis represents time (unit: picosecond (Ps)).

[0126] like Figure 13 As shown, when the high-Z choke resistors HR11 and HR12 are not included (e.g., when the inverter is not implemented with a bulk discrete structure), the threshold voltage of the transistors included in the inverter can change significantly, and the diodes of the transistors included in the inverter can turn on as the output swing increases. Therefore, there may be problems with a decrease in the DC operating point of the inverter and degradation or deterioration of the characteristics of the switching circuit.

[0127] like Figure 14 As shown, when the high-Z choke resistors HR11 and HR12 are included according to the example embodiment (e.g., when inverters INV21 and INV22 are implemented with a bulk-separated structure according to the example embodiment), the diodes of the transistors included in inverters INV21 and INV22 may not conduct even if the output swing increases. Therefore, the DC operating point of inverters INV21 and INV22 can remain constant.

[0128] Figure 15 It is shown Figure 9 The diagram shows examples of buffer circuits and switching circuits. For simplicity, the symbols and symbols are omitted. Figure 11 The description is repetitive or overlapping.

[0129] Reference Figure 15 The buffer circuit 212b may include multiple inverters INV21, INV22, INV23 and INV24.

[0130] Inverters INV21 and INV22 located near switch circuit 262a can be referenced. Figure 11The described body-separated structure is used to implement this. However, inverters INV23 and INV24, located away from the switching circuit 262a, can be implemented without a body-separated structure. For example, although not shown in detail, each of inverters INV23 and INV24 may include two transistors (e.g., PMOS and NMOS transistors) connected between the power supply voltage and ground voltage, and the body of each of the two transistors may be connected to either the power supply voltage or ground voltage without additional resistors.

[0131] However, the example embodiments are not limited thereto, and in addition to the buffer circuit 212, the noise reduction circuit 210 may also include at least one of other components necessary for the operation of the transceiver.

[0132] Figure 16 It is shown Figure 1 A block diagram of an example transceiver. For brevity, the symbols and symbols are omitted. Figure 6 and Figure 8 The description is repetitive or overlapping.

[0133] Reference Figure 16 The transceiver 200a includes a noise reduction circuit 210, a first mixer 220, a first amplifier 230, a second amplifier 240, an I / O port PT, and a switching circuit 260. The transceiver 200a may also include a second mixer 250, a transmitting circuit 270, an output circuit 275, an input circuit 280, and a receiving circuit 285.

[0134] The transmitting circuit 270 can be located at the front end of the first amplifier 230, and can be connected with... Figure 6 The transmitting circuit is basically the same as that of the 160.

[0135] The output circuit 275 can be located at the rear end of the first amplifier 230, and in addition to being combined with the switching circuit 260, the output circuit 275 can also be combined with... Figure 6 The output circuit is basically the same as that of 165.

[0136] The input circuit 280 can be located at the front end of the second amplifier 240, and can be connected with... Figure 6 The input circuit is basically the same as that of 170.

[0137] The receiving circuit 285 can be located at the rear end of the second amplifier 240, and can be connected with... Figure 6 The receiving circuit is basically the same as that of 175.

[0138] Figure 17 It is shown Figure 1 A block diagram of an example transceiver.

[0139] Reference Figure 17The transceiver 300 includes a noise reduction circuit 310, a first mixer 320, a first amplifier 330, a second amplifier 340, an I / O port PT, and a switching circuit 360. The transceiver 300 may also include a second mixer 350.

[0140] The noise reduction circuit 310 and the I / O port PT can be respectively connected to Figure 1 The noise reduction circuit 20 corresponds to the I / O port PT. The first mixer 320, the first amplifier 330, and the switching circuit 360 may be included. Figure 1 The transmitter 30. The second amplifier 340 and the second mixer 350 may be included in... Figure 1 The receiver 40 is included. The transceiver 300 can be combined... Figure 2 transceiver 100 and Figure 8 This is achieved using a transceiver 200. For simplicity, the following will be omitted: Figure 1 , Figure 2 and Figure 8 The description is repetitive or overlapping.

[0141] The noise reduction circuit 310 generates a first clock signal LO1 and a switch control signal SCC based on the enable signal EN. The first mixer (320) can be connected to... Figure 2 The first mixer 120 is basically the same. The first amplifier 330 can be used with... Figure 2 and Figure 8 The first amplifiers 130 and 230 are basically the same. The second amplifier 340 can be used with... Figure 2 and Figure 8 The second amplifiers 140 and 240 are basically the same. The second mixer 350 can be used with... Figure 2 The second mixer 150 is basically the same. The switching circuit 360 can be used with... Figure 8 The switching circuit is basically the same as that of the 260.

[0142] Figure 18 It is shown that it includes Figure 17 A block diagram of an example noise reduction circuit in a transceiver.

[0143] Reference Figure 18 The noise reduction circuit 310a may include an AND gate 312 and a buffer circuit 314.

[0144] AND gate 312 can be ANDed with Figure 3 The AND gate 112 is basically the same. The buffer circuit 314 can be connected to... Figure 9 The buffer circuit 212 is basically the same. In some example embodiments, such as reference Figure 5 The noise reduction circuit 310a may further include a buffer circuit connected to the rear end of the AND gate 112. In some example embodiments, the buffer circuit 314 may be as follows: Figure 11 and Figure 15 The implementation shown is illustrated.

[0145] Figure 19 This is a block diagram illustrating a semiconductor chip according to an example embodiment.

[0146] Reference Figure 19 According to some embodiments, the semiconductor chip 500 includes a processor 510 and a transceiver 520.

[0147] In some example embodiments, the semiconductor chip 500 may be included in an electronic device (e.g., a communication device). In some example embodiments, the processor 510 and transceiver 520 may be implemented as a single IC (or chip or module). For example, the processor 510 and transceiver 520 may be implemented as a system-on-a-chip or as a semiconductor module comprising multiple semiconductor chips.

[0148] Processor 510 generates a first data TDAT to be sent to an external device, and generates an enable signal EN that is activated during the activation time interval of the first data TDAT and deactivated during the deactivation time interval of the first data TDAT. For example, processor 510 can perform various signal processing operations, such as modulation / demodulation, encoding / decoding, channel estimation, etc. Processor 510 may be referred to as a communication processor, modem, etc. Furthermore, processor 510 can transmit and receive baseband signals with transceiver 520 and may be referred to as a baseband processor. Processor 510 may be implemented as, for example, an integrated circuit, and may be a standalone semiconductor chip or package, or may be part of a semiconductor chip, semiconductor package, or semiconductor module that also includes transceiver 520.

[0149] Transceiver 520 receives first data TDAT and an enable signal (EN), and operates based on the first data TDAT and the enable signal EN. For example, transceiver 520 may generate a first signal to be transmitted to an external device based on the first data TDAT and the enable signal EN.

[0150] Transceiver 520 can be based on reference Figures 1 to 18 The transceiver described is an example embodiment. For example, in some embodiments, transceiver 520 includes noise reduction circuitry 522, a transmitter 524, a receiver 526, and an I / O port PT. Transceiver 520 may have a configuration in which the I / O port PT is shared by the transmitter 524 and the receiver 526, and may include noise reduction circuitry 522 that generates a noise reduction control signal NRCON based on an enable signal EN synchronized with first data TDAT.

[0151] For example, as referenced Figures 2 to 7The noise reduction control signal NRCON may include a first clock signal LO1 or a mixer on / off signal MOF, and the transceiver 520 may include a switch-and-gate mixer. For example, as shown in reference... Figures 8 to 16 The noise reduction control signal NRCON may include a switch control signal SCC, and the transceiver 520 may include a low-Z choke switching RF switch with a bulk boost inverter. For example, as shown in reference... Figure 17 and Figure 18 The noise reduction control signal NRCON may include both a first clock signal LO1 and a switch control signal SCC. Transceiver 520 may selectively turn on and off at least one of the mixer and switching circuits included in transmitter 524 based on the enable signal EN. Therefore, noise from transmitter 524 can be efficiently prevented from being transmitted to receiver 526, and transceiver 520 and the semiconductor chip 500 including transceiver 520 may have relatively improved or enhanced performance.

[0152] Transceiver 520 can receive a second signal from an external device and can generate second data RDAT based on the second signal. Processor 510 can receive the second data RDAT and can perform data processing on the second data RDAT.

[0153] In some example embodiments, in transmit mode, processor 510 can provide first data TDAT, and transceiver 520 can receive the first data TDAT and generate and output a first signal. In receive mode, transceiver 520 can receive a second signal and generate second data RDAT, and processor 510 can receive the second data RDAT. When transmitter 524 and receiver 526 are enabled together, transceiver 520 can prevent noise generated by transmitter 524 from being transmitted to receiver 526 through I / O port PT based on the noise reduction control signal NRCON generated from noise reduction circuit 522.

[0154] Figure 20 and Figure 21 This is a flowchart illustrating a method for sending data according to an example embodiment.

[0155] Reference Figure 20 and Figure 21 The method of transmitting data according to the example embodiment may be performed by a transceiver 10 according to the example embodiment, wherein the I / O port PT is shared by the transmitter 30 and the receiver 40, and / or may be performed by a semiconductor chip 500 according to the example embodiment that includes the transceiver according to the example embodiment.

[0156] like Figure 20As shown, in the method for transmitting data according to the example embodiment, an enable signal EN that is activated during the activation time interval of the first data TDAT and deactivated during the deactivation time interval of the first data TDAT is received (operation S110). Based on the enable signal EN and the second clock signal LO2, a first clock signal LO1 that is switched during the activation time interval of the first data TDAT and deactivated during the deactivation time interval of the first data TDAT is generated (operation S120). A first signal TS is generated based on the first data TDAT and the first clock signal LO1 (operation S130). The first signal TS is amplified, and the amplified first signal ATS is output (operation S140). For example, Figure 20 The method can be referenced Figures 2 to 7 The transceiver and / or the semiconductor chip including the transceiver are described. In some example embodiments, operation S110 may be omitted, and the mixer on / off signal MOF may be generated in operation S120 instead of the first clock signal LO1.

[0157] like Figure 21 As shown, in the method for transmitting data according to the example embodiment, an enable signal EN that is activated during the activation time interval of the first data TDAT and deactivated during the deactivation time interval of the first data TDAT is received (operation S210). Based on the enable signal EN, a switch control signal SCC that is activated during the activation time interval of the first data TDAT and deactivated during the deactivation time interval of the first data TDAT is generated (operation S220). A first signal TS is generated based on the first data TDAT and the first clock signal LO (operation S230). The first signal TS is amplified to generate an amplified first signal ATS, and a signal ATS' corresponding to the amplified first signal ATS is output based on the switch control signal SCC (operation S240). For example, Figure 21 The method can be referenced Figures 8 to 16 The transceiver and / or semiconductor chip including the transceiver are performed. In some example embodiments, operation S210 may be omitted.

[0158] In some example embodiments, it can be achieved through combination Figure 20 Methods and Figure 21 The method is implemented to send data according to the example embodiment. In this example, by combining... Figure 20 and Figure 21 The method implementation can be referenced Figure 17 and Figure 18 The transceiver described and / or the semiconductor chip including the transceiver are implemented.

[0159] As those skilled in the art will understand, the exemplary embodiments can be implemented as systems, methods, computer program products having computer-readable program code implemented thereon, and / or computer program products implemented in one or more computer-readable media. The computer-readable program code can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be any tangible medium that can contain or store a program used by or in conjunction with an instruction execution system, device, or apparatus. For example, a computer-readable medium can be a non-transitory computer-readable medium.

[0160] Figure 22 This is a block diagram illustrating an electronic device in a network environment according to an example embodiment.

[0161] Reference Figure 22 In network environment 1300, electronic device 1301 can communicate with electronic device 1302 via a first network 1398 (e.g., a short-range wireless communication network), or with electronic device 1304 or server 1308 via a second network 1399 (e.g., a long-range wireless communication network). For example, electronic device 1301 can communicate with electronic device 1304 via server 1308. For example, electronic device 1301 may include processor 1320, memory 1330, input device 1350, sound output device 1355, display device 1360, audio module 1370, sensor module 1376, interface 1377, haptic module 1379, camera module 1380, power management module 1388, battery 1389, communication module 1390, subscriber identification module (SIM) 1396, and / or antenna module 1397. In some example embodiments, at least one of the components (e.g., display device 1360 or camera module 1380) may be omitted from electronic device 1301, or one or more other components may be added to electronic device 1301. In some example embodiments, some of the components may be implemented as a single integrated circuit. For example, sensor module 1376 (e.g., fingerprint sensor, iris sensor, or illuminance sensor) may be implemented as embedded in display device 1360 (e.g., display).

[0162] Processor 1320 may execute software (e.g., program 1340) for controlling at least one other component (e.g., hardware or software component) of electronic device 1301 associated with processor 1320, and may perform various data processing or calculations. For example, as at least part of data processing or calculation, processor 1320 may load commands or data received from another component (e.g., sensor module 1376 or communication module 1390) into volatile memory 1332, process the commands or data stored in volatile memory 1332, and store the resulting data in non-volatile memory 1334. In some example embodiments, processor 1320 may include a main processor 1321 (e.g., a central processing unit (CPU) or application processor (AP)) and an auxiliary processor 1323 (e.g., a graphics processing unit (GPU), image signal processor (ISP), sensor hub processor, or communication processor (CP)), the auxiliary processor 1323 may operate independently of main processor 1321 or operate in conjunction with main processor 1321. Additionally or optionally, the auxiliary processor 1323 may be adapted to consume less power than the main processor 1321, or may be dedicated to a specific function. The auxiliary processor 1323 may be implemented separately from the main processor 1321, or may be implemented as part of the main processor 1321.

[0163] When the main processor 1321 is inactive (e.g., in sleep mode), the auxiliary processor 1323 may, in place of the main processor 1321, control at least some of the functions or states associated with at least one component of the electronic device 1301 (e.g., display device 1360, sensor module 1376, or communication module 1390). Alternatively, when the main processor 1321 is active (e.g., executing an application), the auxiliary processor 1323 may, together with the main processor 1321, control at least some of the functions or states associated with at least one component of the electronic device 1301 (e.g., display device 1360, sensor module 1376, or communication module 1390). In some example embodiments, the auxiliary processor 1323 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., camera module 1380 or communication module 1390) functionally associated with the auxiliary processor 1323.

[0164] Memory 1330 may store various data used by at least one component of electronic device 1301 (e.g., processor 1320 or sensor module 1376). The various data may include, for example, software (e.g., program 1340) and input or output data for commands associated therewith. Memory 1330 may include volatile memory 1332 and / or non-volatile memory 1334. Memory 1330 (e.g., non-volatile memory 1334) may include internal memory 1336 and external memory 1338.

[0165] The program 1340 may be stored as software in the memory 1330 and may include, for example, an operating system (OS) 1342, middleware 1344 and / or application 1346.

[0166] Input device 1350 can receive commands or data from outside electronic device 1301 (e.g., a user) that will be used by other components of electronic device 1301 (e.g., processor 1320). Input device 1350 may include, for example, a microphone, mouse, keyboard, or digital pen (e.g., stylus).

[0167] The sound output device 1355 can output sound signals to the outside of the electronic device 1301. The sound output device 1355 may include, for example, a speaker or a receiver. The speaker can be used for general purposes (such as playing multimedia or playing recordings), and the receiver can be used for incoming calls. In some example embodiments, the receiver may be implemented separately from the speaker or may be implemented as part of the speaker.

[0168] Display device 1360 can visually provide information to the outside of electronic device 1301 (e.g., to a user). Display device 1360 may include, for example, a display, a holographic device, or a projector, and control circuitry for controlling a corresponding one of the display, holographic device, and projector. In some example embodiments, display device 1360 may include touch circuitry adapted to detect touch or sensor circuitry adapted to measure the intensity of the force caused by touch (e.g., a pressure sensor).

[0169] Audio module 1370 can convert sound into electrical signals and vice versa. In some example embodiments, audio module 1370 can obtain sound via input device 1350, or output sound via sound output device 1355 or headphones of an external electronic device (e.g., electronic device 1302) directly (e.g., wired) or wirelessly connected to electronic device 1301.

[0170] Sensor module 1376 can detect the operating state of electronic device 1301 (e.g., power or temperature) or the environmental state outside electronic device 1301 (e.g., user state), and then generate an electrical signal or data value corresponding to the detected state. In some example embodiments, sensor module 1376 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an accelerometer, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, and / or an illuminance sensor, but the example embodiments are not limited thereto.

[0171] Interface 1377 may support one or more specified protocols for direct (e.g., wired) or wireless connection of electronic device 1301 to external electronic device (e.g., electronic device 1302). In some example embodiments, interface 1377 may include, for example, a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital Card (SD) interface, and / or an audio interface, but the example embodiments are not limited thereto.

[0172] Connection terminal 1378 may include a connector via which electronic device 1301 can be physically connected to an external electronic device (e.g., electronic device 1302). In some example embodiments, connection terminal 1378 may include, for example, an HDMI connector, a USB connector, an SD card connector, and / or an audio connector (e.g., a headphone connector), but the example embodiments are not limited thereto.

[0173] The haptic module 1379 can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that can be recognized by a user through his tactile or kinesthetic senses. In some example embodiments, the haptic module 1379 may include, for example, a motor, a piezoelectric element, and / or an electrical stimulator.

[0174] Camera module 1380 can capture still or moving images. In some example embodiments, camera module 1380 may include one or more lenses, an image sensor, an image signal processor, and / or a flash.

[0175] The power management module 1388 manages the power supplied to the electronic device 1301. In some example embodiments, the power management module 1388 may be implemented as at least part of, for example, a power management integrated circuit (PMIC).

[0176] Battery 1389 may supply power to at least one component of electronic device 1301. In some exemplary embodiments, battery 1389 may include, for example, a non-rechargeable primary cell, a rechargeable secondary cell, or a fuel cell.

[0177] Communication module 1390 can support the establishment of a direct (e.g., wired) or wireless communication channel between electronic device 1301 and external electronic devices (e.g., electronic device 1302, electronic device 1304, or server 1308), and perform communication via the established communication channel. Communication module 1390 may include one or more communication processors that can operate independently of processor 1320 (e.g., application processor (AP)) and support direct (e.g., wired) or wireless communication. In some example embodiments, communication module 1390 may include wireless communication module 1392 (e.g., cellular communication module, short-range wireless communication module, or Global Navigation Satellite System (GNSS) communication module) and / or wired communication module 1394 (e.g., local area network (LAN) communication module or power line communication (PLC) module). One of these communication modules may communicate with an external electronic device via a first network 1398 (e.g., a short-range communication network such as Bluetooth™, Wi-Fi Direct, or Infrared Data Association (IrDA)) or a second network 1399 (e.g., a long-range communication network such as a cellular network, the Internet, or a computer network such as a LAN or a wide area network (WAN)). These various types of communication modules may be implemented as a single component (e.g., a single chip) or as multiple components that are separate from each other (e.g., multiple chips). The wireless communication module 1392 may use user information (e.g., the International Mobile Subscriber Identity (IMSI)) stored in the user identification module 1396 to identify and authenticate the electronic device 1301 in the communication network (e.g., the first network 1398 or the second network 1399).

[0178] Antenna module 1397 can transmit or receive signals or power to or from the exterior of electronic device 1301 (e.g., external electronic device). In some example embodiments, antenna module 1397 may include an antenna comprising a radiating element composed of conductive material or conductive patterns formed in or on a substrate (e.g., a PCB). In some example embodiments, antenna module 1397 may include multiple antennas. In some example embodiments, at least one antenna suitable for a communication scheme used in a communication network (such as a first network 1398 or a second network 1399) may be selected from multiple antennas, for example by communication module 1390 (e.g., wireless communication module 1392). Signals or power can then be transmitted or received between communication module 1390 and external electronic device via the selected at least one antenna. In some example embodiments, additional components besides the radiating element (e.g., a radio frequency integrated circuit (RFIC)) may be additionally incorporated into antenna module 1397.

[0179] In some example embodiments, communication module 1390 may include a transceiver TRX according to an example embodiment. Part or all of processor 1320 may be a processor included in a semiconductor chip according to an example embodiment. In some example embodiments, transceiver TRX and part or all of processor 1320 may be implemented as separate chips or a single chip. Antenna module 1397 may include an antenna connected to transceiver TRX. Similarly, according to example embodiments, other electronic devices 1302 and 1304 may also include transceivers, processors, antennas, etc. For example, each electronic device may be a user equipment (UE) or a base station.

[0180] The example embodiments are applicable to a variety of communication devices and systems, as well as electronic devices and systems that include communication devices and systems. For example, the example embodiments are applicable to systems such as personal computers (PCs), mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, automobiles, and other devices or systems that can communicate using transceivers.

[0181] The foregoing description is illustrative of exemplary embodiments and should not be construed as limiting them. While some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the claims. It will be understood that the foregoing description is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims.

Claims

1. A transceiver, comprising: The first mixer is configured to receive first data and a first clock signal, and generate a first signal to be sent to an external device based on the first data and the first clock signal. The noise reduction circuit is configured to provide a first clock signal to a first mixer. The first amplifier is configured to amplify the first signal received from the first mixer; The second amplifier is configured to amplify a second signal received from an external device. as well as The input / output port is shared by the first and second amplifiers and is configured to output the amplified first signal and receive the second signal. The noise reduction circuit is configured to activate the first clock signal during the activation time interval of the first data and deactivate the first clock signal during the deactivation time interval of the first data.

2. The transceiver as described in claim 1, in, The first clock signal is configured to switch during the activation time interval of the first data and deactivate during the deactivation time interval of the first data. The first mixer is configured to turn on during the activation time interval of the first data and turn off during the deactivation time interval of the first data.

3. The transceiver as described in claim 1, in, The noise reduction circuit is configured to: receive an enable signal and generate a first clock signal based on the enable signal, and The enable signal is active during the activation time interval of the first data and deactivated during the deactivation time interval of the first data.

4. The transceiver as claimed in claim 3, wherein, The noise reduction circuit includes: The AND gate is configured to generate the first clock signal by performing an AND operation on the enable signal and the second clock signal.

5. The transceiver as claimed in claim 4, wherein, The second clock signal is configured to switch continuously regardless of the enable signal.

6. The transceiver as claimed in claim 4, wherein, The noise reduction circuit also includes: A buffer circuit is located between the AND gate and the first mixer.

7. The transceiver as claimed in any one of claims 1 to 5, further comprising: A switching circuit is located between the first amplifier and the input / output port and is configured to be turned on and off based on a switching control signal.

8. The transceiver as claimed in claim 7, wherein, The noise reduction circuit is configured to also generate a switch control signal based on the enable signal.

9. The transceiver as claimed in claim 8, wherein, The noise reduction circuit includes: The buffer circuit is configured to generate a switch control signal based on an enable signal and has the characteristics of a low-pass filter.

10. The transceiver as claimed in claim 9, wherein, The switching circuit is configured to have the characteristics of a high-pass filter.

11. A transceiver, comprising: The first mixer is configured to receive first data and a first clock signal, and generate a first signal to be sent to an external device based on the first data and the first clock signal. The first amplifier is configured to amplify the first signal received from the first mixer; The second amplifier is configured to amplify a second signal received from an external device. The input / output port is shared by the first amplifier and the second amplifier, and is configured to output the amplified first signal and receive the second signal; A switching circuit, located between the first amplifier and the input / output port, is configured to be turned on and off based on a switching control signal; and The noise reduction circuit is configured to provide a switching control signal to the switching circuit, and The noise reduction circuit is configured to output a switch control signal with an active state during the active time interval of the first data, and to output a switch control signal with a deactivated state during the deactivated time interval of the first data.

12. The transceiver of claim 11, wherein, The switching circuit is configured to turn on during the activation time interval of the first data and turn off during the deactivation time interval of the first data.

13. The transceiver as claimed in claim 11, in, The noise reduction circuit is configured to: receive an enable signal and generate a switch control signal based on the enable signal, and The enable signal is active during the activation time interval of the first data and deactivated during the deactivation time interval of the first data.

14. The transceiver of claim 13, wherein, The noise reduction circuit includes: The buffer circuit is configured to generate a switch control signal based on an enable signal and has the characteristics of a low-pass filter.

15. The transceiver as claimed in claim 14, in, The buffer circuit includes multiple inverters connected in series. The first inverter among the plurality of inverters, located closest to the switching circuit, includes: The first transistor is connected between the power supply voltage and the first node of the output switch control signal; The second transistor is connected between the first node and the ground voltage; A first resistor is connected between the body of the first transistor and the power supply voltage; and The second resistor is connected between the body voltage of the second transistor and the ground voltage.

16. The transceiver of claim 15, wherein, The switching circuit includes: The third transistor is connected between the output and input / output ports of the first amplifier; and The third resistor is connected between the first node and the gate of the third transistor.

17. The transceiver as claimed in claim 16, in, The resistance of the first resistor and the resistance of the second resistor are greater than the reference resistance, and The resistance of the third resistor is less than that of the reference resistor.

18. The transceiver of claim 14, wherein, The switching circuit is configured to have the characteristics of a high-pass filter.

19. The transceiver as claimed in any one of claims 11 to 18, wherein, The noise reduction circuit is also configured to generate a first clock signal based on an enable signal.

20. An electronic device comprising: The antenna is configured to transmit a first signal to an external device or receive a second signal from an external device. The processor is configured to: generate first data corresponding to a first signal, generate an enable signal, and receive second data corresponding to a second signal, wherein the enable signal is activated during the activation time interval of the first data and deactivated during the deactivation time interval of the first data; as well as The transceiver is configured to generate a first signal based on first data and an enable signal, and to generate second data based on a second signal. The transceiver includes: The noise reduction circuit is configured to generate a first clock signal based on an enable signal and a second clock signal, and to generate a switch control signal based on the enable signal. The first mixer is configured to generate a first signal based on first data and a first clock signal; The power amplifier is configured to amplify the first signal; A low-noise amplifier is configured to amplify the second signal; The second mixer is configured to generate second data based on the amplified second signal and the second clock signal; The input / output ports are shared by the power amplifier and the low-noise amplifier, and are connected to the antenna; and A switching circuit is located between the power amplifier and the input / output port and is configured to be turned on and off based on a switching control signal.

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