Semiconductor structure and preparation method of semiconductor structure

Abstract

The invention provides a semiconductor structure and a preparation method of the semiconductor structure, and relates to the technical field of semiconductors. The semiconductor structure comprises a substrate, the substrate is internally provided with a plurality of active columns which are arranged at intervals along a first direction and a second direction, and the active columns extend along a third direction; a plurality of first grooves extending in the first direction and a plurality of second grooves extending in the second direction are formed in the substrate, and the active columns are isolated by the first grooves and the second grooves; the first direction and the second direction intersect and are both perpendicular to the third direction; the back gate structure is located in the first groove and extends in the first direction; wherein the depth of the first groove in the third direction is greater than that of the second groove in the third direction, and the bottom surface of the back gate structure is lower than that of the second groove. According to the embodiment of the invention, the electrical performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of volatile memory. It consists of multiple memory cells, each of which mainly includes a transistor and a capacitor. The memory cells are electrically connected to each other through word lines (WL) and bit lines (BL).

[0003] With the development of semiconductor technology, an architectural scheme has been proposed to replace horizontal transistors with vertical channel transistors. This type of DRAM forms vertically extending active pillars on the substrate, forms a surrounding gate on the outside of the active pillars, and forms buried bit lines and buried word lines.

[0004] However, DRAM with vertical transistors still faces many problems, and electrical issues have become a technical problem that urgently needs to be solved.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] This disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure can improve the threshold voltage controllability and current suppression capability of vertical transistors, as well as reduce the coupling capacitance between bit lines and transistors, thereby improving the electrical performance of the semiconductor structure.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0008] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0009] The substrate has a plurality of active pillars arranged at intervals along a first direction and a second direction, and the active pillars all extend along a third direction; and the substrate has a plurality of first trenches extending along the first direction and a plurality of second trenches extending along the second direction, the first trenches and the second trenches isolating the active pillars; the first direction and the second direction intersect and are both perpendicular to the third direction.

[0010] A back grid structure, wherein the back grid structure is located within the first groove and extends along the first direction;

[0011] In this configuration, the depth of the first trench in the third direction is greater than the depth of the second trench in the third direction, and the bottom surface of the back grid structure is lower than the bottom surface of the second trench.

[0012] In one embodiment, a word line structure is further provided in the substrate, the word line structure surrounds the source pillar, adjacent word line structures along the second direction are in contact with each other, and adjacent word line structures along the first direction are insulated from each other; the word line structure in the first trench is above the back gate structure, and the word line structure is isolated from the back gate structure.

[0013] In one embodiment, the word line structure includes a first work function conductive structure and a second work function conductive structure, with the second work function conductive structure above the first work function conductive structure.

[0014] In one embodiment, the work function of the back gate structure is less than the work function of the first work function conductive structure.

[0015] In one embodiment, the work function of the first work function conductive structure is greater than the work function of the second work function conductive structure.

[0016] In one embodiment, the ratio of the height of the first work function conductive structure in the third direction to the height of the second work function conductive structure in the third direction is 1.2-5:1.

[0017] In one embodiment, a bit line structure is further disposed in the substrate. The bit line structure is located on the side of the substrate away from the extension direction of the active pillar. The bit line structure extends along a first direction, and adjacent bit line structures along a second direction are insulated from each other.

[0018] In one embodiment, the orthographic projection of the back gate structure along the second direction partially overlaps with the orthographic projection of the bit line structure along the second direction.

[0019] In one embodiment, the back gate structure is isolated from the active post by a first insulating structure.

[0020] According to another aspect of this disclosure, a method for fabricating the above-described semiconductor structure is provided, comprising:

[0021] A substrate is provided, and a plurality of first trenches extending along a first direction are formed within the substrate;

[0022] A first insulating structure, a back grid structure, and a sacrificial structure extending in a first direction are sequentially formed within the first trench;

[0023] Multiple second trenches extending along a second direction are formed in the substrate, and multiple active pillars are simultaneously formed at intervals along the first and second directions, with each active pillar extending along a third direction; the active pillars are isolated from each other through the first and second trenches.

[0024] A second insulating structure and an isolation structure extending in a second direction are formed in the second trench, with the second insulating structure located between the active post and the isolation structure;

[0025] In this configuration, the depth of the first trench in the third direction is greater than the depth of the second trench in the third direction, and the bottom surface of the back grid structure is lower than the bottom surface of the second trench.

[0026] In one embodiment, the fabrication method further includes removing the sacrificial structure and part of the first insulating structure in the first trench to expose the back gate structure and form a third trench.

[0027] At the same time, part of the second insulation structure in the second trench is removed to form the fourth trench;

[0028] A third insulation structure and a word line structure are formed in the third and fourth trenches; the word line structure is isolated from the active post through the third insulation structure.

[0029] In one embodiment, the bottom surface of the fourth groove is higher than the bottom surface of the isolation structure, and the bottom surface of the word line structure is higher than the bottom surface of the isolation structure.

[0030] In one embodiment, a third insulating structure and a word line structure are formed within the third and fourth trenches, including,

[0031] A third insulating structure is formed conformally within the third and fourth trenches;

[0032] The first work function conductive structure and the second work function conductive structure are formed sequentially.

[0033] In one embodiment, the third insulating structure is achieved through a thermal oxidation process.

[0034] In one embodiment, the fabrication method further includes forming a bit line structure on a side of the substrate opposite to the extension direction of the active pillar, the bit line structure extending along a first direction, and adjacent bit line structures along a second direction being mutually insulated.

[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0037] Figure 1A top perspective view of a substrate for a semiconductor structure provided in an embodiment of this disclosure is shown; Figure 2 For the corresponding Figure 1 Cross-sectional views of the semiconductor structure at points aa and cc; Figure 3 For the corresponding Figure 1 Cross-sectional views of another semiconductor structure at points aa and cc; Figure 4 A flowchart illustrating the steps of a method for fabricating a semiconductor structure according to embodiments of this disclosure; Figure 5-18 Cross-sectional views of points aa and cc during the semiconductor structure fabrication process provided in this embodiment of the disclosure; Detailed Implementation

[0038] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0039] Before introducing the semiconductor structure and its preparation method involved in the embodiments of this disclosure, the technical terms involved in the embodiments of this disclosure will be explained first.

[0040] Dynamic hold time (tRET): Dynamic tRET refers to the time a data bit in dynamic random access memory (DRAM) can remain stable without being refreshed. In VCT DRAM, the vertical stacking structure of transistors may affect the stability of capacitors, thus affecting the dynamic hold time.

[0041] Static hold time (tRET): Static tRET refers to the time a data bit can remain stable under static conditions. In VCT DRAM, static hold time can be affected by transistor threshold voltage drift and leakage current.

[0042] Coupling noise: In DRAM, coupling noise typically refers to signal interference caused by the coupling effect between the bit line and the transistor. In VCT DRAM, coupling noise can be even more significant due to the high-density stacking of transistors.

[0043] With the shift from horizontal transistors to vertical channel transistors, semiconductor structures with vertical transistors have encountered problems in dynamic hold time, static hold time, and coupling noise, which urgently need improvement.

[0044] In view of this, the present disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure has a back gate structure disposed in a first groove, and the bottom surface of the back gate structure is lower than the bottom surface of the second groove. The back gate structure can improve the threshold voltage controllability and current leakage suppression capability of the vertical transistor, thereby improving the dynamic hold time and static hold time, while reducing coupling noise, thereby improving the electrical performance of the semiconductor structure.

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] Figure 1 A top perspective view of a substrate for a semiconductor structure provided in an embodiment of this disclosure; Figure 2 For the corresponding Figure 1 Cross-sectional views of the semiconductor structure at points aa and cc; Figure 3 For the corresponding Figure 1 Cross-sectional views of another semiconductor structure at points aa and cc;

[0047] Reference Figure 1 and Figure 2 As shown, in one embodiment, the semiconductor structure 100 may include:

[0048] The substrate 110 has a plurality of active pillars 120 arranged at intervals along a first direction and a second direction, and the active pillars 120 all extend along a third direction; and the substrate 110 has a plurality of first trenches 111 extending along the first direction and a plurality of second trenches 112 extending along the second direction, the first trenches 111 and the second trenches 112 isolating the active pillars 120; the first direction and the second direction intersect and are both perpendicular to the third direction;

[0049] Continue to refer to Figure 1 As shown, for example, the first direction and the second direction can be perpendicular to each other, and the first direction is, for example, Figure 1 The Y direction in the middle, the second direction is, for example, the Y direction. Figure 1 In the X direction, the third direction is, for example, Figure 1The Z-direction in the figure refers to the thickness direction of the substrate 110. In other embodiments, the first and second directions may not be perpendicular; for example, the angle between the first and second directions may be an acute angle. The material of the substrate 110 may be, for example, single-crystal silicon, polycrystalline silicon, amorphous silicon, or silicon-on-insulator (SOI). Additionally, the material of the substrate 110 may include silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. Active pillars 120 within the substrate 110 are arranged in an array at intervals, extending in the thickness direction of the substrate 110, i.e., the Z-direction. The cross-section of the active pillars 120 may be circular, square, or elliptical, etc., to improve the integration density of the semiconductor structure 100, but is not limited thereto. The active pillars 120 are used to form the channel region (not shown), source region (not shown), and drain region (not shown) of a vertical transistor.

[0050] The back gate structure 312 is located within the first groove 111 and is, for example, along the first direction. Figure 1 Extending in the Y direction;

[0051] Among them, the first trench 111 is in a third direction, for example, Figure 1 The depth in the Z direction is greater than that of the second trench 112 in the third direction, for example, Figure 1 In the Z-direction depth, the bottom surface of the back gate structure 312 is lower than the bottom surface of the second trench 112. The bottom surface of the back gate structure 312 refers to the side of the back gate structure 312 facing away from the extending direction of the active post 120, that is, the back gate structure 312 in a third direction, for example... Figure 1 The side closest to the bottom of the first groove 111 in the Z direction.

[0052] By setting a back gate structure within the first trench, the threshold voltage controllability and current leakage suppression capability of the vertical transistor can be improved, thereby increasing the dynamic hold time and static hold time, while reducing coupling noise. This enhances the electrical performance of the semiconductor structure. Furthermore, the first trench with the back gate structure is located in a third direction, for example... Figure 1 The depth in the Z direction is greater than that of the second trench 112 in the third direction, for example, Figure 1 The depth in the Z direction, the bottom surface of the back gate structure 312 is lower than the bottom surface of the second trench 112, which can provide space for the subsequent word line structure to prevent the word line structure from being too high, that is, to prevent the source or drain region of the active pillar from being too small, which would affect the performance of the vertical transistor.

[0053] Continue to refer to Figure 2 As shown, in one embodiment, a word line structure 130 is further disposed within the substrate 110. The word line structure 130 surrounds the active pillar 120 and extends along a second direction, for example... Figure 1The adjacent word line structures 130 in the X direction are in contact and connected, for example, along the first direction. Figure 1 The adjacent word line structures 130 in the Y direction are insulated from each other; the word line structure 130 in the first groove 111 is above the back gate structure 312, and the word line structure 130 is isolated from the back gate structure 312. It can be seen that the back gate structure 312 extends along the first direction, and the word line structure 130 extends along the second direction. The back gate structure 312 and the word line structure 130 overlap in the orthogonal projection of the third direction, and the overlapping part is exactly located in the first groove 111. By placing the word line structure 130 above the back gate structure 312 and isolating the word line structure 130 from the back gate structure 312, the functions of the word line structure 130 and the back gate structure 312 do not affect each other, that is, setting the back gate structure 312 will not bring any negative effects.

[0054] Continue to refer to Figure 2 As shown, in one embodiment, the word line structure 130 includes a first work function conductive structure 131 and a second work function conductive structure 132, with the second work function conductive structure 132 above the first work function conductive structure 131. By employing two conductive structures with different work functions as the word line structure, the threshold voltage of the vertical transistor can be better matched, unnecessary power consumption can be reduced, and the accuracy of current control can be improved. At the same time, the gate control capability of the transistor can be improved, thereby effectively suppressing leakage current, reducing power consumption, and improving the energy efficiency of the circuit.

[0055] Continue to refer to Figure 2 As shown, in one embodiment, the work function of the back gate structure 312 is lower than the work function of the first work function conductive structure 131. The back gate structure 312 can be made of polysilicon, and the first work function conductive structure 131 can be made of titanium nitride. By adjusting the work function of the back gate structure, the threshold voltage of the vertical transistor can be finely controlled to achieve optimal performance in the circuit design. A lower back gate structure work function can help improve the gate control capability of the vertical transistor, thereby optimizing the threshold voltage and ensuring that the transistor can switch states quickly and accurately when needed. By making the work function of the back gate lower than that of the first work function conductive structure, the gate's control over the channel can be enhanced, reducing leakage current in the transistor's off state, thereby reducing power consumption and improving circuit energy efficiency.

[0056] Continue to refer to Figure 2As shown, in one embodiment, the work function of the first work function conductive structure 131 is greater than the work function of the second work function conductive structure 132. Furthermore, the conductivity of the first work function conductive structure 131 is greater than the conductivity of the second work function conductive structure 132. The material of the first work function conductive structure 131 can be titanium nitride, and the material of the second work function conductive structure 132 can be polysilicon; that is, the material of the second work function conductive structure 132 can be the same as the material of the back gate structure 312. The first work function conductive structure 131 reduces leakage current when the transistor is off, while providing good current control when it is on. This helps to reduce power consumption and improve the energy efficiency of the circuit. The second work function conductive structure 132 allows the vertical transistor to turn on at a lower gate voltage, thereby improving the switching speed and overall performance of the circuit. In other words, when the transistor is on, the word line structure can ensure sufficient current flow, while in the off state, it can effectively suppress leakage current, reduce unnecessary power consumption, and improve the energy efficiency of the circuit. By placing the first work function conductive structure 131 with a high work function below the second work function conductive structure 132 with a low work function, it is possible to reduce signal delay and increase signal propagation speed, which is especially important for high-speed circuit design. At the same time, it helps to control the leakage current of the vertical transistor more effectively, thereby reducing the power consumption of the circuit as a whole.

[0057] Continue to refer to Figure 2 As shown, in one embodiment, the height ratio of the first work function conductive structure 131 in the third direction to the height ratio of the second work function conductive structure 132 in the third direction is 1.2-5:1. By adjusting the height ratio of the first work function conductive structure (high work function material) and the second work function conductive structure (low work function material), the current control capability of the transistor can be optimized, and the conductivity of the word line structure 130 can be improved. That is, when the height ratio of the first work function conductive structure 131 in the third direction to the height ratio of the second work function conductive structure 132 in the third direction is 1.2-5:1, the word line structure 130 has a lower resistivity. If the height ratio is too small, the resistivity of the word line structure 130 is too large; if the height ratio is too large, the control capability of the word line structure 130 is weakened.

[0058] Reference Figure 3 As shown, in one embodiment, a bit line structure 140 is further disposed within the substrate 110. The bit line structure 140 is located on the side of the substrate 110 opposite to the extending direction of the active pillar 120. The bit line structure 140 is, for example, along the first direction. Figure 1 Extending in the Y direction, and along the second direction, for example, Figure 1 The adjacent bit line structures 140 in the X direction are insulated from each other. The bit line structure 140 can be prepared by thinning the side of the substrate 110 away from the extension direction of the active pillar 120, or it can be prepared by existing processes before preparing the word line structure.

[0059] Reference Figure 3 As shown, in one embodiment, the orthographic projection of the back gate structure 312 along the second direction partially overlaps with the orthographic projection of the bit line structure 140 along the second direction. Additionally, the orthographic projection of the back gate structure 312 along the second direction partially overlaps with the orthographic projection of the active pillar 120 along the second direction. By overlapping the orthographic projections of the back gate structure and the bit line structure in the second direction, their relative positions can be optimized, reducing direct coupling between the bit line and the transistor, thereby reducing coupling capacitance or coupling noise, improving signal integrity, and reducing power consumption. Furthermore, the signal transmission path can be optimized, reducing signal delay and increasing circuit operating speed. The partial overlap design of the back gate structure and the bit line structure can reduce the space requirements between components in the circuit, thereby increasing circuit integration and achieving smaller chip size and higher performance. By precisely controlling the relative positions of the back gate structure and the bit line structure, the electrical performance of the transistor, such as threshold voltage control and leakage current suppression, can be optimized, thereby improving circuit stability and reliability.

[0060] Reference Figure 2 As shown, in one embodiment, the back gate structure 312 is isolated from the active pillar 120 by a first insulating structure 211. The material of the first insulating structure 211 can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, photoresist material, or porous material. In this embodiment, the first insulating structure 211 is silicon oxide. The insulating structure between the back gate structure and the active pillar ensures electrical isolation between the two, preventing current from flowing directly from the back gate structure to the active pillar, thereby avoiding unnecessary current paths and power consumption. This isolation is crucial for maintaining the normal operating state of the transistor and the stability of the circuit. Through the isolation of the insulating structure, the voltage of the back gate structure can be controlled independently, unaffected by the voltage of the active pillar. This independent control capability is of great significance for adjusting the threshold voltage (Vth) of the transistor, suppressing leakage current, and optimizing circuit performance.

[0061] Based on the above embodiments, this disclosure also provides a method for fabricating a semiconductor structure (hereinafter referred to as the fabrication method), which is used to fabricate the above-mentioned semiconductor structure 100. The fabrication method will be described in detail below.

[0062] Figure 4 A flowchart illustrating the steps of a method for fabricating a semiconductor structure according to embodiments of this disclosure; Figure 5-18 Cross-sectional views of points aa and cc during the semiconductor structure fabrication process provided in this embodiment of the disclosure;

[0063] Reference Figure 4 As shown, the method for fabricating the semiconductor structure 100 includes:

[0064] See Figures 5-6 As shown, in step S100, a substrate 110 is provided, and a plurality of first trenches 111 extending along a first direction are formed within the substrate 110. Additionally, a first hard mask layer 210 is retained above the substrate 110. The material of the substrate 110 can be, for example, single-crystal silicon, polycrystalline silicon, amorphous silicon, or silicon-on-insulator (SOI). Furthermore, the material of the substrate 110 can include, but is not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The hard mask layer 210 can be made of silicon nitride, silicon carbide, or metal oxides such as silicon oxide.

[0065] See Figures 7-10 As shown in step S200, a first insulating structure 211, a back gate structure 312, and a sacrificial structure 213 extending in a first direction are sequentially formed within the first trench 111. The back gate structure 312 and the sacrificial structure 213 are isolated from the active pillar 120 by the first insulating structure 211, which is conformally formed within the first trench 111. The material of the first insulating structure 211 can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, photoresist material, or porous material. In this embodiment, the first insulating structure 211 is silicon oxide, which is the same material as the first hard mask layer. The material of the back gate structure 312 can be a metal material, a metal alloy, polysilicon, tungsten oxide, etc. In this embodiment, the back gate structure 312 is polysilicon. The material of the sacrificial structure 213 is a germanium-silicon alloy.

[0066] The method for forming the back gate structure 312 further includes depositing a back gate structure material layer 212 on the first insulating structure 211 and the substrate 110, removing the back gate structure material layer 212 on the substrate 110 by an etch-back process, and the remaining back gate structure material layer in the first groove 111 is the back gate structure 312.

[0067] See Figure 11 As shown in S300, a plurality of second trenches 112 extending along the second direction are formed in the substrate 110, and a plurality of active pillars 120 are simultaneously formed at intervals along the first direction and the second direction. The active pillars 120 all extend along the third direction. The active pillars 120 are isolated from each other through the first trenches 111 and the second trenches 112.

[0068] See Figures 12-13As shown, in step S400, a second insulating structure 214 and an isolation structure 215 extending along a second direction are formed within the second trench 112. The second insulating structure 214 is located between the active pillar 120 and the isolation structure 215. The depth of the first trench 111 in the third direction is greater than the depth of the second trench 112 in the third direction, and the bottom surface of the back gate structure 312 is lower than the bottom surface of the second trench 112. The material of the second insulating structure 214 can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, photoresist, or a porous material. In this embodiment, the second insulating structure 214 is silicon oxide, and the material of the isolation structure 215 is different from that of the second insulating structure 214, i.e., the material of the isolation structure 215 has a different etching selectivity than that of the second insulating structure 214. In this embodiment, the isolation structure 215 is silicon nitride.

[0069] By forming a back gate structure within the first trench, the threshold voltage controllability and current leakage suppression capability of the vertical transistor can be improved, thereby increasing the dynamic hold time and static hold time, while reducing coupling noise. This enhances the electrical performance of the semiconductor structure. Furthermore, the first trench with the back gate structure is located in a third direction, for example... Figure 1 The depth in the Z direction is greater than that of the second trench 112 in the third direction, for example, Figure 1 The depth in the Z direction, the bottom surface of the back gate structure 312 is lower than the bottom surface of the second trench 112, which can provide space for the subsequent word line structure to prevent the word line structure from being too high, that is, to prevent the source or drain region of the active pillar from being too small, which would affect the performance of the vertical transistor.

[0070] In one embodiment, the method for fabricating the semiconductor structure 100 further includes: See Figure 14 The second insulating structure 214, the first insulating structure 211, and the first hard mask layer 210 are removed in sequence to expose the top surface of the active pillar 120, as well as the portions of the isolation structure 215 and the sacrificial structure 213 that are above the active pillar 120.

[0071] In one embodiment, the method for fabricating the semiconductor structure 100 further includes: See Figures 15-17 The sacrificial structure 213 and part of the first insulating structure 211 in the first trench 111 are removed to expose the back grid structure 312 and form the third trench 113.

[0072] At the same time, a portion of the second insulation structure 214 within the second trench 112 is removed to form the fourth trench 114;

[0073] A third insulating structure 216 and a word line structure 130 are formed in the third trench 113 and the fourth trench 114; the word line structure 130 is isolated from the active post 120 through the third insulating structure 216.

[0074] In one embodiment, the sacrificial structure 213 within the first trench 111 is removed using a first wet etching process, while a second wet etching process is used to remove a portion of the first insulating structure 211 within the first trench 111 and a portion of the second insulating structure 214 within the second trench 112. Because the sacrificial structure 213 is used, it can be removed first using a wet etching process. This improves etching accuracy during subsequent etching removal of portions of the first and second insulating structures 211 and 214. Therefore, by applying the sacrificial structure to the word line structure formation process, more precise process control can be achieved. Simultaneously, the use of the sacrificial structure provides space for subsequent third insulating structure and word line structure processes.

[0075] In one embodiment, the bottom surface of the fourth groove 114 is higher than the bottom surface of the isolation structure 215, and the bottom surface of the word line structure 130 is higher than the bottom surface of the isolation structure 215. That is, the bottom surface of the isolation structure 215 is lower than the bottom surface of the fourth groove 114 or the bottom surface of the word line structure 130, so that the isolation structure 215 can better perform the isolation function of the word line structure 130.

[0076] In one embodiment, a third insulating structure 216 and a word line structure 130 are formed within the third trench 113 and the fourth trench 114, including,

[0077] A third insulating structure 216 is conformally formed within the third trench 113 and the fourth trench 114. The material of the third insulating structure 216 can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, photoresist material, or porous material. In this embodiment, the third insulating structure 216 is silicon oxide.

[0078] A first work function conductive structure 131 and a second work function conductive structure 132 are sequentially formed, that is, the first work function conductive structure 131 and the second work function conductive structure 132 are deposited sequentially in the third groove 113 and the fourth groove 114. The first work function conductive structure 131 and the second work function conductive structure 132 are isolated from the active pillar 120 by a third insulating structure 216. The work function of the first work function conductive structure 131 is greater than that of the second work function conductive structure 132. In addition, the conductivity of the first work function conductive structure 131 is greater than that of the second work function conductive structure 132. The material of the first work function conductive structure 131 can be titanium nitride, and the material of the second work function conductive structure 132 can be polysilicon. That is, the material of the second work function conductive structure 132 can be the same as that of the back gate structure 312. The first work function conductive structure 131 reduces leakage current when the transistor is off, while providing good current control when it is on. This helps to reduce power consumption and improve the energy efficiency of the circuit. The second work function conductive structure 132 enables the vertical transistor to turn on at a lower gate voltage, thereby improving the switching speed and overall performance of the circuit. Specifically, when the transistor is on, the word line structure ensures sufficient current flow, while in the off state, it effectively suppresses leakage current, reduces unnecessary power consumption, and improves circuit efficiency. By placing the high-work-function first work function conductive structure 131 below the low-work-function second work function conductive structure 132, signal delay can be reduced and signal propagation speed increased, which is particularly important for high-speed circuit design. Simultaneously, it helps to more effectively control the leakage current of the vertical transistor, thereby reducing the overall power consumption of the circuit.

[0079] In one embodiment, the third insulating structure 216 is implemented through a thermal oxidation process. Specifically, the active pillar 120 and gate structure 312 are partially oxidized using this process, creating the third insulating structure 216 on the surfaces of the active pillar 120 and gate structure 312. Therefore, the back gate structure 312 is isolated from the active pillar 120 by the first insulating structure 211. This insulating structure between the back gate structure and the active pillar ensures electrical isolation, preventing current from flowing directly from the back gate structure to the active pillar, thus avoiding unnecessary current paths and power consumption. This isolation is crucial for maintaining the normal operating state of the transistor and the stability of the circuit. Through the isolation of the insulating structure, the voltage of the back gate structure can be controlled independently, unaffected by the voltage of the active pillar. This independent control capability is significant for adjusting the transistor's threshold voltage (Vth), suppressing leakage current, and optimizing circuit performance. The back gate structure 312 is isolated from the word line structure 130 by the third insulating structure 216. Inserting the third insulating structure between the back gate structure and the word line structure ensures complete electrical isolation between them. This isolation layer prevents current from flowing between the back gate and the word lines, avoiding short circuits while maintaining their respective electrical properties. Furthermore, a certain physical distance is maintained between the back gate structure and the word line structure to reduce capacitive coupling and signal interference. This physical isolation helps improve signal integrity and circuit stability.

[0080] In one embodiment, the method for fabricating the semiconductor structure 100 further includes: See Figure 18 and Figure 2 As shown, a fourth insulating structure 217 is formed and planarized to expose the active pillar 120, facilitating the subsequent formation of the capacitor structure.

[0081] In one embodiment, the method for fabricating the semiconductor structure 100 further includes: See Figure 3As shown, a bit line structure 140 is formed on the side of the substrate 110 opposite to the extension direction of the active pillar 120. The bit line structure 140 extends along the first direction, and adjacent bit line structures 140 along the second direction are insulated from each other. The bit line structure 140 can be prepared by thinning the side of the substrate 110 opposite to the extension direction of the active pillar 120, or it can be prepared using existing processes before preparing the word line structure. Furthermore, the orthographic projection of the back gate structure 312 along the second direction partially overlaps with the orthographic projection of the bit line structure 140 along the second direction, and the orthographic projection of the back gate structure 312 along the second direction also overlaps with the orthographic projection of the active pillar 120 along the second direction. By making the orthographic projections of the back gate structure and the bit line structure overlap in the second direction, their relative positions can be optimized, reducing direct coupling between the bit line and the transistor, thereby reducing coupling capacitance or coupling noise, improving signal integrity, and reducing power consumption. Additionally, the signal transmission path can be optimized, signal delay reduced, and circuit operating speed improved. The partial overlap between the back gate structure and the bit line structure reduces the space requirements between components in the circuit, thereby improving circuit integration and achieving smaller chip size and higher performance. By precisely controlling the relative positions of the back gate structure and the bit line structure, the electrical performance of transistors, such as threshold voltage control and leakage current suppression, can be optimized, thereby improving circuit stability and reliability.

[0082] In the description of this disclosure, it should be understood that the terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0083] In the description of this disclosure, it should be understood that the terms “comprising” and “having” as used herein, and any variations thereof, are intended to cover non-exclusive inclusion, such that a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are expressly listed, but may include other steps or units that are not expressly listed or that are inherent to such process, method, product, or apparatus.

[0084] Unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can be a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this invention.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a plurality of active pillars arranged at intervals along a first direction and a second direction, the active pillars all extending along a third direction; and a plurality of first trenches extending along the first direction and a plurality of second trenches extending along the second direction within the substrate, the first trenches and the second trenches isolating the active pillars; the first direction and the second direction intersect and are both perpendicular to the third direction; A back grid structure, wherein the back grid structure is located within the first groove and extends along the first direction; Wherein, the depth of the first trench in the third direction is greater than the depth of the second trench in the third direction, and the bottom surface of the back gate structure is lower than the bottom surface of the second trench.

2. The semiconductor structure according to claim 1, characterized in that, The substrate also contains word line structures that surround the active pillars, with adjacent word line structures in contact and connected along the second direction, and adjacent word line structures in the first direction being insulated from each other; the word line structures in the first trench are above the back gate structure, and the word line structures are isolated from the back gate structure.

3. The semiconductor structure according to claim 2, characterized in that, The word line structure includes a first work function conductive structure and a second work function conductive structure, with the second work function conductive structure located above the first work function conductive structure.

4. The semiconductor structure according to claim 3, characterized in that, The work function of the back gate structure is less than the work function of the first work function conductive structure.

5. The semiconductor structure according to claim 3, characterized in that, The work function of the first work function conductive structure is greater than the work function of the second work function conductive structure.

6. The semiconductor structure according to claim 3, characterized in that, The ratio of the height of the first work function conductive structure in the third direction to the height of the second work function conductive structure in the third direction is 1.2-5:

1.

7. The semiconductor structure according to claim 1, characterized in that, The substrate also contains a bit line structure located on the side of the substrate away from the extension direction of the active pillar. The bit line structure extends along the first direction, and adjacent bit line structures along the second direction are mutually insulated.

8. The semiconductor structure according to claim 7, characterized in that, The orthographic projection of the back gate structure along the second direction partially overlaps with the orthographic projection of the bit line structure along the second direction.

9. The semiconductor structure according to claim 1, characterized in that, The back grid structure is isolated from the active post by a first insulating structure.

10. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A substrate is provided in which a plurality of first trenches extending in a first direction are formed; A first insulating structure, a back grid structure, and a sacrificial structure extending along the first direction are sequentially formed within the first trench; Multiple second trenches extending along a second direction are formed within the substrate, and multiple active pillars are simultaneously formed at intervals along the first direction and the second direction, all of which extend along a third direction; the active pillars are isolated from each other through the first trenches and the second trenches; A second insulating structure and an isolation structure extending along the second direction are formed in the second trench, wherein the second insulating structure is located between the active post and the isolation structure; Wherein, the depth of the first trench in the third direction is greater than the depth of the second trench in the third direction, and the bottom surface of the back gate structure is lower than the bottom surface of the second trench.

11. The preparation method according to claim 10, characterized in that, The preparation method further includes removing the sacrificial structure and part of the first insulating structure in the first trench to expose the back gate structure and form a third trench; Simultaneously, a portion of the second insulating structure within the second trench is removed to form a fourth trench; A third insulating structure and a word line structure are formed in the third trench and the fourth trench; The word line structure is isolated from the active post by the third insulating structure.

12. The preparation method according to claim 11, characterized in that, The bottom surface of the fourth groove is higher than the bottom surface of the isolation structure, and the bottom surface of the character line structure is higher than the bottom surface of the isolation structure.

13. The preparation method according to claim 11, characterized in that, The third insulating structure and the word line structure are formed in the third trench and the fourth trench. include, The third insulating structure is conformally formed within the third and fourth trenches; The first work function conductive structure and the second work function conductive structure are formed sequentially.

14. The preparation method according to claim 13, characterized in that, The third insulation structure is achieved through a thermal oxidation process.

15. The preparation method according to claim 13, characterized in that, The fabrication method further includes forming a bit line structure on a side of the substrate opposite to the extension direction of the active pillar, the bit line structure extending along the first direction, and adjacent bit line structures along the second direction being mutually insulated.

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