Semiconductor memory device

Abstract

A semiconductor memory device may include: a vertical semiconductor pattern extending in a first direction; a plurality of bit lines on a lower surface of the vertical semiconductor pattern, each of the bit lines extending in a second direction perpendicular to the first direction; and a plurality of first gate structures on a first side surface of the vertical semiconductor pattern, each of the first gate structures extending in a third direction, the third direction being perpendicular to the first direction and intersecting the second direction. The bit lines include odd-numbered bit lines and even-numbered bit lines alternately arranged with each other along the third direction. A first vertical semiconductor pattern of the vertical semiconductor patterns electrically connected to the even-numbered bit line is laterally offset from a second vertical semiconductor pattern of the vertical semiconductor patterns electrically connected to the odd-numbered bit line.

Description

Technical Field

[0001] The embodiments of this disclosure described herein relate to a semiconductor memory device. Background Technology

[0002] Semiconductor devices are core components used to control or amplify electrical signals in electronic devices, and various types of semiconductor devices can be manufactured. As design rules for semiconductor devices become increasingly restrictive, manufacturing technologies are evolving towards higher integration density, faster operating speeds, and improved yields. Therefore, vertical-channel transistors have been proposed to improve integration density, reduce resistance, and enhance the current-driving capability of transistors. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor memory device with improved electrical characteristics and improved reliability.

[0004] According to some embodiments, a semiconductor memory device may include: a vertical semiconductor pattern extending in a first direction; a plurality of bit lines electrically connected to a lower surface of the vertical semiconductor pattern, each of the bit lines extending in a second direction perpendicular to the first direction; and a plurality of first gate structures located on a first side surface of the vertical semiconductor pattern, each of the first gate structures extending upward in a third direction perpendicular to the first direction and intersecting the second direction, wherein the bit lines include odd-numbered bit lines and even-numbered bit lines alternating with each other along the third direction, and wherein a first vertical semiconductor pattern electrically connected to the even-numbered bit lines in the vertical semiconductor pattern is laterally offset from a second vertical semiconductor pattern electrically connected to the odd-numbered bit lines in the vertical semiconductor pattern.

[0005] According to some embodiments, a semiconductor memory device may include: a vertical semiconductor pattern extending in a first direction; a plurality of bit lines located on a lower surface of the vertical semiconductor pattern, each of the bit lines extending in a second direction perpendicular to the first direction; and a plurality of first gate structures located on a first side surface of the vertical semiconductor pattern, each of the first gate structures extending upward in a third direction perpendicular to the first direction and intersecting the second direction, wherein the bit lines include odd-numbered bit lines and even-numbered bit lines alternating with each other along the third direction, wherein the first gate structures include odd-numbered first gate structures and even-numbered first gate structures alternating with each other along the second direction, wherein a first vertical semiconductor pattern adjacent to the odd-numbered first gate structure is electrically connected to the odd-numbered bit line, and wherein a second vertical semiconductor pattern adjacent to the even-numbered first gate structure is electrically connected to the even-numbered bit line.

[0006] According to some embodiments, a semiconductor memory device may include: a vertical semiconductor pattern extending in a first direction; a plurality of bit lines located on a lower surface of the vertical semiconductor pattern, each of the bit lines extending in a second direction perpendicular to the first direction; and a plurality of first gate structures located on a first side surface of the vertical semiconductor pattern, each of the first gate structures extending upward in a third direction perpendicular to the first direction and intersecting the second direction, wherein the bit lines include odd-numbered bit lines and even-numbered bit lines alternately arranged along the third direction, wherein the first gate structures include 4N first gate structures arranged sequentially along the second direction, where N is a natural number, wherein a first vertical semiconductor pattern adjacent to the 4N-3rd and 4N-2nd first gate structures of the first gate structures is electrically connected to the odd-numbered bit lines, and wherein a second vertical semiconductor pattern adjacent to the 4N-1st and 4Nth first gate structures of the first gate structures is electrically connected to the even-numbered bit lines. Attached Figure Description

[0007] The above and other objects and features of this disclosure will become clearer from the detailed description of exemplary embodiments with reference to the accompanying drawings.

[0008] Figure 1 This is a rear view showing a semiconductor memory device according to some embodiments of the present disclosure.

[0009] Figure 2 It is along Figure 1 A sectional view taken by line A-A'.

[0010] Figure 3 It is along Figure 1 The sectional view taken by line B-B'.

[0011] Figure 4 This is a rear view showing a semiconductor memory device according to some embodiments of the present disclosure.

[0012] Figure 5 This is a rear view showing a semiconductor memory device according to some embodiments of the present disclosure.

[0013] Figure 6 It is according to some embodiments of this disclosure along Figure 1 A sectional view taken by line A-A'.

[0014] Figure 7 This is a cross-sectional view showing a semiconductor memory device according to some embodiments of the present disclosure.

[0015] Figure 8 This is a rear view showing a semiconductor memory device according to some embodiments of the present disclosure.

[0016] Figure 9 This is a rear view showing a semiconductor memory device according to some embodiments of the present disclosure.

[0017] Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A and Figure 22B These are cross-sectional and rear views illustrating methods of manufacturing semiconductor memory devices according to some embodiments of the present disclosure. Detailed Implementation

[0018] In the following, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0019] Semiconductor memory devices according to some embodiments of this disclosure can be memory devices based on semiconductor elements. For example, semiconductor memory devices can be volatile memory (such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, or thyristor RAM (TRAM)) or non-volatile memory (such as phase change random access memory (PRAM), magnetic random access memory (MRAM), or resistive random access memory (RRAM)).

[0020] Semiconductor memory devices according to some embodiments of the present disclosure may include memory cells including vertical channel transistors (VCTs). A VCT may refer to a transistor in which a semiconductor pattern extends in a direction perpendicular to the upper surface of a semiconductor substrate.

[0021] Figure 1 This is a rear view showing a semiconductor memory device according to some embodiments of the present disclosure. Figure 2 It is along Figure 1 A sectional view taken by line A-A'. Figure 3 It is along Figure 1 The sectional view taken by line B-B'.

[0022] refer to Figures 1 to 3 According to some embodiments of the present disclosure, a semiconductor memory device may include a vertical semiconductor pattern 110, a bit line 210, a first gate structure 130, a second gate structure 150, and a capacitor 310.

[0023] According to some embodiments of this disclosure, the vertical semiconductor pattern 110 can be used as a VCT of a semiconductor memory device. The vertical semiconductor pattern 110 can be disposed on a first surface 210a of the bit line 210 and can extend in a first direction D1. That is, the vertical semiconductor pattern 110 can be perpendicular to the bit line 210 (i.e., can extend perpendicularly to the bit line 210). In some embodiments, the semiconductor memory device may include a plurality of vertical semiconductor patterns 110.

[0024] The vertical semiconductor pattern 110 may include a first source / drain region SD1, a second source / drain region SD2, and a channel region CA. The first source / drain region SD1 may be formed at the upper end of the vertical semiconductor pattern 110, and the second source / drain region SD2 may be formed at the lower end of the vertical semiconductor pattern 110. Here, the upper end may be the end of the vertical semiconductor pattern 110 along the first direction D1, and the lower end may be the end of the vertical semiconductor pattern 110 along a direction opposite to the first direction D1. The first source / drain region SD1 may be connected to a capacitor 310, and the second source / drain region SD2 may be connected to a bit line 210. The first source / drain region SD1 and the second source / drain region SD2 may serve as sources or drains and supply or discharge current-carrying carriers. Here, the carriers may be electrons or holes. The channel region CA may serve as a pathway for the movement of carriers. For example, a first source / drain region SD1 can be used as a source, a second source / drain region SD2 can be used as a drain, and a channel region CA can be used as a pathway (i.e., a channel) through which charge carriers move between the source and drain. The first source / drain region SD1 and the second source / drain region SD2 can be regions doped with impurities having a different conductivity type than that of the channel region CA. For example, when the channel region CA includes a first conductivity type impurity, the first source / drain region SD1 and the second source / drain region SD2 can be regions doped with a second conductivity type impurity, opposite to that conductivity type impurity. For example, the first conductivity type impurity can be a p-type impurity, such as boron (B) of group 3 elements, and the second conductivity type impurity can be an n-type impurity, such as phosphorus (P) and / or arsenic (As) of group 5 elements. As used in this paper, the first source / drain region SD1 can also be called the first source / drain region SD1, the second source / drain region SD2 can also be called the second source / drain region SD2, and the channel region CA can also be called the channel region CA.

[0025] The vertical semiconductor pattern 110 may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), or silicon-germanium (Si-Ge). The vertical semiconductor pattern 110 may also include an oxide semiconductor material. The oxide semiconductor material may be, for example, In... x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sny O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga y At least one of O and / or indium gallium zinc oxide (IGZO). The vertical semiconductor pattern 110 may comprise a single layer or multiple layers made of oxide semiconductor material. The vertical semiconductor pattern 110 may comprise amorphous, crystalline, or polycrystalline oxide semiconductor material. In some embodiments, the vertical semiconductor pattern 110 may have a bandgap energy greater than that of silicon. In some embodiments, the vertical semiconductor pattern 110 may comprise a two-dimensional semiconductor material. The two-dimensional semiconductor material may include, for example, graphene, MoS2, WS2, MoSe2, WSe2, or combinations thereof.

[0026] Bit lines 210 may be disposed on the lower surface of the vertical semiconductor pattern 110. Bit lines 210 may have a first surface 210a and a second surface 210b, with the vertical semiconductor pattern 110 connected to the first surface 210a and the second surface 210b facing the first surface 210a. In other words, the second surface 210b of the bit line 210 may be opposite to the first surface 210a of the bit line 210 (e.g., in the first direction D1). Bit lines 210 may extend in a second direction D2 perpendicular to the first direction D1. In some embodiments, the semiconductor memory device may include a plurality of bit lines 210, and the bit lines 210 may be arranged in a third direction D3 perpendicular to the first direction D1 and intersecting the second direction D2. Bit lines 210 may extend parallel to the second direction D2 and may be spaced apart from each other at regular intervals in the third direction D3.

[0027] Each bit line in bit line 210 may include a buried conductive pattern 211, a contact pattern 213, a metal pattern 215, and a hard mask pattern 217 stacked sequentially in a direction opposite to the first direction D1. The buried conductive pattern 211 may include polycrystalline silicon doped with impurities. The contact pattern 213 may include at least one of the following materials: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), or a two-dimensional (2D) material. The metal pattern 215 may include at least one of the following: a metallic material (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, and / or Co), a conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, and / or RuTiN), a conductive metal silicide, or a conductive metal oxide (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO (Ba, Sr)RuO3, CRO (CaRuO3), and / or LSCo). The hard mask pattern 217 may include an insulating material, such as a silicon nitride or silicon oxide.

[0028] In some embodiments, the vertical semiconductor pattern 110 connected to the even-numbered bit lines 210 located between adjacent odd-numbered bit lines 210 can be laterally offset from the vertical semiconductor pattern 110 connected to adjacent odd-numbered bit lines 210. That is, when viewed in a plane (e.g., rear view), the vertical semiconductor patterns 110 can be spaced apart from each other in the second direction D2 and the third direction D3. Here, the spacing between the vertical semiconductor patterns 110 can be constant.

[0029] For example, bit lines 210 may include odd-numbered bit lines 210 and even-numbered bit lines 210 alternating with each other along the third direction D3. That is, bit lines 210 may alternate between odd-numbered bit lines 210 and even-numbered bit lines 210 along the third direction D3, wherein each odd-numbered bit line 210 is adjacent to an even-numbered bit line 210, and each even-numbered bit line 210 is adjacent to an odd-numbered bit line 210. In some embodiments, a first vertical semiconductor pattern in the vertical semiconductor pattern 110 connected to the even-numbered bit lines 210 may be laterally offset from a second vertical semiconductor pattern in the vertical semiconductor pattern 110 connected to the odd-numbered bit lines 210 (e.g., see...). Figure 1For example, a first vertical semiconductor pattern in vertical semiconductor pattern 110 connected to even-numbered bit lines 210 may be misaligned with a second vertical semiconductor pattern in vertical semiconductor pattern 110 connected to odd-numbered bit lines 210 along a third direction D3. For example, a first vertical semiconductor pattern in vertical semiconductor pattern 110 connected to even-numbered bit lines 210 may be shifted relative to a second vertical semiconductor pattern in vertical semiconductor pattern 110 connected to odd-numbered bit lines 210 in a second direction D2. In other words, a first bit line in bit line 210 may be adjacent to a second bit line in bit line 210 in a third direction D3, and a first vertical semiconductor pattern in vertical semiconductor pattern 110 connected to a first bit line in bit line 210 may be misaligned with a second vertical semiconductor pattern in vertical semiconductor pattern 110 connected to a second bit line in bit line 210 along a third direction D3 (and may be shifted relative to a second vertical semiconductor pattern in vertical semiconductor pattern 110 in a second direction D2).

[0030] In some embodiments, an insulating pattern 219 may be formed on the first surface 210a of the bit line 210, the lower surface of the first gate insulating pattern 133, and the lower surface of the vertical semiconductor pattern 110. The insulating pattern 219 may be a film of insulating material conformally formed on the first surface 210a of the bit line 210, the lower surface of the first gate insulating pattern 133, and the lower surface of the vertical semiconductor pattern 110. In some embodiments, the first surface 210a of the bit line 210 and the insulating pattern 219 may be arranged in the same plane (i.e., they may be coplanar). The insulating pattern 219 may include at least one of, for example, silicon oxide, silicon nitride, silicon nitride, or a low-dielectric-constant insulating material.

[0031] The first gate structure 130 may be located on a first side surface perpendicular to the semiconductor pattern 110 (e.g., it may cover the first side surface and / or overlap with it). Here, the first side surface may refer to a side surface in the second direction D2. The first gate structure 130 may extend in a third direction D3 perpendicular to the first direction D1. In some embodiments, the semiconductor memory device may include a plurality of first gate structures 130, and the first gate structures 130 may be arranged in a second direction D2 perpendicular to the first direction D1 and intersecting the third direction D3. That is, the first gate structures 130 may extend parallel to the third direction D3 and may be spaced apart from each other at regular intervals in the second direction D2. As used herein, "element A overlaps with element B in direction X" (or similar language) means that there is at least one straight line extending in direction X and intersecting both elements A and B.

[0032] The first gate structure 130 may include a first gate electrode 131 and a first gate insulating pattern 133. The first gate electrode 131 may be located on a portion of a side surface of the first gate insulating pattern 133 (e.g., it may cover a portion of the side surface and / or overlap with a portion of the side surface) and may extend in a third direction D3. The first gate electrode 131 may be disposed between a third overlay pattern 145 and a fourth overlay pattern 147, which will be described below. In some embodiments, the first gate electrode 131 may serve as a word line of a semiconductor memory device. The first gate electrode 131 may include a conductive material. The first gate electrode 131 may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, impurity-doped polysilicon, or a combination thereof.

[0033] A first gate insulating pattern 133 may be disposed between a first side surface of the vertical semiconductor pattern 110 and a first gate electrode 131. The first gate insulating pattern 133 may be located on the first side surface of the vertical semiconductor pattern 110 (e.g., it may cover the first side surface and / or overlap with the first side surface) and may extend in a third direction D3. The first gate insulating pattern 133 may include an insulating material. The first gate insulating pattern 133 may include, for example, silicon oxide, silicon nitride, silicon nitride, a high dielectric constant material with a dielectric constant higher than that of silicon oxide, or a combination thereof.

[0034] In some embodiments, such as Figure 1 As shown, the vertical semiconductor pattern 110 covered by the odd-numbered first gate structures in the first gate structure 130 can be connected to the odd-numbered bit lines in the bit line 210, and the vertical semiconductor pattern 110 covered by the even-numbered first gate structures in the first gate structure 130 can be connected to the even-numbered bit lines in the bit line 210. That is, when viewed in a plane, the vertical semiconductor pattern 110 covered by the odd-numbered first gate structures in the first gate structure 130 and the vertical semiconductor pattern 110 covered by the even-numbered first gate structures in the first gate structure 130 can be arranged in a sawtooth (i.e., zigzag) shape on the third direction D3. For example, based on two adjacent first gate structures 130, when viewed in a plane, the vertical semiconductor pattern 110 connected to one of the two first gate structures 130 and the vertical semiconductor pattern 110 connected to the other of the two first gate structures 130 can be offset from each other. Here, offset can mean that in the vertical semiconductor pattern 110 connected to the first gate structure 130, the bit lines 210 connected to the vertical semiconductor pattern 110 in the same order are different from each other.

[0035] For example, the first gate structure 130 may include odd-numbered first gate structures 130 and even-numbered first gate structures 130 arranged alternately along the second direction D2. That is, in the second direction D2, the first gate structures 130 may alternate between odd-numbered first gate structures 130 and even-numbered first gate structures 130, wherein each odd-numbered first gate structure 130 is adjacent to an even-numbered first gate structure 130, and each even-numbered first gate structure 130 is adjacent to an odd-numbered first gate structure 130. In some embodiments, a first vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to an odd-numbered first gate structure 130 (e.g., in the second direction D2) may be connected to an odd-numbered bit line in the bit line 210, and a second vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to an even-numbered first gate structure 130 (e.g., in the second direction D2) may be connected to an even-numbered bit line in the bit line 210. In some embodiments, the first vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the odd-numbered first gate structure 130 may be laterally offset from the second vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the even-numbered first gate structure 130. For example, the first vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the odd-numbered first gate structure 130 may be misaligned with the second vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the even-numbered first gate structure 130 along the second direction D2. For example, the first vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the odd-numbered first gate structure 130 may be shifted relative to the second vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the even-numbered first gate structure 130 in the third direction D3. In other words, the first gate structure in the first gate structure 130 may be adjacent to the second gate structure in the first gate structure 130 in the second direction D2, and the first vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the first gate structure in the first gate structure 130 may be misaligned with the second vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the second gate structure in the first gate structure 130 along the second direction D2 (and may be shifted relative to the second vertical semiconductor pattern in the vertical semiconductor pattern 110 in the third direction D3).

[0036] The second gate structure 150 may be disposed between the second side surfaces of the vertical semiconductor pattern 110. Here, the second side surface may be the surface of the vertical semiconductor pattern 110 facing the first side surface (i.e., opposite to the first side surface). That is, the second gate structure 150 may be located on some of the second side surfaces of the vertical semiconductor pattern 110 (e.g., may cover some of the second side surfaces and / or overlap with some of the second side surfaces). The second gate structure 150 may extend in a third direction D3, which is perpendicular to the first direction D1 and intersects with the second direction D2. In some embodiments, the semiconductor memory device may include a plurality of second gate structures 150, and the second gate structures 150 may be arranged in a second direction D2 that is perpendicular to the first direction D1 and intersects with the third direction D3. That is, the second gate structures 150 may extend parallel to the third direction D3 and may be spaced apart from each other at a regular interval in the second direction D2.

[0037] The second gate structure 150 may include a second gate electrode 151 and two second gate insulating patterns 153. In some embodiments, the second gate electrode 151 may serve as the back gate of a semiconductor memory device. The second gate electrode 151 may extend on a third direction D3. The second gate electrode 151 may be disposed between the first cover pattern 141 and the second cover pattern 143, which will be described below. The second gate electrode 151 may include a conductive material. The second gate electrode 151 may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, doped polysilicon, or a combination thereof.

[0038] The second gate insulating pattern 153 may be disposed on two (i.e., opposite) side surfaces of the second gate electrode 151 (e.g., in the second direction D2). The second gate insulating pattern 153 may contact the second side surfaces of the vertical semiconductor pattern 110 respectively. That is, the second gate insulating pattern 153 may be disposed between the second gate electrode 151 and the second side surfaces of the vertical semiconductor pattern 110. The second gate insulating pattern 153 may extend in the third direction D3. The second gate insulating pattern 153 may include an insulating material. The second gate insulating pattern 153 may include, for example, silicon oxide, silicon nitride, silicon nitride, a high dielectric constant material with a dielectric constant higher than that of silicon oxide, or a combination thereof.

[0039] Capacitor 310 may be disposed on the upper surface of each vertical semiconductor pattern in the vertical semiconductor pattern 110. Here, the upper surface may be the surface of the vertical semiconductor pattern 110 in the first direction D1. As used herein, capacitor 310 may also be referred to as capacitor structure 310. Capacitor 310 may store signals received from transistors within the peripheral circuitry of the semiconductor memory device (e.g., row and column decoders, sense amplifiers, etc.). Capacitor 310 may serve as an information storage element electrically connected to the transistor. For example, capacitor 310 may store charge under the control of the transistor. In some embodiments, capacitor 310 may include storage electrode 311, capacitor dielectric film 313, and plate electrode 315.

[0040] Multiple storage electrodes 311 may be formed to be spaced apart from each other in the second direction D2 and the third direction D3, and may contact the upper surface of each of the corresponding vertical semiconductor patterns 110. That is, the storage electrodes 311 may be spaced apart from each other at a regular interval in the second direction D2 and the third direction D3. In some embodiments, when viewed in a plane, the storage electrodes 311 may be offset from a checkerboard arrangement in the second direction D2 and the third direction D3 to a zigzag or hexagonal honeycomb arrangement. The storage electrodes 311 may include a conductive material. The storage electrodes 311 may include, for example, a metal, a metal nitride, a metal silicide, or a combination thereof. Therefore, the capacitor 310 may be electrically connected to the vertical semiconductor pattern 110.

[0041] The capacitor dielectric film 313 can be disposed on the storage electrode 311, the first gate insulating pattern 133, the second gate insulating pattern 153, the second cover pattern 143, and the fourth cover pattern 147. That is, the capacitor dielectric film 313 can be conformally formed on the storage electrode 311, the first gate insulating pattern 133, the second gate insulating pattern 153, the second cover pattern 143, and the fourth cover pattern 147. Contrary to the illustrations, the capacitor dielectric film 313 may include multiple films. The capacitor dielectric film 313 may include, for example, silicon oxide, silicon nitride, silicon oxide nitride, high-dielectric materials including metals, or combinations thereof.

[0042] The plate electrode 315 may be disposed on the capacitor dielectric film 313. The plate electrode 315 may be located in the empty space between the storage electrodes 311 (e.g., the empty space may be filled). The plate electrode 315 may comprise at least one of an elemental semiconductor material film or a compound semiconductor material film. The plate electrode 315 may comprise doped n-type impurities or doped p-type impurities. The plate electrode 315 may comprise, for example, a metal, a metal nitride, a metal silicide, silicon-germanium doped with impurities, or a combination thereof.

[0043] In some embodiments, the dielectric film 230 may be disposed on the insulating pattern 219 in a direction opposite to the first direction D1. That is, the dielectric film 230 may be disposed on the second surface 210b of the bit line 210 and may be located in the space between the bit lines 210 (e.g., the space may be filled). The dielectric film 230 may comprise, for example, silicon oxide, silicon nitride, silicon nitride, and / or a high dielectric constant material including metals. Therefore, the process of forming the shielding pattern disposed between the bit lines 210 can be omitted. As a result, the process for forming semiconductor memory devices can be simplified.

[0044] The separator pattern 139 may be disposed between adjacent and mutually facing first gate electrodes 131. The separator pattern 139 may electrically insulate adjacent first gate electrodes 131 from each other. The separator pattern 139 may include an insulating material. The separator pattern 139 may include, for example, silicon oxide, silicon nitride, silicon nitride, a high dielectric constant material with a dielectric constant higher than that of silicon oxide, or a combination thereof.

[0045] A first overlay pattern 141 may be disposed between the bit line 210 and the second gate electrode 151. The lower surface of the first overlay pattern 141 may contact the buried conductive pattern 211 of the bit line 210. The first overlay pattern 141 may be disposed between the lower ends of the second gate insulating patterns 153. The first overlay pattern 141 may extend parallel to the second gate electrode 151 in a third direction D3.

[0046] The second cover pattern 143 may be disposed between the capacitor 310 and the second gate electrode 151. The upper surface of the second cover pattern 143 may contact the storage electrode 311 of the capacitor 310 and the capacitor dielectric film 313. The second cover pattern 143 may be disposed between the upper ends of the second gate insulating pattern 153. The second cover pattern 143 may extend parallel to the second gate electrode 151 in a third direction D3.

[0047] A third cover pattern 145 may be disposed between the bit line 210, the first gate electrode 131, and the separator pattern 139. The lower surface of the third cover pattern 145 may contact the buried conductive pattern 211 of the bit line 210. The third cover pattern 145 may be disposed between the lower ends of the first gate insulating pattern 133. The third cover pattern 145 may extend parallel to the first gate electrode 131 in a third direction D3.

[0048] A fourth cover pattern 147 may be disposed between the capacitor 310, the first gate electrode 131, and the separator pattern 139. The upper surface of the fourth cover pattern 147 may contact the capacitor dielectric film 313 of the capacitor 310. The fourth cover pattern 147 may be disposed between the upper ends of the first gate insulating pattern 133. The fourth cover pattern 147 may extend parallel to the first gate electrode 131 in a third direction D3.

[0049] Each of the first cover pattern 141, the second cover pattern 143, the third cover pattern 145, and the fourth cover pattern 147 may include an insulating material. Each of the first cover pattern 141, the second cover pattern 143, the third cover pattern 145, and the fourth cover pattern 147 may include, for example, silicon oxide, silicon nitride, silicon oxide nitride, or combinations thereof.

[0050] When the spacing between bit lines 210 decreases, coupling may occur when all adjacent bit lines 210 are activated, and noise and parasitic capacitance may increase. To prevent this, a shielding pattern can be formed between the bit lines 210. However, in semiconductor memory devices according to some embodiments of this disclosure, different vertical semiconductor patterns 110 can be connected to adjacent bit lines 210 such that adjacent bit lines 210 are not activated simultaneously. In other words, a vertical semiconductor pattern 110 connected to an even-numbered bit line 210 adjacent to an odd-numbered bit line 210 can be laterally offset from a vertical semiconductor pattern 110 connected to an odd-numbered bit line 210 adjacent to an odd-numbered bit line 210. In this way, when a vertical semiconductor pattern 110 is arranged to be offset from a bit line 210 according to its position, two adjacent bit lines 210 are not activated simultaneously. Therefore, even when the spacing between bit lines 210 decreases, coupling that occurs between adjacent bit lines 210 without forming a shielding pattern can be improved. As a result, the parasitic capacitance of the bit lines 210 can be reduced, the process can be simplified, and noise can be improved.

[0051] According to some embodiments, the vertical semiconductor patterns 110 connected to the first gate structure 130 may be offset from each other with a single-line spacing, but the embodiments of this disclosure are not limited thereto. For example, the first gate structure 130 arranged on a third-direction D3 may be offset with a spacing of two lines, three lines, or more lines.

[0052] Figure 4 This is a rear view showing a semiconductor memory device according to some embodiments of the present disclosure. For ease of description, the following description will primarily focus on the differences between the embodiments described above and those described below.

[0053] refer to Figure 4The vertical semiconductor pattern 110 covered by the (4N-3)th and (4N-2)th first gate structures in the first gate structure 130 can be connected to the odd-numbered bit lines in the bit line 210, and the vertical semiconductor pattern 110 covered by the (4N-1)th and (4N)th first gate structures in the first gate structure 130 can be connected to the even-numbered bit lines in the bit line 210 (where "N" is a natural number). That is, when viewed in a plane, the (4N-3)th and (4N-2)th first gate structures in the first gate structure 130, along with the (4N-1)th and (4N)th first gate structures in the first gate structure 130, can be arranged in a sawtooth pattern on the third direction D3. This arrangement reduces the capacitance of the bit line 210 and improves noise.

[0054] For example, the first gate structure 130 may include 4N first gate structures 130 arranged sequentially along the second direction D2, where "N" is a natural number. The first gate structures 130 may extend in the third direction D3 and may be spaced apart from each other in the second direction D2. In some embodiments, a first vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the 4N-3rd and 4N-2nd first gate structures in the first gate structure 130 (e.g., in the second direction D2) may be connected to an odd-numbered bit line in the bit line 210, and a second vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the 4N-1st and 4Nth first gate structures in the first gate structure 130 (e.g., in the second direction D2) may be connected to an even-numbered bit line in the bit line 210. For example, a pair of vertical semiconductor patterns 110 adjacent to each other in the second direction D2, with the second gate structure 150 located therebetween, may be connected to the same bit line 210.

[0055] Figure 5 This is a rear view showing a semiconductor memory device according to some embodiments of the present disclosure. For ease of description, the following description will primarily focus on the differences between the embodiments described above and those described below.

[0056] refer to Figure 5The vertical semiconductor pattern 110 covered by the 6N-5th, 6N-4th, and 6N-3th first gate structures in the first gate structure 130 can be connected to the odd-numbered bit lines in the bit line 210, and the vertical semiconductor pattern 110 covered by the 6N-2th, 6N-1th, and 6Nth first gate structures in the first gate structure 130 can be connected to the even-numbered bit lines in the bit line 210 (where "N" is a natural number). That is, when viewed in a plane, the 6N-5th, 6N-4th, and 6N-3th first gate structures in the first gate structure 130 and the 6N-2th, 6N-1th, and 6Nth first gate structures in the first gate structure 130 can be arranged in a sawtooth pattern on the third direction D3. For example, the first vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the 6N-5th, 6N-4th, and 6N-3th first gate structures in the first gate structure 130 can be connected to the odd-numbered bit lines in the bit line 210, and the second vertical semiconductor pattern in the vertical semiconductor pattern 110 adjacent to the 6N-2th, 6N-1th, and 6Nth first gate structures in the first gate structure 130 can be connected to the even-numbered bit lines in the bit line 210. This arrangement reduces the capacitance of the bit line 210 and improves noise levels.

[0057] Figure 6 It is according to some embodiments of this disclosure along Figure 1 The cross-sectional view is taken along line A-A'. For ease of description, the following will mainly describe the differences between the embodiments described above and those described below.

[0058] refer to Figure 6 The data storage pattern DSP can be disposed on the upper surface of the vertical semiconductor pattern 110. For example, a semiconductor memory device may include a data storage pattern DSP other than the one referenced above. Figures 1 to 3 The capacitor 310 is described. A data storage pattern DSP can be electrically connected to a vertical semiconductor pattern 110. When viewed in a plane, the data storage pattern DSP can be spaced apart from each other at regular intervals in a second direction D2 and a third direction D3. That is, when viewed in a plane, the data storage pattern DSP included in a semiconductor memory device according to some embodiments of this disclosure can be arranged in a sawtooth or honeycomb structure.

[0059] In some embodiments, the data storage pattern DSP can be a variable resistance pattern that can switch between two resistance states by an electrical pulse applied to the memory element. For example, the data storage pattern DSP may include phase change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials whose crystal states change according to the magnitude of the current.

[0060] Figure 7 This is a cross-sectional view illustrating a semiconductor memory device according to some embodiments of the present disclosure, and Figure 8 This is a rear view showing a semiconductor memory device according to some embodiments of the present disclosure. For ease of description, the following description will primarily focus on the differences between the embodiments described above and those described below.

[0061] refer to Figure 7 and Figure 8 Semiconductor memory devices according to some embodiments of this disclosure may include a peripheral circuit structure PS and a cell array structure CS connected to the peripheral circuit structure PS. The semiconductor memory device may have a chip-to-chip (C2C) structure. A C2C structure may refer to: fabricating an upper chip including the cell array structure CS on a first substrate, fabricating a lower chip including the peripheral circuit structure PS on a third substrate, and then connecting the upper and lower chips to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting bonding pads formed on the uppermost metal layer of the upper chip and bonding pads formed on the uppermost metal layer of the lower chip. For example, when the bonding pads are formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method, and the bonding pads may also be formed of aluminum (Al) or tungsten (W). More specifically, the cell array structure CS may be disposed on the peripheral circuit structure PS. (Refer to the above...) Figures 1 to 3 As described, in the cell array structure CS, a vertical semiconductor pattern 110 can be set as the cell transistor of each memory cell and a capacitor 310 can be set as the data storage element of each memory cell, and a passivation film PL can be set on the capacitor 310.

[0062] like Figure 7As shown, the first bonding pad 510a can be disposed on the second interlayer insulating film 530a located on the lowest layer of the cell array structure CS. The first bonding pad 510a can be electrically connected to the first gate electrode 131, the second gate electrode 151, and the bit line 210 via the first contact plug 520a. The first bonding pad 510a can directly contact and bond to the second bonding pad 510b of the peripheral circuit structure PS. The peripheral circuit structure PS can include core and peripheral circuits formed on the third substrate 500. Here, the core can refer to the circuit to which the memory cell of the semiconductor memory device is connected, and the peripheral circuit can refer to other circuits. The core and peripheral circuits can include row and column decoders, sense amplifiers SA, and control logic. For example, the sense amplifiers SA can be formed in the third substrate 500. The third substrate 500 can be located on the lower surface (i.e., the second surface) of the bit line 210. The second bonding pad 510b can be disposed on the uppermost layer of the third interlayer insulating film 530b of the peripheral circuit structure PS. The second bonding pad 510b can be electrically connected to the core and peripheral circuitry of the semiconductor memory device via the peripheral wiring line 540 and the second contact plug 520b.

[0063] In some embodiments, the peripheral circuitry PS of the semiconductor memory device may include a first sense amplifier SA1 and a second sense amplifier SA2. The first sense amplifier SA1 and the second sense amplifier SA2 can sense changes in the voltage of a bit line 210 selected from a plurality of bit lines 210 and amplify and output the changes in voltage.

[0064] like Figure 8 As shown, the cell array structure CS may include multiple bit lines 210, and each bit line 210 included in the cell array structure CS may be connected to a first sense amplifier SA1 or a second sense amplifier SA2. In some embodiments, the first sense amplifier SA1 may be connected to even-numbered bit lines 210, and the second sense amplifier SA2 may be connected to odd-numbered bit lines 210. Therefore, when the semiconductor memory device is operated, the first sense amplifier SA1 may activate the even-numbered bit lines 210. Furthermore, when the even-numbered bit lines 210 are activated, the odd-numbered bit lines 210 that the first sense amplifier SA1 is not connected to may be pre-charged.

[0065] Similarly, when the semiconductor memory device is operated, the second sense amplifier SA2 can activate the odd-numbered bit lines 210. Furthermore, when the odd-numbered bit lines 210 are activated, the even-numbered bit lines 210 that are not connected to the second sense amplifier SA2 can be pre-charged.

[0066] Therefore, when one of the adjacent bit lines 210 is activated, the other bit line in the adjacent bit line 210 can be pre-charged, and the coupling phenomenon that occurs when both adjacent bit lines 210 are activated can be reduced. As a result, the parasitic capacitance of the bit line 210 can be reduced, and noise can be improved.

[0067] Figure 9 This is a rear view showing a semiconductor memory device according to some embodiments of the present disclosure. For ease of description, the following description will primarily focus on the differences between the embodiments described above and those described below.

[0068] refer to Figure 9 Bit line contacts 250 can be disposed inside the first sense amplifier SA1 and the second sense amplifier SA2. Here, bit line contacts 250 can be metallic wiring. Bit line contacts 250 can connect the distal ends of adjacent bit lines 210 inside each of the first sense amplifier SA1 and the second sense amplifier SA2 into pairs. Therefore, adjacent bit lines 210 connected in each of the first sense amplifier SA1 and the second sense amplifier SA2 can respectively form bit line pairs electrically connected by bit line contacts 250. For example, adjacent bit lines in the bit lines 210 (e.g., on the third direction D3) can be grouped into pairs, wherein the bit line pairs are arranged alternately along the third direction D3 as odd-numbered bit line pairs and even-numbered bit line pairs. More specifically, the first sense amplifier SA1 can be connected to even-numbered bit line pairs, and the second sense amplifier SA2 can be connected to odd-numbered bit line pairs. For example, when connected to the first sense amplifier SA1, bit line contacts 250 can be positioned at the distal ends of adjacent third and fourth bit lines 210 and adjacent seventh and eighth bit lines 210. Therefore, the third and fourth bit lines 210 and the seventh and eighth bit lines 210 can be electrically connected in pairs. Since the bit line contacts 250 are positioned in the same manner as the first sense amplifier SA1, odd-numbered bit line pairs connected to the second sense amplifier SA2 can also be electrically connected. Therefore, interference between bit lines 210 can be reduced, and noise can be improved.

[0069] Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A and Figure 22B These are cross-sectional and rear views illustrating methods of manufacturing semiconductor memory devices according to some embodiments of the present disclosure.

[0070] More in detail, Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A and Figure 22A It corresponds to Figure 1 The cross-sectional view along line A-A' illustrates a method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure. Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 18B , Figure 19B , Figure 20B , Figure 21B and Figure 22B It corresponds to Figure 1 The cross-sectional view along line B-B' illustrates a method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure. Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C and Figure 16C It corresponds to Figure 1 The rear view illustrates a method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure.

[0071] refer to Figures 10A to 10CA first substrate 100 can be fabricated. The first substrate 100 can be, for example, a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The first substrate 100 can have a first surface 100a and a second surface 100b facing the first surface 100a (i.e., opposite to the first surface 100a).

[0072] A patterning process can be performed on the first surface 100a of the first substrate 100 to form a first trench TCH1. When viewed in a plane, the first trench TCH1 can extend from the first surface 100a toward the second surface 100b and can extend in a third direction D3 perpendicular to the first surface 100a. Next, a second gate insulating film 153a can be conformally formed on the first surface 100a of the first substrate 100 and on the inner surface of the first trench TCH1. The second gate insulating film 153a can be formed by at least one of an oxidation process or a deposition process.

[0073] refer to Figures 11A to 11C A portion of the second gate insulating film 153a can be etched back, thus forming a second gate insulating pattern 153 on the inner wall of the first trench TCH1. When viewed in a plane, the second gate insulating pattern 153 extends in the third direction D3. A first cover film can be formed on the lower surfaces of the second gate insulating pattern 153 and the first trench TCH1, and a portion of the first cover film can be removed to form a first cover pattern 141. The first cover pattern 141 can be formed by an etch-back process.

[0074] A second gate electrode film can be formed on the first cover pattern 141, the second gate insulating pattern 153, and the first surface 100a of the first substrate 100, to be located in the first trench TCH1 (e.g., filling the first trench TCH1). Subsequently, an etching process can be performed on the second gate electrode film to form the second gate electrode 151. The etching process can be an etch-back process. When viewed in a planar manner, the second gate electrodes 151 can be disposed between the second gate insulating patterns 153, and each of the second gate electrodes 151 can extend in a third direction D3.

[0075] A second cover film can be formed on the second gate insulating pattern 153 and the second gate electrode 151 to be located in the first trench TCH1 (e.g., filling the first trench TCH1). An etching process can be performed on the second cover film to expose the first substrate 100. The etching process can be performed by a chemical mechanical polishing (CMP) process. Thus, a second cover pattern 143 can be formed. Each second cover pattern in the second cover pattern 143 can be formed between the second gate insulating pattern 153 and the second gate electrode 151 present in each first trench in the first trench TCH1.

[0076] refer to Figures 12A to 12C A patterning process can be performed on the first surface 100a of the first substrate 100 to form a second trench TCH2. When viewed in a planar plane, the second trench TCH2 can extend from the first surface 100a toward the second surface 100b and can extend in a third direction D3 perpendicular to the first surface 100a. When viewed in a planar plane, the second trench TCH2 can be formed between spaced-apart second gate insulating patterns 153 and spaced-apart second gate electrodes 151. Therefore, a preliminary vertical semiconductor pattern 110a can be formed. When viewed in a planar plane, the preliminary vertical semiconductor pattern 110a can extend in a third direction D3 perpendicular to the first surface 100a.

[0077] refer to Figures 13A to 13C After an etch mask (not shown) is formed (e.g., covering and / or overlapping the portions) on portions of the initial vertical semiconductor pattern 110a, the second gate insulating pattern 153, and the second cover pattern 143, a patterning process can be performed on the first surface 100a of the first substrate 100 to form the vertical semiconductor pattern 110. When viewed in a plane, each of the vertical semiconductor patterns 110 may extend in a first direction D1, and the vertical semiconductor patterns 110 may be spaced apart from each other. In some embodiments, when viewed in a plane, the vertical semiconductor patterns 110 may have a zigzag arrangement or a honeycomb arrangement.

[0078] refer to Figures 14A to 14C A first gate insulating film 133a can be conformally formed on the first surface 100a of the first substrate 100, the vertical semiconductor pattern 110, the second gate insulating pattern 153, and the inner surface of the second trench TCH2. The first gate insulating film 133a can be formed by at least one of an oxidation process or a deposition process.

[0079] refer to Figures 15A to 15C An etch-back process can be performed on a portion of the first gate insulating film 133a, and thus, the first gate insulating pattern 133 can be formed on one side surface of the second gate insulating pattern 153, on the first side surface of the vertical semiconductor pattern 110, and on the inner wall of the second trench TCH2. When viewed in a plane, the first gate insulating pattern 133 can be located on the first side surface of the vertical semiconductor pattern 110 (e.g., it can cover the first side surface and / or overlap with the first side surface), and can extend in the third direction D3.

[0080] A third cover film can be formed on the lower surface of the first gate insulating pattern 133 and the second trench TCH2, and a portion of the third cover film can be removed to form the third cover pattern 145. The third cover pattern 145 can be formed by an etch-back process.

[0081] A first gate electrode film 131a can be conformally formed on the third cover pattern 145, the first gate insulating pattern 133, and the first surface 100a of the first substrate 100. A separator film 139a can then be formed on the first gate electrode film 131a. Therefore, the separator film 139a can be located in the second trench TCH2 (e.g., it can fill the second trench TCH2). The first gate electrode film 131a and the separator film 139a can be formed by at least one of an oxidation process or a deposition process.

[0082] refer to Figures 16A to 16C An etching process can be performed on the first surface 100a of the first substrate 100 to form a first gate electrode 131 and a partition pattern 139. The etching process can be an etch-back process. Each of the partition patterns 139 can be disposed between the first gate electrode 131 to electrically isolate the first gate electrode 131. When viewed in a plane, the first gate electrode 131 and the partition pattern 139 can be disposed between a first gate insulating pattern 133, and each of the first gate electrode 131 and the partition pattern 139 can extend in a third direction D3.

[0083] A fourth capping layer can be formed on the first gate insulating pattern 133, the first gate electrode 131, and the separator pattern 139 to be located in the second trench TCH2 (e.g., filling the second trench TCH2). An etching process can be performed on the fourth capping layer to expose the first substrate 100. The etching process can be performed by a chemical mechanical polishing (CMP) process. Thus, a fourth capping pattern 147 can be formed. Each of the fourth capping patterns 147 can be formed between the first gate insulating patterns 133 present in each second trench in the second trench TCH2 and formed on the first gate electrode 131 and the separator pattern 139.

[0084] Subsequently, an ion implantation process can be performed at the upper end of each of the vertical semiconductor patterns 110 to form a first source / drain region SD1. The upper end of the vertical semiconductor pattern 110 can be located at a horizontal height (e.g., relative to the second surface 100b of the first substrate 100) that is higher than the horizontal height of the first gate electrode 131 and the second gate electrode 151.

[0085] In the following text, unless otherwise stated, in the operation of a method for manufacturing a semiconductor memory device according to some embodiments of this disclosure, corresponding to Figure 1 The rear view is largely the same as the rear view of Figure 16 C.

[0086] refer to Figure 17A and Figure 17BA storage electrode 311 can be formed on the upper surface of the vertical semiconductor pattern 110, and a capacitor dielectric film 313 can be formed on the surface of the storage electrode 311, conformally extending (e.g., conformally covering and / or overlapping). Next, a plate electrode 315 can be formed on the capacitor dielectric film 313. The sequentially stacked storage electrode 311 and capacitor dielectric film 313 can together with the plate electrode 315 form a capacitor 310.

[0087] refer to Figure 18A and Figure 18B After forming the first interlayer insulating film 331 on the capacitor 310, a first bonding film 351 can be formed on the first interlayer insulating film 331.

[0088] Furthermore, a second bonding film 353 can be formed on the second substrate 300, and after this assembly is inverted, the second bonding film 353 and the first bonding film 351 can come into contact with each other to bond the first substrate 100 and the second substrate 300 to each other.

[0089] refer to Figure 19A and Figure 19B The first substrate 100 and the second substrate 300, which are joined together, can be inverted. In other words, Figure 18A and Figure 18B The structure shown can be inverted (i.e., flipped). Thereafter, the second surface 100b of the first substrate 100 can be polished to expose the vertical semiconductor pattern 110. In some embodiments, the second surface 100b of the first substrate 100 can be polished using a chemical mechanical polishing (CMP) process. In some embodiments, the first substrate 100 can be removed using a CMP process, but this disclosure is not limited thereto.

[0090] An ion implantation process can be performed at the lower end of each of the vertical semiconductor patterns 110 to form a second source / drain region SD2. Therefore, a channel region CA can be defined between the first source / drain region SD1 and the second source / drain region SD2.

[0091] refer to Figure 20A and Figure 20B A buried conductive film 211a can be formed on the vertical semiconductor pattern 110 (e.g., on the second source / drain region SD2). Next, a contact film 213a, a metal film 215a, and a hard mask film 217a can be sequentially formed on the buried conductive film 211a. The buried conductive film 211a, contact film 213a, metal film 215a, and hard mask film 217a can be formed by at least one of an oxidation process or a deposition process.

[0092] refer to Figure 1 , Figure 21A and Figure 21BA mask pattern (not shown) having a line shape extending in the second direction D2 can be formed on the hard mask film 217a, and the hard mask film 217a, metal film 215a, contact film 213a, and buried conductive film 211a can be anisotropically etched sequentially using the mask pattern to form the hard mask pattern 217, metal pattern 215, contact pattern 213, and buried conductive pattern 211, respectively. Therefore, a third trench TCH3 extending from the vertical semiconductor pattern 110 and / or the first gate insulating pattern 133 can be formed. As a result, bit lines 210 extending along the second direction D2 can be formed. Each bit line 210 may include a buried conductive pattern 211, a contact pattern 213, a metal pattern 215, and a hard mask pattern 217. When viewed in a plane, the bit lines 210 can be spaced apart from each other in the third direction D3 by the third trench TCH3.

[0093] refer to Figures 1 to 3 , Figure 22A and Figure 22B After forming bit lines 210, an insulating pattern 219 can be conformally formed on the third trench TCH3. That is, the insulating pattern 219 can be conformally formed on the second surface 210b of the bit line 210, the upper surface of the first gate insulating pattern 133, and the upper surface of the vertical semiconductor pattern 110. The thickness of the insulating pattern 219 can be less than half the spacing between adjacent bit lines 210. Subsequently, a dielectric film 230 can be formed on the insulating pattern 219 to be located in the third trench TCH3 (e.g., filling the third trench TCH3). That is, the dielectric film 230 can be disposed on the second surface 210b of the bit line 210 and can be located in the space between the bit lines 210 (e.g., filling the space). The insulating pattern 219 and the dielectric film 230 can be formed by at least one of an oxidation process or a deposition process. In some embodiments, the second substrate 300, the second bonding film 353, and / or the first bonding film 351 may be removed, and the insulating pattern 219 and the dielectric film 230 may be removed after the formation of the insulating pattern 219 and the dielectric film 230. Figure 22A and Figure 22B The structure shown is inverted (i.e., flipped), but this disclosure is not limited thereto.

[0094] According to an example embodiment of this disclosure, different vertical semiconductor patterns can be connected to adjacent bit lines so that adjacent bit lines are not activated simultaneously. In other words, a vertical semiconductor pattern connected to an even-numbered bit line between adjacent odd-numbered bit lines can be laterally offset from a vertical semiconductor pattern connected to an odd-numbered bit line. Therefore, even when the spacing between bit lines is reduced, coupling phenomena occurring between adjacent bit lines without forming a shielding pattern can be improved. As a result, parasitic capacitance of the bit lines can be reduced, the process can be simplified, and noise can be improved.

[0095] Furthermore, the semiconductor memory device according to an example embodiment of this disclosure may include a first sense amplifier and a second sense amplifier, the first sense amplifier being connected to even-numbered bit lines and the second sense amplifier being connected to odd-numbered bit lines. When one of the adjacent bit lines is activated during operation of the semiconductor memory device, the other adjacent bit line is pre-charged. Therefore, coupling phenomena that occur when both adjacent bit lines are activated can be reduced. As a result, parasitic capacitance of the bit lines can be reduced, and noise can be improved.

[0096] As used herein, the terms “comprising,” “including,” “containing,” “comprising,” “having,” “containing,” and any other variations thereof specify the presence of the stated features, steps, operations, elements, components, and / or groups, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Furthermore, it should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. Rather, these terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Moreover, as used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0097] Although the present disclosure has been described above with reference to exemplary embodiments thereof, those skilled in the art will understand that the disclosure may be modified and altered in various ways without departing from the scope of the disclosure as set forth in the appended claims.

[0098] Therefore, the technical scope of this disclosure should not be limited to what is described in the detailed description of the specification, but should be defined by the appended claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A vertical semiconductor pattern extending in a first direction; Multiple bit lines electrically connected to the lower surface of the vertical semiconductor pattern, each of the bit lines extending in a second direction perpendicular to the first direction; and A plurality of first gate structures are located on a first side surface of the vertical semiconductor pattern, each of the first gate structures extending upward in a third direction, the third direction being perpendicular to the first direction and intersecting with the second direction. The bit lines include odd-numbered bit lines and even-numbered bit lines that alternately arrange themselves along the third direction, and Wherein, the first vertical semiconductor pattern electrically connected to the even-numbered bit line in the vertical semiconductor pattern is laterally offset from the second vertical semiconductor pattern electrically connected to the odd-numbered bit line in the vertical semiconductor pattern.

2. The semiconductor memory device according to claim 1, wherein, The bit line has a first surface and a second surface, the first surface being electrically connected to the lower surface of the vertical semiconductor pattern, and the second surface being opposite to the first surface. The semiconductor memory device further includes a dielectric film located on the second surface of the bit line and between adjacent bit lines.

3. The semiconductor memory device according to claim 2, further comprising: A substrate, the substrate being located on the second surface of the bit line; as well as A first sense amplifier and a second sense amplifier, wherein the first sense amplifier and the second sense amplifier are at least partially located in the substrate. Wherein, the first sense amplifier is electrically connected to the even-numbered bit line, and The second readout amplifier is electrically connected to the odd-numbered bit line.

4. The semiconductor memory device according to claim 3, wherein, When the semiconductor memory device is operated, the first sense amplifier is configured to activate the even-numbered bit lines, and When the even-numbered bit line is activated, the odd-numbered bit line is configured to be pre-charged.

5. The semiconductor memory device according to claim 3, wherein, When the semiconductor memory device is operated, the second sense amplifier is configured to activate the odd-numbered bit lines, and When the odd-numbered bit line is activated, the even-numbered bit line is configured to be pre-charged.

6. The semiconductor memory device according to claim 2, further comprising: A substrate, the substrate being located on the second surface of the bit line; as well as A first sense amplifier and a second sense amplifier, wherein the first sense amplifier and the second sense amplifier are at least partially located in the substrate. The adjacent bit lines in the bit lines are grouped into pairs, and the pairs are arranged alternately along the third direction as odd-numbered bit line pairs and even-numbered bit line pairs. The first and second sense amplifiers include bit line contacts that electrically connect the distal ends of adjacent bit lines in corresponding pairs of the first and second sense amplifiers. Wherein, the first sense amplifier is electrically connected to the even-numbered bit line pair, and The second readout amplifier is electrically connected to the odd-numbered bit line pair.

7. The semiconductor memory device according to claim 1, further comprising: A capacitor structure is located on the upper surface of the vertical semiconductor pattern and is electrically connected to the vertical semiconductor pattern. Wherein, the first vertical semiconductor pattern in the vertical semiconductor pattern is shifted relative to the second vertical semiconductor pattern in the vertical semiconductor pattern in the second direction.

8. The semiconductor memory device according to claim 1, further comprising: A second gate structure is located on a second side surface of the vertical semiconductor pattern opposite to the first side surface and extends upward on the third side surface.

9. The semiconductor memory device according to claim 8, wherein, Each of the first gate structures includes: First gate insulating pattern; and A first gate electrode is located on a side surface of the first gate insulating pattern; and Each of the second gate structures includes: A second gate electrode, the second gate electrode extending upward in the third party; and The second gate insulating pattern is located on the opposite side surface of the second gate electrode and is in contact with at least one of the second side surfaces of the vertical semiconductor pattern.

10. The semiconductor memory device according to claim 9, wherein, The first gate electrode and the second gate electrode comprise metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, polycrystalline silicon doped with impurities, or a combination thereof.

11. The semiconductor memory device according to claim 1, wherein, Each of the vertical semiconductor patterns includes a channel region, a first source / drain region, and a second source / drain region. The first source / drain region is located at the top of each of the vertical semiconductor patterns. Wherein, the second source / drain region is located at the lower end of each of the vertical semiconductor patterns, and The channel region is located between the first source / drain region and the second source / drain region.

12. A semiconductor memory device, the semiconductor memory device comprising: A vertical semiconductor pattern extending in a first direction; Multiple bit lines are located on the lower surface of the vertical semiconductor pattern, each of the bit lines extending in a second direction perpendicular to the first direction; as well as A plurality of first gate structures are located on a first side surface of the vertical semiconductor pattern, each of the first gate structures extending upward in a third direction, the third direction being perpendicular to the first direction and intersecting with the second direction. The bit lines include odd-numbered bit lines and even-numbered bit lines that alternately arrange themselves along the third direction. The first gate structure includes odd-numbered first gate structures and even-numbered first gate structures arranged alternately along the second direction. Wherein, the first vertical semiconductor pattern adjacent to the odd-numbered first gate structure in the vertical semiconductor pattern is electrically connected to the odd-numbered bit line, and The second vertical semiconductor pattern, which is adjacent to the even-numbered first gate structure in the vertical semiconductor pattern, is electrically connected to the even-numbered bit line.

13. The semiconductor memory device of claim 12, further comprising: A dielectric film is located on the lower surface of the bit line and between adjacent bit lines in the bit line; as well as A capacitor structure located on the upper surface of the vertical semiconductor pattern and electrically connected to the vertical semiconductor pattern.

14. The semiconductor memory device of claim 12, further comprising: A second gate structure is located on a second side surface of the vertical semiconductor pattern opposite to the first side surface and extends upward on the third side surface.

15. The semiconductor memory device of claim 14, wherein, Each of the first gate structures includes: First gate insulating pattern; and The first gate electrode is located on the side surface of the first gate insulating pattern, and Each of the second gate structures includes: A second gate electrode, the second gate electrode extending upward in the third party; and The second gate insulating pattern is located on the opposite side surface of the second gate electrode and is in contact with at least one of the second side surfaces of the vertical semiconductor pattern.

16. The semiconductor memory device according to claim 12, wherein, When viewed on a plane, the first vertical semiconductor pattern and the second vertical semiconductor pattern in the vertical semiconductor pattern are arranged in a sawtooth shape along the third direction.

17. The semiconductor memory device of claim 12, further comprising: A substrate, the substrate being located on the lower surface of the bit line; as well as A first sense amplifier and a second sense amplifier, wherein the first sense amplifier and the second sense amplifier are at least partially located in the substrate. Wherein, the first sense amplifier is electrically connected to the even-numbered bit line, and The second readout amplifier is electrically connected to the odd-numbered bit line.

18. The semiconductor memory device according to claim 17, wherein, When the semiconductor memory device is operated, the first sense amplifier is configured to activate the even-numbered bit lines, and When the even-numbered bit line is activated, the odd-numbered bit line is configured to be pre-charged.

19. The semiconductor memory device according to claim 17, wherein, When the semiconductor memory device is operated, the second sense amplifier is configured to activate the odd-numbered bit lines, and When the odd-numbered bit line is activated, the even-numbered bit line is configured to be pre-charged.

20. A semiconductor memory device, the semiconductor memory device comprising: A vertical semiconductor pattern extending in a first direction; Multiple bit lines are located on the lower surface of the vertical semiconductor pattern, each of the bit lines extending in a second direction perpendicular to the first direction; as well as A plurality of first gate structures are located on a first side surface of the vertical semiconductor pattern, each of the first gate structures extending upward in a third direction, the third direction being perpendicular to the first direction and intersecting with the second direction. The bit lines include odd-numbered bit lines and even-numbered bit lines that alternately arrange themselves along the third direction. The first gate structure comprises 4N first gate structures arranged sequentially along the second direction, where N is a natural number. Wherein, the first vertical semiconductor pattern adjacent to the 4N-3rd and 4N-2th first gate structures in the first gate structure is electrically connected to the odd-numbered bit lines, and Wherein, the second vertical semiconductor pattern in the vertical semiconductor pattern, which is adjacent to the 4N-1th first gate structure and the 4Nth first gate structure in the first gate structure, is electrically connected to the even-numbered bit line.

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