Semiconductor device
By introducing a second dielectric layer and an oxide layer into the dielectric layer, the short-circuit problem in semiconductor devices caused by dielectric layer gaps is solved, resulting in a more stable isolation structure and improved performance.
Patent Information
- Application Number
- CN202511881205.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-04-07
- Publication Date
- 2026-03-03
AI Technical Summary
When depositing a dielectric layer in the groove of a semiconductor structure, gaps can easily form, leading to short circuits in semiconductor devices during subsequent processes and affecting performance.
By introducing a second dielectric layer and an oxide layer into the dielectric layer, gaps are eliminated or reduced, forming a stable isolation structure and improving device performance.
Effectively eliminates or reduces gaps in the dielectric layer, improving the stability and performance of semiconductor devices.
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Figure CN121604411A_ABST
Abstract
Description
[0001] This application is a divisional application. The original application has the application number 202310369444.1 and the original application date is April 7, 2023. The entire contents of the original application are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, specifically to a semiconductor device. Background Technology
[0003] In the process of forming semiconductor structures, dielectric layers and other structures are often deposited in deep trenches. The inventors discovered that when depositing these structures within the trenches, the dielectric layer forms along the sidewalls and gradually closes towards the center, thus easily resulting in gaps in the middle of the formed structure. Figure 1a and Figure 1b The study focuses on semiconductor devices such as dynamic random access memory (DRAM), among which... Figure 1a This is a plan view of a dynamic random access memory. Figure 1b for Figure 1a A cross-sectional view along the BB' direction in the middle; During the research process, the inventors discovered that if a gap is formed in the middle of the dielectric layer in the groove used to form the dielectric layer, it is easy to cause a short circuit in the semiconductor structure in the subsequent manufacturing process, thereby affecting the performance of the semiconductor device. Summary of the Invention
[0004] This application provides semiconductor devices to improve their performance.
[0005] In a first aspect, embodiments of this application provide a semiconductor device, including:
[0006] Substrate;
[0007] Word lines are located within the substrate;
[0008] An isolation structure, located on the substrate and corresponding to the word line, the isolation structure includes:
[0009] A first dielectric layer, the first dielectric layer including a gap;
[0010] A first oxide layer conformally covers the gap in the first dielectric layer. The first oxide layer defines a recess, which includes an upper recess and a lower recess, wherein the lower recess is located between the gaps and the upper recess is located on top of the first dielectric layer.
[0011] The second dielectric layer is located on the first oxide layer and within the upper recess.
[0012] The aforementioned semiconductor device utilizes a second dielectric layer to eliminate gaps in the isolation structure, or minimizes gaps in the first isolation structure, resulting in more stable performance and thus improving the performance of the semiconductor device.
[0013] Optionally, the width of the lower recess is less than or equal to the width of the upper recess.
[0014] Optionally, the word line includes a top mask cover layer that is in direct contact with the bottom of the isolation structure.
[0015] Optionally, the first dielectric layer and the second dielectric layer comprise the same material.
[0016] Optionally, the first dielectric layer and the second dielectric layer comprise silicon nitride.
[0017] Optionally, the semiconductor device further includes:
[0018] A buffer layer is located on the substrate, in direct contact with the substrate, and in direct contact with the side of the isolation structure.
[0019] Optionally, the semiconductor device further includes:
[0020] A sacrificial layer is located on the substrate and defines the isolation structure.
[0021] Secondly, embodiments of this application provide a semiconductor device, including:
[0022] Substrate;
[0023] Word lines are located within the substrate;
[0024] An isolation structure, located on the substrate and corresponding to the word line, the isolation structure includes:
[0025] A first dielectric layer, the first dielectric layer including a gap;
[0026] A first oxide layer conformally covers the gap in the first dielectric layer, and the first oxide layer defines a recess;
[0027] The second dielectric layer is located on the first oxide layer and within the recess;
[0028] The second oxide layer is located on the second dielectric layer.
[0029] The aforementioned semiconductor device utilizes a second dielectric layer to eliminate gaps in the isolation structure or to minimize gaps in the first isolation structure, and utilizes a second oxide layer to provide stability to the isolation structure, thereby enabling the semiconductor device to have more stable performance and thus improving the performance of the semiconductor device.
[0030] Optionally, the recess includes an upper recess and a lower recess, wherein the lower recess is located between the gaps and the upper recess is located on top of the first dielectric layer;
[0031] The second dielectric layer is located within the upper recess.
[0032] Optionally, the width of the lower recess is less than or equal to the width of the upper recess.
[0033] Optionally, the word line includes a top mask cover layer that is in direct contact with the bottom of the isolation structure.
[0034] Optionally, the first dielectric layer and the second dielectric layer comprise the same material.
[0035] Optionally, the first dielectric layer and the second dielectric layer comprise silicon nitride.
[0036] Optionally, the semiconductor device further includes:
[0037] A buffer layer is located on the substrate, in direct contact with the substrate, and in direct contact with the side of the isolation structure.
[0038] Optionally, the semiconductor device further includes:
[0039] A sacrificial layer is located on the substrate and defines the isolation structure.
[0040] Optionally, the top surface of the second oxide layer is aligned with the top surface of the sacrificial layer. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1a and Figure 1b A schematic diagram of the semiconductor structure during the inventor's research process;
[0043] Figure 2 This is a flowchart of a method for forming a semiconductor device according to an embodiment of this application;
[0044] Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 3e , Figure 3f , Figure 3g , Figure 3h and Figure 3i This is a schematic diagram of the structure obtained in each step of an embodiment of this application;
[0045] Figure 4 This is a schematic diagram of the structure obtained by the relevant steps in one embodiment of this application;
[0046] Figure 5a and Figure 5b This is a schematic diagram of the structure obtained by the relevant steps in one embodiment of this application;
[0047] Figure 6a , Figure 6b and Figure 6c This is a schematic diagram of the structure obtained by the relevant steps in one embodiment of this application. Detailed Implementation
[0048] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.
[0049] This application provides a method for forming a semiconductor device in its first aspect, with reference to... Figure 2 As shown, the forming method includes steps S110 to S180.
[0050] S110, Reference Figure 3a As shown, a substrate 110 is provided.
[0051] The substrate 110 may include semiconductor materials, such as silicon substrate, silicon-germanium substrate, or silicon-on-insulator substrate, etc. An isolation region 111a and multiple active regions 111b defined by the isolated region 111a are formed within the substrate 110. The active regions 111b can form various functional regions within the substrate 110. Optionally, multiple buried word lines 112 may also be formed within the substrate 110, and the multiple buried word lines 112 can cut through each active region 111b.
[0052] S120, Reference Figure 3b As shown, a sacrificial layer 121 is formed on the substrate 110. This step can be performed by a deposition process to form the sacrificial layer 121 on the surface of the substrate 110.
[0053] S130, Reference Figure 3c As shown, a first etching process is performed to remove part of the sacrificial layer 121, forming multiple first grooves 122.
[0054] S140, Reference Figure 3dAs shown, a first dielectric layer 123 is formed, covering the sacrificial layer 121 and filling a plurality of first grooves 122. This step can be performed using a deposition process to form the first dielectric layer 123, and the material of the first dielectric layer 123 may include dielectric materials such as silicon oxide and / or silicon nitride. Specifically, the first dielectric layer 123 within the first groove 122 needs to be deposited along the sidewall of the first groove 122. During this deposition process, gaps are easily formed in the middle of the first dielectric layer 123 within the first groove 122.
[0055] S150, Reference Figure 3e As shown, a second etching process is performed to remove the first dielectric layer outside the multiple first grooves 122 to form a first isolation structure 124, in which there are gaps 125.
[0056] S160, Reference Figure 3f and Figure 3g As shown, a third etching process is performed to etch multiple first isolation structures 124 to remove part of the dielectric material at the top of the multiple first isolation structures 124 and expose the gap 125.
[0057] Specifically, the gap 125 may include multiple recesses. For example, the third etching process may include forming multiple recesses in the first isolation structure 124, the multiple recesses including an upper recess 125a and a lower recess 125b, wherein the lower recess 125b is formed between the gaps and the upper recess 125a is formed on the top of the first isolation structure 124.
[0058] Optionally, the width of the lower recess 125b is less than or equal to the width of the upper recess 125a. The lower recess 125b may include an elongated slit; the upper recess 125a may be triangular (e.g., Figure 3f As shown), the upper depression 125a can also be semi-elliptical (as shown). Figure 3g (As shown).
[0059] S170, Reference Figure 3h As shown, a second dielectric layer 126 is formed, covering a plurality of first isolation structures 124 and a sacrificial layer 121. The second dielectric layer 126 fills at least a portion of the space in each gap 125 to minimize or eliminate the gaps 125 in the first isolation structures 124. This step can be performed using a deposition process to form the second dielectric layer 126, and the material of the second dielectric layer 126 may include dielectric materials such as silicon oxide and / or silicon nitride.
[0060] Optionally, the first dielectric layer 123 and the second dielectric layer 126 may be made of the same material, so that the materials of each part of the subsequently formed second isolation structure 127 are the same, which can simplify the corresponding formation process and make the second isolation structure 127 including the first isolation structure 124 have more stable performance.
[0061] Optionally, the first dielectric layer 123 and the second dielectric layer 126 comprise silicon nitride.
[0062] S180, Reference Figure 3i As shown, a fourth etching process is performed to remove the top of the second dielectric layer 126 until the sacrificial layer 121 is exposed, forming a new isolation structure 127a on the surface of the first isolation structure 124. The new isolation structure 127a and the first isolation structure 124 below it constitute the second isolation structure 127 in the first groove 122. The gaps 125 in the second isolation structure 127 are eliminated or effectively reduced, resulting in more stable performance.
[0063] The above-described semiconductor device formation method involves a second etching process to remove the first dielectric layer outside multiple first grooves 122, forming a first isolation structure 124 with gaps 125. A third etching process is then performed to etch the multiple first isolation structures 124 to remove part of the dielectric material at the top of the multiple first isolation structures 124, exposing the gaps 125 and forming a second dielectric layer 126 that fills at least part of the space of each gap 125, so that the gaps 125 in the first isolation structures 124 are as small as possible or eliminated. Then, a fourth etching process is performed to remove the top of the second dielectric layer 126 until the sacrificial layer 121 is exposed, forming a second isolation structure 127. At this time, the gaps 125 in the second isolation structure 127 are eliminated or effectively reduced, resulting in more stable performance and thus improving the performance of the obtained semiconductor device.
[0064] In one embodiment, before forming the second dielectric layer 126, the formation method further includes: referencing Figure 4 As shown, a first oxide layer 128 is formed to conformally cover the recess 125, so that the recess 125 is located between the first oxide layers 128. This makes the surface of the first isolation structure 124, i.e., the bottom of the recess 125, smoother, which can improve the quality of the subsequently deposited second dielectric layer 126. This allows the second dielectric layer 126 to fill as many gaps 125 as possible, thereby eliminating gaps 125 or minimizing them. Optionally, the first oxide layer 128 can be made of a stable oxide material such as silicon oxide. Optionally, the first oxide layer 128 can be formed by a thermal oxidation process.
[0065] Optionally, the fourth etching process includes: [reference] Figure 5a and Figure 5b As shown, a second oxide layer 129 is formed on the surface of the second isolation structure 127 to further improve the stability of the isolation structure within the first groove 122. Optionally, the second oxide layer 129 can be made of a stable oxide material such as silicon oxide. Optionally, the second oxide layer 129 can be formed by a thermal oxidation process.
[0066] Optionally, such as Figure 5b As shown, the surface of the second oxide layer 129 can be aligned with the surface of the sacrificial layer 121 to simplify subsequent processes and improve the quality of the structure obtained by subsequent processes.
[0067] In one embodiment, the method further includes, prior to forming the sacrificial layer 121: a reference Figure 6a As shown, multiple buried word lines 112 are formed in the substrate 110, and the multiple buried word lines 112 include a top mask capping layer 112a; a buffer layer 131 is formed, and the buffer layer 131 covers the substrate 110 and the multiple buried word lines 112.
[0068] In one example, refer to Figure 6b As shown, the bottom of the multiple first grooves 122 formed by the first etching process is lower than the buffer layer 131, so that the first grooves 122 can expose the mask cover layer 112a on top of the buried word line 112, so that the structure subsequently formed in the first grooves 122 can directly contact the mask cover layer 112a on top of the buried word line 112.
[0069] In one example, refer to Figure 6c As shown, the bottom of the multiple first isolation structures 124 formed by the second etching process is in direct contact with the mask cover layer 112a on top of the multiple buried word lines 112.
[0070] In one example, the bottom of the plurality of second isolation structures 127 formed by the fourth etching process is in direct contact with the mask capping layer 112a on top of the plurality of buried word lines 112.
[0071] In one example, the sacrificial layer 121 can also be removed to form a second groove between the various second isolation structures 127, and a contact structure can be formed in the second groove to electrically lead out the corresponding active region 111b.
[0072] The above method for forming a semiconductor device involves a second etching process to remove the first dielectric layer outside multiple first grooves 122, forming a first isolation structure 124 with gaps 125. A third etching process is then performed to etch the multiple first isolation structures 124 to remove part of the dielectric material at the top of the multiple first isolation structures 124, exposing the gaps 125 and forming a second dielectric layer 126 that fills at least part of the space of each gap 125, thereby eliminating the gaps 125 in the first isolation structures 124 or making the gaps 125 in the first isolation structures 124 as small as possible. Then, a fourth etching process is performed to remove the top of the second dielectric layer 126 until the sacrificial layer 121 is exposed, forming a second isolation structure 127. At this point, the gaps 125 in the second isolation structure 127 are eliminated or effectively reduced, resulting in more stable performance and thus improving the performance of the obtained semiconductor device.
[0073] This application provides a semiconductor device in a second aspect, which can be formed using the semiconductor device formation method described above. (Reference) Figure 3i As shown, the semiconductor device may include:
[0074] Substrate 110;
[0075] An isolation structure located on the substrate surface, the isolation structure including a second isolation structure 127, wherein gaps in the second isolation structure 127 are eliminated or reduced.
[0076] Optionally, if multiple buried word lines 112 are formed in the substrate 110, the second isolation structure 127 is located above the buried word lines 112, and the bottom of the second isolation structure 127 is in direct contact with the mask cover layer 112a at the top of the buried word lines 112.
[0077] The semiconductor device described above can be formed using the semiconductor device formation method of any of the above embodiments, and has all the beneficial effects of the semiconductor device formation method of any of the above embodiments, which will not be repeated here.
[0078] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., is functionally equivalent to it), even if it is not necessarily structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of this specification shown herein.
[0079] That is, the above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application’s specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
[0080] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0081] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.
Claims
1. A semiconductor device, characterized in that, include: Substrate; Word lines are located within the substrate; An isolation structure, located on the substrate and corresponding to the word line, the isolation structure includes: A first dielectric layer, the first dielectric layer including a gap; A first oxide layer conformally covers the gap in the first dielectric layer. The first oxide layer defines a recess, which includes an upper recess and a lower recess, wherein the lower recess is located between the gaps and the upper recess is located on top of the first dielectric layer. The second dielectric layer is located on the first oxide layer and within the upper recess.
2. The semiconductor device according to claim 1, characterized in that, The width of the lower recess is less than or equal to the width of the upper recess.
3. The semiconductor device according to claim 1, characterized in that, The letter line includes a top mask cover layer that is in direct contact with the bottom of the isolation structure.
4. The semiconductor device according to any one of claims 1-3, characterized in that, The first dielectric layer and the second dielectric layer comprise the same material.
5. The semiconductor device according to claim 4, characterized in that, The first dielectric layer and the second dielectric layer comprise silicon nitride.
6. The semiconductor device according to any one of claims 1-3, characterized in that, The semiconductor device further includes: A buffer layer is located on the substrate, in direct contact with the substrate, and in direct contact with the side of the isolation structure.
7. The semiconductor device according to any one of claims 1-3, characterized in that, The semiconductor device further includes: A sacrificial layer is located on the substrate and defines the isolation structure.
8. A semiconductor device, characterized in that, include: Substrate; Word lines are located within the substrate; An isolation structure, located on the substrate and corresponding to the word line, the isolation structure includes: A first dielectric layer, the first dielectric layer including a gap; A first oxide layer conformally covers the gap in the first dielectric layer, and the first oxide layer defines a recess; The second dielectric layer is located on the first oxide layer and within the recess; The second oxide layer is located on the second dielectric layer.
9. The semiconductor device according to claim 8, characterized in that, The recess includes an upper recess and a lower recess, wherein the lower recess is located between the gaps and the upper recess is located on top of the first dielectric layer; The second dielectric layer is located within the upper recess.
10. The semiconductor device according to claim 9, characterized in that, The width of the lower recess is less than or equal to the width of the upper recess.
11. The semiconductor device according to any one of claims 8-10, characterized in that, The letter line includes a top mask cover layer that is in direct contact with the bottom of the isolation structure.
12. The semiconductor device according to any one of claims 8-10, characterized in that, The first dielectric layer and the second dielectric layer comprise the same material.
13. The semiconductor device according to claim 12, characterized in that, The first dielectric layer and the second dielectric layer comprise silicon nitride.
14. The semiconductor device according to any one of claims 8-10, characterized in that, The semiconductor device further includes: A buffer layer is located on the substrate, in direct contact with the substrate, and in direct contact with the side of the isolation structure.
15. The semiconductor device according to any one of claims 8-10, characterized in that, The semiconductor device further includes: A sacrificial layer is located on the substrate and defines the isolation structure.
16. The semiconductor device according to claim 15, characterized in that, The top surface of the second oxide layer is aligned with the top surface of the sacrificial layer.