Semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor device may include forming a lower mold structure on a substrate; forming a first molding structure on the lower molding structure, the first molding structure including first interlayer insulating layers and first sacrificial layers alternately stacked in a vertical direction; forming a first vertical channel hole to penetrate the first molding structure, the lower molding structure, and a portion of the substrate; and forming an active layer to cover a top surface of the first molding structure and to extend to an upper side surface of each of the first vertical channel holes. The active layer may include a horizontal portion covering a top surface of the first molded structure and a vertical portion covering an upper side surface of each of the first vertical channel holes, and the active layer may include a metal material.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0113033, filed with the Korean Intellectual Property Office on August 22, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a semiconductor device and an electronic system including the semiconductor device, and more particularly, to a non-volatile semiconductor memory device including a vertical channel structure, a method of manufacturing the non-volatile semiconductor memory device, and an electronic system including the non-volatile semiconductor memory device. Background Technology

[0003] Semiconductor devices capable of storing large amounts of data are needed as part of electronic systems. Higher integration levels of semiconductor devices are required to meet consumer demands for large data storage capacity, superior performance, and low cost. In the case of two-dimensional or planar semiconductor devices, their integration level is heavily influenced by the level of fine patterning technology, as it is primarily determined by the area occupied by a single memory cell. However, the extremely expensive process equipment required to improve pattern fineness sets a practical limit on increasing the integration level of two-dimensional or planar semiconductor devices. Therefore, three-dimensional semiconductor memory devices incorporating three-dimensionally arranged memory cells have recently been proposed. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device with improved electrical and reliability characteristics and a method for manufacturing the semiconductor device.

[0005] An embodiment of the present invention provides an electronic system including the semiconductor device.

[0006] According to embodiments of the present invention, a method of manufacturing a semiconductor device may include: forming a lower molding structure on a substrate; forming a first molding structure on the lower molding structure, the first molding structure including a first interlayer insulating layer and a first sacrificial layer alternately stacked in a vertical direction; forming a first vertical channel via to penetrate a portion of the substrate, the first molding structure, and the lower molding structure; and forming an active layer to cover the top surface of the first molding structure and extend to the upper surface of each of the first vertical channel vias. The active layer may include a horizontal portion covering the top surface of the first molding structure and a vertical portion covering the upper surface of each of the first vertical channel vias, and the active layer may include a metallic material.

[0007] According to an embodiment of the present invention, a method of manufacturing a semiconductor device may include: forming a first molding structure on a substrate, the first molding structure including a first interlayer insulating layer and a first sacrificial layer alternately stacked in a vertical direction; forming a first vertical channel via to penetrate the first molding structure; and forming an active layer to cover the top surface of the first molding structure and extend to the upper surface of the first vertical channel via. The active layer includes a horizontal portion covering the top surface of the first molding structure and a vertical portion covering the upper surface of each of the first vertical channel vias, and the width of the vertical portion, measured in a horizontal direction parallel to the top surface of the substrate, may increase with increasing distance from the substrate.

[0008] According to embodiments of the present invention, a method of manufacturing a semiconductor device may include: forming a first molding structure on a substrate to include a first interlayer insulating layer and a first sacrificial layer alternately stacked in a vertical direction; forming a first vertical channel via to penetrate a portion of the substrate and the first molding structure; forming an active layer to cover the top surface of the first molding structure and extend to the upper surface of each of the first vertical channel vias; forming a molding sacrificial layer on the active layer to fill the upper portion of each of the first vertical channel vias; forming a void in the remaining portion of each of the first vertical channel vias; and removing the active layer and the molding sacrificial layer from the top surface of the first molding structure. Following the first molding structure, a second molding structure is formed on the first molding structure to include a second interlayer insulating layer and a second sacrificial layer stacked alternately in a vertical direction; a second vertical channel hole is formed to penetrate the second molding structure, and each of the second vertical channel holes vertically overlaps each of the first vertical channel holes; a first stack is formed by filling the empty space formed by removing the first sacrificial layer to include a first interlayer insulating layer and a first gate electrode stacked alternately in a vertical direction; and a second stack is formed by filling the empty space formed by removing the second sacrificial layer to include a second interlayer insulating layer and a second gate electrode stacked alternately in a vertical direction. Attached Figure Description

[0009] Figure 1 This is a schematic diagram illustrating an electronic system including semiconductor devices according to an embodiment of the present invention.

[0010] Figure 2 This is a perspective view schematically illustrating an electronic system including semiconductor devices according to an embodiment of the present invention.

[0011] Figure 3 and Figure 4 They are respectively along Figure 2 The cross-sectional views taken by lines I-I' and II-II' are used to illustrate a semiconductor package including a semiconductor device according to an embodiment of the concept of the present invention.

[0012] Figure 5 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention.

[0013] Figure 6A and Figure 6B They are respectively along Figure 5 The cross-sectional views taken by lines A-A' and B-B' are used to illustrate a semiconductor device according to an embodiment of the concept of the present invention.

[0014] Figure 7A and Figure 7B This is a portion of a semiconductor device illustrating an embodiment of the concept according to the present invention (e.g., respectively). Figure 6A Enlarged cross-sectional views of “A” and “B”.

[0015] Figure 8 This is a portion of a semiconductor device illustrating an embodiment of the concept according to the present invention (e.g., Figure 6A Enlarged cross-sectional view of “B”.

[0016] Figure 9A , Figure 9B , Figures 10A to 10D , Figures 11A to 11H , Figures 12A to 12D as well as Figures 13 to 23 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0017] Figure 24 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention.

[0018] Figure 25A and Figure 25B They are respectively along Figure 24 The cross-sectional views taken by lines A-A' and B-B' are used to illustrate a semiconductor device according to an embodiment of the concept of the present invention. Detailed Implementation

[0019] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0020] Figure 1 This is a schematic diagram illustrating an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the present invention.

[0021] refer to Figure 1The electronic system 1000 may include a three-dimensional semiconductor memory device 1100 and a controller 1200 electrically connected to the three-dimensional semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or more three-dimensional semiconductor memory devices 1100, or an electronic device including the storage device. For example, the electronic system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical system, or a communication system equipped with at least one three-dimensional semiconductor memory device 1100.

[0022] The three-dimensional semiconductor memory device 1100 may be a non-volatile memory device (e.g., a three-dimensional NAND flash memory device described below). The three-dimensional semiconductor memory device 1100 may include a first region 1100F and a second region 1100S on the first region 1100F. For example, the first region 1100F may be located near the second region 1100S. The first region 1100F may be a peripheral circuit region including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second region 1100S may be a memory cell region including bit line BL, common source line CSL, word line WL, first lines LL1 and LL2, second lines UL1 and UL2, and a memory cell string CSTR between bit line BL and common source line CSL.

[0023] In the second region 1100S, each memory cell string CSTR may include first transistors LT1 and LT2 adjacent to the common source line CSL, second transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the first transistors LT1 and LT2 and the second transistors UT1 and UT2. According to embodiments, the number of first transistors LT1 and LT2 and the number of second transistors UT1 and UT2 may vary.

[0024] For example, each of the memory cell transistors (MCTs) may include a data storage element comprising a ferroelectric material. By using a data storage element comprising a ferroelectric material, a three-dimensional semiconductor memory device capable of operating with relatively low power and at a fast operating speed can be realized. The word line WL can serve as the gate electrode of the memory cell transistor (MCT). The voltage difference between the word line WL and the channel region of the memory cell transistor (MCT) can be adjusted to cause a change in the polarization of the dipoles of the ferroelectric material, and this can be used to perform data write or erase operations on the memory cell transistor (MCT).

[0025] In this embodiment, the first transistors LT1 and LT2 may include ground select transistors, and the second transistors UT1 and UT2 may include string select transistors. First lines LL1 and LL2 may serve as the gate electrodes of the first transistors LT1 and LT2, respectively. The word line WL may serve as the gate electrode of the memory cell transistor MCT. Second lines UL1 and UL2 may serve as the gate electrodes of the second transistors UT1 and UT2, respectively.

[0026] The common source line CSL, first lines LL1 and LL2, word line WL, and second lines UL1 and UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first region 1100F to the second region 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the first region 1100F to the second region 1100S.

[0027] In the first region 1100F, the decoder circuit 1110 and page buffer 1120 can be configured to perform control operations on at least one selected memory cell transistor (MCT). The decoder circuit 1110 and page buffer 1120 can be controlled by logic circuit 1130. The three-dimensional semiconductor memory device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output interconnects 1135 extending from the first region 1100F to the second region 1100S.

[0028] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. For example, the electronic system 1000 may include a plurality of three-dimensional semiconductor memory devices 1100, and in this case, the controller 1200 may control the plurality of three-dimensional semiconductor memory devices 1100.

[0029] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Based on specific firmware, processor 1210 can perform operations to control NAND controller 1220 and access three-dimensional semiconductor memory device 1100. NAND controller 1220 may include NAND interface 1221 for communicating with three-dimensional semiconductor memory device 1100. NAND interface 1221 can be used to send and receive control commands for controlling three-dimensional semiconductor memory device 1100, data to be written to or read from memory cell transistors (MCTs) of three-dimensional semiconductor memory device 1100, etc. Host interface 1230 can be configured to allow communication between electronic system 1000 and external host. If a control command is received from an external host through host interface 1230, processor 1210 can control three-dimensional semiconductor memory device 1100 in response to the control command.

[0030] Figure 2 This is a perspective view schematically illustrating an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the present invention.

[0031] refer to Figure 2 The electronic system 2000 may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, at least one semiconductor package 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 and interconnected with each other by setting interconnect patterns 2005 in the main substrate 2001.

[0032] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the pins in the connector 2006 may depend on the communication interface between the electronic system 2000 and the external host. In embodiments, the electronic system 2000 may communicate with the external host via one of the following interfaces: for example, Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI Fast), Serial Advanced Technology Attachment (SATA), Universal Flash Memory (UFS) M-PHY, etc. In embodiments, the electronic system 2000 may be driven by power supplied from the external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0033] The controller 2002 can be configured to control write or read operations on the semiconductor package 2003 and improve the operating speed of the electronic system 2000.

[0034] DRAM 2004 can be a buffer memory that alleviates the technical difficulties caused by the speed difference between the semiconductor package 2003, which acts as a data storage device, and an external host. In embodiments, DRAM 2004 in electronic system 2000 can act as a cache memory and can provide temporary storage space for data during various control operations performed on semiconductor package 2003. Where electronic system 2000 includes DRAM 2004, controller 2002 may also include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0035] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include: a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, adhesive layers 2300 respectively disposed on the bottom surface of the semiconductor chips 2200, connection structures 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 disposed on the package substrate 2100 to cover the semiconductor chips 2200 and the connection structures 2400.

[0036] The package substrate 2100 may be a printed circuit board including on-package pads 2130. Each of the semiconductor chips 2200 may include input / output pads 2210. Each of the input / output pads 2210 may correspond to... Figure 1 The input / output pads 1101. Each of the semiconductor chips 2200 may include a gate stack 3210 and a vertical channel structure 3220. Each of the semiconductor chips 2200 may include a three-dimensional semiconductor memory device, which will be described below.

[0037] In an embodiment, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 to the on-package pads 2130. In each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner and may be electrically connected to the on-package pads 2130 of the package substrate 2100. In an embodiment, the semiconductor chips 2200 in each of the first semiconductor package 2003a and the second semiconductor package 2003b may be electrically connected to each other via through-silicon vias (TSVs) instead of via the connection structure 2400 provided in the form of bonding wires.

[0038] In this embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on an insertion substrate fabricated independently of the main substrate 2001 and may be interconnected with each other via interconnects disposed in the insertion substrate.

[0039] Figure 3 and Figure 4 They are respectively along Figure 2 The cross-sectional views taken by lines I-I' and II-II' are used to illustrate a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the present invention.

[0040] refer to Figure 3 and Figure 4 Semiconductor package 2003 may include package substrate 2100, a plurality of semiconductor chips on package substrate 2100, and molding layer 2500 covering package substrate 2100 and semiconductor chips.

[0041] The package substrate 2100 may include: a package substrate body portion 2120, an upper package pad 2130 disposed on the top surface of the package substrate body portion 2120, a lower package pad 2125 disposed on or exposed through the bottom surface of the package substrate body portion 2120, and an internal line 2135 disposed in the package substrate body portion 2120 to electrically connect the upper package pad 2130 to the lower package pad 2125. The upper package pad 2130 may be electrically connected to the connection structure 2400. The lower package pad 2125 may be connected to the conductive connection portion 2800. Figure 2 The interconnect pattern 2005 of the main substrate 2001 of the electronic system 2000 is shown.

[0042] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region provided with a peripheral line 3110. The second structure 3200 may include: a common source line 3205, a gate stack 3210 on the common source line 3205, a vertical channel structure 3220 penetrating the gate stack 3210 and a separation structure 3230, a bit line 3240 electrically connected to the vertical channel structure 3220, and a word line WL electrically connected to the gate stack 3210 (see, for example, see...). Figure 1 The gate connection line 3235 and the conductive line 3250 are respectively.

[0043] Each of the semiconductor chips 2200 may be electrically connected to the peripheral line 3110 of the first structure 3100 and may include a through-line 3245 extending into the second structure 3200. The through-line 3245 may be configured to penetrate the gate stack 3210 and may be disposed outside the gate stack 3210. Each of the semiconductor chips 2200 may also include an input / output connection line 3265 extending into the second structure 3200 and an input / output pad 2210 electrically connected to the input / output connection line 3265.

[0044] Figure 5 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figure 6A and Figure 6B They are respectively along Figure 5 The cross-sectional views taken by lines A-A' and B-B' are used to illustrate a semiconductor device according to an embodiment of the concept of the present invention.

[0045] refer to Figure 5 , Figure 6A and Figure 6B The semiconductor device may include a peripheral substrate 10, a peripheral circuit structure PS on the peripheral substrate 10, and a cell array structure CS on the peripheral circuit structure PS. The peripheral substrate 10, the peripheral circuit structure PS, and the cell array structure CS may respectively correspond to... Figure 3 and Figure 4 The semiconductor substrate 3010, the first structure 3100 on the semiconductor substrate 3010, and the second structure 3200 on the first structure 3100 are shown.

[0046] The peripheral substrate 10 may include a cell array region CAR and a contact region CCR. The peripheral substrate 10 may extend from the cell array region CAR toward the contact region CCR in a first direction D1 and a second direction D2 that are not parallel to each other. The first direction D1 and the second direction D2 may be parallel to the top surface of the peripheral substrate 10 and may be orthogonal to each other. A third direction D3 may be a vertical direction D3 perpendicular to the top surface of the peripheral substrate 10. For example, the first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other.

[0047] When viewed in a plan view, the contact region CCR can extend from the cell array region CAR in a first direction D1 or in a direction opposite to the first direction D1. The cell array region CAR may have a reference set thereon. Figure 3 and Figure 4The vertical channel structure 3220, the separation structure 3230, and the area of ​​the bit line 3240 electrically connected to the vertical channel structure 3220 are described. The contact area CCR may be a region on which a stepped structure including the pad portion ELp described below is provided. Unlike that shown in the figures, the contact area CCR may extend from the cell array region CAR in the second direction D2 or in a direction opposite to the second direction D2.

[0048] In this embodiment, the peripheral substrate 10 may be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a structure comprising a single-crystal silicon substrate and a single-crystal epitaxial layer grown from the single-crystal silicon substrate. A device isolation layer 11 may be disposed in the peripheral substrate 10. The device isolation layer 11 may define an active region of the peripheral substrate 10. The device isolation layer 11 may be formed of, for example, silicon oxide, or may include, for example, silicon oxide.

[0049] The peripheral circuit structure PS can be disposed on the peripheral substrate 10. The peripheral circuit structure PS may include a peripheral circuit transistor PTR on the active region of the peripheral substrate 10, a peripheral contact plug 31, a peripheral circuit interconnect 33 electrically connected to the peripheral circuit transistor PTR via the peripheral contact plug 31, and a first insulating layer 30 surrounding them. Figure 1 The first region 1100F, and the peripheral circuit interconnect 33 can correspond to Figure 3 and Figure 4 The outer perimeter is 3110.

[0050] The peripheral circuit transistor PTR, peripheral contact plug 31, and peripheral circuit interconnect 33 can constitute the peripheral circuit. For example, the peripheral circuit transistor PTR can constitute... Figure 1 The decoder circuit 1110, page buffer 1120, and logic circuit 1130 are included. More specifically, each of the peripheral circuit transistors (PTRs) may include a peripheral gate insulating layer 21, a peripheral gate electrode 23, a peripheral capping pattern 25, a peripheral gate spacer 27, and a peripheral source / drain region 29.

[0051] A peripheral gate insulating layer 21 may be disposed between the peripheral gate electrode 23 and the peripheral substrate 10. A peripheral gate capping pattern 25 may be disposed on the peripheral gate electrode 23. A peripheral gate spacer 27 may cover the side surfaces of the peripheral gate insulating layer 21, the peripheral gate electrode 23, and the peripheral gate capping pattern 25. A peripheral source / drain region 29 may be disposed in the portion of the peripheral substrate 10 located on both sides of the peripheral gate electrode 23.

[0052] The peripheral circuit interconnect 33 can be electrically connected to the peripheral circuit transistor PTR via the peripheral contact plug 31. Each of the peripheral circuit transistors PTR can be an n-type metal-oxide-semiconductor (NMOS) transistor or a p-type metal-oxide-semiconductor (PMOS) transistor, and in an embodiment, it can be a gate-to-ring transistor. The width of each of the peripheral contact plugs 31 in the first direction D1 or the second direction D2 can increase with the increase of the distance from the peripheral substrate 10. The peripheral contact plugs 31 and the peripheral circuit interconnect 33 can be formed of or include at least one of conductive materials (e.g., metallic materials).

[0053] A first insulating layer 30 may be disposed on the top surface of the peripheral substrate 10. The first insulating layer 30 may be disposed on the peripheral substrate 10 to cover the peripheral circuit transistor PTR, the peripheral contact plug 31, and the peripheral circuit interconnect 33. The first insulating layer 30 may have a multilayer structure comprising multiple insulating layers. For example, the first insulating layer 30 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material.

[0054] A cell array structure CS can be disposed on the first insulating layer 30, and here, the cell array structure CS can include a substrate 100 and a stack of STs on the substrate 100. The substrate 100 can extend in a first direction D1 and a second direction D2. The substrate 100 may not be disposed on a portion of the contact region CCR. The substrate 100 can be a semiconductor substrate comprising a semiconductor material. The substrate 100 can be formed of at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs), or include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs).

[0055] A stacked ST can be disposed on substrate 100. The stacked ST can extend from the cell array region CAR to the contact region CCR. The stacked ST can correspond to Figure 3 and Figure 4 The gate stack 3210. In an embodiment, multiple stacked STs may be arranged along the second direction D2 and may be spaced apart from each other in the second direction D2, with the separation structure 160 interposed therebetween. For the sake of brevity, only one stacked ST will be described below, but other stacked STs may also have substantially the same features as described below.

[0056] The stacked ST may include alternately stacked interlayer insulating layers ILD1 and ILD2 and gate electrodes EL1 and EL2. Gate electrodes EL1 and EL2 may correspond to... Figure 1The letter lines are WL, the first lines are LL1 and LL2, and the second lines are UL1 and UL2.

[0057] In an embodiment, the stacked ST may include a first stacked ST1 on substrate 100 and a second stacked ST2 on the first stacked ST1. The first stacked ST1 may include an alternately stacked first interlayer insulating layer ILD1 and a first gate electrode EL1, and the second stacked ST2 may include an alternately stacked second interlayer insulating layer ILD2 and a second gate electrode EL2. The first gate electrode EL1 and the second gate electrode EL2 may have substantially the same thickness in the third direction D3. Hereinafter, the term "thickness" may be used to refer to the length of the element measured in the third direction D3.

[0058] As the height from the substrate 100 (i.e., in the third direction D3) increases, the length of each of the first gate electrode EL1 and the second gate electrode EL2 in the first direction D1 can decrease. For example, the length of each of the first gate electrode EL1 and the second gate electrode EL2 in the first direction D1 can be greater than the length of the other electrode thereon in the first direction D1. The lowermost first gate electrode EL1 in the first stack ST1 can have the longest length in the first direction D1, and the uppermost second gate electrode EL2 in the second stack ST2 can have the shortest length in the first direction D1.

[0059] The first gate electrode EL1 and the second gate electrode EL2 may have pad portions ELp located on the contact region CCR. The pad portions ELp of the first gate electrode EL1 and the second gate electrode EL2 may be located at different positions in the horizontal and vertical directions. The pad portions ELp may be formed in a stepped structure in the first direction D1.

[0060] Due to the stepped structure, each of the first stack ST1 and the second stack ST2 can have a thickness that decreases with increasing distance from the outermost vertical channel structure VS in the vertical channel structure VS described below, and when viewed in a plan view, the side surfaces of the first gate electrode EL1 and the second gate electrode EL2 can be spaced apart from each other by a specific distance in the first direction D1.

[0061] The first gate electrode EL1 and the second gate electrode EL2 may be formed of at least one of, for example, doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper, aluminum), conductive metal nitrides (e.g., titanium nitride, tantalum nitride), and transition metals (e.g., titanium, tantalum), or may include at least one of, for example, doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper, aluminum), conductive metal nitrides (e.g., titanium nitride, tantalum nitride), and transition metals (e.g., titanium, tantalum). In an embodiment, the first gate electrode EL1 and the second gate electrode EL2 may be formed of tungsten or may include tungsten.

[0062] A first interlayer insulating layer ILD1 and a second interlayer insulating layer ILD2 may be disposed between a first gate electrode EL1 and a second gate electrode EL2, and each of them may have a side surface of the first gate electrode EL1 and the second gate electrode EL2 that is aligned with the side surface of the corresponding gate electrode disposed below and in contact with it. For example, the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may be configured such that their length in the first direction D1 decreases with increasing distance from the substrate 100, similar to the first gate electrode EL1 and the second gate electrode EL2.

[0063] The lowest interlayer insulating layer ILD2 in the second interlayer insulating layer ILD2 can contact the highest interlayer insulating layer ILD1 in the first interlayer insulating layer ILD1. For example, the thickness of each of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 can be less than the thickness of each of the first gate electrode EL1 and the second gate electrode EL2. For example, the thickness of the lowest interlayer insulating layer ILD1 in the first interlayer insulating layer ILD1 can be less than the thickness of each of the other interlayer insulating layers in ILD1 and ILD2. For example, the thickness of the highest interlayer insulating layer ILD2 in the second interlayer insulating layer ILD2 can be greater than the thickness of each of the other interlayer insulating layers in ILD1 and ILD2.

[0064] Apart from the lowest first interlayer insulating layer ILD1 in the first interlayer insulating layer ILD1 and the uppermost second interlayer insulating layer ILD2 in the second interlayer insulating layer ILD2, the remaining interlayer insulating layers in ILD1 and ILD2 can have substantially the same thickness. However, the invention is not limited to this example, and the thicknesses of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 can vary depending on the technical requirements of each semiconductor device.

[0065] In embodiments, the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material. For example, the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may be formed from high-density plasma (HDP) oxide or tetraethyl orthosilicate (TEOS), or may comprise high-density plasma (HDP) oxide or tetraethyl orthosilicate (TEOS).

[0066] The source structure SC can be disposed on the cell array region CAR and between the substrate 100 and the lowest first interlayer insulating layer ILD1. Figure 1 Common source line CSL and Figure 3 and Figure 4 The common source line 3205. The source structure SC may include a first source conductive pattern SCP1 and a second source conductive pattern SCP2 sequentially stacked on the substrate 100. The second source conductive pattern SCP2 may be disposed between the first source conductive pattern SCP1 and the lowest first interlayer insulating layer ILD1. The thickness of the first source conductive pattern SCP1 may be greater than the thickness of the second source conductive pattern SCP2. The first source conductive pattern SCP1 and the second source conductive pattern SCP2 may include a semiconductor material (e.g., silicon) or a doped semiconductor material. When the first source conductive pattern SCP1 and the second source conductive pattern SCP2 include a doped semiconductor material, the impurity concentration of the first source conductive pattern SCP1 may be higher than the impurity concentration of the second source conductive pattern SCP2.

[0067] The first source conductive pattern SCP1 of the source structure SC can be disposed only on the cell array region CAR, and not on the contact region CCR. In contrast, the second source conductive pattern SCP2 of the source structure SC can extend from the cell array region CAR to the contact region CCR. The second source conductive pattern SCP2 on the contact region CCR can be referred to as the second semiconductor layer 123.

[0068] The lower molded structure MSa can be disposed on the contact region CCR and between the substrate 100 and the lowest first interlayer insulating layer ILD1. The lower molded structure MSa may include a first buffer insulating layer 111, a first semiconductor layer 121, a second buffer insulating layer 113 and a second semiconductor layer 123 sequentially stacked on the substrate 100.

[0069] A first semiconductor layer 121 may be disposed between a substrate 100 and a second semiconductor layer 123. A first buffer insulating layer 111 may be disposed between the substrate 100 and the first semiconductor layer 121, and a second buffer insulating layer 113 may be disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The bottom surface of the first buffer insulating layer 111 may be substantially coplanar with the bottom surface of the first source conductive pattern SCP1. The top surface of the second buffer insulating layer 113 may be substantially coplanar with the top surface of the first source conductive pattern SCP1.

[0070] In the embodiments, the first buffer insulating layer 111 and the second buffer insulating layer 113 may be formed of or comprise silicon oxide. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be formed of or comprise semiconductor material (e.g., silicon).

[0071] Multiple vertical channel structures (VS) can be disposed on the cell array region CAR to penetrate the stacked ST and source structure SC. Each vertical channel structure (VS) can penetrate at least a portion of the substrate 100, and the bottom surface of each vertical channel structure (VS) can be located at a lower height than the top surface of the substrate 100 and the bottom surface of the source structure SC. In other words, the vertical channel structure (VS) can be in direct contact with the substrate 100.

[0072] When in Figure 5 When viewed in a plan view, the vertical channel structure VS can be arranged in a Z-shape along either the first direction D1 or the second direction D2. In an embodiment, the vertical channel structure VS may not be located on the contact area CCR. The vertical channel structure VS can correspond to... Figures 2 to 4 The vertical channel structure 3220. The vertical channel structure VS can serve as... Figure 1 The first transistors LT1 and LT2, the memory cell transistor MCT, and the channel regions of the second transistors UT1 and UT2.

[0073] A vertical channel structure VS can be disposed in a vertical channel via CH, which is formed to penetrate the stack ST. Each of the vertical channel vias CH can include a first vertical channel via CH1 penetrating the first stack ST1 and a second vertical channel via CH2 penetrating the second stack ST2. The first vertical channel via CH1 can further penetrate the source structure SC. In addition, the first vertical channel via CH1 can further penetrate at least a portion of the substrate 100. The first vertical channel via CH1 and the second vertical channel via CH2 of each of the vertical channel vias CH can be connected to each other on a third direction D3.

[0074] Each of the vertical channel structures VS may include a first portion VSa and a second portion VSb. The first portion VSa may be disposed in a first vertical channel hole CH1, and the second portion VSb may be disposed in a second vertical channel hole CH2. The second portion VSb may be disposed on and connected to the first portion VSa.

[0075] Each of the vertical channel structures VS may include: a data storage pattern DSP and a vertical semiconductor pattern VSP, sequentially disposed on the inner surface of each of the vertical channel vias CH; an insulating gap fill pattern VI, filling the internal space defined by the vertical semiconductor pattern VSP; and a conductive pad PAD on the insulating gap fill pattern VI. The conductive pad PAD may be disposed in an empty space defined or surrounded by the insulating gap fill pattern VI and the data storage pattern DSP (or the vertical semiconductor pattern VSP). Specifically, each of the vertical channel structures VS may include: an insulating gap fill pattern VI, filling the internal space of each of the vertical channel vias CH; and a data storage pattern DSP, located between the inner surface of each of the vertical channel vias CH and the insulating gap fill pattern VI. Furthermore, each of the vertical channel structures VS may include a vertical semiconductor pattern VSP located between the data storage pattern DSP and the insulating gap fill pattern VI. The conductive pad PAD may be disposed in the internal empty space of each vertical channel via CH and on the insulating gap fill pattern VI. Vertical semiconductor pattern (VSP) can extend in the area between data storage pattern (DSP) and conductive pad (PAD).

[0076] Each of the vertical channel structures (VS) can have a circular, elliptical, or strip-shaped top surface. The data storage pattern (DSP) can surround the vertical semiconductor pattern (VSP). The vertical semiconductor pattern (VSP) can conformally cover the inner surface of the data storage pattern (DSP).

[0077] Vertical semiconductor patterned VSPs can be formed from or include at least one of doped semiconductor materials and undoped or intrinsic semiconductor materials, and can have a polycrystalline or single-crystal structure. (See reference...) Figure 7B The vertical semiconductor pattern VSP can contact a portion of the source structure SC. The conductive pad PAD can be formed of or include at least one of a doped semiconductor material and a conductive material.

[0078] Multiple dummy vertical channel structures (DVSs) can be disposed on the contact region CCR to penetrate the second insulating layer 170, the stack ST, and the lower molding structure MSa. More specifically, the dummy vertical channel structures (DVSs) can be configured to penetrate the pad portions ELp of the first gate electrode EL1 and the second gate electrode EL2. The dummy vertical channel structures (DVSs) can be disposed near the cell contact plug CCP, which will be described below. The dummy vertical channel structures (DVSs) may not be disposed on the cell array region CAR. The dummy vertical channel structures (DVSs) and the vertical channel structures (VSs) can be formed simultaneously and can have substantially the same structure. However, in embodiments, unlike the structures shown, the dummy vertical channel structures (DVSs) can be omitted.

[0079] The second insulating layer 170 may be disposed on the contact region CCR to cover a portion of the first insulating layer 30 and the stacked ST. More specifically, the second insulating layer 170 may cover the stepped structure of the stacked ST and may be disposed on the pad portions ELp of the first gate electrode EL1 and the second gate electrode EL2. The second insulating layer 170 may have a substantially flat top surface. The top surface of the second insulating layer 170 may be substantially coplanar with the topmost surface of the stacked ST. More specifically, the top surface of the second insulating layer 170 may be substantially coplanar with the top surface of the uppermost second interlayer insulating layer ILD2 in the second interlayer insulating layer ILD2 of the stacked ST.

[0080] The second insulating layer 170 may include an insulating layer or multiple stacked insulating layers. The second insulating layer 170 may be formed of or include at least one of an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material). The second insulating layer 170 may include an insulating material different from the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 of the stacked ST. In the case that the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 of the stacked ST comprise high-density plasma oxides, the second insulating layer 170 may be formed of or include TEOS.

[0081] The third insulating layer 230 may be disposed on the second insulating layer 170 and the stack ST. The third insulating layer 230 may cover the top surface of the second insulating layer 170, the top surface of the uppermost second interlayer insulating layer ILD2 in the stack ST, and the top surfaces of the vertical channel structure VS and the dummy vertical channel structure DVS.

[0082] The third insulating layer 230 may comprise a single insulating layer or multiple stacked insulating layers. The third insulating layer 230 may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material, or may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material. The third insulating layer 230 may be formed of or comprise an insulating material substantially the same as that of the second insulating layer 170, and may include an insulating material different from the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 of the stacked ST.

[0083] Bit line contact plugs (BLCPs) can be configured to penetrate the third insulating layer 230 and can be connected to the vertical channel structure VS. Cell contact plugs (CCPs) can be configured to penetrate the third insulating layer 230 and the second insulating layer 170 and can be connected to the first gate electrode EL1 and the second gate electrode EL2. Each of the cell contact plugs (CCPs) can be configured to penetrate one of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 and can contact one of the pad portions ELp of the first gate electrode EL1 and the second gate electrode EL2. Each of the cell contact plugs (CCPs) can be adjacent to a plurality of dummy vertical channel structures DVS, but can be spaced apart from the dummy vertical channel structures DVS. The cell contact plugs (CCPs) can correspond to Figure 4 Gate connection line 3235.

[0084] The peripheral contact plug TCP can be configured to penetrate at least a portion of the first insulating layer 30, the third insulating layer 230, and the second insulating layer 170, and can be electrically connected to the peripheral circuit transistor PTR of the peripheral circuit structure PS. Unlike the figures shown, multiple peripheral contact plugs TCP can be configured. The peripheral contact plug TCP can be spaced apart from the substrate 100, the source structure SC, and the stacked ST in the first direction D1. The peripheral contact plug TCP can correspond to... Figure 3 and Figure 4 The penetrating line is 3245.

[0085] The width of the bit line contact plug BLCP, the unit contact plug CCP, and the peripheral contact plug TCP in the first direction D1 or the second direction D2 can increase with the increase of the vertical height in the third direction D3.

[0086] Bit lines BL can be disposed on the third insulating layer 230 and can be connected to bit line contact plugs BLCP respectively. Bit lines BL can correspond to Figure 1 bit line BL and Figure 3 and Figure 4 The bit line is 3240.

[0087] The first conductive line CL1, which connects to the unit contact plug CCP, and the second conductive line CL2, which connects to the peripheral contact plug TCP, can be disposed on the third insulating layer 230. The first conductive line CL1 and the second conductive line CL2 can correspond to... Figure 4 The conductive wire is 3250.

[0088] Bit line contact plug BLCP, cell contact plug CCP, peripheral contact plug TCP, bit line BL, and first conductive line CL1 and second conductive line CL2 may be formed of or include at least one of conductive materials (e.g., metallic materials). Although not shown, additional interconnects and additional vias electrically connected to bit line BL and first conductive line CL1 and second conductive line CL2 may be further provided on third insulating layer 230.

[0089] In the case of multiple stacked STs, a separation structure 160 can be disposed in a second trench TR2, which is formed between the stacked STs and extends in the first direction D1. The second trench TR2 may not extend into the contact region CCR of the peripheral substrate 10. The separation structure 160 may be spaced apart from the vertical channel structure VS and the dummy vertical channel structure DVS in the second direction D2. In an embodiment, the top surface of the separation structure 160 may be located at a height higher than the top surfaces of the vertical channel structure VS and the dummy vertical channel structure DVS. The bottom surface of the separation structure 160 may be substantially coplanar with the top surface of the first source conductive pattern SCP1 and may be located at a height higher than the top surface of the substrate 100.

[0090] In this embodiment, multiple separation structures 160 may be provided, and in this case, the separation structures 160 may be spaced apart from each other in the second direction D2, with a stack ST between them. The separation structures 160 may correspond to... Figure 3 The separation structure 3230.

[0091] A spacer 130 may be disposed between the separation structure 160 and the stack ST to surround the separation structure 160. The spacer 130 may conformally cover the side surfaces of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, as well as the first gate electrode EL1 and the second gate electrode EL2. In an embodiment, the separation structure 160 may be formed of or comprise silicon oxide. The spacer 130 may be formed of or comprise a material having etch selectivity relative to the second source conductive pattern SCP2, the first semiconductor layer 121, and the second semiconductor layer 123. The spacer 130 may, for example, be formed of or comprise silicon nitride.

[0092] Figure 7A and Figure 7B It shows Figure 6A Enlarged cross-sectional views of parts “A” and “B”. Figure 8 It shows Figure 6A Enlarged cross-sectional view of part "C". For the sake of brevity, the previously described elements may be identified by the same reference numerals and will not be repeated.

[0093] Figure 7A and Figure 7B One of a source structure SC and a vertical channel structure VS is shown. The source structure SC includes a first source conductive pattern SCP1 and a second source conductive pattern SCP2. Each of the vertical channel structures VS includes a data storage pattern DSP, a vertical semiconductor pattern VSP, an insulating gap filling pattern VI, and a lower data storage pattern DSPr. For ease of description, one of the stacked STs and one of the vertical channel structures VS will be described below, but the remaining stacked STs and the remaining vertical channel structures VS can be configured to have substantially the same characteristics.

[0094] The data storage pattern DSP may include a sequentially stacked barrier insulating layer BLK, a charge storage layer CIL, and a tunneling insulating layer TIL. The barrier insulating layer BLR may be adjacent to a stacked ST or source structure SC, and the tunneling insulating layer TIL may be adjacent to a vertical semiconductor pattern VSP. The charge storage layer CIL may be located between the barrier insulating layer BLR and the tunneling insulating layer TIL. The barrier insulating layer BLR may conformally cover the inner surface of each of the vertical channel vias CH. The charge storage layer CIL may conformally cover the inner surface of the barrier insulating layer BLR. The charge storage layer CIL may be spaced apart from each of the first interlayer insulating layers ILD1, each of the second interlayer insulating layers ILD2, each of the first gate electrode EL1, and each of the second gate electrode EL2, with the barrier insulating layer BLR located therebetween. The tunneling insulating layer TIL may conformally cover the inner surface of the charge storage layer CIL. The charge storage layer CIL may be located between the barrier insulating layer BLR and the tunneling insulating layer TIL.

[0095] The barrier insulating layer BLK, charge storage layer CIL, and tunneling insulating layer TIL may extend onto the third direction D3. In an embodiment, the Fowler-Nordheim (FN) tunneling phenomenon caused by the voltage difference between the vertical semiconductor pattern VSP and the first gate electrode EL1 and the second gate electrode EL2 can be used to store and modify data in the data storage pattern DSP. For example, the barrier insulating layer BLK and the tunneling insulating layer TIL may comprise silicon oxide, and the charge storage layer CIL may comprise silicon nitride or silicon oxynitride.

[0096] The first source conductive pattern SCP1 of the source structure SC can be in contact with the vertical semiconductor pattern VSP, and the second source conductive pattern SCP2 can be spaced apart from the vertical semiconductor pattern VSP, with the data storage pattern DSP located between them. The first source conductive pattern SCP1 can be spaced apart from the insulating gap-filling pattern VI, with the vertical semiconductor pattern VSP located between them.

[0097] More specifically, the first source conductive pattern SCP1 may include a protruding portion SCPbt located at a height higher than the bottom surface SCP2b of the second source conductive pattern SCP2 or lower than the bottom surface SCP1b of the first source conductive pattern SCP1. The surface of the protruding portion SCPbt in contact with the data storage pattern DSP or the lower data storage pattern DSPr may have a curved shape.

[0098] even though Figure 7B As not shown, each of the data storage pattern DSP and the lower data storage pattern DSPr may also include sequentially stacked barrier insulating layer BLK, charge storage layer CIL, and tunneling insulating layer TIL, such as Figure 7A As shown.

[0099] refer to Figure 8 The widths of the first portion VSa and the second portion VSb of the vertical channel structure VS in the first direction D1 or the second direction D2 can increase with the increase of the vertical height in the third direction D3. The uppermost width of the first portion VSa can be greater than the lowermost width of the second portion VSb. For example, the side surface of each of the vertical channel structures VS can have a stepped surface SP at the interface between the first portion VSa and the second portion VSb. For example, the side surface of each of the vertical channel structures VS can have a stepped surface SP at the boundary between the first stack ST1 and the second stack ST2. The stepped surface SP can be the top surface of the first portion VSa exposed through the second portion VSb. The stepped surface SP can connect the side surface of the first portion VSa to the side surface of the second portion VSb at the boundary between the first portion VSa and the second portion VSb. The stepped surface SP can be located at the same height as the boundary between the first portion VSa and the second portion VSb. The stepped surface SP can be located at the same height as the boundary between the first stack ST1 and the second stack ST2. Due to the stepped surface SP, the width of the vertical channel structure VS can change abruptly at the boundary between the first portion VSa and the second portion VSb. However, the invention is not limited to this example, and each side surface of the vertical channel structure VS can have two or more stepped surfaces at different heights.

[0100] The uppermost first interlayer insulating layer ILD1 in the first interlayer insulating layer ILD1 may include a quasi-metallic element M, which is contained in the reducing gas used when forming the active layer AL in the region adjacent to the vertical channel structure VS. As an example, when the reducing gas is B2H6, the quasi-metallic element may be boron (B). Furthermore, the first portion VSa of each of the vertical channel structures VS may have a height measured along a third direction D3 from the bottom surface of the first portion VSa. The first interlayer insulating layer ILD1 located at a height greater than half the total height of the first portion VSa may include the quasi-metallic element M in the region adjacent to the vertical channel structure VS. Additionally, the top surface of the uppermost first interlayer insulating layer ILD1 in the first interlayer insulating layer ILD1 may include the quasi-metallic element M. For example, the uppermost first interlayer insulating layer ILD1 in the first interlayer insulating layer ILD1 may include boron (B) on its top surface and on its side surface adjacent to the vertical channel structure VS.

[0101] Figure 9A , Figure 9B , Figures 10A to 10D , Figures 11A to 11H , Figures 12A to 12D as well as Figures 13 to 23 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. In detail, Figure 9A as well as Figures 13 to 23 It is along Figure 5 A cross-sectional view taken from line A-A'. Figure 9B as well as Figures 10A to 10D , Figures 11A to 11H , Figures 12A to 12D Is with Figure 9A The enlarged cross-sectional view corresponding to the "D" part. Refer to the following text. Figure 5 , Figure 6A and Figure 6B ,as well as Figure 9A , Figure 9B , Figures 10A to 10D , Figures 11A to 11H , Figures 12A to 12D and Figures 13 to 23 The manufacturing method according to an embodiment of the present invention will be described in more detail below.

[0102] refer to Figure 5 , Figure 9A and Figure 9B A peripheral substrate 10 may be provided, comprising a cell array region (CAR) and a contact region (CCR). A device isolation layer 11 may be formed in the peripheral substrate 10 to define an active region. Forming the device isolation layer 11 may include forming a trench in the upper portion of the peripheral substrate 10 and filling the trench with a silicon oxide layer.

[0103] The peripheral circuit transistor PTR can be formed on the active region defined by the device isolation layer 11. The peripheral contact plug 31 and the peripheral circuit interconnect 33 can be formed to connect to the peripheral source / drain region 29 of the peripheral circuit transistor PTR. The first insulating layer 30 can be formed to cover the peripheral circuit transistor PTR, the peripheral contact plug 31, and the peripheral circuit interconnect 33.

[0104] The substrate 100 may be formed on the first insulating layer 30. The substrate 100 may extend from the cell array region CAR toward the contact region CCR.

[0105] A portion of the substrate 100 on the contact region CCR can be removed. Partial removal of the substrate 100 may include: forming a mask pattern to cover a portion of the contact region CCR and the cell array region CAR, and using the mask pattern as an etching mask to etch the substrate 100. Partial removal of the substrate 100 may be performed to form an area where the aforementioned peripheral contact plug TCP will be disposed.

[0106] The undermolded structure MSa can be formed on the substrate 100. Forming the undermolded structure MSa may include sequentially stacking a first buffer insulating layer 111, a first semiconductor layer 121, a second buffer insulating layer 113, and a second semiconductor layer 123 on the substrate 100. The first buffer insulating layer 111 and the second buffer insulating layer 113 may be formed of or comprise silicon oxide, for example. The first semiconductor layer 121 and the second semiconductor layer 123 may be formed of or comprise a semiconductor material (e.g., silicon).

[0107] A first molding structure MS1 may be formed on a lower molding structure MSa. In an embodiment, the formation of the first molding structure MS1 may include: alternately stacking a first interlayer insulating layer ILD1 and a first sacrificial layer SL1 on a substrate 100. The first sacrificial layer SL1 may include a material different from the first interlayer insulating layer ILD1. The first sacrificial layer SL1 may include a material with etch selectivity relative to the first interlayer insulating layer ILD1. For example, the first sacrificial layer SL1 may include silicon nitride, and the first interlayer insulating layer ILD1 may include silicon oxide. The first sacrificial layer SL1 may be formed to have substantially the same thickness, and the first interlayer insulating layer ILD1 may have at least two different thicknesses depending on its vertical position. As an example, the lowest first interlayer insulating layer ILD1 may be thinner than the other first interlayer insulating layers ILD1.

[0108] The first vertical channel hole CH1 can be formed to penetrate the first molded structure MS1 and the lower molded structure MSa. In an embodiment, the first vertical channel hole CH1 can be formed to penetrate a portion of the substrate 100. The bottom surface of each of the first vertical channel holes CH1 can be located in the substrate 100. In an embodiment, the formation of the first vertical channel hole CH1 can include: forming a mask pattern (not shown) on the first molded structure MS1, and using the mask pattern as an etching mask to sequentially etch the first molded structure MS1, the lower molded structure MSa, and a portion of the substrate 100. An anisotropic etching process can be used to perform the etching steps. The width of each of the first vertical channel holes CH1 in the first direction D1 or the second direction D2 can increase with increasing distance from the substrate 100 (i.e., in the third direction D3).

[0109] refer to Figure 10A and Figure 10B An active layer AL can be formed on a first molded structure MS1. Specifically, the active layer AL can cover the top surface MS1u of the first molded structure MS1 and can extend to cover the upper surface of each of the first vertical channel holes CH1. The active layer AL can include a horizontal portion H covering the top surface MS1u of the first molded structure MS1 and a vertical portion V covering the upper surface of each of the first vertical channel holes CH1. For example, the vertical portion V can be a portion of the active layer AL that horizontally overlaps with the first molded structure MS1, and the horizontal portion H can be the remaining portion of the active layer AL excluding the vertical portion V. The width of the vertical portion V in the horizontal direction D1 or D2 can increase with increasing distance from the substrate 100 (i.e., in the third direction D3). The active layer AL can be a metal layer containing quasi-metallic elements.

[0110] In embodiments, the active layer AL can be formed using deposition methods (e.g., chemical vapor deposition (CVD) or atomic layer deposition (ALD). As an example, the active layer AL can be formed via a chemical reaction using a precursor and a reducing gas. In embodiments, WF6 can be used as the precursor, and at least one of H2, SiH4, and B2H6 can be used as the reducing gas. In embodiments, the active layer AL can be formed using atomic layer deposition (ALD), where WF6 and B2H6 are used as the precursor and reducing gas, respectively. In this case, the active layer AL can be a boron-rich tungsten (W) layer. Therefore, a quasi-metallic element (e.g., boron (B)) can permeate into the region of the first molded structure MS1 covering the active layer AL. For example, at least a portion of the first interlayer insulating layer ILD1 can contain a quasi-metallic element (e.g., boron (B)).

[0111] Each of the first vertical channel holes CH1 may have a hole length CH1h in the third direction D3. The vertical portion V of the active layer AL may have a vertical length Vh in the third direction D3. For example, the hole length CH1h of each of the first vertical channel holes CH1 may be the distance from the top surface MS1u of the first molded structure MS1 to the bottom surface of each of the first vertical channel holes CH1, measured along the third direction D3 or in the opposite direction. The vertical length Vh of the vertical portion V may be the distance from the top surface MS1u of the first molded structure MS1 to the bottommost portion of the vertical portion V, measured along the third direction D3 or in the opposite direction. The vertical length Vh may be less than the hole length CH1h. As an example, refer to Figure 10A The vertical length Vh can be less than half the hole length CH1h. As another example, see [reference needed]. Figure 10B The vertical length Vh can be approximately half the aperture length CH1h. For example, the vertical length Vh can be 15% to 50% of the aperture length CH1h. In an embodiment, the vertical length Vh can be 55% to 60% of the aperture length CH1h. The vertical portion V can be formed to at least cover the side surface of the uppermost first interlayer insulating layer ILD1 in the first interlayer insulating layer ILD1. The vertical length Vh can be controlled by adjusting the injection time of the reducing gas in the aforementioned step of forming the active layer AL. When adjusting the injection time of the reducing gas in increments of 0.1 seconds, the vertical length Vh can be controlled in increments of 10 nm. For example, if the injection time of the reducing gas increases or decreases by 0.1 seconds, the vertical length Vh can increase or decrease by 10 nm.

[0112] refer to Figure 10C and Figure 10D The barrier layer BaL can be formed after the formation of the first vertical channel holes CH1 and before the formation of the active layer AL. The barrier layer BaL can conformally cover the side and bottom surfaces of each of the first vertical channel holes CH1 and can extend to a region on the top surface MS1u of the first molded structure MS1. In embodiments, the barrier layer BaL can be formed of or include at least one of a metal and a metal nitride material (e.g., Ti, TiN, Ta, and TaN).

[0113] The barrier layer BaL can be used to protect the first molded structure MS1. Specifically, lifting problems can occur when the precursor (which is supplied to form the active layer AL) reacts with the first molded structure MS1. By forming the barrier layer BaL, lifting problems can be prevented in subsequent processes that form the active layer AL.

[0114] refer to Figures 11A to 11DA molded sacrificial layer (MSL) can be formed on the active layer AL to fill the upper portion of each of the first vertical channel holes CH1. Therefore, voids VD can be formed in the remainder of each of the first vertical channel holes CH1. In an embodiment, the molded sacrificial layer MSL can be formed by a chemical reaction using a precursor and a reducing gas. In an embodiment, WF6 can be used as the precursor for forming the molded sacrificial layer MSL, and H2 can be used as the reducing gas. This is because if hydrogen H2 (which results in a relatively slow reaction) is used for the chemical reaction, a bulk tungsten (W) layer with good step coverage properties can be formed. The molded sacrificial layer MSL may not be formed on the side surfaces of the first vertical channel holes CH1 that are not covered by the active layer AL.

[0115] Void VD can be placed in the first vertical channel hole CH1. Void VD can be the remaining portion of the first vertical channel hole CH1 that is not filled with the active layer AL and the molded sacrificial layer MSL. As an example, refer to Figure 11A and Figure 11C The volume of the void VD can be less than half the volume of the first vertical channel hole CH1. As another example, see [reference needed]. Figure 11B and Figure 11D The volume of the void VD can be approximately half the volume of the first vertical channel hole CH1. For example, the volume of the void VD can be 15% to 50% of the volume of the first vertical channel hole CH1. In an embodiment, the volume of the void VD can be 55% to 60% of the volume of the first vertical channel hole CH1.

[0116] The materials of the active layer AL and the molded sacrificial layer MSL are not limited to the examples described above. As an example, the active layer AL may be formed of a material containing metal, or may include such a material, which is contained within the molded sacrificial layer MSL. In this case, the molded sacrificial layer MSL may not be formed on the side surface of the first vertical channel hole CH1 that is not covered by the active layer AL, and may be formed locally on the active layer AL. Therefore, a void VD may be formed on the side surface of the first vertical channel hole CH1 that is not covered by the active layer AL. For example, by adjusting the area covered by the active layer AL, the void VD can be controlled to a desired size.

[0117] In an embodiment, such as Figures 11A to 11D As shown, the upper part of the void VD can have a conical shape. For example, the bottom surface of the molded sacrificial layer MSL located in the first vertical channel hole CH1 can have a conical shape instead of a flat shape. In another embodiment, as... Figures 11E to 11H As shown, the upper part of the void VD can have a flat shape. However, in this invention, the shape of the void VD is not limited to these examples.

[0118] According to an embodiment of the present invention, after forming the first vertical channel via CH1, a void VD can be intentionally formed in each of the first vertical channel via CH1. For example, since the first vertical channel via CH1 is not completely filled, stress-induced cracking or warping problems in the first molded structure MS1 can be prevented. This facilitates the formation of the second molded structure MS2 in subsequent processes and improves the electrical and reliability characteristics of the manufactured semiconductor device. Furthermore, since cracking or warping problems in the first molded structure MS1 are prevented, the yield can be improved. Additionally, by adjusting the size of the void VD, unintentional supply of etchant to the first vertical channel via CH1 in subsequent processes can be prevented.

[0119] refer to Figure 12A and Figure 12B Active pattern AP and molded sacrificial pattern MSP can be formed in the upper portion of each of the first vertical channel holes CH1. In an embodiment, forming the active pattern AP and molded sacrificial pattern MSP may include removing the active layer AL and molded sacrificial layer MSL from the top surface MS1u of the first molded structure MS1. Partial removal of the active layer AL and molded sacrificial layer MSL may include planarizing the molded sacrificial layer MSL and the active layer AL to expose the top surface MS1u of the first molded structure MS1. Planarization may be performed using a chemical mechanical polishing (CMP) process or an etch-back process.

[0120] refer to Figure 12C and Figure 12D In addition to the active pattern AP and the molded sacrificial pattern MSP, a barrier pattern BaP may also be formed in the upper part of each of the first vertical channel holes CH1. In an embodiment, the formation of the barrier pattern BaP may include: planarizing the molded sacrificial layer MSL, the active layer AL, and the barrier layer BaL to expose the top surface MS1u of the first molded structure MS1.

[0121] refer to Figure 5 , Figure 6A , Figure 6B and Figure 13A second molding structure MS2 can be formed on a first molding structure MS1. Specifically, the second molding structure MS2 can be formed on the first molding structure MS1, as well as an active pattern AP and a molded sacrificial pattern MSP, which are formed in the upper portion of each of the first vertical channel vias CH1. In an embodiment, forming the second molding structure MS2 may include alternately stacking a second interlayer insulating layer ILD2 and a second sacrificial layer SL2 on the first molding structure MS1. The second sacrificial layer SL2 may include a material different from the second interlayer insulating layer ILD2. The second sacrificial layer SL2 may include a material with etch selectivity relative to the second interlayer insulating layer ILD2. For example, the second sacrificial layer SL2 may include silicon nitride, and the second interlayer insulating layer ILD2 may include silicon oxide. The second sacrificial layer SL2 may be formed to have substantially the same thickness, and at least one of the second interlayer insulating layers ILD2 may be formed to have a thickness different from the other second interlayer insulating layers ILD2. As an example, the uppermost second interlayer insulation layer ILD2 in the second interlayer insulation layer ILD2 can be thicker than the other second interlayer insulation layers ILD2 in the second interlayer insulation layer ILD2.

[0122] refer to Figure 5 , Figure 6A , Figure 6B and Figure 14 A second vertical channel hole CH2 can be formed. The second vertical channel hole CH2 can be formed to penetrate the second molding structure MS2. The second vertical channel hole CH2 can vertically overlap with the first vertical channel hole CH1. In an embodiment, the formation of the second vertical channel hole CH2 may include: forming a mask pattern (not shown) on the second molding structure MS2, and using the mask pattern as an etching mask to etch the second molding structure MS2. An anisotropic etching process can be used to perform the etching process. The width of each of the second vertical channel holes CH2 in the first direction D1 or the second direction D2 can increase with the increase of the vertical height from the substrate 100 (i.e., in the third direction D3).

[0123] Before forming the second vertical channel hole CH2, a trimming process can be performed on the second molded structure MS2 on the contact region CCR. The trimming process may include: forming a mask pattern to cover a portion of the top surface of the second molded structure MS2 on the cell array region CAR and the contact region CCR; using the mask pattern as a patterning mask to pattern the second molded structure MS2; reducing the area of ​​the mask pattern; and using the mask pattern with the reduced area as a patterning mask to pattern the second molded structure MS2. In embodiments, the following steps—reducing the area of ​​the mask pattern and using the mask pattern to pattern the second molded structure MS2—may be repeated several times during the trimming process. As a result of the trimming process, the second molded structure MS2 may have a stepped structure.

[0124] refer to Figure 5 , Figure 6A , Figure 6B and Figure 15 The active pattern AP and the molded sacrificial pattern MSP can be removed from the upper part of each of the first vertical channel holes CH1. In an embodiment, the removal of the active pattern AP and the molded sacrificial pattern MSP can be achieved by an ashing process or a wet etching process. Next, a first channel sacrificial pattern CSP1 and a second channel sacrificial pattern CSP2 can be formed to fill the first vertical channel holes CH1 and the second vertical channel holes CH2. Specifically, a first channel sacrificial pattern CSP1 can be formed to fill each of the first vertical channel holes CH1, and a second channel sacrificial pattern CSP2 can be formed to fill each of the second vertical channel holes CH2.

[0125] The first insulating pattern 210 can be formed on the second molded structure MS2. The first insulating pattern 210 can cover the top surface of the second molded structure MS2 (i.e., the top surface of the uppermost second interlayer insulating layer ILD2 in the second interlayer insulating layer ILD2) and the top surface of the second channel sacrificial pattern CSP2.

[0126] refer to Figure 5 , Figure 6A , Figure 6B and Figure 16The first trench TR1 can be formed to penetrate the first insulating pattern 210, the second molding structure MS2, and the first molding structure MS1. The first trench TR1 can further penetrate at least a portion of the lower molding structure MSa (more specifically, at least a portion of the second semiconductor layer 123). In an embodiment, the bottom surface TR1b of the first trench TR1 can be located at a height lower than the bottom surface of the first molding structure MS1 (i.e., the bottom surface of the lowest first interlayer insulating layer ILD1 in the first interlayer insulating layer ILD1) and the top surface of the lower molding structure MSa. The side surfaces of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, as well as the side surfaces of the first sacrificial layer SL1 and the second sacrificial layer SL2, can be exposed through the first trench TR1. The first trench TR1 can extend from the cell array region CAR toward the contact region CCR.

[0127] refer to Figure 5 , Figure 6A , Figure 6B and Figure 17 The first sacrificial layer SL1 and the second sacrificial layer SL2 exposed through the first trench TR1 can be selectively removed. The selective removal of the first sacrificial layer SL1 and the second sacrificial layer SL2 can be performed using a wet etching process with an etch solution. A first gate electrode EL1 and a second gate electrode EL2 can be formed to fill the empty spaces created by removing the first sacrificial layer SL1 and the second sacrificial layer SL2. Therefore, a stack ST including the first gate electrode EL1 and the second gate electrode EL2, as well as a first interlayer insulating layer ILD1 and a second interlayer insulating layer ILD2, can be formed.

[0128] Because the first gate electrode EL1 and the second gate electrode EL2 are formed before the vertical channel structure VS is formed, partial etching of the vertical channel structure VS can be prevented when the first sacrificial layer SL1 and the second sacrificial layer SL2 are removed. This allows for improvements in the electrical and reliability characteristics of the semiconductor device.

[0129] Separation spacers 130 and sacrificial separation patterns 140 can be formed to fill the first trench TR1. Separation spacers 130 and sacrificial separation patterns 140 can extend from the cell array region CAR toward the contact region CCR.

[0130] refer to Figure 5 , Figure 6A , Figure 6B and Figure 18A second insulating pattern 220 can be formed to cover a portion of the top surface of the first insulating pattern 210. The second insulating pattern 220 can be used as a mask to perform an etching process. As a result of the etching process, a first opening OP1 can be formed. The first opening OP1 can be formed to expose a portion of the top surface of the stacked ST and the top surface of the second channel sacrificial pattern CSP2. The first opening OP1 may not expose the spacer 130 and the sacrificial separation pattern 140. For example, the first insulating pattern 210 and the second insulating pattern 220 may cover the spacer 130 and the sacrificial separation pattern 140.

[0131] refer to Figure 5 , Figure 6A , Figure 6B and Figure 19 The second channel sacrificial pattern CSP2 and the first channel sacrificial pattern CSP1 exposed through the first opening OP1 can be removed. A vertical channel structure VS can be formed on the cell array region CAR to fill the space (i.e., the vertical channel hole CH) formed by removing the first channel sacrificial pattern CSP1 and the second channel sacrificial pattern CSP2. Similarly, a dummy vertical channel structure DVS can be formed on the contact region CCR to fill the vertical channel hole CH.

[0132] Forming each of the vertical channel structure VS and the dummy vertical channel structure DVS may include: forming a data storage pattern DSP to conformally cover the inner surface of each of the vertical channel vias CH; forming a vertical semiconductor pattern VSP to conformally cover the side surface of the data storage pattern DSP; forming an insulating gap fill pattern VI to fill at least a portion of the space surrounded by the vertical semiconductor pattern VSP; and forming a conductive pad PAD to fill the space surrounded by the vertical semiconductor pattern VSP and the insulating gap fill pattern VI. Reference Figure 7A The formation of the data storage pattern DSP may include: sequentially depositing a barrier insulating layer BLK, a charge storage layer CIL, and a tunneling insulating layer TIL on the inner surface of each of the vertical channel holes CH.

[0133] After the vertical channel structure VS is formed, the first insulating pattern 210 and the second insulating pattern 220 can be removed. In addition, during the removal of the first insulating pattern 210, the separation spacer 130 and the sacrificial separation pattern 140 can also be partially etched, and the top surface of the stacked ST can be exposed to the outside.

[0134] refer to Figure 5 , Figure 6A , Figure 6B and Figure 20 The third insulating pattern 230 can be formed on the top surface of the stack ST. The third insulating pattern 230 can correspond to a reference. Figure 6A and Figure 6B The third insulating layer 230 is described.

[0135] The third insulating pattern 230 can be formed to expose the top surface of the sacrificial separation pattern 140 to the outside. The second trench TR2 can be formed by selectively removing the sacrificial separation pattern 140 exposed through the third insulating pattern 230. In an embodiment, during the process of removing the sacrificial separation pattern 140, at least a portion of the undermolded structure MSa on the cell array region CAR can be removed. The undermolded structure MSa on the contact region CCR may not be removed.

[0136] The second trench TR2 can extend from the cell array region CAR toward the contact region CCR. On the cell array region CAR, the bottom surface TR2b of the second trench TR2 can be located between the top surface of the first semiconductor layer 121 and the top surface of the substrate 100.

[0137] refer to Figure 5 , Figure 6A , Figure 6B and Figure 21 The first semiconductor layer 121 exposed through the second trench TR2 can be selectively removed. This selective removal of the first semiconductor layer 121 can be performed using a wet etching process with an etching solution. As a result of removing the first semiconductor layer 121, a first horizontal cavity HC1 can be formed between the top surface of the first buffer insulating layer 111 and the bottom surface of the second buffer insulating layer 113. The first horizontal cavity HC1 can refer to the empty space between the first buffer insulating layer 111 and the second buffer insulating layer 113. A portion of the data storage pattern DSP in each of the vertical channel structures VS can be exposed through the first horizontal cavity HC1.

[0138] The removal of the first semiconductor layer 121 can be performed on the cell array region CAR, and the lower molded structure MSa (e.g., a portion of the first semiconductor layer 121) can be left on the contact region CCR.

[0139] refer to Figure 5 , Figure 6A , Figure 6B and Figure 22 The second horizontal cavity HC2 can be formed by removing the first buffer insulating layer 111 and the second buffer insulating layer 113 exposed through the first horizontal cavity HC1. The second horizontal cavity HC2 can refer to the empty space between the substrate 100 and the second semiconductor layer 123. Furthermore, the portion of the data storage pattern DSP exposed through the second horizontal cavity HC2 can be removed. A portion of the vertical semiconductor pattern VSP of each of the vertical channel structures VS can be exposed through the second horizontal cavity HC2.

[0140] The removal of the first buffer insulation layer 111 and the second buffer insulation layer 113 can be performed on the cell array region CAR, and the lower molded structure MSa on the contact region CCR (specifically, the portion of each of the first buffer insulation layer 111 and the second buffer insulation layer 113 disposed on the contact region CCR) can remain as is.

[0141] refer to Figure 5 , Figure 6A , Figure 6B and Figure 23 A first source conductive pattern SCP1 can be formed to fill the second horizontal cavity HC2. Although not shown, an air gap can be formed in the first source conductive pattern SCP1. The second semiconductor layer 123 on the cell array region CAR can be referred to as the second source conductive pattern SCP2, and thus, a source structure SC comprising the first source conductive pattern SCP1 and the second source conductive pattern SCP2 can be formed.

[0142] Return to reference Figure 5 , Figure 6A and Figure 6B A separation structure 160 can be formed to fill the second trench TR2. The top surface of the separation structure 160 can be coplanar with the top surface of the third insulating layer 230.

[0143] Subsequently, the bit line contact plug BLCP can be formed to penetrate the third insulating layer 230, the cell contact plug CCP can be formed to penetrate the third insulating layer 230 and the second insulating layer 170, and the peripheral contact plug TCP can be formed to penetrate at least a portion of the third insulating layer 230, the second insulating layer 170, and the first insulating layer 30. The bit line BL connected to the bit line contact plug BLCP, the first conductive line CL1 connected to the cell contact plug CCP, and the second conductive line CL2 connected to the peripheral contact plug TCP can be formed on the third insulating layer 230.

[0144] Figure 24 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figure 25A and Figure 25B They are respectively along Figure 24 The cross-sectional views taken along lines A-A' and B-B' are used to illustrate a semiconductor device according to an embodiment of the concept of the present invention. In the following, for ease of description, reference has been previously made to... Figure 5 , Figure 6A and Figure 6B The described components can be identified by the same reference numerals, and will not be described again.

[0145] refer to Figure 24 , Figure 25A and Figure 25BThe peripheral circuit structure PS can be disposed on the peripheral substrate 10. In an embodiment, the peripheral circuit structure PS may include a peripheral circuit transistor PTR, a peripheral contact plug 31, a peripheral circuit interconnect 33 electrically connected to the peripheral circuit transistor PTR via the peripheral contact plug 31, a first bonding pad 35 electrically connected to the peripheral circuit interconnect 33, and a first insulating layer 30 surrounding the peripheral circuit transistor PTR, the peripheral contact plug 31, the peripheral circuit interconnect 33, and the first bonding pad 35. The first insulating layer 30 may not cover the top surface of the first bonding pad 35. The top surface of the first insulating layer 30 may be coplanar with the top surface of the first bonding pad 35.

[0146] A cell array structure CS, including a second bonding pad 45, a stack ST, and a substrate 100, can be disposed on a peripheral circuit structure PS. The substrate 100 can be disposed on the stack ST. The stack ST can be disposed between the substrate 100 and the peripheral circuit structure PS.

[0147] The second bonding pad 45, the connecting contact plug 41, the connecting circuit interconnect 43, and the fourth insulating layer 40 can be disposed on the first insulating layer 30. Here, the second bonding pad 45 can be configured to contact the first bonding pad 35 of the peripheral circuit structure PS, the connecting circuit interconnect 43 can be electrically connected to the second bonding pad 45 via the connecting contact plug 41, and the fourth insulating layer 40 can be configured to surround the second bonding pad 45, the connecting contact plug 41, and the connecting circuit interconnect 43. The fourth insulating layer 40 can have a multilayer structure comprising multiple insulating layers. For example, the fourth insulating layer 40 can be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material, or include at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material. The width of the connecting contact plug 41 in the first direction D1 or the second direction D2 can decrease as the height in the third direction D3 or the distance from the peripheral substrate 10 increases. The connecting contact plug 41 and the connecting circuit interconnect 43 can include at least one of a metal or a conductive material.

[0148] The fourth insulating layer 40 may not cover the bottom surface of the second bonding pad 45. The bottom surface of the fourth insulating layer 40 may be substantially coplanar with the bottom surface of the second bonding pad 45. The bottom surface of each of the second bonding pads 45 may be in direct contact with the top surface of each of the first bonding pads 35. The first bonding pads 35 and the second bonding pads 45 may be formed of at least one of a metallic material (e.g., copper (Cu), tungsten (W), aluminum (Al), nickel (Ni), or tin (Sn)), or may include at least one of a metallic material (e.g., copper (Cu), tungsten (W), aluminum (Al), nickel (Ni), or tin (Sn)). For example, the first bonding pads 35 and the second bonding pads 45 may be formed of copper (Cu) or may include copper (Cu). The first bonding pads 35 and the second bonding pads 45 may be connected to each other without any interface between them to form a single object. The side surfaces of the first bonding pads 35 and the second bonding pads 45 are shown as aligned with each other, but the invention is not limited to this example. For example, when viewed in a plan view, the side surfaces of the first bonding pad 35 and the second bonding pad 45 may be spaced apart from each other.

[0149] The bit line BL, which contacts the connecting contact plug 41, as well as the first conductive line CL1 and the second conductive line CL2, can be disposed in the upper part of the fourth insulating layer 40. The third insulating layer 230 can be disposed on the fourth insulating layer 40, and the stacked ST and the second insulating layer 170 can be disposed on the third insulating layer 230.

[0150] The lengths of the first gate electrode EL1 of the first stack ST1 and the second gate electrode EL2 of the second stack ST2 in the first direction D1 can increase with the increase of the distance from the peripheral substrate 10 in the third direction D3. Figure 24 When viewed in a plan view, the side surfaces of the first gate electrode EL1 and the second gate electrode EL2 can be spaced apart from each other by a specific distance in the first direction D1. The lowermost second gate electrode EL2 in the second gate electrode EL2 of the second stack ST2 can have the minimum length in the first direction D1, and the uppermost first gate electrode EL1 in the first gate electrode EL1 of the first stack ST1 can have the maximum length in the first direction D1. Similar to the first gate electrode EL1 and the second gate electrode EL2, the lengths of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 in the first direction D1 can increase with the increase of the distance from the peripheral substrate 10 in the third direction D3.

[0151] The widths of the bit-line contact plug BLCP, unit contact plug CCP, peripheral contact plug TCP, vertical channel structure VS, and dummy vertical channel structure DVS in the first direction D1 or the second direction D2 can decrease as the height in the third direction D3 increases. The width of the separation structure 160 in the second direction D2 can decrease as the height in the third direction D3 increases.

[0152] Input / output pads (IOPs) can be disposed on the second insulating layer 170. These IOPs are electrically connected to at least one peripheral circuit transistor (PTR) of the peripheral circuit structure PS via peripheral contact plugs (TCPs). The input / output pads (IOPs) can correspond to... Figure 1 Input / output pads 1101 or Figure 3 and Figure 4 One of the input / output pads 2210.

[0153] Because the cell array structure CS is placed on the peripheral circuit structure PS, the cell capacity per unit area in the semiconductor device can be increased. Furthermore, the peripheral circuit structure PS and the cell array structure CS can be fabricated separately and then coupled to each other, thus preventing damage to the peripheral circuit transistor PTR due to various thermal processing steps. Therefore, the electrical and reliability characteristics of the semiconductor device can be improved.

[0154] According to embodiments of the present invention, voids can be intentionally formed in each of the vertical channel holes penetrating the molded structure. In this case, cracking or warping problems due to stress in the molded structure can be prevented. Therefore, semiconductor devices with improved electrical and reliability characteristics can be provided.

[0155] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A lower molded structure is formed on the substrate; A first molding structure is formed on the lower molding structure, the first molding structure comprising a first interlayer insulating layer and a first sacrificial layer alternately stacked in a vertical direction; A first vertical channel hole is formed to penetrate a portion of the substrate, the first molding structure, and the lower molding structure; as well as An active layer is formed to cover the top surface of the first molded structure and extend to the upper surface of each of the first vertical channel holes. The active layer includes a horizontal portion covering the top surface of the first molded structure and a vertical portion covering the upper surface of each of the first vertical channel holes. The active layer comprises a metallic material.

2. The method according to claim 1, wherein, When measured along the vertical direction, the vertical length of the vertical portion is 15% to 50% of the length of each of the first vertical channel holes.

3. The method according to claim 1, further comprising: A molded sacrificial layer is formed on the active layer to fill the upper part of each of the first vertical channel holes; as well as A void is formed in the remainder of each of the first vertical channel holes.

4. The method according to claim 3, further comprising: The active layer and the molding sacrificial layer are removed from the top surface of the first molded structure to form an active pattern and a molding sacrificial pattern in the upper part of each of the first vertical channel holes.

5. The method according to claim 4, further comprising: A second molding structure is formed on the first molding structure to include a second interlayer insulating layer and a second sacrificial layer that are alternately stacked along the vertical direction.

6. The method according to claim 5, further comprising: A second vertical channel hole is formed to pass through the second molding structure. The second vertical channel hole overlaps vertically with the first vertical channel hole.

7. The method according to claim 1, further comprising: After the first vertical channel hole is formed and before the active layer is formed, a barrier layer is formed to conformally cover the side and bottom surfaces of each of the first vertical channel holes and extend to a region on the top surface of the first molded structure.

8. The method according to claim 7, further comprising: A molded sacrificial layer is formed on the active layer to fill the upper portion of each of the first vertical channel holes and to form voids in the remaining portion of each of the first vertical channel holes. The active layer and the molding sacrificial layer are removed from the top surface of the first molded structure to form an active pattern and a molding sacrificial pattern in the upper part of each of the first vertical channel holes; as well as The barrier layer is removed from the top surface of the first molded structure to form a barrier pattern in the side and bottom surfaces of each of the first vertical channel holes.

9. The method according to claim 8, further comprising: A second molding structure is formed on the first molding structure, the second molding structure comprising a second interlayer insulating layer and a second sacrificial layer alternately stacked along the vertical direction; as well as A second vertical channel hole is formed to penetrate the second molded structure. The second vertical channel hole overlaps vertically with the first vertical channel hole.

10. A method for manufacturing a semiconductor device, the method comprising: A first molded structure is formed on a substrate, the first molded structure comprising a first interlayer insulating layer and a first sacrificial layer alternately stacked in a vertical direction; A vertical channel hole is formed to penetrate the first molded structure; as well as An active layer is formed to cover the top surface of the first molded structure and extend to the upper surface of the vertical channel hole. The active layer includes a horizontal portion covering the top surface of the first molded structure and a vertical portion covering the upper surface of the vertical channel hole. The width of the vertical portion, measured in a horizontal direction parallel to the top surface of the substrate, increases with increasing distance from the substrate.

11. The method according to claim 10, wherein, The active layer comprises a metallic material.

12. The method according to claim 11, wherein, The active layer includes boron (B).

13. The method according to claim 10, wherein, When measured along the vertical direction, the vertical length of the vertical portion is 15% to 50% of the length of the vertical channel hole.

14. The method of claim 10, further comprising: A molded sacrificial layer is formed on the active layer to fill the upper part of the vertical channel hole; as well as A void is formed in the remaining portion of the vertical channel hole.

15. The method according to claim 14, wherein, The upper part of the gap has a conical shape.

16. The method of claim 14, further comprising: The active layer and the molding sacrificial layer are removed from the top surface of the first molded structure to form an active pattern and a molding sacrificial pattern in the upper part of the vertical channel hole.

17. The method of claim 16, further comprising: A second molding structure is formed on the first molding structure, the second molding structure comprising a second interlayer insulating layer and a second sacrificial layer alternately stacked along the vertical direction.

18. The method of claim 10, further comprising: After the vertical channel hole is formed and before the active layer is formed, a barrier layer is formed to conformally cover the side and bottom surfaces of the vertical channel hole and extend to the top surface of the first molded structure.

19. A method for manufacturing a semiconductor device, the method comprising: A first molded structure is formed on a substrate to include a first interlayer insulating layer and a first sacrificial layer that are alternately stacked in a vertical direction; A first vertical channel hole is formed to penetrate a portion of the substrate and the first molded structure; An active layer is formed to cover the top surface of the first molded structure and extend to the upper surface of each of the first vertical channel holes; A molded sacrificial layer is formed on the active layer to fill the upper part of each of the first vertical channel holes; A void is formed in the remainder of each of the first vertical channel holes; After removing the active layer and the molding sacrificial layer from the top surface of the first molding structure, a second molding structure is formed on the first molding structure to include a second interlayer insulating layer and a second sacrificial layer that are alternately stacked along the vertical direction. A second vertical channel hole is formed to penetrate the second molded structure, and each of the second vertical channel holes vertically overlaps each of the first vertical channel holes; The first stack is formed by filling the empty space created by removing the first sacrificial layer, to include the first interlayer insulating layer and the first gate electrode alternately stacked along the vertical direction; as well as A second stack is formed by filling the empty spaces created by removing the second sacrificial layer, to include a second interlayer insulating layer and a second gate electrode that are alternately stacked along the vertical direction.

20. The method according to claim 19, wherein, The uppermost first interlayer insulation layer in the first interlayer insulation layer of the first molded structure includes boron (B) on its top surface and on each of the adjacent side surfaces of the first vertical channel hole.

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