Semiconductor device and preparation method thereof, and storage system

Abstract

The invention discloses a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises a semiconductor structure and a peripheral circuit structure, the peripheral circuit structure is located on one side of the semiconductor structure in the first direction and coupled with the semiconductor structure, the semiconductor structure comprises a storage array, the peripheral circuit structure comprises a first semiconductor layer and a capacitor structure, and the capacitor structure comprises a first electrode layer and an electrode structure. The first electrode layer is located on the side, facing the semiconductor structure, of the first semiconductor layer in the first direction, and the electrode structure is opposite to the first electrode layer in the first direction.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and in particular to semiconductor devices, methods for fabricating them, and memory systems. Background Technology

[0002] Semiconductor devices are memory devices used in modern information technology to store information. Their main function is to store programs and various data, and to perform high-speed, automatic access to programs or data during computer operation. For example, a semiconductor device includes a memory array and peripheral circuitry. The peripheral circuitry can accurately control the access to programs or data in the memory array, ensuring the speed and accuracy of information processing.

[0003] Currently, how to further improve the performance of semiconductor devices is one of the technical problems that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a semiconductor device, a method for fabricating the same, and a storage system.

[0005] The first aspect of this application provides a semiconductor device, which includes a semiconductor structure and a peripheral circuit structure. The peripheral circuit structure is located on one side of the semiconductor structure along a first direction and is coupled to the semiconductor structure. The semiconductor structure includes a memory array. The peripheral circuit structure includes a first semiconductor layer and a capacitor structure. The capacitor structure includes a first electrode layer and an electrode structure. The first electrode layer is located on the side of the first semiconductor layer facing the semiconductor structure along the first direction. The electrode structure is disposed opposite to the first electrode layer in the first direction.

[0006] In some embodiments, the electrode structure extends through the first semiconductor layer along a first direction, and the capacitor structure further includes a first isolation layer that at least partially covers the sidewalls of the electrode structure extending along the first direction.

[0007] In some embodiments, the electrode structure includes a second isolation layer and a second electrode, the second isolation layer extending at least partially into the first semiconductor layer along a first direction, and the second electrode layer covering the sidewalls of the second isolation layer extending along the first direction and the side of the second isolation layer facing the first electrode layer along the first direction.

[0008] In some embodiments, the second isolation layer protrudes from the first semiconductor layer in a direction away from the first electrode layer along a first direction. The peripheral circuit structure also includes a first connection structure and a second connection structure. The first connection structure is located on the side of the first electrode layer away from the first semiconductor layer and is connected to the first electrode layer. The second connection structure penetrates the second isolation layer along the first direction and is connected to the second electrode layer.

[0009] In some embodiments, the second isolation layer is provided with a plurality of second connection structures, which are spaced apart in a second direction, and the second direction intersects with the first direction.

[0010] In some embodiments, the electrode structure is a single-layer structure, and the electrode structure protrudes from the first semiconductor layer along a first direction away from the first electrode layer.

[0011] In some embodiments, the portion of the electrode structure located in and close to the first semiconductor layer has a smaller dimension in the second direction than the portion located in and far from the first semiconductor layer in the second direction, and the second direction intersects the first direction.

[0012] In some embodiments, the capacitor structure further includes a capacitor dielectric layer located between the first electrode layer and the capacitor structure along a first direction, and the capacitor dielectric layer includes a first high dielectric layer in contact with the electrode structure.

[0013] In some embodiments, the electrode structure includes a third electrode layer located along a first direction on the side of the first electrode layer away from the first semiconductor layer, and the capacitor structure further includes a second high-dielectric layer located between the first electrode layer and the first semiconductor layer, and a capacitor dielectric layer located between the first electrode layer and the third electrode layer.

[0014] In some embodiments, the peripheral circuit structure further includes a third connection structure and a fourth connection structure. The third connection structure extends through the first semiconductor layer and the second high dielectric layer along a first direction and is connected to the first electrode layer. The fourth connection structure is located on the side of the third electrode layer opposite to the capacitor dielectric layer and is connected to the third electrode layer.

[0015] In some embodiments, the third connection structure protrudes from the first semiconductor layer in a direction away from the first electrode layer along a first direction. The third connection structure includes a conductive connection structure and a third isolation layer. The conductive connection structure extends along the first direction, and the third isolation layer at least partially covers the sidewalls of the conductive connection structure extending along the first direction.

[0016] In some implementations, the peripheral circuit structure includes multiple capacitor structures, which have different structures.

[0017] In some implementations, the peripheral circuit structure includes a transistor and a trench isolation structure, wherein the transistor is at least partially located in a first semiconductor layer, and the trench isolation structure is at least partially located in the first semiconductor layer and surrounds the active region of the transistor and the capacitor structure.

[0018] In some embodiments, the transistor includes a gate conductive layer and a gate dielectric layer, the gate conductive layer being located along a first direction on the side of the first semiconductor layer facing the semiconductor structure, the gate dielectric layer being located between the gate conductive layer and the first semiconductor layer, and the gate conductive layer being made of the same material as the first electrode layer.

[0019] In some embodiments, the peripheral circuit structure further includes a first dielectric layer and a first interconnect layer. The first dielectric layer is located on the side of the first semiconductor layer facing the semiconductor structure and covers the first electrode layer. The first dielectric layer is bonded to the semiconductor structure. The first interconnect layer is located on the side of the first semiconductor layer away from the first dielectric layer. The electrode structure is connected to the first interconnect layer.

[0020] In some embodiments, the semiconductor structure further includes a second interconnect layer located on the side of the memory array facing the first semiconductor layer and connected to the memory array, and the second interconnect layer is bonded to the peripheral circuit structure.

[0021] A second aspect of this application provides a method for fabricating a semiconductor device, the method comprising: forming an initial peripheral circuit structure, the initial peripheral circuit structure including a first semiconductor layer and a first electrode layer of a capacitor structure; coupling the initial peripheral circuit structure to a semiconductor structure, the semiconductor structure including a memory array; and forming a peripheral circuit structure based on the initial peripheral circuit structure; wherein the peripheral circuit structure includes a first semiconductor layer and a capacitor structure, the capacitor structure includes a first electrode layer and an electrode structure, the first electrode is located along a first direction on the side of the first semiconductor layer facing the semiconductor structure, and the electrode structure is disposed opposite to the first electrode layer along the first direction.

[0022] In some embodiments, the first electrode layer is located on the side of the first surface of the first semiconductor layer facing the semiconductor structure; wherein forming the initial peripheral circuit structure includes: forming an initial isolation structure from the first surface and in the first semiconductor layer; and forming the first electrode layer on the side of the initial isolation structure away from the second surface of the first semiconductor layer, the first surface and the second surface being disposed opposite to each other along a first direction.

[0023] In some embodiments, forming a peripheral circuit structure based on an initial peripheral circuit structure includes: thinning a first semiconductor layer from a second surface to expose an initial isolation structure; forming a first electrode trench extending through the initial isolation structure along a first direction from a side of the first semiconductor layer away from the semiconductor structure; and forming an electrode structure within the first electrode trench.

[0024] In some embodiments, after thinning the first semiconductor layer and before forming the first electrode trench, the fabrication method further includes: depositing a first insulating material on the side of the first semiconductor layer opposite to the semiconductor structure; wherein forming the electrode structure in the first electrode trench includes: depositing a conductive material in the first electrode trench to form the electrode structure.

[0025] In some embodiments, forming an electrode structure within a first electrode trench includes: forming a second electrode layer on the inner wall of the first electrode trench, the second electrode layer surrounding the second electrode trench; and forming a second isolation layer that fills the second electrode trench and protrudes from the first semiconductor layer, the electrode structure including the second electrode layer and the second isolation layer.

[0026] In some embodiments, the fabrication method further includes: forming a second connection structure extending through the second isolation layer and extending to the second electrode layer along a first direction from the side of the second isolation layer away from the semiconductor structure.

[0027] In some embodiments, forming the initial peripheral circuit structure includes: forming a second high-dielectric layer on one side of the first semiconductor layer; forming a first electrode layer on the side of the second high-dielectric layer opposite to the first semiconductor layer; forming a capacitor dielectric layer on the side of the first electrode layer opposite to the second high-dielectric layer; and forming a third electrode layer on the side of the capacitor dielectric layer opposite to the first electrode layer, wherein the electrode structure includes the third electrode layer.

[0028] A third aspect of this application provides a storage system, which includes a controller and a semiconductor device according to the first aspect of this application. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0029] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0030] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of the application. In the drawings:

[0031] Figure 1 This is a top view schematic diagram of a semiconductor device according to one embodiment of this application;

[0032] Figure 2 This is a top view schematic diagram of a semiconductor device according to another embodiment of this application;

[0033] Figure 3 , Figure 5, Figures 7 to 11 These are cross-sectional schematic diagrams of semiconductor devices according to different embodiments of this application;

[0034] Figure 4 This is a top view schematic diagram of a capacitor structure according to one embodiment of this application;

[0035] Figure 6 This is a top view schematic diagram of a capacitor structure according to another embodiment of this application;

[0036] Figure 12 This is a schematic flowchart of a method for fabricating a semiconductor device according to one embodiment of this application;

[0037] Figures 13 to 20 This is a process schematic diagram of a method for fabricating a semiconductor device according to one embodiment of this application;

[0038] Figures 21 to 24 This is a process schematic diagram of a method for fabricating a semiconductor device according to another embodiment of this application;

[0039] Figures 25 to 28 This is a process schematic diagram of a method for fabricating a semiconductor device according to yet another embodiment of this application;

[0040] Figure 29 This is a block diagram of a system having semiconductor devices according to one embodiment of this application;

[0041] Figure 30 This is a schematic diagram of a memory card having a semiconductor device according to one embodiment of this application; and

[0042] Figure 31 This is a schematic diagram of a solid-state driver with semiconductor devices according to one embodiment of this application.

[0043] Figure label:

[0044] 100. Semiconductor structure; 101. First region; 102. Second region;

[0045] 110. Memory array; 111. Peripheral circuitry; 120. Second interconnect layer;

[0046] 130. Stacked structure; 131. Interlayer dielectric layer; 132. First gate layer;

[0047] 140. Channel structure; 150. Semiconductor pillar; 160. Gate structure;

[0048] 161. Gate dielectric layer; 162. Second gate layer; 170. Second bonding layer;

[0049] 171. Second bonding contact; 200. Peripheral circuit structure;

[0050] 200' Initial peripheral circuit structure; 210 First semiconductor layer; 211 First surface;

[0051] 212. Second surface; 220. Capacitor structure; 221. First electrode layer;

[0052] 222, Electrode structure; 222-1, Second isolation layer; 222-2, Second electrode layer;

[0053] 222-3, First electrode trench; 222-4, Second electrode trench; 223, Capacitor dielectric layer;

[0054] 223', First high dielectric layer; 224, First isolation layer; 225, Third electrode layer;

[0055] 226. Second high dielectric layer; 227. Initial isolation structure; 228. Isolation capping layer;

[0056] 231. First connection structure; 232. Second connection structure; 233. Third connection structure;

[0057] 233-1, Conductive connection structure; 233-2, Third isolation layer; 234, Fourth connection structure;

[0058] 240. Transistor; 241. Gate conductive layer; 242. Gate dielectric layer; 243. Drain;

[0059] 244. Source electrode; 250. Trench isolation structure; 260. First dielectric layer;

[0060] 270, First interconnect layer; 280, Passivation layer; 290, First bonding layer;

[0061] 291, First bonding contact; 300, System; 301, Memory system;

[0062] 302. Semiconductor device; 303. Memory controller; 304. Main unit;

[0063] 310. Memory card; 311. Memory card connector; 320. SSD;

[0064] 321. SSD connector. Detailed Implementation

[0065] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0066] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0067] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale.

[0068] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0069] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0070] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0071] Furthermore, in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. Furthermore, in this application, the use of "connection" or "joint" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context.

[0072] Figure 1 A top view schematic diagram of a semiconductor device according to one embodiment of this application is shown. Figure 1 As shown, this application provides a semiconductor device including a dielectric capping layer, a semiconductor layer, a memory array 110, and peripheral circuitry 111. The memory array 110 and peripheral circuitry 111 are located on the same side of the semiconductor layer in a first direction, and the dielectric capping layer covers both the memory array 110 and the peripheral circuitry 111. The semiconductor layer includes a first region 101 and a second region 102 located on one side of the first region 101 along a second direction. The memory array 110 is located in the first region 101, and the peripheral circuitry 111 is located in the second region 102. The first direction and the second direction intersect. As an example, the first direction can be the z-direction, and the second direction can be the x-direction shown in the figures.

[0073] The peripheral circuit 111 includes a capacitor structure, a first electrode lead-out structure, and a second electrode lead-out structure (not shown). The capacitor structure includes an electrode layer and a capacitor dielectric layer located between the electrode layer and the semiconductor layer. The first electrode lead-out structure penetrates the dielectric cap layer along a first direction and is connected to the electrode layer. The second electrode lead-out structure penetrates the dielectric cap layer and the capacitor dielectric layer along the first direction and is connected to the semiconductor layer.

[0074] As can be seen from the above, in the embodiments of this application, the storage array 110 and the peripheral circuit 111 are formed on the same semiconductor layer. The semiconductor layer, the capacitor dielectric layer and the electrode layer together constitute a capacitor. The semiconductor layer and the electrode layer are the two electrodes of the capacitor. The first electrode lead-out structure and the second electrode lead-out structure lead out the two electrodes from the same side of the dielectric cover layer, respectively.

[0075] As the storage density of the memory array increases, the number of peripheral devices such as capacitors in the peripheral circuit also increases. In order to reduce the overall area of ​​the semiconductor device, this application provides another semiconductor device. Figure 2 A top view schematic diagram of a semiconductor device according to another embodiment of this application is shown. Figure 3 , Figure 5 , Figures 7 to 11Cross-sectional schematic diagrams of semiconductor devices according to different embodiments of this application are shown. For example... Figure 2 , Figure 3 , Figure 5 , Figures 7 to 11 As shown, the semiconductor device includes a semiconductor structure 100 and a peripheral circuit structure 200. The peripheral circuit structure 200 is located on one side of the semiconductor structure 100 along a first direction and coupled to the semiconductor structure 100. The semiconductor structure 100 includes a memory array 110, and the peripheral circuit structure 200 includes a first semiconductor layer 210 and a capacitor structure 220. The capacitor structure 220 may include a first electrode layer 221 and an electrode structure 222. The first electrode layer 221 is located on the side of the first semiconductor layer 210 facing the semiconductor structure 100 along the first direction, and the electrode structure 222 is disposed opposite to the first electrode layer 221 in the first direction.

[0076] In this embodiment, the semiconductor structure 100 and the peripheral circuit structure 200 are coupled in a first direction. The capacitor structure 220 of the peripheral circuit structure 200 no longer occupies the area of ​​the storage array 110. Therefore, with a fixed overall area of ​​the semiconductor device, this embodiment not only allows for a larger area of ​​the storage array 110 (in other words, a larger storage capacity), but also allows for a higher density of capacitor structures 220 in the peripheral circuit structure 200. Furthermore, in this embodiment, the first electrode layer 221 and the electrode structure 222 are respectively two electrodes of the capacitor structure 220, eliminating the need to use the semiconductor layer as one of the electrodes.

[0077] It should be noted that the semiconductor device provided in the embodiments of this application can be a memory or a part of a memory. As an example, the first direction in the embodiments of this application can be the z-direction shown in the figures.

[0078] In some implementations, such as Figure 3 and Figure 5 As shown, the first electrode layer 221 is located on one side of the first semiconductor layer 210, and the electrode structure 222 penetrates the first semiconductor layer 210 along a first direction. The first electrode layer 221 and the electrode structure 222 are disposed opposite to each other in the first direction, and the first electrode layer 221 and the electrode structure 222 are respectively the two electrodes of the capacitor structure 220. As an example, in order to isolate the electrode structure 222 from the first semiconductor layer 210, the capacitor structure 220 further includes a first isolation layer 224. The first isolation layer 224 at least partially covers the sidewall of the electrode structure 222 extending along the first direction; in other words, at least a portion of the first isolation layer 224 surrounds the electrode structure 222. The material of the first isolation layer 224 may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride.

[0079] In the embodiments of this application, the electrode structure 222 can be a single-layer structure or a multi-layer structure. Figure 4 and Figure 5 Top views of electrode structures 222 in different embodiments are shown. For example, as... Figure 3 and Figure 4 As shown, the electrode structure 222 is a multilayer structure extending through the first semiconductor layer 210 along a first direction. The electrode structure 222 includes a second isolation layer 222-1 and a second electrode layer 222-2. The second isolation layer 222-1 extends at least partially into the first semiconductor layer 210 along the first direction. The second electrode layer 222-2 covers the sidewalls of the second isolation layer 222-1 extending along the first direction and the side of the second isolation layer 222-1 facing the first electrode layer 221 along the first direction. The material of the second isolation layer 222-1 may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. The material of the second electrode layer 222-2 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, and silicides. For example, as... Figure 5 and Figure 6 As shown, electrode structure 222 is a single-layer structure penetrating the first semiconductor layer 210 along a first direction. The material of electrode structure 222 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, and silicides. As an example, the portion of electrode structure 222 located in the first semiconductor layer 210 and close to the first electrode layer 221 has a smaller dimension in the second direction than the portion of electrode structure 222 located in the first semiconductor layer 210 and far from the first electrode layer 221, and the first direction intersects the second direction. The intersection of the first and second directions can generally be understood as an angle between them. For example, the first and second directions are perpendicular or approximately perpendicular to each other. As an example, the first direction may be the z-direction in the figure, and the second direction may be the x-direction in the figure.

[0080] like Figure 3 As shown, considering that the electrode structure 222 includes a second isolation layer 222-1 and a second electrode layer 222-2, the area of ​​the second electrode layer 222-2 exposed on the surface of the first semiconductor layer 210 at the end facing away from the first electrode layer 221 is small. To facilitate the lead-out of the first electrode layer 221 and reduce contact resistance, the peripheral circuit structure 200 may also include a first connection structure 231 and a second connection structure 232. The first connection structure 231 is connected to the first electrode layer 221, and the second connection structure 232 penetrates the second isolation layer 222-1 along a first direction and is connected to the second electrode layer 222-2. The second isolation layer 222-1 protrudes from the first semiconductor layer 210 in a direction away from the first electrode layer 221 along the first direction. As an example, such as Figure 4As shown, the second isolation layer 222-1 may have multiple second connection structures 232, which are spaced apart in the second direction. It should be noted that the first connection structure 231 and the second connection structure 232 may lead the first electrode layer 221 and the second electrode layer 222-2 out from opposite directions, respectively. In this case, the first connection structure 231 may be located on the side of the first electrode layer 221 away from the first semiconductor layer 210. In other embodiments, if the projection of the first electrode layer 221 and the projection of the second electrode layer 222-2 do not overlap on a plane perpendicular to the first direction, then the first connection structure 231 and the second connection structure 232 may also lead the first electrode layer 221 and the second electrode layer 222-2 out from the same direction, respectively. In this case, the first connection structure 231 may be located on the side of the first electrode layer 221 away from the semiconductor structure 100.

[0081] like Figure 5 As shown, when the electrode structure 222 is a single-layer structure, the electrode structure 222 can protrude from the first semiconductor layer 210 along the first direction away from the first electrode layer 221. The electrode structure 222 can be directly connected to other components such as interconnect layers, and the first electrode layer 221 is led out through the first connection structure 231. As an example, the first connection structure 231 can be located on the side of the first electrode layer 221 away from the first semiconductor layer 210 and connected to the first electrode layer 221. In this case, the leading directions of the first electrode layer 221 and the electrode structure 222 are opposite. In other embodiments, if the projection of the first electrode layer 221 and the projection of the electrode structure 222 do not overlap on a plane perpendicular to the first direction, then the first connection structure 231 can be located on the side of the first electrode layer 221 away from the semiconductor structure 100. In this case, the leading directions of the first electrode layer 221 and the electrode structure 222 are the same.

[0082] In some embodiments, the capacitor structure 220 further includes a capacitor dielectric layer 223, which is located between the first electrode layer 221 and the electrode structure 222 in a first direction. The capacitor dielectric layer 223 includes a first high-dielectric layer 223' that contacts the electrode structure 222. The material of the first high-dielectric layer 223' may include, but is not limited to, materials with high dielectric constants such as alumina, hafnium oxide, zirconium oxide, tantalum pentoxide, or silicon oxynitride. As an example, the first high-dielectric layer 223' contacts both the first electrode layer 221 and the electrode structure 222. Since the first high-dielectric layer 223' contacts both the first electrode layer 221 and the electrode structure 222 in this embodiment, in other words, there is no silicon oxide film between the first electrode layer 221 and the electrode structure 222. Therefore, the problem of reduced EOT (Equivalence Oxide Thickness) due to the presence of a silicon oxide film can be avoided, thereby increasing the capacitance density of the entire capacitor structure 220.

[0083] like Figure 7 As shown, in some other embodiments, the first electrode layer 221 and the electrode structure 222 are located on the same side of the first semiconductor layer 210. For example, the capacitor structure 220 further includes a capacitor dielectric layer 223 and a second high-dielectric layer 226. The electrode structure 222 includes a third electrode layer 225. The second high-dielectric layer 226 is located between the first electrode layer 221 and the first semiconductor layer 210. The third electrode layer 225 is located in a first direction on the side of the first electrode layer 221 away from the second high-dielectric layer 226. The capacitor dielectric layer 223 is located between the first electrode layer 221 and the third electrode layer 225. The material of the third electrode layer 225 may include, but is not limited to, titanium nitride. The material of the second high-dielectric layer 226 may include, but is not limited to, materials with high dielectric constants such as alumina, hafnium oxide, zirconium oxide, tantalum pentoxide, or silicon oxynitride. The material of the capacitor dielectric layer 223 may include, but is not limited to, dielectric materials such as silicon oxide. As an example, the first electrode layer 221 and the third electrode layer 225 can be led out through the third connection structure 233 and the fourth connection structure 234, respectively. The third connection structure 233 and the fourth connection structure 234 can lead out the first electrode layer 221 and the third electrode layer 225 from the same direction or from opposite directions. For example, the third connection structure 233 penetrates the first semiconductor layer 210 and the second high dielectric layer 226 along a first direction and is connected to the first electrode layer 221, and the fourth connection structure 234 is located on the side of the third electrode layer 225 away from the capacitor dielectric layer 223 and is connected to the third electrode layer 225.

[0084] Since the third connection structure 233 needs to penetrate the first semiconductor layer 210, in order to achieve electrical isolation, the third connection structure 233 includes a conductive connection structure 233-1 and a third isolation layer 233-2. The conductive connection structure 233-1 extends along a first direction, and at least a portion of the third isolation layer 233-2 covers the sidewalls of the conductive connection structure 233-1 extending along the first direction. The material of the conductive connection structure 233-1 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, and silicides. The material of the third isolation layer 233-2 may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. To facilitate connection with other components such as interconnect layers, the third connection structure 233 protrudes from the first semiconductor layer 210 along the first direction away from the first electrode layer 221; in other words, the conductive connection structure 233-1 protrudes from the first semiconductor layer 210 along the first direction away from the first electrode layer 221.

[0085] It should be noted that, as Figures 8 to 11 As shown, the peripheral circuit structure 200 in this embodiment may include multiple capacitor structures 220 with different structures to improve the freedom of capacitor selection. For example, at least one capacitor structure 220 may include a first electrode layer 221, a first isolation layer 224, a second isolation layer 222-1, a first high dielectric layer 223', and a second electrode layer 222-2; at least one capacitor structure 220 may include a first electrode layer 221, a first isolation layer 224, a first high dielectric layer 223', and an electrode structure 222 with a single-layer structure; at least one capacitor structure 220 may include a first electrode layer 221, a second high dielectric layer 226, a third electrode layer 225, and a capacitor dielectric layer 223.

[0086] In some embodiments, the peripheral circuit structure 200 may further include at least one of high-voltage devices, low-voltage devices, and ultra-low-voltage devices. High-voltage devices may include, but are not limited to, at least one of row decoders, column decoders, word line drivers, and bit line drivers; low-voltage devices may include, but are not limited to, page buffers or logic devices; and ultra-low-voltage devices may include, but are not limited to, I / O circuits. High-voltage devices typically operate at voltages greater than 3.3V, for example, 5V to 30V. For example, the operating voltage of a high-voltage device could be 5V, 10V, 15V, 20V, 25V, or 30V. Low-voltage devices typically operate at voltages between 1.3V and 3.3V. For example, the operating voltage of a low-voltage device could be 1.3V, 1.8V, 2.3V, 2.8V, or 3.3V. Ultra-low-voltage devices typically operate at voltages lower than 1.3V, for example, 0.9V to 1.2V. For example, the operating voltage of an ultra-low-voltage device could be 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, or 1.2V. It should be noted that the operating voltage of a high-voltage, low-voltage, or ultra-low-voltage device can also be any value between any two of the above voltage values. Those skilled in the art should understand that the description of the operating voltage ranges of high-voltage, low-voltage, and ultra-low-voltage devices above is for better understanding of this solution and does not constitute a limitation of this application.

[0087] As an example, high-voltage devices, ultra-low-voltage devices, and controllers may include, but are not limited to, at least one of transistors, diodes, resistors, and inductors. For instance, the peripheral circuit structure 200 also includes a transistor 240 and a trench isolation structure 250, with at least a portion of the transistor 240 located in the first semiconductor layer 210, and at least a portion of the trench isolation structure 250 located in the first semiconductor layer 210 and surrounding the active region of the transistor 240 and the capacitor structure 220. The transistor 240 may include a gate conductive layer 241 and a gate dielectric layer 242. The gate conductive layer 241 is located along a first direction on the side of the first semiconductor layer 210 facing the semiconductor structure 100, and the gate dielectric layer 242 is located between the gate conductive layer 241 and the first semiconductor layer 210. In some embodiments, the gate conductive layer 241 and the first electrode layer 221 are made of the same material; in other words, the gate conductive layer 241 and the first electrode layer 221 can be formed in the same process, and the first electrode layer 221 is a virtual gate conductive layer. The embodiments of this application utilize a virtual gate conductive layer as the first electrode layer 221 of the capacitor structure 220, which is not only compatible with existing processes, but also does not occupy additional area.

[0088] In some embodiments, the peripheral circuit structure 200 further includes a first dielectric layer 260 and a first interconnect layer 270. The first dielectric layer 260 is located on the side of the first semiconductor layer 210 facing the semiconductor structure 100 and covers the first electrode layer 221. The first dielectric layer 260 is bonded to the semiconductor structure 100. The first interconnect layer 270 is located on the side of the first semiconductor layer 210 away from the first dielectric layer 260. The electrode structure 222 is connected to the first interconnect layer 270. As an example, the first interconnect layer 270 includes a first interconnect structure connected to the electrode structure 222.

[0089] In some embodiments, the semiconductor structure 100 further includes a second interconnect layer 120, which is located on the side of the memory array 110 facing the first semiconductor layer 210 and connected to the memory array 110. The second interconnect layer 120 is bonded to the peripheral circuit structure 200. As an example, the second interconnect layer 120 includes a plurality of second interconnect structures connected to the memory array 110.

[0090] It should be noted that, in the embodiments of this application, the memory array 110 of the semiconductor structure 100 can be a non-volatile memory array such as a NAND memory array, a PROM (Programmable Read-Only memory) memory array, or a NOR memory array, or a volatile memory array such as a DRAM (Dynamic Random Access Memory) memory array or an SRAM (Static Random-Access Memory) memory array. This application does not limit it in this respect.

[0091] For example, such as Figure 3As shown, the memory array 110 includes a stacked structure 130 and a channel structure 140. The channel structure 140 extends through the stacked structure 130 along a first direction. The stacked structure 130 includes an interlayer dielectric layer 131 and a first gate layer 132 alternately stacked along the first direction. The channel structure 140 includes a functional layer and a channel layer. The functional layer includes a barrier layer, a charge trapping layer, and a tunneling layer. The tunneling layer is located at least on the sidewall of the channel layer extending along the first direction. The charge trapping layer is located on the side of the tunneling layer opposite to the channel layer, and the barrier layer is located on the side of the charge trapping layer opposite to the tunneling layer. The material of the channel layer may include, but is not limited to, semiconductor materials such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The materials of the barrier layer and the tunneling layer may be, but are not limited to, silicon oxide. The material of the charge trapping layer may be, but is not limited to, silicon nitride. In other words, the functional layer may have an ONO structure. In the embodiments of this application, both the functional layer and the channel layer can be formed by thin film deposition process. The thin film deposition process can be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination of the above processes.

[0092] The functional layer and channel layer of the channel structure 140, along with a portion of the first gate layer 132 of the stacked structure 130 and a portion of the first gate layer 132, together constitute a memory cell. Multiple memory cells are connected in series along the stacking direction of the stacked structure 130, i.e., the first direction, to form a memory string. Memory cells located in the same row, i.e., distributed along the second direction, can be connected to the same word line. The remaining portion of the first gate layer 132 can serve as the word line for multiple memory cells in the corresponding memory string. Memory cells in each memory string, i.e., the same column, can be connected to the same bit line. Under the voltage control of the corresponding word line, charge carriers in the channel layer of the memory cell enter the charge trapping layer of the functional layer, or charge carriers in the charge trapping layer of the functional layer retreat back to the channel layer, thereby realizing the programming or erasure of the memory cell. In the case where the peripheral circuit structure 200 includes a page buffer, a word line driver, and I / O circuitry, the page buffer is connected to the bit line to apply a bit line voltage to the bit line. The bit line voltage corresponds to the data DATA to be programmed, and the data DATA may include multiple bits of data. During a read operation, the page buffer can sense the data DATA stored in the selected memory cell via the bit line and output the sensed data DATA to the I / O circuit. The word line driver connects to the word line via word line contacts to apply a word line voltage to the word line, thereby performing an erase operation on the memory cell corresponding to that word line.

[0093] In other implementations, such as Figure 10 and Figure 11As shown, the memory array 110 may include a semiconductor pillar 150 and a gate structure 160. The semiconductor pillar 150 extends along a first direction, and the gate structure 160 is located on the sidewall of the semiconductor pillar 150 extending along the first direction. The semiconductor pillar 150 includes a source and a drain distributed along the first direction and a channel located between the source and the drain. The gate structure 160 includes a gate dielectric layer 161 and a second gate layer 162. The second gate layer 162 is located in a second direction on the side of the gate dielectric layer 161 opposite to the semiconductor pillar 150.

[0094] This application also provides a method for fabricating a semiconductor device. Figure 12 A schematic flowchart of a method for fabricating a semiconductor device according to one embodiment of this application is shown.

[0095] Figures 13 to 28 A schematic diagram of the fabrication process of a semiconductor device according to one embodiment of this application is shown. Figures 12 to 28 As shown, the preparation method 1000 includes:

[0096] S100, forming an initial peripheral circuit structure 200', the initial peripheral circuit structure 200' including a first semiconductor layer 210 and a first electrode layer 221 of a capacitor structure 220;

[0097] S200, the initial peripheral circuit structure 200' is coupled to the semiconductor structure 100, the semiconductor structure 100 including the memory array 110;

[0098] S300. Based on the initial peripheral circuit structure 200', a peripheral circuit structure 200 is formed. The peripheral circuit structure 200 includes a first semiconductor layer 210 and a capacitor structure 220. The capacitor structure 220 includes a first electrode layer 221 and an electrode structure 222. The first electrode is located on the side of the first semiconductor layer 210 facing the semiconductor structure 100 along a first direction. The electrode structure 222 is disposed opposite to the first electrode layer 221 along the first direction.

[0099] The following is a detailed description of each step in the semiconductor device fabrication method in the embodiments of this application.

[0100] Step S100

[0101] like Figure 13As shown, in step S100, an initial peripheral circuit structure 200' is formed, which includes a first semiconductor layer 210 and a first electrode layer 221. The first semiconductor layer 210 has a first surface 211 and a second surface 212 disposed opposite to each other along a first direction. The first electrode layer 221 may be located on the side of the first surface 211 of the first semiconductor layer 210 facing the semiconductor structure 100. As an example, the first semiconductor layer 210 can be a single-layer structure or a multi-layer structure. For example, the material of the first semiconductor layer 210 may include, but is not limited to, group III-V compounds such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide. In some embodiments, a portion of the first semiconductor layer 210 may have a well region formed by doping with an N-type or P-type dopant. The dopant may include at least one of phosphorus (P), arsenic (As), and antimony (Sb).

[0102] In some embodiments, the initial peripheral circuit structure 200' includes a first semiconductor layer 210, a first electrode layer 221, and a capacitor dielectric layer 223. Thus, the initial peripheral circuit structure 200' can be formed as follows: an isolation trench (not shown) is formed in the first semiconductor layer 210 from its first surface 211; as an example, the isolation trench can be formed in the first semiconductor layer 210 using a dry etching process, a combination of dry and wet etching processes, or a patterning process; the dimension of the isolation trench in the second direction can be smaller than the dimension of the isolation trench in the third direction, and the first, second, and third directions intersect each other; an initial isolation structure 227 is formed within the isolation trench; the material of the initial isolation structure 227 can be, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. As an example, a thin-film deposition process can be used to deposit an isolation material on one side of the first semiconductor layer 210 to form the initial isolation structure 227 filling the isolation trench. Since the isolation material covers the first surface 211 of the first semiconductor layer 210 during the actual deposition process, a chemical mechanical polishing (CMP) process can be used to remove the isolation material covering the first surface 211 of the first semiconductor layer 210 after the deposition process is completed. A capacitor dielectric layer 223 is formed on the side of the initial isolation structure 227 away from the second surface 212. The capacitor dielectric layer 223 includes a first high dielectric layer 223' in contact with the initial isolation structure 227. The first high dielectric layer 223' can be, but is not limited to, materials with high dielectric constants such as alumina, hafnium oxide, zirconium oxide, tantalum pentoxide, or silicon oxynitride. A first electrode layer 221 is formed on the side of the capacitor dielectric layer 223 away from the initial isolation structure 227. The first electrode layer 221 can also be formed using a thin film deposition process. The material of the first electrode layer 221 can be, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and silicides. The aforementioned thin film deposition process may be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination of the above processes.

[0103] Given that the surface of the first semiconductor layer 210 is easily oxidized to form a very thin silicon oxide film, the embodiments of this application can remove part of the silicon oxide film by forming an isolation trench, i.e., an initial isolation structure 227, in the first semiconductor layer 210. This results in almost no silicon oxide film between the subsequently formed first electrode layer 221 and electrode structure 222, thereby avoiding the problem of reduced EOT (Equivalence Oxide Thickness) due to the presence of silicon oxide film, and thus improving the capacitance density of the entire capacitor structure 220.

[0104] In some embodiments, step S100 may further include forming a first dielectric layer 260 covering the first electrode layer 221 and the first semiconductor layer 210. The material of the first dielectric layer 260 may include, but is not limited to, dielectric materials such as silicon oxide, silicon nitride, and / or silicon oxynitride. As an example, the first dielectric layer 260 may include multiple sub-dielectric layers. At least one sub-dielectric layer covering the first electrode layer 221 and the first semiconductor layer 210 may be formed first; then, a first connection hole is formed from the side of the at least one sub-dielectric layer away from the first semiconductor layer 210, extending through the at least one sub-dielectric layer in a first direction and reaching the first electrode layer 221; a first connection structure 231 is formed in the first connection hole, and the material of the first connection structure 231 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, and silicides; and the remaining sub-dielectric layers covering the first connection structure 231 are formed.

[0105] In some embodiments, the initial peripheral circuit structure 200' further includes a transistor 240 and a trench isolation structure 250, so step S100 may further include: forming the transistor 240 on the first semiconductor layer 210, with at least a portion of the transistor 240 located in the first semiconductor layer 210; for example, a well region may be formed in the first semiconductor layer 210, and if the transistor 240 is an N-type transistor, an ion implantation process or a diffusion process may be used to implant the transistor from the first surface 211 of the first semiconductor layer 210, or from within the first semiconductor layer 210. A P-type doped well is formed, and the dopant can be a P-type dopant such as boron (B). If transistor 240 is a P-type transistor, an N-type doped well can be formed in the first semiconductor layer 210 from the first surface 211 using an ion implantation process or a doping process. The dopant can be an N-type dopant such as phosphorus (P), arsenic (As), and antimony (Sb). A drain 243 and a source 244 are formed in the well region. If transistor 240 is an N-type transistor, phosphorus (P), arsenic (As), and antimony (Sb) can be used. N-type dopants are used to form the drain 243 and source 244 in the well region; if the transistor 240 is a P-type transistor, P-type dopants such as boron (B) can be used to form the source 244 and drain 243 in the well region; a gate dielectric layer 242 is formed on the first surface 211 of the first semiconductor layer 210, and the material of the gate dielectric layer 242 may include, but is not limited to, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, magnesium oxide, and tantalum oxide; a portion of the gate dielectric layer 242 is removed by an etching process to leave the remaining The remaining gate dielectric layer 242 is located between the source 244 and the drain 243 in the second direction. A gate conductive layer 241 is formed on the side of the gate dielectric layer 242 away from the first semiconductor layer 210. The material of the gate conductive layer 241 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and silicide. A portion of the gate conductive layer 241 is removed by an etching process, so that the remaining gate conductive layer 241 is located between the source 244 and the drain 243 in the second direction and covers the gate dielectric layer 242 in the first direction. A trench isolation structure 250 is formed in the first semiconductor layer 210 surrounding the active region of the transistor 240 and the initial isolation structure 227. The material of the trench isolation structure 250 may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. A passivation layer 280 is formed covering the transistor 240, the first electrode, and the first semiconductor layer 210. The material of the passivation layer 280 may include, but is not limited to, silicon nitride.

[0106] It should be noted that if transistor 240 has a low threshold voltage, then a lower concentration of dopant can be used to dope the first semiconductor layer 210 when forming the well region; if transistor 240 has a high threshold voltage, then a higher concentration of dopant can be used to dope the first semiconductor layer 210 when forming the well region. In some other embodiments, the source 244 and drain 243 can be directly formed in the first semiconductor layer 210; in other words, the step of forming the well region may not be included in the above steps. Furthermore, in order to improve the compactness of the trench isolation structure 250 and thus improve its electrical isolation effect, a high-temperature annealing treatment can be performed on the trench isolation structure 250 after its formation.

[0107] To simplify the process and reduce costs, the gate dielectric layer 242 and the first high-dielectric layer 223' can be formed in the same process; in other words, the gate dielectric layer 242 and the first high-dielectric layer 223' are made of the same material. For example, both the gate dielectric layer 242 and the first high-dielectric layer 223' can be formed from the same high-dielectric-constant material. Similarly, the gate conductive layer 241 and the first electrode layer 221 can also be formed in the same process; in other words, the gate conductive layer 241 and the first electrode layer 221 are made of the same material, and the first electrode layer 221 is a virtual gate conductive layer. Therefore, the embodiment of this application utilizes a virtual gate conductive layer as the first electrode layer 221 of the capacitor structure 220, which is not only compatible with existing processes but also does not occupy additional area.

[0108] In some embodiments, the initial peripheral circuit structure 200' may further include a first bonding layer 290 and a first bonding contact 291. Therefore, step S100 may further include: forming the first bonding layer 290 on the side of the first dielectric layer 260 opposite to the first semiconductor layer 210; the material of the first bonding layer 290 may include, but is not limited to, dielectric materials such as silicon oxide, silicon nitride, or silicon oxynitride; forming a first bonding contact 291 extending through the first bonding layer 290 along a first direction from the side of the first bonding layer 290 opposite to the first dielectric layer 260; the material of the first bonding contact 291 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, and silicides.

[0109] Step S200

[0110] In step S200, the initial peripheral circuit structure 200' is coupled to the semiconductor structure 100, which includes a memory array 110. As an example, the initial peripheral circuit structure 200' and the semiconductor structure 100 can be coupled by bonding. The memory array 110 of the semiconductor structure 100 can be a non-volatile memory array such as a NAND memory array, a PROM (Programmable Read-Only memory) memory array, or a NOR memory array, or a volatile memory array such as a DRAM (Dynamic Random Access Memory) memory array or an SRAM (Static Random-Access Memory) memory array; this application does not limit the specific type of memory array used.

[0111] In some embodiments, the fabrication method may further include: forming a memory array 110; forming a second interconnect layer 120 on one side of the memory array 110, the second interconnect layer 120 including a plurality of second interconnect structures connected to the memory array 110; forming a second bonding layer 170 on the side of the second interconnect layer 120 opposite to the memory array 110, the material of the second bonding layer 170 may include, but is not limited to, dielectric materials such as silicon oxide, silicon nitride, or silicon oxynitride; forming a second bonding contact 171 extending through the second bonding layer 170 along a first direction from the side of the second bonding layer 170 opposite to the second interconnect layer 120, the material of the second bonding contact 171 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, and silicides.

[0112] Based on this, such as Figure 15 As shown, the initial peripheral circuit structure 200' and the semiconductor structure 100 can be coupled in the following manner: the first bonding layer 290 of the initial peripheral circuit structure 200' and the second bonding layer 170 of the semiconductor structure 100 are bonded and aligned so that the first bonding contact 291 contacts the second bonding contact 171; the initial peripheral circuit structure 200' and the semiconductor structure 100 are annealed.

[0113] like Figure 14As shown, taking a memory array 110 including a stacked structure 130 and a channel structure 140 as an example, the memory array 110 can be formed as follows: a stacked structure (not shown) is formed on one side of a substrate, the stacked structure including an interlayer dielectric layer 131 and an interlayer sacrificial layer alternately stacked along a first direction; a channel structure 140 is formed that penetrates the stacked structure along the first direction; for example, a channel hole can be formed from the side of the stacked structure away from the substrate that penetrates the stacked structure along the first direction; a barrier layer is formed on the inner wall of the channel hole to block the outflow of charge stored in the subsequently formed charge trapping layer; wherein, the material of the barrier layer may include, but is not limited to, silicon oxide, silicon nitride, high-k dielectric material, or any combination thereof. A charge trapping layer is formed on the side of the barrier layer away from the inner wall of the channel hole to store charge. The material of the charge trapping layer may include, but is not limited to, silicon nitride, silicon oxynitride, silicon, or any combination thereof. A tunneling layer is formed on the side of the charge trapping layer away from the barrier layer, and the functional layer includes the barrier layer, the charge trapping layer, and the tunneling layer. The tunneling layer can be made of, but is not limited to, silicon oxide or silicon nitride. A channel layer is formed on the side of the tunneling layer away from the charge trapping layer. The channel layer is used to transport the required charge, i.e., electrons or holes. The channel layer can be made of, but is not limited to, amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the channel layer does not fill the gaps formed by the tunneling layer, so that after the channel layer is formed, a filling material can be deposited in the gaps formed by the channel layer to form a filled core layer. The filling core layer can be made of, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, spin-coated glass, carbon-doped oxides, etc. In addition, to reduce structural stress, at least one air gap can be formed in the filled core layer by controlling the corresponding parameters in the filling process during the formation of the filled core layer. A gate line slot is formed that penetrates the stacked structure in a first direction and extends in a second direction; at least a portion of the interlayer sacrificial layer is replaced with the first gate layer 132 through the gate line slot to form a stacked structure 130; a gate line isolation structure is formed within the gate line slot.

[0114] The stacked structure can be formed on one side of the substrate using a thin-film deposition process. The stacked structure may include, but is not limited to, 64, 128, or more pairs of interlayer dielectric layers 131 and interlayer sacrificial layers. The more interlayer dielectric layers 131 and interlayer sacrificial layers there are, the higher the integration density and the more memory cells the memory array 110 can have. The number of interlayer dielectric layers 131 and interlayer sacrificial layers can be designed according to actual needs, and this application does not limit this. The material of the interlayer dielectric layer 131 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. The material of the interlayer sacrificial layer may include, but is not limited to, silicon oxynitride, polycrystalline silicon, or polycrystalline germanium. As an example, the stacked structure may include a core region and a connection region located on at least one side of the core region along a second direction. It should be noted that the connection region can be a stepped structure or a non-stepped structure; for example, in an SCT (Staircase Contact) architecture, the connection region does not need to be stepped. If the connection region of the stacked structure is a stepped structure, then after alternately stacking the interlayer dielectric layer 131 and the interlayer sacrificial layer on one side of the substrate, the stepped structure can be formed by performing multiple trim-etch cycles on the portion of the interlayer dielectric layer 131 and the interlayer sacrificial layer located in the connection region.

[0115] Step S300

[0116] In step S300, a peripheral circuit structure 200 is formed based on the initial peripheral circuit structure 200'. The peripheral circuit structure 200 includes a first semiconductor layer 210 and a capacitor structure 220. The capacitor structure 220 includes a first electrode layer 221 and an electrode structure 222. The electrode structure 222 can be located within the first semiconductor layer 210, or it can be located on the same side of the first semiconductor layer 210 as the first electrode layer 221. This application does not limit this; the electrode structure 222 and the first electrode layer 221 can simply be arranged opposite each other in a first direction. Furthermore, the electrode structure 222 can be a single-layer structure or a multi-layer structure, and this application also does not limit this.

[0117] As an example, the electrode structure 222 is a multilayer structure that penetrates the first semiconductor layer 210 along the first direction. Therefore, the peripheral circuit structure 200 can be formed in the following manner: Figure 16 As shown, the first semiconductor layer 210 is thinned from its second surface 212 to expose the initial isolation structure 227; as Figure 17 As shown, a first electrode trench 222-3 is formed on the side of the first semiconductor layer 210 opposite to the semiconductor structure 100, penetrating the initial isolation structure 227 along the first direction, exposing the capacitor dielectric layer 223. The remaining initial isolation structure 227 constitutes the first isolation layer 224; as Figure 18 As shown, a second electrode layer 222-2 is formed on the inner wall of the first electrode groove 222-3. The second electrode layer 222-2 covers the surface of the first insulating layer 224 facing away from the inner wall of the first electrode groove 222-3 and the surface of the capacitor dielectric layer 223 exposed within the first electrode groove 222-3. The second electrode layer 222-2 surrounds and forms a second electrode groove 222-4. The material of the second electrode layer 222-2 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, and silicides. Figure 19 As shown, a second isolation material is deposited from the side of the first semiconductor layer 210 away from the semiconductor structure 100 to form a second isolation layer 222-1 filling the second electrode trench 222-4. The second isolation layer 222-1 protrudes along a first direction from the side of the first semiconductor layer 210 away from the semiconductor structure 100. The second isolation material may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. During the actual deposition of the second isolation material, the second isolation material covers the surface of the first semiconductor layer 210 away from the semiconductor structure 100. The second isolation material covering the surface of the first semiconductor layer 210 can be removed by a process such as dry etching. The remaining second isolation material is located on one side of the capacitor dielectric layer 223 in the first direction and forms the second isolation layer 222-1. The capacitor structure 220 includes a second electrode layer 222-2 and a second isolation layer 222-1. A second connection structure 232 is formed on the side of the second isolation layer 222-1 away from the semiconductor structure 100, extending along the first direction through the second isolation layer 222-1 and to the second electrode layer 222-2. The material of the second connection structure 232 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, and silicide.

[0118] In some implementations, such as Figure 20 As shown, after the second interconnection structure 232 is formed, a first interconnection layer 270 can also be formed on the side of the first semiconductor layer 210 away from the semiconductor structure 100. The first interconnection layer 270 includes a second interconnection structure connected to the second interconnection structure 232.

[0119] As can be seen from the above, in this embodiment, the electrode structure 222 is a multilayer structure penetrating the first semiconductor layer 210. The electrode structure 222 includes a second electrode layer 222-2 and a second isolation layer 222-1. The first electrode layer 221 and the second electrode layer 222-2 are the two electrodes of the capacitor structure 220, respectively. The first electrode layer 221 is connected to the first connection structure 231, and the second electrode layer 222-2 is connected to the second connection structure 232. The first connection structure 231 and the second connection structure 232 can respectively lead out the first electrode layer 221 and the second electrode layer 222-2 from opposite directions. It should be noted that if the projection of the first electrode layer 221 and the projection of the second electrode layer 222-2 do not overlap on a plane perpendicular to the first direction, then the first electrode layer 221 and the second electrode layer 222-2 can also be led out from the same direction.

[0120] In some other embodiments, the electrode structure 222 is a single-layer structure that penetrates the first semiconductor layer 210 along the first direction. Therefore, the peripheral circuit structure 200 can be formed in the following manner: Figure 21 As shown, the first semiconductor layer 210 is thinned from its second surface 212 to expose the initial isolation structure 227; as Figure 22 As shown, a first isolation material is deposited on the side of the first semiconductor layer 210 facing away from the semiconductor structure 100 to form an isolation capping layer 228 covering the first semiconductor layer 210 and the initial isolation structure 227. The first isolation material may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. The material of the initial isolation structure 227 may be the same as the first isolation material. In this case, there is no clearly detectable interface between the isolation capping layer 228 and the initial isolation structure 227. A first electrode trench 222-3 is formed on the side of the isolation capping layer 228 facing away from the initial isolation structure 227, penetrating the isolation capping layer 228 and the initial isolation structure 227 along a first direction, exposing the capacitor dielectric layer 223. Figure 23 As shown, conductive material is deposited in the first electrode trench 222-3 to form an electrode structure 222. The material of the electrode structure 222 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, and silicides. Figure 24 As shown, the isolation capping layer 228 covering the surface of the first semiconductor layer 210 is removed, and the remaining isolation capping layer 228 and the remaining initial isolation structure 227 constitute the first isolation layer 224, which surrounds the electrode structure 222. It should be noted that in some other embodiments, the isolation capping layer 228 covering the surface of the first semiconductor layer 210 may also be retained.

[0121] In some embodiments, after the electrode structure 222 is formed, a first interconnect layer 270 may be formed on the side of the first semiconductor layer 210 opposite to the semiconductor structure 100. The first interconnect layer 270 includes a first interconnect structure connected to the electrode structure 222.

[0122] As can be seen from the above, in this embodiment, the electrode structure 222 is a single-layer structure penetrating the first semiconductor layer 210. The first electrode layer 221 and the electrode structure 222 are the two electrodes of the capacitor structure 220, respectively. The first electrode layer 221 is connected to the first connection structure 231, which is located on the side of the first electrode layer 221 away from the first semiconductor layer 210. The electrode structure 222 is directly connected to the first interconnect structure of the first interconnect layer 270. The first electrode layer 221 and the electrode structure 222 are led out from opposite directions. It should be noted that if the projection of the first electrode layer 221 and the projection of the electrode structure 222 do not overlap on a plane perpendicular to the first direction, then the first connection structure 231 can also be located on the side of the first electrode layer 221 away from the semiconductor structure 100, and the first electrode layer 221 and the electrode structure 222 are led out from the same direction.

[0123] The above mainly illustrates the fabrication method of a semiconductor device when the electrode structure 222 is located within the first semiconductor layer 210. The following will illustrate the fabrication method of a semiconductor device when the electrode structure 222 is located on one side of the first semiconductor layer 210.

[0124] The methods for forming the semiconductor structure 100 and transistor 240 and the coupling method between the semiconductor structure 100 and the initial peripheral circuit structure 200' in this embodiment are similar to those described above and will not be repeated here.

[0125] like Figure 25 As shown, the initial peripheral circuit structure 200' in this embodiment further includes a first electrode layer 221, a capacitor dielectric layer 223, a second high-dielectric layer 226, and a third electrode layer 225. The initial peripheral circuit structure 200' can be formed as follows: a second high-dielectric layer 226 is formed on one side of the first semiconductor layer 210. The second high-dielectric layer 226 may include, but is not limited to, materials with high dielectric constants such as alumina, hafnium oxide, zirconium oxide, tantalum pentoxide, or silicon oxynitride; a first electrode layer 221 is formed on the side of the second high-dielectric layer 226 away from the first semiconductor layer 210; a capacitor dielectric layer 223 is formed on the side of the first electrode layer 221 away from the second high-dielectric layer 226. The material of the capacitor dielectric layer 223 may include, but is not limited to, dielectric materials such as silicon oxide; a third electrode layer 225 is formed on the side of the capacitor dielectric layer 223 away from the first electrode layer 221. The electrode structure 222 includes the third electrode layer 225. The material of the third electrode layer 225 may include, but is not limited to, titanium nitride.

[0126] To simplify the process and reduce costs, the gate dielectric layer 242 and the second high-dielectric layer 226 can be formed in the same process; in other words, the gate dielectric layer 242 and the second high-dielectric layer 226 are made of the same material. For example, both the gate dielectric layer 242 and the second high-dielectric layer 226 can be formed of the same high-dielectric-constant material. Similarly, the gate conductive layer 241 and the first electrode layer 221 can also be formed in the same process; that is, the gate conductive layer 241 and the first electrode layer 221 are made of the same material, and the first electrode layer 221 is a virtual gate conductive layer. Therefore, the embodiment of this application utilizes a virtual gate conductive layer as the first electrode layer 221 of the capacitor structure 220, which is not only compatible with existing processes but also does not occupy additional area.

[0127] In some embodiments, after forming the third electrode layer 225, a first dielectric layer 260 covering the third electrode layer 225 and the first semiconductor layer 210 may be formed on one side of the first semiconductor layer 210. The material of the first dielectric layer 260 may include, but is not limited to, dielectric materials such as silicon oxide, silicon nitride, and / or silicon oxynitride. As an example, the first dielectric layer 260 may include multiple sub-dielectric layers. At least one sub-dielectric layer covering the third electrode layer 225 and the first semiconductor layer 210 may be formed first; then, a fourth connection hole is formed from the side of the at least one sub-dielectric layer away from the first semiconductor layer 210, extending through the at least one sub-dielectric layer in a first direction and reaching the third electrode layer 225; a fourth connection structure 234 is formed in the fourth connection hole, and the material of the fourth connection structure 234 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, and silicide; the remaining sub-dielectric layers covering the fourth connection structure 234 are formed.

[0128] Based on this, such as Figures 25 to 28As shown, the peripheral circuit structure 200 can be formed as follows: a third connection structure 233 is formed from the side of the first semiconductor layer 210 away from the semiconductor structure 100, penetrating the first semiconductor layer 210 and the second high-dielectric layer 226 along a first direction, and the third connection structure 233 is connected to the third electrode layer 225. Specifically, a third connection hole can be formed from the side of the first semiconductor layer 210 away from the semiconductor structure 100, penetrating the first semiconductor layer 210 and the second high-dielectric layer 226 along a first direction; a third isolation layer 233-2 is formed on the sidewall of the third connection hole extending along the first direction, and the material of the third isolation layer 233-2 may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride; a conductive material is deposited in the gap formed by the third isolation layer 233-2 to form a conductive connection structure 233-1. The third connection structure 233 includes the third isolation layer 233-2 and the conductive connection structure 233-1. It should be noted that during the actual deposition of the isolation material to form the third isolation layer 233-2, the isolation material will cover the surface of the first semiconductor layer 210 facing away from the semiconductor structure 100. The isolation material covering the surface of the first semiconductor layer 210 can be removed by a process such as dry etching. The remaining isolation material is located on one side of the second high-dielectric layer 226 in the first direction and forms the third isolation layer 233-2. Of course, in some other embodiments, the isolation material covering the surface of the first semiconductor layer 210 may not be removed. In other words, a portion of the third isolation layer 233-2 surrounds the conductive connection structure 233-1, and a portion covers the surface of the first semiconductor layer 210.

[0129] As can be seen from the above, in this embodiment, the electrode structure 222 is located on one side of the first semiconductor layer 210. The electrode structure 222 includes a third electrode layer 225, and both the third electrode layer 225 and the first electrode layer 221 are located on the side of the first semiconductor layer 210 facing the semiconductor structure 100. The first electrode layer 221 and the third electrode layer 225 are respectively connected to the two electrodes of the capacitor structure 220. The first electrode layer 221 is connected to the third connection structure 233, and the third electrode layer 225 is connected to the fourth connection structure 234. The third connection structure 233 and the fourth connection structure 234 can respectively lead out the first electrode layer 221 and the third electrode layer 225 from opposite directions. It should be noted that if the projection of the first electrode layer 221 and the projection of the third electrode layer 225 do not overlap on the plane perpendicular to the first direction, then the first electrode layer 221 and the third electrode layer 225 can also be led out from the same direction.

[0130] This application also provides another method for fabricating a semiconductor device. The fabrication method of the semiconductor structure 100 differs from that described above, but other aspects are basically similar and will not be repeated here. In the embodiments of this application, the memory array 110 may include semiconductor pillars 150 and gate structures 160. The memory array 110 can be formed as follows: from a first surface of the wafer, a plurality of first trenches extending along a second direction are formed in the wafer, the plurality of first trenches being spaced apart along a third direction; a dielectric material is filled in the first trenches, the dielectric material may include, but is not limited to, silicon dioxide, silicon nitride, or other dielectric materials. The material of the wafer may be a single-element semiconductor material such as silicon (Si) or germanium (Ge), or a composite semiconductor material such as silicon-on-insulator (SOI) or germanium-on-insulator (GeOI). From the first surface of the wafer, second trenches and third trenches are formed in the wafer, which are alternately distributed along the second direction and both extend along the third direction, to divide the wafer into a plurality of initial semiconductor pillars; a gate structure 160 is formed in the second trench, for example, a gate dielectric layer 161 is formed in the second trench; a second gate layer 162 is formed on the side of the gate dielectric layer 161 opposite to the inner wall of the second trench; at least the portion of the second gate layer 162 located at the bottom surface of the second trench is removed by a punching process; the remaining space in the second trench is filled with dielectric material; gate cut structures are formed at both ends of the second gate layer 162 along the third direction, and the gate cut structures penetrate the second gate layer 162 along the first direction to divide the second gate layer 162 into two parts disposed opposite to each other along the second direction. An isolation structure is formed within the third trench; a drain and a source are formed based on the initial semiconductor pillar, for example, the source can be formed based on the end of the initial semiconductor pillar away from the second surface of the wafer; the wafer is thinned from the second surface to expose the dielectric material located in the first trench; the drain is formed based on the end of the initial semiconductor pillar away from the first surface, and the remaining portion of the initial semiconductor pillar constitutes the channel. The semiconductor pillar 150 includes a source, a drain, and a channel. Both the source and the drain can be formed by doping the ends of the initial semiconductor pillar. The drain and the source can be both doped with P-type dopant or both doped with N-type dopant. The dopants of the drain and the source can be the same or different. For example, the dopant can include, but is not limited to, boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), or antimony (Sb).

[0131] In addition, this application also provides a storage system, which includes a controller and the aforementioned semiconductor device. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0132] Figure 29A block diagram of a system with semiconductor devices according to one embodiment of this application is shown. System 300 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage located therein. Figure 29 As shown, system 300 may include host 304 and memory system 301, the memory system 301 having one or more semiconductor devices 302 and memory controller 303. Host 304 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-a-chip (SoC), such as an application processor (AP). Host 304 may be configured to send or receive data from semiconductor devices 302.

[0133] Semiconductor device 302 can be any semiconductor device disclosed in this application, such as Figures 3 to 11 The semiconductor device is shown. According to some embodiments, a memory controller 303 is coupled to the semiconductor device 302 and the host 304, and is configured to control the semiconductor device 302. The memory controller 303 can manage data stored in the semiconductor device 302 and communicate with the host 304.

[0134] In some embodiments, the memory controller 303 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 303 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 303 can be configured to control the operation of the semiconductor device 302, such as read, erase, and program operations. The memory controller 303 can also be configured to manage various functions related to data stored in or to be stored in the semiconductor device 302, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 303 is further configured to process error correction codes (ECC) related to data read from or written to the semiconductor device 302. The memory controller 303 may also perform any other appropriate functions, such as formatting the semiconductor device 302. The memory controller 303 may communicate with external devices (e.g., the host 304) according to a specific communication protocol. For example, the memory controller 303 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0135] The memory controller 303 and one or more semiconductor devices 302 can be integrated into various types of memory devices, for example, contained within the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 301 can be implemented and packaged into different types of end electronic products. Figure 30 In one example shown, the memory controller 303 and a single semiconductor device 302 can be integrated into the memory card 310. The memory card 310 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 310 may further include a connection between the memory card 310 and a host computer (e.g., Figure 29 The memory card connector 311 is coupled to the host 304 in the memory card. In such a way... Figure 31 In another example shown, the memory controller 303 and multiple semiconductor devices 302 can be integrated into a solid-state drive, i.e., an SSD 320. The SSD 320 may further include a connection between the SSD 320 and a host (e.g., Figure 29 The SSD connector 321 is coupled to the host 304. In some embodiments, the storage capacity and / or operating speed of the SSD 320 is higher than that of the memory card 310.

[0136] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. As an example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0137] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, comprising: Semiconductor structures, including memory arrays; as well as An external circuit structure is located on one side of the semiconductor structure along a first direction and coupled to the semiconductor structure, the external circuit structure including a first semiconductor layer and a capacitor structure; The capacitor structure includes a first electrode layer and an electrode structure. The first electrode layer is located on the side of the first semiconductor layer facing the semiconductor structure along the first direction, and the electrode structure is disposed opposite to the first electrode layer in the first direction.

2. The semiconductor device according to claim 1, wherein, The electrode structure penetrates the first semiconductor layer along the first direction; The capacitor structure further includes: A first insulating layer at least partially covers the sidewalls of the electrode structure extending along a first direction.

3. The semiconductor device according to claim 2, wherein, The electrode structure includes: A second isolation layer extends at least partially into the first semiconductor layer along the first direction; and The second electrode layer covers the sidewall of the second isolation layer extending along the first direction and the side of the second isolation layer facing the first electrode layer along the first direction.

4. The semiconductor device according to claim 3, wherein, The second isolation layer protrudes from the first semiconductor layer along the first direction in a direction away from the first electrode layer; The peripheral circuit structure further includes: A first connection structure is located on the side of the first electrode layer opposite to the first semiconductor layer and is connected to the first electrode layer; and The second connection structure extends through the second isolation layer along the first direction and is connected to the second electrode layer.

5. The semiconductor device according to claim 4, wherein, The second isolation layer is provided with a plurality of second connection structures, which are spaced apart in a second direction, and the second direction intersects with the first direction.

6. The semiconductor device according to claim 2, wherein, The electrode structure is a single-layer structure, and the electrode structure protrudes from the first semiconductor layer along the first direction in a direction away from the first electrode layer.

7. The semiconductor device according to claim 2, wherein, The portion of the electrode structure located in the first semiconductor layer and close to the first electrode layer has a smaller dimension in the second direction than the portion located in the first semiconductor layer and far from the first electrode layer in the second direction, the second direction intersecting the first direction.

8. The semiconductor device according to claim 2, wherein, The capacitor structure also includes: A capacitor dielectric layer is located between the first electrode layer and the electrode structure along the first direction, and the capacitor dielectric layer includes a first high dielectric layer in contact with the electrode structure.

9. The semiconductor device according to claim 1, wherein, The electrode structure includes: The third electrode layer is located along the first direction on the side of the first electrode layer that is away from the first semiconductor layer; The capacitor structure further includes a second high-dielectric layer located between the first electrode layer and the first semiconductor layer, and a capacitor dielectric layer located between the first electrode layer and the third electrode layer.

10. The semiconductor device according to claim 9, wherein, The peripheral circuit structure also includes: A third connection structure extends along the first direction through the first semiconductor layer and the second high-dielectric layer and is connected to the first electrode layer; and The fourth connection structure is located on the side of the third electrode layer opposite to the capacitor dielectric layer and is connected to the third electrode layer.

11. The semiconductor device according to claim 10, wherein, The third connection structure protrudes from the first semiconductor layer along the first direction in a direction away from the first electrode layer; The third connection structure includes: A conductive connection structure extending along the first direction; and A third insulating layer at least partially covers the sidewalls of the conductive connection structure extending along the first direction.

12. The semiconductor device according to any one of claims 1 to 11, wherein, The peripheral circuit structure includes multiple capacitor structures, and the multiple capacitor structures have different structures.

13. The semiconductor device according to any one of claims 1 to 11, wherein, The peripheral circuit structure also includes: Transistors, at least partially located in the first semiconductor layer; and A trench isolation structure, at least partially located in the first semiconductor layer and surrounding the active region of the transistor and the capacitor structure.

14. The semiconductor device according to claim 13, wherein, The transistor includes: A gate conductive layer, located along the first direction on the side of the first semiconductor layer facing the semiconductor structure; and A gate dielectric layer is located between the gate conductive layer and the first semiconductor layer; The gate conductive layer is made of the same material as the first electrode layer.

15. The semiconductor device according to any one of claims 1 to 11, wherein, The peripheral circuit structure also includes: A first dielectric layer is located on the side of the first semiconductor layer facing the semiconductor structure and covers the first electrode layer; the first dielectric layer is bonded to the semiconductor structure. The first interconnect layer is located on the side of the first semiconductor layer opposite to the first dielectric layer, and the electrode structure is connected to the first interconnect layer.

16. The semiconductor device according to any one of claims 1 to 11, wherein, The semiconductor structure also includes: The second interconnect layer is located on the side of the memory array facing the first semiconductor layer and is connected to the memory array. The second interconnect layer is bonded to the peripheral circuit structure.

17. A method for fabricating a semiconductor device, comprising: An initial peripheral circuit structure is formed, the initial peripheral circuit structure including a first semiconductor layer and a first electrode layer of a capacitor structure; The initial peripheral circuit structure is coupled to a semiconductor structure, the semiconductor structure including a memory array; as well as The peripheral circuit structure is formed based on the initial peripheral circuit structure; The peripheral circuit structure includes the first semiconductor layer and the capacitor structure. The capacitor structure includes the first electrode layer and the electrode structure. The first electrode is located on the side of the first semiconductor layer facing the semiconductor structure along a first direction, and the electrode structure is disposed opposite to the first electrode layer along the first direction.

18. The method for fabricating a semiconductor device according to claim 17, wherein, The first electrode layer is located on the side of the first surface of the first semiconductor layer facing the semiconductor structure; The initial peripheral circuit structure includes: An initial isolation structure is formed from the first surface and in the first semiconductor layer; and A first electrode layer is formed on the side of the initial isolation structure opposite to the second surface of the first semiconductor layer, and the first surface and the second surface are arranged opposite to each other along the first direction.

19. The method for fabricating a semiconductor device according to claim 18, wherein, The formation of the peripheral circuit structure based on the initial peripheral circuit structure includes: The first semiconductor layer is thinned from the second surface to expose the initial isolation structure; A first electrode trench is formed from the side of the first semiconductor layer opposite to the semiconductor structure, penetrating the initial isolation structure along the first direction; and The electrode structure is formed within the first electrode groove.

20. The method for fabricating a semiconductor device according to claim 19, wherein, After thinning the first semiconductor layer and before forming the first electrode trench, the fabrication method further includes: A first insulating material is deposited on the side of the first semiconductor layer opposite to the semiconductor structure; The formation of the electrode structure within the first electrode groove includes: Conductive material is deposited in the first electrode groove to form the electrode structure.

21. The method for fabricating a semiconductor device according to claim 19, wherein, Forming the electrode structure within the first electrode groove includes: A second electrode layer is formed on the inner wall of the first electrode groove, and the second electrode layer surrounds and forms the second electrode groove; and A second isolation layer is formed to fill the second electrode trench and protrude from the first semiconductor layer, the electrode structure including the second electrode layer and the second isolation layer.

22. The method for fabricating a semiconductor device according to claim 21, wherein, The preparation method further includes: A second connection structure is formed from the side of the second isolation layer away from the semiconductor structure, extending through the second isolation layer along the first direction and reaching the second electrode layer.

23. The method for fabricating a semiconductor device according to claim 17, wherein, The initial peripheral circuit structure includes: A second high-dielectric layer is formed on one side of the first semiconductor layer; The first electrode layer is formed on the side of the second high dielectric layer that is away from the first semiconductor layer; A capacitor dielectric layer is formed on the side of the first electrode layer opposite to the second high-dielectric layer; and A third electrode layer is formed on the side of the capacitor dielectric layer opposite to the first electrode layer, and the electrode structure includes the third electrode layer.

24. A storage system, characterized in that, The storage system includes a controller and a semiconductor device according to any one of claims 1 to 16, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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