Managing contact structures in semiconductor devices

Abstract

The invention relates to a method, an apparatus and a system for managing contact structures in a semiconductor device. An example semiconductor device includes a first stack of conductive layers and isolation layers alternating with each other along a first direction, and a second stack of dielectric layers and isolation layers alternating with each other along the first direction. The semiconductor device also includes a first contact structure and a second contact structure each extending in the second stack. The first contact structure is coupled to a first conductive layer in the first stack through a first connection layer in the second stack. The second contact structure is coupled to a second conductive layer in the first stack through a second connection layer in the second stack. The first contact structure extends through the second connection layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers of volume over a similar occupied area. 3D memory devices typically include a memory array of memory cells and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for managing contact structures in semiconductor devices.

[0004] One aspect of this disclosure features a semiconductor device. The semiconductor device includes a first stack of conductive and insulating layers alternating with each other along a first direction, and a second stack of dielectric and insulating layers alternating with each other along the first direction. The second stack is adjacent to the first stack along a second direction perpendicular to the first direction. The semiconductor device also includes a first contact structure extending in the second stack and a second contact structure extending in the second stack. The first contact structure is coupled to a first conductive layer in the first stack through a first interconnect layer in the second stack. The second contact structure is coupled to a second conductive layer in the first stack through a second interconnect layer in the second stack. The first contact structure extends through the second interconnect layer.

[0005] In some embodiments, a first contact structure extends through a first portion of the second stack to reach a first connection layer, and a second contact structure extends through a second portion of the second stack to reach a second connection layer. The second stack includes a surface layer comprising an insulating material. The second connection layer is closer to the surface layer along a first direction than the first connection layer.

[0006] In some implementations, the first connecting layer has a circular shape in a planar view perpendicular to the first direction, and the second connecting layer has an annular shape in the planar view.

[0007] In some implementations, the first interconnect layer is separated from the second interconnect layer by one or more alternating dielectric and isolation layers of the second stack.

[0008] In some implementations, in a plan view perpendicular to the first direction, the second connecting layer at least partially overlaps with the first connecting layer.

[0009] In some implementations, the size of the first contact structure at the surface layer of the second stack is larger than the size of the second contact structure at the surface layer.

[0010] In some implementations, the diameter of the first contact structure at the surface layer of the second stack is larger than the diameter of the second contact structure at the surface layer.

[0011] In some embodiments, the second connection layer includes a first portion and a second portion that is closer to the first contact structure than the first portion. The thickness of the first portion along the first direction is less than the thickness of the second portion along the first direction.

[0012] In some implementations, the second contact structure is coupled to a second portion of the second connection layer.

[0013] In some embodiments, the semiconductor device further includes a third contact structure extending in a second stack. The third contact structure is coupled to a third conductive layer in a first stack via a third interconnect layer in the second stack. The third interconnect layer runs along a first direction between the first interconnect layer and the second interconnect layer. The first contact structure extends through the third interconnect layer.

[0014] In some embodiments, the second connection layer includes a first outer surface that contacts a first corresponding dielectric layer of the second stack, and the third connection layer includes a second outer surface that contacts a second corresponding dielectric layer of the second stack. The first outer surface of the second connection layer is closer to the first contact structure than the second outer surface of the third connection layer.

[0015] In some embodiments, the second connecting layer includes an inner surface spaced from the first contact structure by a first insulating structure made of an insulating material, and the third connecting layer includes an inner surface spaced from the first contact structure by a second insulating structure made of an insulating material. The first and second insulating structures have substantially the same thickness along a third direction perpendicular to the first and second directions.

[0016] In some embodiments, the semiconductor device further includes a first isolation structure between the first contact structure and the second connection layer along a third direction perpendicular to the first and second directions, and a second isolation structure between the first contact structure and the third connection layer along the third direction. The thickness of the first isolation structure along the third direction is greater than the thickness of the second isolation structure along the third direction.

[0017] In some embodiments, the third contact structure extends through the first isolation structure. The third contact structure is separated from the second contact structure by at least a portion of the first isolation structure.

[0018] In some embodiments, the first contact structure includes a body and an outer layer surrounding the body. The body includes a first dielectric material, and the outer layer and a first connecting layer include conductive materials. The first contact structure is surrounded by contact spacers including a second dielectric material.

[0019] Another aspect of this disclosure features a semiconductor device. The semiconductor device includes a first stack of conductive and insulating layers alternating with each other along a first direction, and a second stack of dielectric and insulating layers alternating with each other along the first direction. The second stack is adjacent to the first stack along a second direction perpendicular to the first direction. The semiconductor device also includes a first contact structure extending in the second stack and a second contact structure extending in the second stack. The first contact structure is coupled to a first conductive layer in the first stack. The second contact structure is coupled to a second conductive layer. The dimension of the second contact structure at the surface layer of the second stack is smaller than the dimension of the first contact structure at the surface layer of the second stack.

[0020] In some embodiments, one or more first contact structures are arranged in a row along a third direction perpendicular to the first and second directions. The first contact structures and the second contact structures are arranged along a fourth direction perpendicular to the first direction and different from the third direction.

[0021] In some embodiments, the semiconductor device further includes a first gate gap structure and a second gate gap structure, both extending along a third direction. A first stack and a second stack are disposed between the first gate gap structure and the second gate gap structure. More than one row of first contact structures are disposed between the first gate gap structure and the second gate gap structure along a second direction.

[0022] In some embodiments, the first contact structure is coupled to the first conductive layer via a first connection layer in the second stack, and the second contact structure is coupled to the second conductive layer via a second connection layer in the second stack. In a plan view perpendicular to the first direction, the second connection layer at least partially overlaps the first connection layer.

[0023] In some embodiments, the first contact structure extends through the second connection layer along a first direction. At least one second contact structure is coupled to the second connection layer.

[0024] Another aspect of this disclosure features a method for forming a semiconductor device. The method includes: forming a first stack of conductive and insulating layers alternating with each other along a first direction; and forming a second stack of dielectric and insulating layers alternating with each other along the first direction. The second stack is adjacent to the first stack along a second direction perpendicular to the first direction. The method further includes: forming a first contact structure in the second stack; and forming a second contact structure in the second stack. The first contact structure reaches a first interconnect layer in the second stack. The first interconnect layer is coupled to a first conductive layer in the first stack. The second contact structure reaches a second interconnect layer in the second stack. The second interconnect layer is coupled to a second conductive layer in the first stack. The first contact structure extends through the second interconnect layer.

[0025] In some embodiments, forming a first contact structure in a second stack includes: etching a first portion of the second stack to a first dielectric layer to form a first via structure along a first direction; removing the first dielectric layer and forming a first metal layer; extending the first via structure in the second stack along the first direction by etching the first metal layer to further etch a second portion of the second stack to a second dielectric layer; removing the second dielectric layer and forming a second metal layer as a first interconnect layer; and depositing one or more conductive layers in the first via structure to contact the first interconnect layer.

[0026] In some embodiments, etching the first metal layer includes: etching the first metal layer away from the bottom of the first hole structure along a third direction perpendicular to the first and second directions. The method further includes: forming an isolation structure in the bottom of the first hole structure to contact the etched first metal layer; and etching the isolation structure to extend the first hole structure along the first direction.

[0027] In some embodiments, forming a second contact structure in a second stack includes: etching a third portion of the second stack to reach a first metal layer to form a second hole structure spaced apart from the first hole structure along a second direction; and depositing one or more conductive layers in the second hole structure to contact the first metal layer as a second connection layer.

[0028] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0029] Figure 1A-Figure 1B An example semiconductor device is shown.

[0030] Figures 2A-2B A cross-sectional view of a semiconductor device is shown.

[0031] Figures 3A-3M An example process for manufacturing semiconductor devices is shown.

[0032] Figure 4 A flowchart illustrating an example process for manufacturing semiconductor devices is shown.

[0033] Figure 5 A block diagram of the example system is shown.

[0034] The same reference numerals and designations in the various figures denote the same elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative and are not necessarily drawn to scale. Detailed Implementation

[0035] Due to the demand for high-density memory devices, memory devices (e.g., 3D NAND flash memory) can be formed with a large number of layers and word lines. Contact structures can be configured to connect conductive layers (e.g., as word lines) to control circuitry. The design and fabrication of these contact structures can have a substantial impact on the chip size and manufacturing cost of the memory device.

[0036] In some cases, the same type of contact structure (e.g., a first contact structure) is used to connect the conductive layer to the control circuitry. For example, each first contact structure may include a body made of a first conductive material and an outer layer made of a second conductive material surrounding the body. However, as the number of conductive layers in a memory device increases, a larger number of first contact structures may be needed to connect the conductive layer to the control circuitry, and the size (e.g., diameter) and depth of the first contact structures may increase. Therefore, the first contact structures may occupy a large area, which could reduce the memory cell density of the memory device.

[0037] This disclosure provides techniques for reducing the area occupied by contact structures in memory devices. In some embodiments, different types of contact structures can be used to connect conductive layers to control circuitry. For example, some conductive layers are connected using a first contact structure, while others are connected using a second contact structure. The second contact structure may have a smaller size than the first contact structure and may not be present in the first contact structure. The bottom of each of the first and second contact structures is coupled to a connection layer. In some embodiments, the second contact structure may overlap with a first connection layer coupled to the first contact structure in a planar view perpendicular to the vertical direction. The first contact structure may extend through a second connection layer coupled to the second contact structure.

[0038] The technology disclosed herein can provide one or more of the following technical advantages and / or benefits. For example, by using both a first contact structure and a second contact structure, a smaller area is required to arrange the contact structures compared to using only the first contact structure. Therefore, the memory cell density of the memory device can be increased, and the chip size of the memory device can be reduced. As another example, the described technology can be implemented with simple process steps and has a large process window based on existing technologies for manufacturing memory devices. In some embodiments, different or more technical advantages can be achieved.

[0039] The described technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), etc.). The technology can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate based memory devices. The technology can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as SLC (single-cell flash memory) devices, MLC (multi-cell flash memory) devices (e.g., two-cell flash memory devices), TLC (three-cell flash memory) devices, QLC (four-cell flash memory) devices, or PLC (five-cell flash memory) devices. Alternatively or concurrently, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0040] It should be noted that, Figures 1A-3B The X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of the components in the semiconductor device. The substrate of the semiconductor device may include two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the substrate on which components of the semiconductor device may be formed, and a bottom surface on the back side opposite the front side of the substrate. The Z direction is perpendicular to both the X and Y directions. As used in this disclosure, when the substrate is positioned in the lowest plane of the semiconductor device in the Z direction, the Z direction (a direction perpendicular to the XY plane, such as the thickness direction of the substrate) determines whether a component (e.g., a layer or device) of the semiconductor device is "on," "above," or "below" another component (e.g., a layer or device) of the semiconductor device relative to the substrate of the semiconductor device. The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0041] Figure 1A A top view of an example semiconductor device 100 is shown. In some embodiments, the semiconductor device 100 may be a memory device, such as a three-dimensional (3D) NAND memory device. The semiconductor device 100 may include one or more array regions and one or more connection regions configured to provide conductive connections to the one or more array regions. In some embodiments, such as Figure 1AAs shown, the semiconductor device 100 includes an array region 102 and a connection region 104 adjacent to the array region 102 along a first horizontal direction (e.g., the X direction). It should be understood that... Figure 1A The examples in the examples are for illustrative purposes only and are not intended to be interpreted in a limiting sense. In practice, any suitable arrangement of various regions in the semiconductor device 100 can be applied. In some cases, the semiconductor device 100 may have two connecting regions 104 and an array region 102 arranged along the X direction between the two connecting regions 104. In some other cases, the semiconductor device 100 may have two array regions 102 and a connecting region 104 along the X direction between the two array regions 102.

[0042] Semiconductor device 100 includes alternating conductive layers and insulating layers (e.g., as shown in the image). Figure 1B The first stack 106 (shown as conductive layer 106A and isolation layer 106B) is a first stack. In some embodiments, a portion of the first stack 106 may be in the array region 102, and another portion of the first stack 106 may be in the connection region 104. For example, a portion of the first stack 106 may be in the channel region 105 of the connection region 104. The semiconductor device 100 also includes alternating dielectric layers and isolation layers (e.g., as shown in the diagram). Figure 1B The second stack 108 (shown as dielectric layer 106D and isolation layer 106B) is shown. In some embodiments, the second stack 108 may be in the connection region 104. The first stack 106 is connected to the second stack 108.

[0043] Semiconductor device 100 may include an array of channel structures 110 extending through a first stack 106 in array region 102. Each channel structure 110 may be used to form a string of memory cells coupled in series along a vertical direction (e.g., the Z direction) perpendicular to a first horizontal direction. In some embodiments, semiconductor device 100 may include dummy channel structures 112 (also referred to as dummy memory strings) for process variation control during manufacturing and / or for additional mechanical support. Dummy channel structures 112 may extend through the first stack 106 in channel region 105. In some embodiments, dummy channel structures 112 may be in one or more dummy regions or peripheral regions (not shown in FIG. 1).

[0044] Semiconductor device 100 may include one or more gate slot structures 120. Each gate slot structure 120 may extend along the X direction. The gate slot structure 120 may extend into both the array region 102 and the interconnect region 104. The region surrounding the gate slot structure 120 in the interconnect region 104 may be used as a channel region 105. In some embodiments, the gate slot structure 120 may divide the array region 102 into multiple memory blocks. For example, memory blocks (such as...) Figure 1A As shown, the gate slot structure 120 can be arranged between two memory blocks (not shown in FIG. 1) in array region 102 along a second horizontal direction (e.g., the Y direction), where the gate slot structure 120 is the boundary separating adjacent memory blocks. In some embodiments, the gate slot structure 120 can be used as a common source contact for the channel structure 110 in array region 102. Figure 1A As shown, each gate slot structure 120 may include multiple segments separated and spaced apart by a separation structure 122. The separation structure 122 can eliminate or reduce stresses established in the gate slot structure 120 during the manufacturing process, thereby preventing the gate slot structure 120 from bending or breaking. In some embodiments, the separation structure 122 can separate a first portion of the gate slot structure 120 in the array region 120 from a second portion of the gate slot structure 120 in the connection region 104, allowing different etching processes to be performed on different portions of the gate slot structure 120. For example, a first etching process can be performed to etch away the dielectric layer 106D in the array region 102 that passes through the first portion of the gate slot structure 120. A second etching process can be performed to etch away the dielectric layer 106D in the channel region 105 that passes through the second portion of the gate slot structure 120. A conductive layer 106A can be formed to replace the dielectric layer 106D in the array region 104 and the channel region 105.

[0045] In some implementation methods ( Figure 1A (Not shown in the diagram), the gate slot structure 120 may further include one or more segments extending along a second horizontal direction. In some embodiments, the gate slot structure 120 may include multiple segments connected in an H-shape or T-shape. In some embodiments, the segments of each gate slot structure 120 may have similar or identical widths (e.g., measured along the Y direction). In some other embodiments, the segments of each gate slot structure 120 may have different widths (e.g., measured along the Y direction). In some embodiments, along the Y direction, the width of the segments of the gate slot structure 120 in the connecting region 104 is greater than the width of the segments of the gate slot structure 120 in the array region 102. For example, the width of the segments in the connecting region 104 may be approximately 1.5 to 2 times the width of the segments in the array region 102.

[0046] Semiconductor device 100 may include contact structures in connection region 104. The contact structures may be configured to connect corresponding conductive layers in the conductive layers of the first stack 106 to control circuitry. In some embodiments, semiconductor device 100 may include different types of contact structures, such as first contact structures 150a and 150b (collectively referred to as 150) and second contact structures 152a and 152b (collectively referred to as 152). The first and second contact structures are located on the surface layer of the second stack 108 (e.g., as shown in the image). Figure 1BThe surface layer 107 shown has different dimensions. In some embodiments, the size of the first contact structure 150 is larger than the size of the second contact structure 152. In some embodiments, at the surface layer of the second stack 108, the diameter of the first contact structure 150 is larger than the diameter of the second contact structure 152. For example, the diameter of the first contact structure 150 is in the range of 300 nm to 2 μm, for example, 500 nm, and the diameter of the second contact structure 152 is in the range of 300 nm to 400 nm, for example, about 300 nm. In some embodiments, the semiconductor device 100 may further include third contact structures 153a and 153b (collectively referred to as 153). The third contact structure 153 may have the same or similar dimensions as the second contact structure 152.

[0047] Each of the first contact structure 150, the second contact structure 152, and the third contact structure 153 is coupled to a connection layer 156 having a conductive material. The connection layer 156 is located in a connection region 104 beneath the surface layer of the second stack 108. In some embodiments, the connection layers 156 coupled to the first contact structure 150a, the second contact structure 152a, and the third contact structure 153a overlap or partially overlap each other in a planar view perpendicular to the vertical direction (e.g., the Z direction). Furthermore, the first contact structure 150a extends vertically through the connection layers 156 coupled to the second contact structure 152a and the third contact structure 153a. In some embodiments, the second contact structure 152a overlaps with the connection layer 156 coupled to the first contact structure 150a in a planar view. The connection layer 156 coupled to the second contact structure 152a is closer to the surface layer of the second stack 108 than the connection layer 156 coupled to the first contact structure 150a.

[0048] Similarly, in the plan view, the connection layer 156 coupled to the first contact structure 150b, the connection layer 156 coupled to the second contact structure 152b, and the connection layer 156 coupled to the third contact structure 153b overlap or partially overlap each other. The first contact structure 150b extends vertically through the connection layer 156 connected to the second contact structure 152b and the third contact structure 153b.

[0049] Each connection layer 156 is also coupled to a conductive layer 106A of the first stack 106 (e.g., the first stack 106 in the channel region 105). In other words, the conductive layer 106A of the first stack 106 forms a connection to the control circuit via one of the contact structures 150, 152, and 153. In some embodiments, the semiconductor device 100 includes only the first contact structure 150 and the second contact structure 152. Therefore, half of the conductive layer 106A of the first stack 106 (e.g., the lower half) forms a connection to the control circuit via the first contact structure 150, and the other half of the conductive layer 106A (e.g., the upper half) forms a connection to the control circuit via the second contact structure 152. In some embodiments, the semiconductor device 100 includes the first contact structure 150, the second contact structure 152, and the third contact structure 153. Therefore, the third conductive layer (e.g., the bottom portion) of the conductive layer 106A of the first stack 106 is connected to the control circuit through the first contact structure 150, the third conductive layer (e.g., the middle portion) of the conductive layer 106A of the first stack 106 is connected to the control circuit through the third contact structure 153, and the third conductive layer (e.g., the top portion) of the conductive layer 106A of the first stack 106 is connected to the control circuit through the second contact structure 152. As an example, if the first stack 106 has 360 conductive layers 106A stacked in a vertical direction, then the first to the 120th conductive layers 106A (e.g., in the top portion of the first stack 106) form connections to the control circuit through the second contact structure 152, the 121st to the 240th conductive layers 106A (e.g., in the middle portion of the first stack 106) form connections to the control circuit through the third contact structure 153, and the 241st to the 360th conductive layers 106A (e.g., in the bottom portion of the first stack 106) form connections to the control circuit through the first contact structure 150.

[0050] In some embodiments, one or more first contact structures 150 are arranged in a row along a first horizontal direction (e.g., the X direction). Each of the second contact structures 152 and each of the third contact structures 153 are arranged around the corresponding first contact structure 150. For example, the second contact structure 152a or the third contact structure 153a may each be arranged relative to the first contact structure 150a along a direction different from the first horizontal direction (e.g., the Y direction), allowing for a more efficient layout of the contact structures in the connection region 104. In some embodiments, there is one row of first contact structures 150 between two gate slot structures 120. In some embodiments, there are more than one row of first contact structures 150 between two gate slot structures 120. For example, as Figure 1AAs shown, two rows of first contact structures are arranged in the connection region 104 between two gate slot structures 120. The connection layer 156 of each first contact structure 150, each second contact structure 152, and each third contact structure 153 is coupled to the conductive layer 106A of the first stack 106 in at least one of the channel regions 105. It should be noted that... Figure 1A The number of the first contact structure 150, the second contact structure 152, and the third contact structure 153 is for illustrative purposes only. In some embodiments, the semiconductor device may include a fourth contact structure and a fifth contact structure having the same or similar structure as the second contact structure 152.

[0051] Figure 1B Semiconductor device 100 is shown along... Figure 1A The cross-sectional views of cut lines AA', BB', and CC' are shown. Semiconductor device 100 includes a substrate 101, a first stack 106 of alternating conductive layers 106A and isolation layers 106B, and a second stack 108 of alternating dielectric layers 106D and isolation layers 106B. Each isolation layer 106B may have a portion between two adjacent conductive layers 106A in the first stack 106 and another portion between two adjacent dielectric layers 106D in the second stack 108. The first stack 106 and the second stack 108 are disposed on the substrate 101. The substrate 101 may be any suitable semiconductor substrate having any suitable semiconductor material (e.g., single crystal, polycrystalline, or single-crystal semiconductor). For example, substrate 101 may include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, the substrate 101 can be removed from the semiconductor device 100 in a later process of fabricating the semiconductor device 100 to expose the ends of the channel structure 110. The channel structure may include multiple layers, including an isolation layer 111A (e.g., a silicon oxide layer), a dielectric layer 111B (e.g., a silicon nitride layer), an isolation layer 111C (e.g., a silicon oxide layer), and a channel layer 111D (e.g., a polysilicon layer). The isolation layers 111A, 111B, and 111C at the exposed ends of the channel structure 110 may be further removed to expose the channel layer 111D. A semiconductor layer ( Figure 1B (Not shown) to contact the exposed channel layer 11D of different channel structures 110 (e.g., all channel structures 110 of the memory block) to form a common source. The semiconductor device 100 may include a surface layer 107 made of an insulating material (e.g., oxide).

[0052] The first stack 106 may extend in a second horizontal direction (e.g., Y direction) parallel to the top surface of the substrate 101 and perpendicular to the first horizontal direction (e.g., X direction). The conductive layer 106A and the insulating layer 106B may alternate in a vertical direction (e.g., Z direction) perpendicular to the second horizontal direction. The conductive layers 106A may be the same or different in thickness, for example, in the range of 10-500 nm, e.g., about 35 nm. The insulating layers 106B may also be the same or different in thickness, for example, in the range of 10-500 nm, e.g., about 25 nm. It should be noted that... Figure 1B The number of conductive layers 106A and insulating layers 106B shown is for illustrative purposes only, and any suitable number of conductive layers 106A and insulating layers 106B may be included in the first stack 106. Conductive layer 106A may comprise any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, doped silicon, silicides, or any combination thereof. Insulating layer 106B may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, insulating layer 106B may also comprise a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof.

[0053] In some implementations, such as Figure 1B As shown, the first stack 106 includes a liner 106C. The liner 106C may cover part or all sides of the corresponding conductive layer 106A and is located between the conductive layer 106A and two insulating layers 106B adjacent to the corresponding conductive layer 106A. The liner 106C may include a high-k dielectric material (e.g., Al2O3). In some examples, the conductive layer 106A includes (e.g., W) and an adhesive material (e.g., TiN), and the adhesive material may be deposited between the metallic material and the high-k dielectric material. In some examples, the conductive layer 106A includes a metallic material (e.g., W), and the liner 106C includes an adhesive material (e.g., TiN) and a high-k dielectric material.

[0054] like Figure 1B As shown, the first stack 106 may include a channel structure 110 extending in a vertical direction. For example, the first stack may include two memory blocks separated by a gate gap structure 102. The first memory block may include a channel structure 110a, and the second memory block may include a channel structure 110b.

[0055] The second stack 108 includes dielectric layers 106D and isolation layers 106B that alternate with each other along a vertical direction (e.g., the Z direction). The second stack 108 can be connected to the first stack 106. The isolation layer 106B can extend in the connection region 104 into both the first stack 106 and the second stack 108 along a second horizontal direction (e.g., the Y direction). The dielectric layer 106D in the second stack 108 can extend to and contact the corresponding conductive layer 106A (or a substrate 106C surrounding the corresponding conductive layer 106A) in the first stack 106. To fabricate the first stack 106 and the second stack 108, a series of alternating dielectric layers 106D and isolation layers 106B can be formed first. Then, the dielectric layer 106D in the region of the first stack 106 can be etched away, for example, through an opening formed in the location of the gate slot structure 120, while the dielectric layer 106D in the second stack 108 remains unchanged. Then, a liner 106C and a conductive layer 106A can be formed to replace the dielectric layer 106D in the region of the first stack 106 to form the first stack 106.

[0056] The gate slot structure 120 may extend through the first stack 106 in a vertical direction (e.g., the Z direction). In some embodiments, such as Figure 1B As shown, the gate slot structure 120 can extend vertically from the surface layer 107 into the substrate 101. The dummy channel structure 112 can also extend vertically (e.g., the Z-direction) through the first stack 106. In some embodiments, such as Figure 1B As shown, the dummy channel structure 112 can extend into the substrate 101 along the Z direction.

[0057] The first contact structure 150a or 150b (collectively referred to as 150) may extend vertically through at least a portion of the second stack 108 (e.g., a set of dielectric layers 106D and insulating layers 106B of the second stack 108). Figure 1B As shown, the first contact structure 150 may include a body 154 and an outer layer 155. The first contact structure 150 is coupled to a first connection layer 160a or 160b (collectively referred to as 160, for example, Figure 1A(One of the connecting layers 156). The body 154 and the outer layer 155 may extend along the Z direction, and the first connecting layer 160 may extend in the XY plane (e.g., perpendicular to the Z direction). The first connecting layer 160 may have a circular shape in the XY plane. The outer layer 155 may surround and contact the body 154. The body 154 and the outer layer 155 may be connected to the first connecting layer 160. The body 154 may include a first conductive material. Both the outer layer 155 and the first connecting layer 160 may include the same conductive material, which may be referred to as a second conductive material and may be different from the first conductive material of the body 154. In some embodiments, the first conductive material and the second conductive material may be one of metallic materials (e.g., W or TiN). In some embodiments, the first contact structure 150 may be surrounded by a contact spacer 158, and the contact spacer 158 may include a dielectric material (e.g., silicon oxide).

[0058] The second contact structure 152a or 152b (collectively referred to as 152) may extend vertically through a portion of the second stack 108 (e.g., a set of dielectric layers 106D and insulating layers 106B of the second stack 108). Figure 1B As shown, the second contact structure 152 is coupled to the second connection layer 162a or 162b (collectively referred to as 162, for example, Figure 1A The second contact structure 152 and the second connection layer 162 may comprise a conductive material such as W or TiN. The second contact structure 152 may extend along the Z direction, and the second connection layer 162 may extend in the XY plane (e.g., perpendicular to the Z direction). The second connection layer 162 extends along the Z direction above the first connection layer 160, for example, closer to the surface layer 107 than the first connection layer 160. The second connection layer 162 is separated from the first connection layer 160 by one or more dielectric layers 106D and isolation layers 106B of the second stack 108. In some embodiments, the second connection layer 162 may have an annular shape in the XY plane, and the first contact structure 150 may extend through the second connection layer 162 through an opening at the center of the annular shape. In some embodiments, an isolation structure 172 is located between the first contact structure 150 and the second connection layer 162. The isolation structure 172 may comprise a dielectric material (e.g., silicon oxide) to separate the first contact structure 150 and the second connection layer 162.

[0059] The first contact structure 150 and the second contact structure 152 can be exposed from the surface layer 107, which can be configured to couple to external circuitry (e.g., control circuitry). The first connection layer 160 and the second connection layer 162 are each coupled to a corresponding conductive layer 106A of the first stack 106. For example, as... Figure 1BAs shown, a first connecting layer 160a is coupled to a conductive layer 106A-1. The first connecting layer 160a and the conductive layer 106A-1 are located along the Z-direction between two adjacent insulating layers 106B. A second connecting layer 162a is coupled to a conductive layer 106A-2. The second connecting layer 162a and the conductive layer 106A-2 are located along the Z-direction between two adjacent insulating layers 106B.

[0060] In some embodiments, the second connection layer 162a has a first portion 167 and a second portion 168. The first portion 167 is closer to the first contact structure 150a than the second portion 168. The thickness of the first portion 167 (e.g., measured along the Z direction) is less than the thickness of the second portion 168. The first portion 167 of the second connection layer 162a is coupled to the conductive layer 106A-1 of the first stack 106, and the second portion 168 of the second connection layer 162a is coupled to the second contact structure 152.

[0061] Figures 2A-2B A cross-sectional view of the semiconductor device along the cut line BB' is shown. In some embodiments, the semiconductor device includes a first contact structure 150, a second contact structure 152, and a third contact structure 153.

[0062] The third contact structures 153a and 153b (collectively referred to as 153) may have the same or similar structure as the second contact structure 152. The third contact structure 153 may extend vertically through a portion of the second stack 108. The third contact structure 153 is coupled to a third connection layer 163a or 163b (collectively referred to as 163). The third connection layer 163 is located along the Z-direction between the second connection layer 162 and the first connection layer 160. In some embodiments, the third connection layer 163 may have an annular shape in the XY plane, and the first contact structure 150 may extend through the third connection layer 163 through an opening at the center of the annular shape.

[0063] In some embodiments, the second connection layer 162a is separated from the first contact structure 150a by an isolation structure 172a, and the third connection layer 163a is separated from the first contact structure 150a by an isolation structure 172b. Each of the second connection layer 162 and the third connection layer 163 has an inner surface 173 that contacts the isolation structure 172 and an outer surface 174 that contacts the dielectric layer 106D. The third contact structure 153 extends below the second connection layer 162 along the Z direction, but the third contact structure 153 does not contact the second connection layer 162.

[0064] In some implementations, such as Figure 2AAs shown, the isolation structures 172a and 172b have the same or substantially the same width along the X direction, such that the inner surface 173a of the second connecting layer 162 and the inner surface 173b of the third connecting layer 163 are at the same distance from the first contact structure 150. The third connecting layer 163 extends further along the X direction than the second connecting layer 162, such that the outer surface 174b of the third connecting layer 163 is further away from the first contact structure 150 than the outer surface 174a of the second connecting layer 162. Thus, the third contact structure 153 can extend along the Z direction to contact the third connecting layer 163 at a portion near the outer surface 174b, without contacting the second connecting layer 162.

[0065] In some implementations, such as Figure 2B As shown, the width of the isolation structure 172a along the X direction is greater than the width of the isolation structure 172b, such that the inner surface 173a of the second connecting layer 162 is further away from the first contact structure 150 than the inner surface 173b of the third connecting layer 163. In some embodiments, the outer surfaces 174a of the second connecting layer 162 and 174b of the third connecting layer 163 have the same distance from the first contact structure 150. Thus, the third contact structure 153 can extend along the Z direction to contact the third connecting layer 163 at a portion near the inner surface 173b, without contacting the second connecting layer 162.

[0066] Figures 3A-3M This illustrates the manufacture of semiconductor devices (e.g., Figure 1A-Figure 2B Example process of the semiconductor device shown. Figures 3A-3M Example semiconductor structures are shown at various stages of the manufacturing process along... Figure 1A The cross-sectional view of the cutting line BB'.

[0067] like Figure 3A As shown, a semiconductor structure 300a is formed. The semiconductor structure 300a includes a substrate 301 and a stack 308 of alternating dielectric layers 306D and isolation layers 306B disposed on the substrate 301. The dielectric layers 306D and isolation layers 306B may alternate in a vertical direction (e.g., the Z direction). The isolation layer 306B may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the dielectric layer 306D may include a dielectric material different from the dielectric material of the isolation layer 306B. For example, the isolation layer 306B may include silicon oxide, and the dielectric layer 306D may include silicon nitride. In some embodiments, the semiconductor structure 300a may also include a polysilicon layer 303 along a vertical direction between the stack 308 and the substrate 301.

[0068] like Figure 3AAs shown, first contact holes 310a, 310b, and 310c (collectively referred to as 310) are formed through a portion of the stack 308 by an etching process. Each first contact hole 310 extends from the top surface of the semiconductor structure 300a (e.g., a surface further away from the substrate 301) to the isolation layer 306B of the stack 308. In some embodiments, the first contact holes 310 extend to different isolation layers 306B of the stack 308. For example, the first contact hole 310a may extend to the Mth (e.g., numbered from the top surface of the stack 308 to the substrate 301) isolation layer 306B-1 of the stack 308; the first contact hole 310b may extend to the (M+k)th isolation layer 306B-2 of the stack 308; and the first contact hole 310c may extend to the (M+2k)th isolation layer 306B-3 of the stack 308, where M and k are integers.

[0069] like Figure 3B As shown in the semiconductor structure 300b, contact spacers 320 can be deposited on the inner surface of each first contact hole 310. The contact spacers 320 may include a dielectric material, such as silicon oxide. The contact spacers 320 can be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD) methods. In some embodiments, the contact spacers 320 are first deposited on both the inner and bottom surfaces of the first contact holes 310a. Then, the contact spacers 320 on the bottom surface of the first contact holes 310a are removed by an etching process, and the first contact holes 310a may be deepened to reach the dielectric layer 306D-1 beneath the isolation layer 306B-1. In some embodiments, the contact spacers 320 may protect the dielectric layer 306D exposed by the first contact holes 310 from subsequent etching processes.

[0070] like Figure 3CAs shown in the semiconductor structure 300c, a space 312a can be formed at the bottom of the first contact hole 310a by removing a portion of the dielectric layer 306D-1. A portion of the dielectric layer 306D-1 can be removed by an etching process (e.g., wet etching). In some embodiments, the etching process can cause the space 312a to expand closer to the first contact hole 310a, such that the dimension of the space 312a along the Z-direction at position 332 is larger than the dimension of the space 312a along the Z-direction at position 334. For example, a first etchant can be used during a first time period of the etching process. The first etchant can etch away the sacrificial layer 306D-1 and the two isolation layers 306B-1 and 306B-7 adjacent to the sacrificial layer 306D-1. Therefore, a first portion of the sacrificial layer 306D-1 and portions of the isolation layers 306B-1 and 306B-7 can be etched away during the first time period of the etching process. A second etchant can be used during a second time period of the etching process. The second etchant can etch away the sacrificial layer 306D-1 and has less or no effect on the isolation layers 306B-1 and 306B-7. Therefore, a second portion of the sacrificial layer 306D-1 can be etched away during the second time period of the etching process.

[0071] Similarly, spaces 312b and 312c can be formed at the bottom of the first contact hole 310b and the first contact hole 310c.

[0072] like Figure 3D As shown in the semiconductor structure 300d, a metal layer 362 can be formed by filling the space 312 with a metal material (e.g., W). In some embodiments, when the metal material is deposited in the space 312, the metal material is also deposited on the inner surface of the first contact hole 310 and the top surface of the semiconductor structure 300d.

[0073] Figure 3E A semiconductor structure 300e is shown, which can be formed by removing metal material from the inner surface of the first contact hole 310 and the top surface of the semiconductor structure 300d. A portion of the metal layer 362a is etched away along the X direction from the bottom of the first contact hole 310a to create a space 314a. In some embodiments, the length 322 of the space 314a along the X direction is greater than the length 324 of the bottom of the first contact hole 310. Similarly, spaces 314b and 314c can be formed below the first contact holes 310b and 310c.

[0074] Figure 3F A semiconductor structure 300f is shown that can be formed by filling space 314 with a dielectric material (e.g., silicon oxide). In some embodiments, the dielectric material can be deposited into space 314 using an ALD method.

[0075] Figure 3G A semiconductor structure 300g formed by extending the first contact hole 310 is shown. In some embodiments, the first contact holes 310a, 310b, and 310c are extended by etching away the same number of isolation layers 306B and dielectric layers 306D of the stack 308. For example, the first contact hole 310a may extend to the (M+j)th isolation layer 306B-4 of the stack 308; the first contact hole 310b may extend to the (M+k+j)th isolation layer 306B-5 of the stack 308; and the first contact hole 310a may extend to the (M+2k+j)th isolation layer 306B-6 of the stack 308, where M, k, and j are integers.

[0076] In some embodiments, the contact spacer 320 is also removed during the etching process. A portion of the dielectric material filling the space 314 is retained during the etching process to form an isolation structure 372 adjacent to the remaining metal layer 362.

[0077] Figure 3H A semiconductor structure 300h is shown that can be formed by depositing contact spacers 358 on the inner surface of an extended first contact hole 310.

[0078] like Figure 3I As shown in the semiconductor structure 300i, the first contact hole 310a can be deepened to reach the dielectric layer 306D-4 beneath the isolation layer 306B-4. A space 316a can be formed at the bottom of the first contact hole 310a by removing a portion of the dielectric layer 306D-4. A portion of the dielectric layer 306D-4 can be removed by an etching process (e.g., wet etching). Similarly, spaces 316b and 316c can be formed at the bottom of the first contact holes 310b and 310c.

[0079] like Figure 3J As shown in the semiconductor structure 300j, a metal layer 360 can be formed by filling the space 316 with a metal material (e.g., W). Furthermore, the metal material is deposited on the inner surface of the first contact hole 310 to contact the metal layer 360.

[0080] Figure 3K A semiconductor structure 300k is shown that can be formed by filling the first contact hole 310 with a conductive material (e.g., W or TiN). The conductive material can contact the metal layer 360. In some embodiments, excess metal and conductive material on the top surface of the semiconductor structure 300k can be removed by performing a planarization process such as chemical mechanical polishing (CMP). Figure 3JAs shown, a first contact structure 350 is formed. Each first contact structure 350 is coupled to a metal layer 360 that can be used as a first connection layer.

[0081] Figure 3L A semiconductor structure 300l is shown, which can be formed by means of an etching process (e.g., photolithography) to form second contact holes 330a, 330b, and 330c (collectively referred to as 330) passing through a portion of a stack 308. The second contact holes 330 can extend along the Z-direction from the top surface of the semiconductor structure 300l to reach the corresponding metal layer 362. For example, second contact hole 330a reaches metal layer 362a, second contact hole 330b reaches metal layer 362b, and second contact hole 330c reaches metal layer 362c.

[0082] Figure 3M A semiconductor structure 300m is shown that can be formed by filling the second contact hole 330 with a metallic material (e.g., W) to contact the metal layer 362. In some embodiments, excess metallic material on the top surface of the semiconductor structure 300m is removed, for example, by CMP. Figure 3M As shown, a second contact structure 352 is formed. Each second contact structure 352 is coupled to a metal layer 362 that can be used as a second connection layer.

[0083] Figure 4 A flowchart of example process 400 is shown. Process 400 can be performed to form a semiconductor device (e.g., by...). Figure 1A-Figure 2B The semiconductor device 100 shown can be based on... Figures 3A-3M To describe process 400. Process 400 may include forming Figures 3A-3M The process of manufacturing a semiconductor structure in [the document] includes one or more steps. It should be understood that the operations shown in process 400 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with [other operations]. Figure 4 The different execution sequences are shown.

[0084] At position 402, a first stack is formed (e.g., Figure 1A-Figure 1B The first stack 106). The first stack includes conductive layers (e.g., the Z direction) alternating with each other along a first direction (e.g., the Z direction). Figure 1A-Figure 1B The conductive layer 106A) and the insulating layer (e.g., Figure 1A-Figure 1B The isolation layer 106B). The first stack body can be arranged in the array region of the semiconductor device (e.g., Figure 1A-Figure 1B The array region 102) and a portion of the connection region (e.g., Figure 1A-Figure 1B In the channel region 105 of the connection region 104.

[0085] At 404, a second stack is formed (e.g., Figure 1A-Figure 2B The second stack 108). The second stack includes dielectric layers that alternate with each other along the first direction (e.g., Figures 1A-2B The dielectric layer 106D) and the isolation layer (e.g., Figure 1A-Figure 2B The isolation layer 106B). The second stack can be disposed in the connection region of the semiconductor device. The second stack is adjacent to the first stack (e.g., the first stack in channel region 105) along a second direction perpendicular to the first direction (e.g., the Y direction).

[0086] At position 406, a first contact structure is formed in the second stack (e.g., Figures 1A-2B First contact structure 150a Figure 3J The first contact structure 350a). The first contact structure reaches the first connection layer in the second stack (e.g., Figures 1A-2B The first interconnect layer 160a). The first interconnect layer is coupled to the first conductive layer in the first stack body (e.g., the first interconnect layer). Figure 1B The conductive layer 106A-1).

[0087] In some implementations, forming the first contact structure includes etching a first portion of the second stack into a first dielectric layer (e.g., Figure 3B The dielectric layer 306D-1 is used to form a first hole structure (e.g., a first contact hole 310a) along a first direction.

[0088] In some embodiments, forming the first contact structure further includes removing the first dielectric layer and forming a first metal layer (e.g., Figure 3D Metal layer 362a).

[0089] In some embodiments, forming the first contact structure further includes etching a second portion of the second stack body to a second dielectric layer by etching a first metal layer (e.g., Figure 3I The dielectric layer 306D-4), and the first hole structure extends in the second stack along the first direction, as shown in the reference. Figures 3E-3I Described.

[0090] In some embodiments, forming the first contact structure further includes removing the second dielectric layer and forming a second metal layer (e.g., Figure 3J The metal layer 360a) serves as the first connecting layer.

[0091] In some embodiments, forming the first contact structure further includes depositing one or more conductive layers in the first hole structure to contact the first connection layer.

[0092] At 408, a second contact structure is formed in the second stack (e.g., Figure 1A-Figure 2BSecond contact structure 152a Figure 3M The second contact structure 352a). The second contact structure reaches the second connection layer in the second stack (e.g., Figure 1A-Figure 2B The second connection layer 162a). The second connection layer is coupled to the second conductive layer in the first stack body (e.g., the second connection layer). Figure 1B The conductive layer 106A-2). The first contact structure extends through the second connection layer along a first direction (e.g., at the center of the annular shape of the second connection layer). In some embodiments, the size of the second contact structure at the surface layer of the second stack is smaller than the size of the first contact structure.

[0093] In some embodiments, forming the second contact structure includes etching the first metal layer away from the bottom of the first hole structure along a third direction (e.g., the X direction) perpendicular to the first and second directions. Process 400 further includes forming an isolation structure (e.g., filling in) at the bottom of the first hole structure. Figures 3E-3F The dielectric material in space 314a is contacted with the etched first metal layer; and the isolation structure is etched to extend the first hole structure along the first direction.

[0094] In some embodiments, forming the second contact structure includes etching a third portion of the second stack to reach the first metal layer to form a second hole structure spaced apart from the first hole structure along a second direction (e.g., Figure 3L (Second contact hole 330a). One or more conductive layers are deposited in the second hole structure to contact the first metal layer used as the second connection layer.

[0095] Figure 5 A block diagram of an example system 500 is shown. According to one or more embodiments of this disclosure, system 500 may have one or more semiconductor devices (e.g., memory devices). System 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage devices. Figure 5 As shown, system 500 may include a host device 508 and a storage system 502 having one or more memory devices 504 and a memory controller 506. The host device 508 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host device 508 may be configured to send data to or receive data from one or more memory devices 504.

[0096] Memory device 504 can be any memory device disclosed in this disclosure, such as... Figure 1A-Figure 1B The illustrated semiconductor device is a NAND flash memory. A memory controller 506 (also referred to as controller circuitry) is coupled to the memory device 504 and the host device 508. Consistent with embodiments of this disclosure, the memory device 504 may include a plurality of conductive interconnects through a cover layer contacting conductive pads in a conductive pad layer, and the memory controller 506 may be coupled to the memory device 504 through at least one of the plurality of conductive interconnects. The memory controller 506 is configured to control the memory device 504. For example, the memory controller 506 may be configured to operate a plurality of channel structures via word lines. The memory controller 506 may manage data stored in the memory device 504 and communicate with the host device 508.

[0097] In some embodiments, the memory controller 506 is designed / configured to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 506 is designed / configured to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage devices in mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 506 may be configured to control the operation of the memory device 504, such as read, erase, and program (or write) operations. The memory controller 506 may also be configured to manage various functions regarding data stored or to be stored in the memory device 504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 506 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 504. The memory controller 506 may also perform any other appropriate function, such as formatting the memory device 504.

[0098] The memory controller 506 can communicate with external devices (e.g., host device 508) according to a specific communication protocol. For example, the memory controller 506 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Fast PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0099] The memory controller 506 and one or more memory devices 504 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the storage system 502 can be implemented and packaged into different types of end electronic products. Figure 5 In one example shown, the memory controller 506 and a single memory device 504 can be integrated into the memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMC), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0100] The subjects and embodiments of action and operation described in this disclosure can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or in a combination of one or more of them. Embodiments of the subjects described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, for example, a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of these, or as part of a combination of one or more of these. The computer storage medium is not a propagation signal.

[0101] It should be noted that references to "an embodiment," "an embodiment," "an example embodiment," "some embodiments," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations is within the knowledge of those skilled in the art.

[0102] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can also be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, again at least partly depending on the context.

[0103] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with an intermediate feature or layer in between. Furthermore, “above” or “on top of” means not only “above” or “on top of” something, but also includes “above” or “on top of” something without an intermediate feature or layer in between (i.e., directly on) something.

[0104] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element(s). In addition to the orientations shown in the accompanying drawings, the spatially relative terms are also intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially related descriptive terms used herein may be interpreted accordingly.

[0105] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed; therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, so the bottom side of the substrate is opposite to the top side. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0106] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect vias are formed) and one or more dielectric layers.

[0107] As used herein, the term “nominal / nominally” refers to the expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term “about” or “approximately” may indicate a value of a given quantity that varies, for example, within 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value). As used herein, the term “substantially” means most or a majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0108] In this disclosure, the terms "horizontal / horizontally / laterally" refer to a lateral surface that is nominally parallel to the substrate, and the terms "vertical" or "perpendicularly" refer to a lateral surface that is nominally perpendicular to the substrate.

[0109] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having strings of vertically oriented memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in the vertical direction relative to the substrate.

[0110] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include embodiments in which the first and second features can directly contact each other, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not directly contact each other. Additionally, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0111] The foregoing description of a particular implementation can be readily modified / adapted for various applications. Therefore, based on the teachings and guidance presented herein, such modifications and adjustments are intended to fall within the meaning and scope of equivalent variations of the disclosed implementation.

[0112] While this disclosure contains numerous details of specific embodiments, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Certain features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may be directed to sub-combinations or variations thereof.

[0113] Similarly, although operations are shown in a specific order in the accompanying drawings and recited in a specific order in the claims, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order, or to perform all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0114] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the appended claims. For example, the actions recited in the claims can be performed in different orders and still achieve the desired result. As an example, the processes shown in the figures do not necessarily require the specific order or sequential order shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0115] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: A first stack of conductive and insulating layers alternating with each other along a first direction; A second stack of dielectric and insulating layers alternating with each other along the first direction, wherein the second stack is adjacent to the first stack along a second direction perpendicular to the first direction; A first contact structure extending in the second stack, wherein the first contact structure is coupled to a first conductive layer in the first stack via a first connection layer in the second stack; and A second contact structure extending in the second stack, wherein the second contact structure is coupled to a second conductive layer in the first stack via a second connection layer in the second stack, and wherein the first contact structure extends through the second connection layer.

2. The semiconductor device according to claim 1, wherein, The first contact structure extends through a first portion of the second stack to reach the first connection layer, and the second contact structure extends through a second portion of the second stack to reach the second connection layer. The second stack includes a surface layer comprising an insulating material, and the second connecting layer is closer to the surface layer along the first direction than the first connecting layer.

3. The semiconductor device according to claim 1 or claim 2, wherein, The first connecting layer has a circular shape in a planar view perpendicular to the first direction, and the second connecting layer has an annular shape in the planar view.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The first interconnect layer is separated from the second interconnect layer by one or more alternating dielectric and isolation layers of the second stack.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The size of the first contact structure at the surface layer of the second stack is larger than the size of the second contact structure at the surface layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein, The second connection layer includes a first portion and a second portion that is closer to the first contact structure than the first portion, wherein the thickness of the first portion along the first direction is less than the thickness of the second portion along the first direction.

7. The semiconductor device according to claim 6, wherein, The second contact structure is coupled to the second portion of the second connection layer.

8. The semiconductor device according to any one of claims 1 to 7, further comprising: A third contact structure extending in the second stack, wherein the third contact structure is coupled to a third conductive layer in the first stack via a third connection layer in the second stack. Wherein, the third connecting layer is located between the first connecting layer and the second connecting layer along the first direction, and The first contact structure extends through the third connection layer.

9. The semiconductor device according to claim 8, wherein, The second connecting layer includes a first outer surface that contacts a first corresponding dielectric layer of the second stack, and the third connecting layer includes a second outer surface that contacts a second corresponding dielectric layer of the second stack. In this case, the first outer surface of the second connecting layer is closer to the first contact structure than the second outer surface of the third connecting layer.

10. The semiconductor device according to claim 9, wherein, The second connection layer includes an inner surface spaced from the first contact structure by a first isolation structure made of an insulating material, and the third connection layer includes an inner surface spaced from the first contact structure by a second isolation structure made of the insulating material. The first isolation structure and the second isolation structure have substantially the same thickness along a third direction perpendicular to the first direction and the second direction.

11. The semiconductor device according to claim 8, further comprising: A first isolation structure between the first contact structure and the second connection layer along a third direction perpendicular to the first direction and the second direction; as well as A second isolation structure along the third direction between the first contact structure and the third connection layer. Wherein, the thickness of the first isolation structure along the third direction is greater than the thickness of the second isolation structure along the third direction.

12. A semiconductor device, comprising: A first stack of conductive and insulating layers alternating with each other along a first direction; A second stack of dielectric and insulating layers alternating with each other along the first direction, wherein the second stack is adjacent to the first stack along a second direction perpendicular to the first direction; A first contact structure extending in the second stack, wherein the first contact structure is coupled to a first conductive layer in the first stack; and A second contact structure extending in the second stack, wherein the second contact structure is coupled to a second conductive layer in the first stack, and wherein the size of the second contact structure at the surface layer of the second stack is smaller than the size of the first contact structure at the surface layer of the second stack.

13. The semiconductor device according to claim 12, wherein, One or more first contact structures are arranged in a row along a third direction perpendicular to the first direction and the second direction, wherein the first contact structures and the second contact structures are arranged along a fourth direction perpendicular to the first direction and different from the third direction.

14. The semiconductor device of claim 13, further comprising a first gate gap structure and a second gate gap structure both extending along the third direction, wherein, The first stack and the second stack are arranged between the first gate slot structure and the second gate slot structure, and The first contact structure, which has more than one row, is arranged along the second direction between the first gate gap structure and the second gate gap structure.

15. The semiconductor device according to claim 13 or claim 14, wherein, The first contact structure is coupled to the first conductive layer through a first connection layer in the second stack. The second contact structure is coupled to the second conductive layer through a second connection layer in the second stack, and In a planar view perpendicular to the first direction, the second connecting layer at least partially overlaps with the first connecting layer.

16. The semiconductor device according to claim 15, wherein, The first contact structure extends through the second connection layer along the first direction, and wherein at least one second contact structure is coupled to the second connection layer.

17. A method of forming a semiconductor device, the method comprising: A first stack of conductive and insulating layers alternating with each other along a first direction is formed; A second stack of dielectric and insulating layers alternating with each other along the first direction is formed, wherein the second stack is adjacent to the first stack along a second direction perpendicular to the first direction; A first contact structure is formed in the second stack, wherein the first contact structure reaches a first connection layer in the second stack, and wherein the first connection layer is coupled to a first conductive layer in the first stack; and A second contact structure is formed in the second stack, wherein the second contact structure reaches a second connection layer in the second stack, and wherein the second connection layer is coupled to a second conductive layer in the first stack. The first contact structure extends through the second connection layer.

18. The method according to claim 17, wherein, Forming the first contact structure in the second stack includes: The first portion of the second stack is etched into the first dielectric layer to form a first hole structure along the first direction; Remove the first dielectric layer and form a first metal layer; The first hole structure extends in the second stack by etching the first metal layer to further etch the second portion of the second stack to the second dielectric layer, while extending the first hole structure in the second stack along the first direction. Remove the second dielectric layer and form a second metal layer as the first interconnect layer; and One or more conductive layers are deposited in the first pore structure to contact the first connection layer.

19. The method according to claim 18, wherein, Etching the first metal layer includes: The first metal layer is etched away from the bottom of the first hole structure along a third direction perpendicular to the first and second directions. The method further includes: An isolation structure is formed in the bottom of the first hole structure to contact the etched first metal layer; and The isolation structure is etched to extend the first hole structure along the first direction.

20. The method according to claim 18 or claim 19, wherein, Forming the second contact structure in the second stack includes: Etching a third portion of the second stack to reach the first metal layer to form a second hole structure spaced apart from the first hole structure along the second direction; and One or more conductive layers are deposited in the second hole structure to contact the first metal layer, which serves as the second connection layer.

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