Fast recovery diode and manufacturing method thereof

Abstract

The invention relates to a fast recovery diode and a manufacturing method thereof, and the method comprises the following steps: depositing a hard mask on an active region on the front surface of an n-type substrate, and etching an injection window on the hard mask; injecting p-type impurities into the front surface of the n-type substrate through the window, and performing thermal diffusion to form a p-well; etching the hard mask and the n-type substrate, and forming a groove in the n-type substrate; injecting p-type impurities into the front surface of the n-type substrate, and activating to form a p well; and injecting n-type impurities into the back surface of the n-type substrate to form an n-buffer layer and an n + layer. The doping dosage of p-type impurities on the front face of the n-type substrate is reduced, the injection efficiency is reduced, the n-buffer layer is arranged between the n-type base region and the n + layer, the electron injection efficiency of the back face is reduced, and compromise optimization of device conduction loss and switching loss is achieved by reducing the positive electrode hole injection efficiency on the front face and the negative electrode electron injection efficiency on the back face. And meanwhile, negative effects caused by a service life control means are avoided.

Description

Technical Field

[0001] This invention relates to the field of fast recovery diode technology, and more particularly to a fast recovery diode and its manufacturing method. Background Technology

[0002] In power topologies, apart from IGBTs, fast recovery diodes account for a significant proportion of power losses. In practical applications, heavy metal doping or irradiation to create deep-level defects is typically used to adjust the carrier lifetime of the diode, thereby achieving a trade-off between device conduction and switching losses.

[0003] However, both methods have their own problems. Heavy metal doping technology imposes very strict requirements on product control, and the device has a severe negative temperature coefficient of resistance, making it extremely challenging to ensure consistent device performance in parallel applications. Irradiation technology, on the other hand, results in short low-current lifetimes for diodes, severe EMI during reverse recovery, and places higher demands on device robustness. Furthermore, in the long run, irradiated diodes are more prone to performance degradation.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention discloses a fast recovery diode and its fabrication method, thereby solving the problem of negative impacts on device performance when achieving a trade-off between conduction loss and switching loss through lifetime control.

[0006] The technical solution adopted in this invention is as follows: A fast recovery diode, wherein the vertical structure of the fast recovery diode comprises, from bottom to top, an n+ layer, an n- buffer layer and an n-type base region, wherein grooves are spaced apart on the front side of the n-type base region, and a p-well is formed on the front side of the n-type base region around the grooves by ion implantation, and a p-well is also formed on the front side of the n-type base region by ion implantation, wherein the p-well is located at the lower end of the p-well.

[0007] A further technical solution is that the groove is an inverted trapezoid, and the included angle between the waist and the top edge of the groove is 30~80°.

[0008] A further technical solution is that the p-trap ion implantation concentration is 1e14~1e15 cm⁻¹. -2 The p-trap ion implantation concentration is 1e12~1e14 cm⁻¹ -2 The p-well has a depth greater than 2 μm and a total longitudinal dose greater than 2e12 / cm. -2The ion implantation concentration of the n-buffer layer is 1e13~1e16 cm⁻¹ -2 The ion implantation concentration in the n+ layer is 1e18~1e20 cm⁻¹ -2 .

[0009] A further technical solution is that a cathode metal layer is disposed on the back side of the n-type base region, and an anode metal layer is disposed on the front side of the n-type base region.

[0010] This invention also discloses a method for manufacturing a fast recovery diode as described above, comprising the following steps: A hard mask is deposited on the active region on the front side of the n-type substrate, and an injection window is etched on the hard mask. P-type impurities are injected into the front side of the n-type substrate through a window, and a p-well is formed by thermal diffusion. Etch the hard mask and the n-type substrate to form a groove on the n-type substrate; p-type impurities are implanted on the front side of the n-type substrate and activated to form a p-well; n-type impurities are implanted on the back side of the n-type substrate to form an n-buffer layer and an n+ layer.

[0011] A further technical solution is that the injection window and the groove are inverted trapezoids, the angle between the waist and the top edge of the injection window is 30~80°, the angle between the waist and the top edge of the groove is 30~80°, and the thickness ratio of the injection window to the groove is 2:1; after the groove is formed, the depth of the p-well is >2μm, and the total longitudinal dose is greater than 2e12 / cm. -2 .

[0012] The further technical solution is that the hard mask is made of non-metallic material and the n-type substrate is made of single-crystal silicon material.

[0013] A further technical solution involves using boron as the p-type impurity in the p-well formation step, with an implantation concentration of 1e12~1e14 cm⁻¹. -2 The thermal diffusion temperature is 1050~1300℃, and the thermal diffusion time is 30~300min.

[0014] A further technical solution involves using boron as the p-type impurity in the p-well formation step, with an implantation concentration of 1e14~1e15 cm⁻¹. -2 The concentration of n-type impurities implanted in the n-buffer layer is 1e13~1e16 cm⁻¹ -2 The concentration of n-type impurities implanted in the n+ layer is 1e18~1e20 cm⁻¹ -2 .

[0015] A further technical solution is that, after the step of implanting n-type impurities on the back side of the n-type substrate to form an n-buffer layer and an n+ layer, the solution further includes the steps of depositing an anode metal layer on the front side of the n-type substrate and depositing a cathode metal layer on the back side of the n-type substrate.

[0016] The beneficial effects of the embodiments of the present invention are as follows: (I) A fast recovery diode and its fabrication method according to an embodiment of the present invention reduces the doping dose of p-type impurities on the front side of the n-type substrate, thereby reducing the hole emission efficiency of the anode, i.e., reducing the injection efficiency. In addition, by setting an n- buffer layer between the n-type base region and the n+ layer, the resistive injection of n+ is blocked, i.e., reducing the electron injection efficiency on the back side. By reducing the hole injection efficiency of the front anode and the electron injection efficiency of the back cathode, the device conduction loss and switching loss are optimized at a trade-off, while avoiding the negative impact of lifetime control measures.

[0017] (ii) Furthermore, the injection window and the groove are inverted trapezoidal, and the angle between the waist and the top edge of the injection window is 30~80°. When the hard mask has an angle, the final etching shape of the n-type substrate can be adjusted by a certain angle. After the groove is formed, the depth of the p-well is greater than 2μm, and the total longitudinal dose is greater than 2e12 / cm. -2 This ensures the device's withstand voltage performance. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the fast recovery diode of the present invention.

[0019] Figure 2 This is a schematic diagram of the fast recovery diode of the present invention after step S1 is completed.

[0020] Figure 3 This is a schematic diagram of the fast recovery diode of the present invention after step S2 is completed.

[0021] Figure 4 This is a schematic diagram of the fast recovery diode of the present invention after step S3 is completed.

[0022] In the picture: 1. n+ layer; 2. n- buffer layer; 3. n-type base region; 4. p-well; 5. p-well; 6. n-type substrate; 61. groove; 7. hard mask; 71. injection window. Detailed Implementation

[0023] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0024] Example: This embodiment discloses a fast recovery diode.

[0025] like Figure 1As shown, the vertical structure of the fast recovery diode includes an n+ layer 1, an n- buffer layer 2 and an n-type base region 3 stacked sequentially from bottom to top. Grooves 61 are spaced apart on the front side of the n-type base region 3. A p-well 4 is formed on the front side of the n-type base region 3 around the grooves 61 by ion implantation. A p-well 5 is also formed on the front side of the n-type base region 3 by ion implantation. The p-well 4 is located at the lower end of the p-well 5.

[0026] like Figure 1 As shown, for example, the groove 61 is an inverted trapezoid, and the included angle α between the waist and the top edge of the groove 61 is 30~80°. When the hard mask 7 has an angle, the final etched shape of the n-type substrate 6 can be adjusted by a certain angle.

[0027] Specifically, the ion implantation concentration in p-trap 5 is 1e14~1e15 cm⁻¹. -2 The ion implantation concentration in p-trap 4 is 1e12~1e14 cm⁻¹ -2 The ion implantation concentration in the n-buffer layer 2 is 1e13~1e16 cm⁻¹ -2 The ion implantation concentration in layer n+1 is 1e18~1e20 cm⁻¹ -2 The device's withstand voltage and leakage current are ensured by injecting p-well 4 from the front. Preferably, the depth of p-well 4 is greater than 2 μm, and the total longitudinal dose is greater than 2e12 / cm. -2 This ensures the device's withstand voltage performance.

[0028] Furthermore, a cathode metal layer is disposed on the back side of the n-type base region 3, and an anode metal layer is disposed on the front side of the n-type base region 3.

[0029] like Figures 1-4 As shown, the present invention also discloses a method for manufacturing the aforementioned fast recovery diode, comprising the following steps: Step S1: Deposit a hard mask 7 on the active region on the front side of the n-type substrate 6, and etch an injection window 71 on the hard mask.

[0030] like Figure 2 As shown, specifically, the hard mask 7 is made of non-metallic material, and the n-type substrate 6 is made of single-crystal silicon material. The injection window 71 is an inverted trapezoid, and the included angle β between the waist and the top edge of the injection window 71 is 30~80°.

[0031] In step S2, p-type impurities are injected into the front side of the n-type substrate 6 through the window, and thermal diffusion forms a p-well 4.

[0032] like Figure 3 As shown, specifically, in the step of forming p-well 4, the p-type impurity is boron, and the implantation concentration is 1e12~1e14 cm⁻¹. -2 The thermal diffusion temperature is 1050~1300℃, and the thermal diffusion time is 30~300min.

[0033] Step S3: Etch the hard mask 7 and the n-type substrate 6 to form a groove 61 on the n-type substrate 6.

[0034] like Figure 4 As shown, specifically, the groove 61 is an inverted trapezoid, with an angle of 30~80° between the waist and top edge of the groove 61. The thickness ratio of the injection window 71 to the groove 61 is 2:1. After forming the groove 61, the depth x of the p-well 4 is greater than 2μm, and the total longitudinal dose is greater than 2e12 / cm. -2 In embodiments of the present invention, the hard mask 7 and the substrate can be etched simultaneously, or the substrate can be etched first by wet etching and then the hard mask 7 can be removed.

[0035] In step S4, p-type impurities are implanted on the front side of the n-type substrate 6, and activated to form a p-well 5.

[0036] like Figure 1 As shown, specifically, in the step of forming p-well 5, the p-type impurity is boron, and the implantation concentration is 1e14~1e15 cm⁻¹. -2 .

[0037] In step S5, n-type impurities are implanted into the back side of the n-type substrate 6 to form an n-buffer layer 2 and an n+ layer 1.

[0038] like Figure 1 As shown, specifically, the n-type impurity injection concentration in n-buffer layer 2 is 1e13~1e16 cm⁻¹. -2 The concentration of n-type impurities implanted in layer n+1 is 1e18~1e20 cm⁻¹. -2 .

[0039] Step S6: An anode metal layer is deposited on the front side of the n-type substrate 6, and a cathode metal layer is deposited on the back side of the n-type substrate 6.

[0040] Furthermore, controlling the injection efficiency does not yield higher frequency devices. If high-frequency devices are required, lifetime control measures must be added, such as using heavy metal doping or irradiation to form deep-level defects in the 6-lattice of the semiconductor n-type substrate.

[0041] In this embodiment, by reducing the doping dose of p-type impurities on the front side of the n-type substrate 6, the hole emission efficiency of the anode is reduced, which in turn reduces the injection efficiency. Furthermore, by setting an n-buffer layer 2 between the n-type base region 3 and the n+ layer 1, the resistive injection of n+ is blocked, which reduces the electron injection efficiency on the back side. By reducing the hole injection efficiency of the front anode and the electron injection efficiency of the back cathode, a trade-off optimization between device conduction loss and switching loss is achieved, while avoiding the negative impact of lifetime control measures.

[0042] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A fast recovery diode, characterized in that: The vertical structure of the fast recovery diode includes an n+ layer, an n- buffer layer and an n-type base region stacked sequentially from bottom to top. The n-type base region has grooves spaced apart on its front side. The front side of the n-type base region is circumferentially surrounded by grooves to form a p-well by ion implantation. The front side of the n-type base region is also ion implanted to form a p-well, which is located at the lower end of the p-well.

2. The fast recovery diode according to claim 1, characterized in that: The groove is an inverted trapezoid, and the angle between the waist and the top edge of the groove is 30~80°.

3. The fast recovery diode according to claim 1, characterized in that: The p-well ion implantation concentration is 1e14~1e15 cm⁻¹ -2 The p-trap ion implantation concentration is 1e12~1e14 cm⁻¹ -2 The p-well has a depth greater than 2 μm and a total longitudinal dose greater than 2e12 / cm. -2 ; The ion implantation concentration of the n-buffer layer was 1e13~1e16 cm⁻¹ -2 The ion implantation concentration in the n+ layer is 1e18~1e20 cm⁻¹ -2 .

4. The fast recovery diode according to claim 1, characterized in that: A cathode metal layer is disposed on the back side of the n-type base region, and an anode metal layer is disposed on the front side of the n-type base region.

5. The method for manufacturing a fast recovery diode as described in any one of claims 1 to 4, characterized in that, Includes the following steps: A hard mask is deposited on the active region on the front side of the n-type substrate, and an injection window is etched on the hard mask. P-type impurities are injected into the front side of the n-type substrate through a window, and a p-well is formed by thermal diffusion. Etch the hard mask and the n-type substrate to form a groove on the n-type substrate; p-type impurities are implanted on the front side of the n-type substrate and activated to form a p-well; n-type impurities are implanted on the back side of the n-type substrate to form an n-buffer layer and an n+ layer.

6. The manufacturing method according to claim 5, characterized in that: The injection window and the groove are inverted trapezoidal. The angle between the waist and top edge of the injection window is 30-80°, and the angle between the waist and top edge of the groove is 30-80°. The thickness ratio of the injection window to the groove is 2:

1. After the groove is formed, the depth of the p-well is >2μm, and the total longitudinal dose is greater than 2e12 / cm. -2 .

7. The manufacturing method according to claim 5, characterized in that: The hard mask is made of non-metallic material, and the n-type substrate is made of monocrystalline silicon material.

8. The manufacturing method according to claim 5, characterized in that: In the step of forming the p-well, the p-type impurity is boron, and the implantation concentration is 1e12~1e14 cm⁻¹. -2 The thermal diffusion temperature is 1050~1300℃, and the thermal diffusion time is 30~300min.

9. The manufacturing method according to claim 5, characterized in that: In the step of forming the p-well, the p-type impurity is boron, and the implantation concentration is 1e14~1e15 cm⁻¹. -2 The concentration of n-type impurities implanted in the n-buffer layer is 1e13~1e16 cm⁻¹ -2 The concentration of n-type impurities implanted in the n+ layer is 1e18~1e20 cm⁻¹ -2 .

10. The manufacturing method according to claim 5, characterized in that: After the step of implanting n-type impurities on the back side of the n-type substrate to form an n-buffer layer and an n+ layer, the following step is also included: An anode metal layer is deposited on the front side of the n-type substrate, and a cathode metal layer is deposited on the back side of the n-type substrate.

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