A super-junction insulated gate bipolar transistor, transistor manufacturing method and chip

Abstract

The embodiment of the present application provides a super-junction insulated gate bipolar transistor, a manufacturing method of the super-junction insulated gate bipolar transistor and a chip, and the super-junction insulated gate bipolar transistor can include: first cross-section regions and second cross-section regions arranged alternately along a first direction; the first cross-section regions and the second cross-section regions both include a collector, a collector region, a buffer layer, an epitaxial layer, a super-junction P column, and a P-type buried layer, a carrier storage layer, a P-type well region, an N-type doped region, an oxide insulating layer, a first gate, a second gate, a third gate and an emitter arranged on the upper surface of the super-junction P column and not overlapping with the super-junction P column in a projection position; and the device gate-collector capacitance can be further reduced, and the device switching stability can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a superjunction insulated gate bipolar transistor, a method for fabricating a superjunction insulated gate bipolar transistor, and a chip thereof. Background Technology

[0002] With the development of technology, insulated gate bipolar transistors (IGBTs) have been widely used in power switching devices. However, in the current technology, IGBTs do not have strong electromagnetic interference resistance and are not applicable to high frequencies. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a superjunction insulated gate bipolar transistor, a method for fabricating a superjunction insulated gate bipolar transistor, and a chip that overcomes or at least partially solves the above problems.

[0004] To address the aforementioned problems, embodiments of the present invention disclose a superjunction insulated-gate bipolar transistor, comprising:

[0005] The first and second cross-sectional areas are arranged alternately along the first direction;

[0006] Both the first cross-sectional region and the second cross-sectional region include a collector, a collector region, a buffer layer, an epitaxial layer, a superjunction P-pillar, and a P-type buried layer, a carrier storage layer, a P-type well region, an N-type doped region, an oxide insulating layer, a first gate, a second gate, a third gate, and an emitter disposed on the superjunction P-pillar and whose projected position does not overlap with the upper surface of the superjunction P-pillar.

[0007] The collector electrode, the collector region, and the buffer layer are connected in sequence.

[0008] The epitaxial layer is located on the upper surface of the buffer layer;

[0009] The superjunction P-pillar is disposed on the side of the epitaxial layer;

[0010] The P-type buried layer is located within the epitaxial layer;

[0011] The carrier storage layer is located on the upper surface of the P-type buried layer in the epitaxial layer;

[0012] The P-type well region is located on the upper surface of the carrier storage layer in the epitaxial layer;

[0013] The N-type doped region is located on the upper surface of the P-type well region in the epitaxial layer;

[0014] The oxide insulating layer is located on the upper surface of the epitaxial layer;

[0015] The first gate, the second gate, and the third gate are respectively located in the oxide insulating layer and between adjacent carrier storage layers;

[0016] The emitter is located on the upper surface of the oxide insulating layer and is in contact with the P-type well region, the third gate, and the N-type doped region;

[0017] The first cross-sectional area also includes a P-type buried layer disposed on the superjunction P-pillar and whose projected position does not exceed the upper surface of the superjunction P-pillar.

[0018] Optionally, the first gate and the second gate are isolated by the oxide insulating layer, and the third gate is located between the first gate and the second gate.

[0019] Optionally, the height of the first gate in the oxide insulating layer is the same as the height of the second gate in the oxide insulating layer.

[0020] Optionally, the height of the first gate in the oxide insulating layer is higher than the height of the third gate.

[0021] Optionally, the doping concentration of the N-type doped region is 10. 15 ~10 17 cm -3 .

[0022] Optionally, the first gate and the second gate have the same length, and the length of the first gate is less than the length of the third gate.

[0023] This invention also discloses a method for fabricating a superjunction insulated gate bipolar transistor, the method comprising:

[0024] Provide an epitaxial layer;

[0025] Superjunction P-pillars are generated in the region on the side of the epitaxial layer;

[0026] A P-type buried layer is generated in the epitaxial layer, wherein both the first cross-sectional area and the second cross-sectional area include a P-type buried layer disposed on the superjunction P-pillar and whose projected position does not overlap with the upper surface of the superjunction P-pillar; the first cross-sectional area also includes a P-type buried layer disposed on the upper surface of the superjunction P-pillar and whose projected position does not exceed the upper surface of the superjunction P-pillar.

[0027] A carrier storage layer is formed on the upper surface of the P-type buried layer in the epitaxial layer;

[0028] An oxide insulating layer is formed on the upper surface of the epitaxial layer;

[0029] In the oxide insulating layer, a first gate, a second gate, and a third gate are formed in the region between adjacent charge carrier storage layers;

[0030] The emitter is formed on the upper surface of the oxide insulating layer;

[0031] The buffer layer is formed on the lower surface of the epitaxial layer;

[0032] The current-collecting region is generated on the lower surface of the buffer layer;

[0033] The current collector electrode is generated on the lower surface of the current collector region.

[0034] Optionally, the first gate and the second gate are isolated by the oxide insulating layer, and the third gate is located between the first gate and the second gate.

[0035] Optionally, the generation of a current collector on the lower surface of the current collector region includes:

[0036] The current collector is generated by deposition or sputtering on the lower surface of the current collector region.

[0037] Optionally, the generation of the emitter on the upper surface of the oxide insulating layer includes:

[0038] The emitter is formed beneath the oxide insulating layer by deposition or sputtering.

[0039] Optionally, the height of the first gate in the oxide insulating layer is the same as the height of the second gate in the oxide insulating layer.

[0040] Optionally, the height of the first gate in the oxide insulating layer is higher than the height of the third gate.

[0041] The present invention also discloses a chip comprising the superjunction insulated gate bipolar transistor as described above.

[0042] The embodiments of the present invention have the following advantages:

[0043] This invention discloses a superjunction insulated-gate bipolar transistor (SMT), a method for fabricating a superjunction SMT, and a chip. By introducing a carrier storage layer and adding a P-type buried layer at a certain interval below the carrier storage layer, the buried layer connects to the superjunction P-pillar and forms a self-biased P MOSFET structure with the N-type carrier storage layer and the P-type well region. This enhances the transistor's conductivity modulation effect and reduces the on-state voltage drop. Furthermore, by setting a first gate, a second gate, and a third gate in the carrier storage layer to form a split-gate structure, this invention improves the applicable frequency, further reduces the gate-collector capacitance and gate charge, enhances the device's switching stability, and reduces coupling oscillations during switching caused by parasitic parameters, thereby improving its electromagnetic interference immunity. Attached Figure Description

[0044] Figure 1 This is a structural block diagram of a superjunction insulated gate bipolar transistor provided in an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of a superjunction insulated gate bipolar transistor in the first cross-section region provided by an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of a superjunction insulated gate bipolar transistor with a second cross-section region provided in an embodiment of the present invention;

[0047] Figure 4 This is a flowchart illustrating the steps of a method for fabricating a superjunction insulated gate bipolar transistor according to an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of an epitaxial layer provided in an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of the fabrication of a superjunction insulated gate bipolar transistor provided in an embodiment of the present invention. Figure 1 ;

[0050] Figure 7 This is a schematic diagram of the fabrication of a superjunction insulated gate bipolar transistor provided in an embodiment of the present invention. Figure 2 ;

[0051] Figure 8 This is a schematic diagram of the fabrication of a superjunction insulated gate bipolar transistor provided in an embodiment of the present invention. Figure 3 ;

[0052] Figure 9 This is a schematic diagram of the fabrication of a superjunction insulated gate bipolar transistor provided in an embodiment of the present invention. Figure 4 ;

[0053] Figure 10This is a schematic diagram of the fabrication of a superjunction insulated gate bipolar transistor provided in an embodiment of the present invention. Figure 5 ;

[0054] Figure 11 This is a structural block diagram of another superjunction insulated gate bipolar transistor provided in an embodiment of the present invention;

[0055] Figure 12 This is a structural block diagram of another superjunction insulated gate bipolar transistor provided in an embodiment of the present invention;

[0056] Figure 13 This is a structural block diagram of the second cross-sectional region of another superjunction insulated gate bipolar transistor provided in an embodiment of the present invention. Detailed Implementation

[0057] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0058] One of the core concepts of this invention is that by introducing a carrier storage layer and adding a P-type buried layer at a certain interval below the carrier storage layer, the buried layer is connected to the superjunction P-pillar at the superjunction P-pillar and forms a self-biased P MOSFET structure with the N-type carrier storage layer and the P-type well region, thereby enhancing the conductivity modulation effect of the transistor and reducing the on-state voltage drop. By setting a first gate, a second gate, and a third gate in the carrier storage layer to form a split gate structure, this invention can further reduce the gate-collector capacitance and gate charging charge of the device, improve the switching stability of the device, and at the same time reduce the coupling oscillations during the switching process caused by parasitic parameters, thereby improving its electromagnetic interference resistance.

[0059] Reference Figure 1 The diagram shows a structural block diagram of a superjunction insulated gate bipolar transistor according to the present invention, comprising:

[0060] The first cross-sectional region AA' and the second cross-sectional region BB' are alternately arranged along the first direction; both the first cross-sectional region and the second cross-sectional region include a collector 1, a collector region 2, a buffer layer 3, an epitaxial layer 4, a superjunction P pillar 5, and a P-type buried layer 6, a carrier storage layer 7, a P-type well region 8, an N-type doped region 9, an oxide insulating layer 10, a first gate 11, a second gate 12, a third gate 13, and an emitter 14, which are disposed on the superjunction P pillar 5 and whose projected position does not overlap with the upper surface of the superjunction P pillar 5.

[0061] In this embodiment of the invention, the P-type buried layer disposed on the superjunction P-pillar 5 and whose projection position does not overlap with the upper surface of the superjunction P-pillar 5 refers to the P-type buried layer 6 being physically located above the superjunction P-pillar 5. However, when viewed from a direction perpendicular to the device surface, the projection area formed by the P-type buried layer 6 on the horizontal plane is completely offset from the projection area formed by the upper surface of the superjunction P-pillar 5 on the same horizontal plane, with no overlap. This also means that there is no direct physical contact between the two inside the device.

[0062] like Figure 1 It can be seen that the superjunction insulated gate bipolar transistor has a first cross-sectional region AA' and a second cross-sectional region BB' in the first direction. The difference between the two cross-sectional regions is the difference of the P-type buried layer 6. The second cross-sectional region BB' only has the P-type buried layer 6 in the area where the projected position does not overlap with the upper surface of the superjunction P pillar 5.

[0063] Among them, collector 1, collector region 2, and buffer layer 3 are connected in sequence.

[0064] In this embodiment of the invention, the superjunction insulated gate bipolar transistor is composed of a collector 1, a collector region 2, and a buffer layer 3 connected in sequence. These three layers together form the basis of the current path and the charge buffer region of the device. The collector 1 is directly connected to the collector region 2, which plays the core role of collecting charge carriers. The buffer layer 3 is located above the collector region, and its main function is to alleviate the lattice mismatch problem between the collector region and the epitaxial layer above. At the same time, it plays a certain role in buffering and regulating the transport of charge carriers, reducing the recombination loss of charge carriers at the interface, and providing a stable underlying environment for the operation of various functional regions in the subsequent epitaxial layer.

[0065] Epitaxial layer 4 is located on the upper surface of buffer layer 3.

[0066] Superjunction P-pillar 5 is located on the side of epitaxial layer 4.

[0067] In this embodiment of the invention, the epitaxial layer 4 is the core carrier of the entire superjunction insulated gate bipolar transistor functional region, in which various doped regions, storage layers and well regions are integrated. Its material properties and thickness directly affect key performance indicators such as carrier mobility and device breakdown voltage. In the epitaxial layer, the first thing to pay attention to is the superjunction P pillar. These P pillars are located on both sides of the epitaxial layer. The purpose of adopting the superjunction structure design is to optimize the electric field distribution inside the device by alternating the P-type semiconductor and the N-type semiconductor of the epitaxial layer itself, which greatly improves the voltage withstand capability of the transistor, while avoiding the electric field concentration problem caused by a single doping type in the traditional structure, thus ensuring the stable operation of the device under high voltage conditions.

[0068] In this embodiment of the invention, a P-type buried layer 6 is also provided on the upper surface of the superjunction P-pillar 5 and in the area not in contact with the superjunction P-pillar inside the epitaxial layer 4. This buried layer structure does not completely cover the epitaxial layer, but is specifically distributed above and in the middle area of ​​the superjunction P-pillar. Its core function is to form a specific potential distribution with the surrounding area. The P-type buried layer is directly connected to the superjunction P-pillar at the superjunction P-pillar. This connection method allows the P-type buried layer to obtain stable potential support with the help of the superjunction P-pillar. At the same time, together with the carrier storage layer (N-type) above it and the P-type well region above it, it constitutes a self-biased PMOSFET structure. The formation of the self-biased structure does not require the introduction of an external bias circuit. Instead, it achieves spontaneous bias through the doping type and potential difference of each region itself. This structure can significantly enhance the conductivity modulation effect of the transistor. When the device is turned on, the conductivity modulation effect will cause a large accumulation of carriers in a specific region, reducing the resistance in the current transmission process, thereby effectively reducing the on-state voltage drop of the device, reducing the power loss during device operation, and improving the energy conversion efficiency.

[0069] Carrier storage layer 7 is located on the upper surface of the P-type buried layer in epitaxial layer 4;

[0070] P-type well region 8 is located on the upper surface of the carrier storage layer in the epitaxial layer;

[0071] In this embodiment of the invention, the carrier storage layer 4 is located on the upper surface of the P-type buried layer 6, and is also inside the epitaxial layer. Its function is to temporarily store carriers during device operation. During the conduction phase, the carrier storage layer can accumulate a large number of carriers, further enhancing the conductivity modulation effect and helping to reduce the conduction voltage drop. During the turn-off phase, the stored carriers are released in an orderly manner, avoiding the turn-off delay problem caused by carrier residue, laying the foundation for the rapid response of the device switching process. On the upper surface of the carrier storage layer, a P-type well region 8 is provided. The P-type well region 8 is a local doped region, and its function is to form a specific potential well, restricting and regulating the movement range of carriers, while providing isolation and potential support for the N-type doped region above, ensuring that the charges between the functional regions do not interfere with each other and maintaining the stability of device operation.

[0072] N-type doped region 9 is located on the upper surface of the P-type well region in the epitaxial layer;

[0073] An oxide insulating layer 10 is located on the upper surface of the epitaxial layer 4;

[0074] In this embodiment of the invention, the N-type doped region 9 is located on the upper surface of the P-type well region. Its main function is to provide a large number of electron carriers. When the device is turned on, electrons will start from the N-type doped region, pass through the P-type well region, the carrier storage layer and other regions, and finally form a conduction current. Its doping concentration and area will directly affect the current driving capability of the device. On the upper surface of the epitaxial layer, there is an oxide insulating layer. This insulating layer can be made of insulating materials such as silicon oxide. Its core function is to achieve electrical isolation and avoid leakage between the upper gate and the lower epitaxial layer, doped region and other structures. At the same time, it provides a stable support structure for the gate, ensuring that the gate can effectively control the conduction and turn-off of the lower channel through the electric field effect.

[0075] The first gate 11, the second gate 12 and the third gate 13 are located in the oxide insulating layer 10 and between adjacent carrier storage layers 7.

[0076] In this embodiment of the invention, a first gate, a second gate, and a third gate are disposed inside the oxide insulating layer. These three gates are not traditional single-gate structures, but rather adopt a discrete design, located between adjacent carrier storage layers. This discrete gate structure is a key design for optimizing the switching performance of the device. First, compared to the traditional integral gate, the discrete gate can significantly reduce the overlap area between the gate and the drain and source, thereby shielding part of the gate-collector capacitance Cgc and converting it into the gate-emitter capacitance Cge. That is, this structure can increase the gate-emitter capacitance Cge and decrease the gate-collector capacitance Cgc, reducing the ratio of input capacitance to feedback capacitance Ciss / Crss, improving the dv / dt processing capability during switching, improving the switching stability of the device, and enabling the transistor to adapt to higher frequency operating scenarios. Second, the reduction of the gate-collector capacitance can effectively suppress the coupling oscillation phenomenon caused by the interaction of parasitic capacitance and inductance during switching. Therefore, the discrete gate structure not only improves the switching speed, but also significantly enhances the transistor's anti-electromagnetic interference capability, ensuring that the device can operate stably in complex circuit environments.

[0077] In this configuration, when the polysilicon gate is connected to the emitter, its potential is the same as that of the emitter. Together with the N-type carrier storage layer, the P-type buried layer, and the P Well region, it forms a self-biased P MOSFET structure. When the SJ-IGBT is turned off, the voltage from the emitter to the N-type carrier storage layer is less than the threshold voltage of the self-biased P MOSFET. The N-type carrier storage layer is controlled by the polysilicon gate to turn on the inverted self-biased P MOSFET, which accelerates the extraction of excess carriers from the P-type pillar to the emitter, thereby increasing the turn-off di / dt and reducing the turn-off time. When the SJ-IGBT is turned on, since the voltage of the polysilicon gate is greater than the threshold voltage of the self-biased P MOSFET, it is turned off, preventing holes from being extracted from the current to the emitter. This enhances the conductivity modulation effect of the SJ-IGBT and reduces the on-state voltage drop.

[0078] The emitter 14 is located on the upper surface of the oxide insulating layer 10 and is in contact with the P-type well region 8, the third gate 13, and the N-type doped region.

[0079] In this embodiment of the invention, an emitter 14 is disposed on the upper surface of the oxide insulating layer 10. The emitter serves as the terminal for current inflow and is in contact with the P-type well region, the third gate, and the N-type doped region. This multi-region contact method ensures that the emitter can effectively collect carriers from the N-type doped region and regulate the potential of the well region through contact with the P-type well region. At the same time, the contact with the third gate further optimizes the potential coordination between the gate and the emitter, ensuring that the current path of the entire transistor is complete and the potential distribution is reasonable, ultimately realizing the normal conduction and turn-off functions of the device.

[0080] The first section region AA' also includes a P-type buried layer disposed on the upper surface of the superstructure P-column and whose projected position does not exceed the upper surface of the superstructure P-column.

[0081] In this embodiment of the invention, the first cross-sectional area also includes another P-type buried layer. The physical location of the P-type buried layer is directly set on the upper surface of the superjunction P-pillar 5, forming a direct vertical contact with the superjunction P-pillar 5. When viewed by projection from a direction perpendicular to the device surface, the projection area formed by the P-type buried layer 6 on the horizontal plane falls completely within the projection area of ​​the upper surface of the superjunction P-pillar, but does not exceed the horizontal boundary of the upper surface of the superjunction P-pillar 5.

[0082] like Figure 2 This diagram illustrates a transistor with a first cross-sectional region AA' according to an embodiment of the present invention. Figure 3The schematic diagram of the transistor in the second cross-sectional region BB' provided in the embodiment of the present invention shows that there is no P buried layer 6 injected in the BB' cross-section. At this time, the SJ-IGBT, which serves as the N-type carrier storage region, conducts in the same way as the carrier storage IGBT. The difference is that since there is no P buried layer, the N-type doping in this region is more concentrated than that of conventional doping, which can block more holes from entering the emitter and further enhance the conductivity modulation effect.

[0083] This invention discloses a superjunction insulated gate bipolar transistor (SMT). By introducing a carrier storage layer and adding a P-type buried layer at a certain interval below the carrier storage layer, the buried layer connects to the superjunction P-pillar at the superjunction P-pillar and forms a self-biased P MOSFET structure with the N-type carrier storage layer and the P-type well region. This enhances the transistor's conductivity modulation effect and reduces the on-state voltage drop. Furthermore, by setting a first gate, a second gate, and a third gate in the carrier storage layer to form a split gate structure, this invention can further reduce the device's gate parasitic capacitance and gate charging charge, improve the device's switching speed, and simultaneously reduce coupling oscillations during switching caused by parasitic parameters, thereby enhancing its electromagnetic interference immunity.

[0084] In one embodiment of the present invention, such as Figure 2 The first gate 11 and the second gate 12 are isolated by an oxide insulating layer 10, and the third gate 13 is located between the first gate 11 and the second gate 12.

[0085] In this embodiment of the invention, the oxide insulating layer 10 effectively isolates the first gate 11 and the second gate 12, which can avoid leakage or signal interference between the two gates and ensure the stable operation of each gate. At the same time, the third gate 13 is disposed between the first gate 11 and the second gate 12, which can further optimize the electric field distribution in the gate region, enhance the precise control capability of the transistor channel, help improve the switching speed of the device, reduce conduction loss, and thus improve the overall electrical performance and operational reliability, making the transistor more suitable for complex application scenarios such as high voltage and high current.

[0086] In one embodiment of the present invention, the height of the first gate in the oxide insulating layer is the same as the height of the second gate in the oxide insulating layer.

[0087] In this embodiment of the invention, the first gate and the second gate are at the same height in the oxide insulating layer, and are at the same horizontal level in the vertical direction. The distance from the bottom of the oxide insulating layer to the lower surface of the two gates is the same, and the distance from the upper surface of the gate to the top of the oxide insulating layer is also consistent. This consistent height design makes the electric field intensity distribution between the two gates and the carrier storage layer below symmetrical. When a control voltage is applied to the gate, it can produce a balanced regulation effect on the adjacent carrier storage layer, avoiding the problem of uneven electric field distribution caused by height differences. This ensures that the movement law of carriers in the relevant areas is consistent, reducing the abnormal carrier transport caused by excessively strong or weak local electric fields. At the same time, the same height setting helps to simplify the fabrication process of the oxide insulating layer. The same process parameters can be used in the photolithography, etching and other manufacturing processes to achieve synchronous forming of the two gates, reducing the process complexity and error risk caused by height differences, and improving the consistency and yield of device manufacturing.

[0088] In one embodiment of the present invention, the height of the first gate in the oxide insulating layer is higher than the height of the third gate.

[0089] In this embodiment of the invention, the first gate and the third gate exhibit different height distributions in the oxide insulating layer, with the first gate being higher than the third gate. This height difference design results in different electric field strengths and ranges between the two gates and their respective functional regions below them. The third gate is closer to the carrier storage layer below, generating a stronger electric field effect when a voltage is applied, which can more effectively regulate the movement of carriers in the carrier storage layer, especially playing a more direct control role in the accumulation and release of carriers. The first gate is relatively higher, with a slightly greater distance from the P-type well region, N-type doped region, and other structures below, resulting in a relatively weaker electric field strength. It is mainly used to assist in regulating the carrier behavior in the region near the emitter, and its contact with the emitter focuses more on achieving stable potential transfer and current collection. At the same time, this highly differentiated layout can optimize the electric field distribution according to the functional requirements of different gates, avoid mutual interference between the electric fields of each gate, and ensure that each gate can play a precise regulatory role in its specific functional region.

[0090] Since the third gate is located below the first and second polysilicon gates and is isolated by an oxide layer, it partially shields the gate-collector capacitance Cgc and converts it into the gate-emitter capacitance Cge. This structure increases the gate-emitter capacitance Cge and decreases the gate-collector capacitance Cgc, thereby increasing the ratio of input capacitance to feedback capacitance Ciss / Crss, improving the dv / dt handling capability during switching, and enhancing the switching stability of the device.

[0091] By making the height of the first gate higher than that of the third gate, this invention achieves differentiated and precise control of the corresponding functional regions by different gates, enhances the control capability of the first gate over the carrier storage layer, reduces electric field interference between gates, further optimizes the conductivity modulation effect and switching characteristics of the device, and improves the overall working performance of the transistor.

[0092] In one embodiment of the present invention, the doping concentration of the N-type doped region is 10. 15 ~10 17 cm -3 .

[0093] In this embodiment of the invention, the doping concentration of the N-type doped region is set at 10¹. 5 ~10¹ 7 cm - Within this concentration range, which falls under the category of moderate doping, from the perspective of carrier modulation, the N-type doped region within this concentration range can form a suitable potential barrier. When the transistor is operating, holes, as minority carriers, may move towards the emitter. The moderately doped N-type region will have a strong blocking effect on holes. When the concentration is too high, although the blocking ability may be stronger, the excessive number of impurity atoms will lead to lattice distortion, affecting carrier mobility. When the concentration is too low, the potential barrier is insufficient and it is difficult to effectively block holes, allowing some holes to reach the emitter and recombine, weakening the conductivity modulation effect. 5 ~10¹ 7 cm - The concentration of ³ can achieve a balance between the two, forming a strong enough barrier to prevent more holes from entering the emitter and reduce ineffective recombination of charge carriers, while ensuring that it provides a sufficient number of electron charge carriers to ensure a smooth current path.

[0094] At the same time, this doping concentration matches the doping characteristics of the surrounding P-type well region, carrier storage layer and other structures, which can form a reasonable PN junction barrier, avoid electric field concentration or carrier injection imbalance caused by excessive concentration difference, ensure the coordination of carrier transport between regions, and lay the foundation for the stable performance of the overall transistor.

[0095] The present invention sets the doping concentration of the N-type doped region to 10¹. 5 ~10¹ 7 cm - ³ can effectively block more holes from entering the emitter, reduce carrier recombination losses, further enhance the conductivity modulation effect of the transistor, and at the same time ensure a sufficient supply and smooth transmission of electron carriers, thereby reducing the on-state voltage drop of the device and improving energy conversion efficiency.

[0096] In one embodiment of the present invention, the first gate and the second gate have the same length, and the length of the first gate is less than the length of the third gate.

[0097] In this embodiment of the invention, in the transistor structure, the lengths of the first gate and the second gate are consistent, while the lengths of both are less than the length of the third gate.

[0098] As components of the separated gate structure, the first and second gates have the same length, which ensures that the regulation range of adjacent carrier storage layers is consistent. This enables symmetrical control during the accumulation, maintenance and release of carriers, avoiding imbalance in carrier regulation in a certain region due to length differences. It ensures that carriers are evenly distributed in the storage layer, providing a basis for the stable performance of conductivity modulation effect.

[0099] The third gate is relatively longer, which can expand its electric field control range and more effectively cooperate to collect and conduct charge carriers in the near-surface region, forming a functional complement to the first and second gates.

[0100] This length difference design is not a simple size adjustment, but a precise match based on the functional requirements of each gate. The first and second gates focus on the local precise control of the carrier storage layer, while the third gate undertakes the coordinated control and potential conduction of a wider area. The differentiated length design achieves the optimal performance of each gate function, while avoiding functional overlap or control blind spots.

[0101] This invention discloses a superjunction insulated gate bipolar transistor (SMT). By introducing a carrier storage layer and adding a P-type buried layer at a certain interval below the carrier storage layer, the buried layer connects to the superjunction P-pillar at the superjunction P-pillar and forms a self-biased P MOSFET structure with the N-type carrier storage layer and the P-type well region. This enhances the transistor's conductivity modulation effect and reduces the on-state voltage drop. Furthermore, by setting a first gate, a second gate, and a third gate in the carrier storage layer to form a split gate structure, this invention can further reduce the device's gate-collector capacitance and gate charge, improve the device's switching speed, and reduce coupling oscillations during switching caused by parasitic parameters, thereby enhancing its electromagnetic interference immunity.

[0102] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0103] Reference Figure 4 The diagram illustrates a step-by-step flowchart of a method for fabricating a superjunction insulated gate bipolar transistor according to an embodiment of the present invention. This method may include the following steps:

[0104] Step 201: Provide the epitaxial layer.

[0105] In embodiments of the present invention, such as Figure 5 The diagram shows a schematic of an epitaxial layer provided by an embodiment of the present invention. The epitaxial layer can be an N-type epitaxial layer.

[0106] Step 202: Generate a superjunction P-pillar in the region on the side of the epitaxial layer.

[0107] In this embodiment of the invention, superjunction P pillars can be generated in the regions on both sides of the epitaxial layer. The epitaxial layer serves as the carrier for all subsequent functional regions, and its material properties are predetermined. When generating superjunction P pillars, processes such as ion implantation or epitaxial growth are typically used to introduce P-type impurities in the predetermined regions on both sides to form a columnar structure with a specific doping concentration and depth. The position and size of these P pillars can be set according to requirements.

[0108] like Figure 6 This illustrates the fabrication of a superjunction insulated gate bipolar transistor. Figure 1 The diagram shows that the superjunction P-pillar 5 can be generated by etching and implantation in the regions on both sides of the epitaxial layer 4.

[0109] Furthermore, such as Figure 7 This illustration shows a fabrication diagram of a superjunction insulated gate bipolar transistor provided in an embodiment of the present invention. Figure 2 A new epitaxial layer can be grown on the N-type epitaxial layer that forms the SJ structure, serving as the fabrication area for the subsequent SJ-IGBT front-side structure. Its doping and resistivity are the same as the first epitaxial layer.

[0110] Step 203: Generate the P-type buried layer in the epitaxial layer, wherein both the first cross-sectional area and the second cross-sectional area include a P-type buried layer disposed on the upper surface of the superjunction P-pillar and whose projected position does not overlap with the upper surface of the superjunction P-pillar; the first cross-sectional area also includes a P-type buried layer disposed on the upper surface of the superjunction P-pillar and whose projected position does not exceed the upper surface of the superjunction P-pillar.

[0111] In this embodiment of the invention, after the fabrication of the superjunction P-pillar is completed, a P-type buried layer can be generated in the region on the upper surface of the superjunction P-pillar and in the region between the two superjunction P-pillars in the epitaxial layer, thereby forming different cross-sectional regions of the superjunction insulated gate bipolar transistor. This step requires accurate positioning to ensure that the generated P-type buried layer can reliably connect with the underlying superjunction P-pillar, while covering the middle region to form a continuous functional layer. During the fabrication process, by controlling the doping dose and diffusion depth, a suitable potential distribution is formed in the P-type buried layer.

[0112] Step 204: Generate a carrier storage layer on the upper surface of the P-type buried layer in the epitaxial layer.

[0113] In this embodiment of the invention, the layer can be obtained by trench etching inside the epitaxial layer. Its formation process needs to match the underlying P-type buried layer to ensure lattice integrity and carrier transport characteristics at the interface. The thickness and doping concentration of the carrier storage layer need to be precisely controlled to meet the functional requirements of storing enough carriers when conducting and releasing them quickly when turning off. At the same time, it forms good electrical contact with the P-type buried layer to ensure the enhancement of the conductivity modulation effect.

[0114] like Figure 8 This illustration shows a fabrication diagram of a superjunction insulated gate bipolar transistor according to an embodiment of the present invention. Figure 3 A P-type buried layer 6 can be generated by etching and implanting into the region located on the upper surface of the superjunction P-pillar 5 in the epitaxial layer, and a P-type buried layer 6 can be generated in the region located between the two superjunction P-pillars 5. A carrier storage layer 7 can be generated on the upper surface of the P-type buried layer 6 in the epitaxial layer.

[0115] Step 205: An oxide insulating layer is formed on the upper surface of the epitaxial layer;

[0116] In this embodiment of the invention, the material can be prepared by methods such as thermal oxidation or chemical vapor deposition. The material is mostly silicon dioxide. The thickness of the oxide insulating layer needs to be uniform. It must not only ensure sufficient insulation performance to prevent leakage between the gate and the underlying epitaxial layer and various functional areas, but also provide stable support for the gate. Its quality directly affects the effectiveness of gate control and the reliability of the device.

[0117] Step 206: In the oxide insulating layer, in the region between adjacent carrier storage layers, a first gate, a second gate, and a third gate are generated.

[0118] like Figure 9 This illustration shows a fabrication diagram of a superjunction insulated gate bipolar transistor provided in an embodiment of the present invention. Figure 4 The first gate 11, the second gate 12, and the third gate 13 can be generated in the region between adjacent carrier storage layers within the oxide insulating layer 10 formed on the upper surface of the epitaxial layer 4.

[0119] In this embodiment of the invention, trenches can be formed on the oxide insulating layer by photolithography, etching and other processes, and then filled with conductive materials such as polycrystalline silicon or metal. During the fabrication process, the position, height and length of each gate need to be precisely controlled to ensure that the first gate and the second gate have the same height and the same length, and that the length of the first gate is less than the length of the third gate, so as to achieve the design goal of the split gate structure and create conditions for reducing parasitic capacitance and improving switching speed.

[0120] Step 207: An emitter is generated on the upper surface of the oxide insulating layer;

[0121] In this embodiment of the invention, the emitter is typically made of metal material and prepared by processes such as evaporation or sputtering. It forms good ohmic contact with the underlying P-type well region, the third gate, and the N-type doped region. Its pattern design needs to cover the predetermined contact area to ensure that the current can flow smoothly into the device, while realizing potential regulation of the relevant region to ensure the normal conduction and turn-off of the device.

[0122] Step 208: Generate a buffer layer on the lower surface of the epitaxial layer.

[0123] In this embodiment of the invention, the buffer layer can serve as an electric field cutoff during withstand voltage. It is achieved through processes such as epitaxial growth or ion implantation. Its function is to alleviate carrier recombination at the interface and provide a buffer for current transmission.

[0124] Step 209: Generate a collector region on the lower surface of the buffer layer;

[0125] In this embodiment of the invention, the collector region can be a P-type collector region. The collector region can be formed by a doping process using a suitable doping type and concentration. Its main function is to collect charge carriers. It needs to form a continuous current path with the buffer layer and the epitaxial layer above to ensure that the charge carriers can be transported efficiently.

[0126] Step 210: Generate a collector electrode on the lower surface of the collector region.

[0127] like Figure 10 This illustration shows a fabrication diagram of a superjunction insulated gate bipolar transistor provided in an embodiment of the present invention. Figure 5 An emitter 14 can be formed on the upper surface of the oxide insulating layer, a buffer layer 3 can be formed on the lower surface of the epitaxial layer, a collector region 2 can be formed on the lower surface of the buffer layer, and a collector electrode 1 can be formed on the lower surface of the collector region.

[0128] In this embodiment of the invention, the collector electrode can be formed by sputtering. The collector electrode is also made of metal material and forms a good ohmic contact with the collector region. As the terminal of the current outflow device, it is necessary to ensure low contact resistance and good conductivity to ensure the integrity of the current path of the entire device.

[0129] This invention discloses a method for fabricating a superjunction insulated gate bipolar transistor (SMT). By introducing a carrier storage layer and adding a P-type buried layer at a certain interval below the carrier storage layer, the buried layer connects to the superjunction P-pillar at the superjunction P-pillar and forms a self-biased P MOSFET structure with the N-type carrier storage layer and the P-type well region. This enhances the conductivity modulation effect of the transistor and reduces the on-state voltage drop. Furthermore, by setting a first gate, a second gate, and a third gate in the carrier storage layer to form a split gate structure, this invention can further reduce the gate-collector capacitance and gate charging charge of the device, improve the switching stability of the device, and reduce coupling oscillations during switching caused by parasitic parameters, thereby enhancing its electromagnetic interference immunity.

[0130] Reference Figure 11 The diagram illustrates a structural block diagram of another superjunction insulated gate bipolar transistor provided by an embodiment of the present invention, in which the superjunction region formed on the first epitaxial layer and the trench formed on the second epitaxial layer are perpendicularly intersecting.

[0131] Reference Figure 12 The diagram illustrates a structural block diagram of another superjunction insulated gate bipolar transistor provided by an embodiment of the present invention, in which the superjunction P-pillar regions on the first epitaxial layer can be arranged in an array of a certain width, while the structures formed on the second epitaxial layer remain unchanged.

[0132] Reference Figure 13 The diagram shows a schematic of the second cross section of another superjunction insulated gate bipolar transistor provided in an embodiment of the present invention. It can be seen that in the middle region of the second cross section, since the second gate 12 does not need to form a self-biased P MOSFET structure with the N-type carrier storage layer 7, the P-type buried layer 6, and the P Well region 8, the first gate 11 structure at the middle cross section can be separated from the first cross section and connected to the second gate 12 to become a new SJ-IGBT conduction path, which can increase the current density of the SJ-IGBT.

[0133] In one embodiment of the present invention, the first gate and the second gate are isolated by an oxide insulating layer, and the third gate is located between the first gate and the second gate.

[0134] In one embodiment of the present invention, a collector electrode is generated on the lower surface of the collector region, including:

[0135] Collectors are generated on the lower surface of the collector region by deposition or sputtering.

[0136] In one embodiment of the present invention, an emitter is formed on the upper surface of the oxide insulating layer, including:

[0137] The emitter is generated beneath the oxide insulating layer by deposition or sputtering.

[0138] In one embodiment of the present invention, the height of the first gate in the oxide insulating layer is the same as the height of the second gate in the oxide insulating layer.

[0139] In one embodiment of the present invention, the height of the first gate in the oxide insulating layer is higher than the height of the third gate.

[0140] In one embodiment of the present invention, the doping concentration of the N-type doped region is 10. 15 ~10 17 cm -3 .

[0141] In one embodiment of the present invention, the first gate and the second gate have the same length, and the length of the first gate is less than the length of the third gate.

[0142] This invention discloses a method for fabricating a superjunction insulated gate bipolar transistor (SMT). By introducing a carrier storage layer and adding a P-type buried layer at a certain interval below the carrier storage layer, the buried layer connects to the superjunction P-pillar at the superjunction P-pillar and forms a self-biased P MOSFET structure with the N-type carrier storage layer and the P-type well region. This enhances the conductivity modulation effect of the transistor and reduces the on-state voltage drop. Furthermore, by setting a first gate, a second gate, and a third gate in the carrier storage layer to form a split gate structure, this invention can further reduce the gate-collector capacitance and gate charging charge of the device, improve the switching stability of the device, and reduce coupling oscillations during switching caused by parasitic parameters, thereby enhancing its electromagnetic interference immunity.

[0143] This invention also provides a chip that includes the superjunction insulated gate bipolar transistor described above and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0144] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0145] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0146] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0147] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0148] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0149] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0150] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0151] The superjunction insulated gate bipolar transistor, its fabrication method, and chip provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A superjunction insulated-gate bipolar transistor, characterized in that, include: The first and second cross-sectional areas are arranged alternately along the first direction; Both the first cross-sectional region and the second cross-sectional region include a collector, a collector region, a buffer layer, an epitaxial layer, a superjunction P-pillar, and a P-type buried layer, a carrier storage layer, a P-type well region, an N-type doped region, an oxide insulating layer, a first gate, a second gate, a third gate, and an emitter disposed on the superjunction P-pillar and whose projected position does not overlap with the upper surface of the superjunction P-pillar. The collector electrode, the collector region, and the buffer layer are connected in sequence. The epitaxial layer is located on the upper surface of the buffer layer; The superjunction P-pillar is disposed on the side of the epitaxial layer; The P-type buried layer is located within the epitaxial layer; The carrier storage layer is located on the upper surface of the P-type buried layer in the epitaxial layer; The P-type well region is located on the upper surface of the carrier storage layer in the epitaxial layer; The N-type doped region is located on the upper surface of the P-type well region in the epitaxial layer; The oxide insulating layer is located on the upper surface of the epitaxial layer; The first gate, the second gate, and the third gate are respectively located in the oxide insulating layer and between adjacent carrier storage layers; The emitter is located on the upper surface of the oxide insulating layer and is in contact with the P-type well region, the third gate, and the N-type doped region; The first cross-sectional area also includes a P-type buried layer disposed on the superjunction P-pillar and whose projected position does not exceed the upper surface of the superjunction P-pillar.

2. The superjunction insulated gate bipolar transistor according to claim 1, characterized in that, The first gate and the second gate are isolated by the oxide insulating layer, and the third gate is located between the first gate and the second gate.

3. The superjunction insulated gate bipolar transistor according to claim 1, characterized in that, The height of the first gate in the oxide insulating layer is the same as the height of the second gate in the oxide insulating layer.

4. The superjunction insulated gate bipolar transistor according to claim 3, characterized in that, The height of the first gate in the oxide insulating layer is higher than the height of the third gate.

5. The transistor according to claim 1, characterized in that, The doping concentration of the N-type doped region is 10. 15 ~10 17 cm -3 .

6. The superjunction insulated gate bipolar transistor according to claim 1, characterized in that, The first gate and the second gate have the same length, and the length of the first gate is less than the length of the third gate.

7. A method for fabricating a superjunction insulated gate bipolar transistor, characterized in that, The method for fabricating a superjunction insulated gate bipolar transistor as described in any one of claims 1-6 comprises: Provide an epitaxial layer; The superjunction P-pillar is generated in the region on the side of the epitaxial layer; The P-type buried layer is generated in the epitaxial layer, wherein both the first cross-sectional area and the second cross-sectional area include a P-type buried layer disposed on the superjunction P-pillar and whose projected position does not overlap with the upper surface of the superjunction P-pillar; the first cross-sectional area also includes a P-type buried layer disposed on the upper surface of the superjunction P-pillar and whose projected position does not exceed the upper surface of the superjunction P-pillar. The carrier storage layer is formed on the upper surface of the P-type buried layer in the epitaxial layer; The oxide insulating layer is formed on the upper surface of the epitaxial layer; In the oxide insulating layer, the first gate, the second gate, and the third gate are formed in the region between adjacent carrier storage layers; The emitter is formed on the upper surface of the oxide insulating layer; The buffer layer is formed on the lower surface of the epitaxial layer; The current-collecting region is generated on the lower surface of the buffer layer; The current collector electrode is generated on the lower surface of the current collector region.

8. The method for fabricating a superjunction insulated gate bipolar transistor according to claim 7, characterized in that, The first gate and the second gate are isolated by the oxide insulating layer, and the third gate is located between the first gate and the second gate.

9. The method for fabricating a superjunction insulated gate bipolar transistor according to claim 7, characterized in that, The process of generating a collector electrode on the lower surface of the collector region includes: The current collector is generated by deposition or sputtering on the lower surface of the current collector region.

10. The method for fabricating a superjunction insulated gate bipolar transistor according to claim 7, characterized in that, The process of generating the emitter on the surface of the oxide insulating layer includes: The emitter is formed beneath the oxide insulating layer by deposition or sputtering.

11. The method for fabricating a superjunction insulated gate bipolar transistor according to claim 7, characterized in that, The height of the first gate in the oxide insulating layer is the same as the height of the second gate in the oxide insulating layer.

12. The method for fabricating a superjunction insulated gate bipolar transistor according to claim 7, characterized in that, The height of the first gate in the oxide insulating layer is higher than the height of the third gate.

13. A chip, characterized in that, The chip includes a superjunction insulated gate bipolar transistor as described in any one of claims 1-6.

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