Anti-short-circuit semiconductor field effect transistor

Abstract

The invention provides an anti-short-circuit semiconductor field effect transistor, which comprises a second conductive type contact region in contact with a first conductive type drift region and a first conductive type conduction region, heterojunction diodes are formed on different surfaces, when the field effect transistor is reversely conducted, the heterojunction has a hole barrier, and when the field effect transistor is reversely conducted, the heterojunction has a hole barrier. Injection of minority carriers is inhibited, and reverse recovery loss is reduced; when the device has a short-circuit effect, the doping concentration of the second conductive type contact region is high, the saturation current under the short-circuit effect is reduced, the positive conduction is not influenced, and the anti-short-circuit time of the device is prolonged. The anti-short-circuit semiconductor field effect transistor provided by the invention has longer short-circuit tolerance time under the condition that other working characteristics of a device are not deteriorated, so that the anti-short-circuit semiconductor field effect transistor has good reliability under the short-circuit condition.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a short-circuit resistant semiconductor field-effect transistor. Background Technology

[0002] Silicon carbide (SiC) possesses excellent material properties and has attracted much attention as a next-generation power semiconductor material to replace Si. With the development of power integrated circuits, the application of silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) has become increasingly mature. Compared to bipolar devices, MOSFETs have the unparalleled advantage of being able to conduct in reverse. However, the high power density of silicon carbide power MOSFETs also brings reliability challenges. When a short circuit occurs, the extremely high current density will cause a surge in instantaneous power, resulting in a rapid increase in the chip junction temperature, ultimately significantly reducing its short-circuit tolerance.

[0003] In the prior art, on the one hand, by forming a PN superjunction-like structure in the drift region of the silicon carbide semiconductor field-effect transistor, the electronic current path width of the low-doped N-type semiconductor region (N-drift region) is reduced by utilizing the depletion region of the PN junction, thereby reducing the saturation current and improving the short-circuit withstand time; on the other hand, by implementing reverse P-well doping on the source side of the silicon carbide semiconductor field-effect transistor, the current density in the junction field-effect transistor region (JFET region) is reduced, which can also extend the device withstand time.

[0004] However, existing short-circuit protection schemes for silicon carbide power metal-oxide-semiconductor field-effect transistors simultaneously increase minority carrier injection during reverse conduction, leading to increased reverse recovery losses and increased operating losses.

[0005] Therefore, how to provide a field-effect transistor with a long short-circuit withstand time and unchanged other properties is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] This invention provides a short-circuit resistant semiconductor field-effect transistor to solve the problem mentioned above, which, although extending the short-circuit withstand time of the field-effect transistor by setting a PN superjunction-like structure in the drift region or implementing reverse P-well doping on the source side, increases the reverse recovery loss of the device and thus increases the device loss.

[0007] This invention provides a short-circuit resistant semiconductor field-effect transistor, comprising: A substrate, comprising a front side and a back side disposed opposite to each other; An epitaxial layer disposed on the front side of the substrate; A first conductivity type conductive region is disposed on the side of the epitaxial layer away from the substrate; The second conductivity type contact region is disposed on both sides of the first conductivity type conductive region and located on the side of the epitaxial layer away from the substrate; A second conductivity type gate body region is disposed on the side of the second conductivity type contact region away from the substrate; A first conductive type contact region is disposed on the side of the second conductive type contact region away from the substrate, and the upper surface of the first conductive type contact region is flush with the upper surfaces of the first conductive type conductive region, the second conductive type contact region and the second conductive type gate body region. A gate-source composite structure is disposed on the side of the first conductivity type conductive region away from the substrate; A drain metal layer is disposed on the back side of the substrate.

[0008] In one embodiment of the present invention, the first conductive type conductive region is located in the horizontal direction, with a portion between the second conductive type contact regions and a portion between the second conductive type gate body regions; the first conductive type contact region is located in the horizontal direction between the second conductive type contact regions and the second conductive type gate body regions, and the horizontal direction is parallel to the substrate.

[0009] In one embodiment of the present invention, the epitaxial layer includes: a first conductivity type buffer layer disposed on the front side of the substrate; and a first conductivity type drift region disposed on the side of the first conductivity type buffer layer opposite to the substrate.

[0010] In one embodiment of the present invention, the band gap width of the second conductivity type contact region is smaller than the band gap width of the first conductivity type conductive region and the band gap width of the first conductivity type contact region.

[0011] In one embodiment of the present invention, the gate-source composite structure includes: an oxide layer disposed on the side of the first conductivity type conductive region away from the substrate, and the oxide layer covering the first conductivity type conductive region, the second conductivity type gate body region, and a portion of the first conductivity type contact region; a first conductivity type gate polysilicon layer disposed on the side of the oxide layer away from the substrate and encapsulated by the oxide layer; and a source metal layer disposed on the side of the second conductivity type contact region away from the substrate, and the source metal layer covering a portion of the second conductivity type contact region, a portion of the first conductivity type contact region, and the oxide layer.

[0012] In one embodiment of the present invention, the second conductivity type contact region and the first conductivity type conduction region constitute a heterojunction diode, and the second conductivity type contact region and the first conductivity type drift region constitute the heterojunction diode.

[0013] In one embodiment of the present invention, during the reverse conduction process of the field-effect transistor, the heterojunction diode forms a hole barrier.

[0014] In one embodiment of the present invention, when the field-effect transistor is short-circuited, the electronic path of the second conductivity type gate body region is compressed based on the second conductivity type contact region to reduce the saturation current under the short-circuit state.

[0015] In one embodiment of the present invention, the doping concentration of the second conductivity type contact region ranges from 1×10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 .

[0016] The beneficial effects of this invention are as follows: This invention provides a short-circuit resistant semiconductor field-effect transistor (FET). The FET includes a second conductivity type contact region that contacts a first conductivity type drift region and a first conductivity type conduction region, forming a heterojunction diode on different surfaces. When the FET is reverse-biased, the heterojunction has a hole barrier, suppressing minority carrier injection and reducing reverse recovery loss. When a short-circuit effect occurs, the high doping concentration of the second conductivity type contact region reduces the saturation current under short-circuit conditions, does not affect forward conduction, and extends the short-circuit time of the device. The short-circuit resistant semiconductor field-effect transistor provided by this invention has a longer short-circuit withstand time without degrading other operating characteristics of the device, thus exhibiting good reliability under short-circuit conditions. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] In the attached diagram: Figure 1 This is a schematic cross-sectional view of a short-circuit resistant semiconductor field-effect transistor provided in one embodiment of the present invention; Figure 2 This is an energy band diagram formed when the novel K material and silicon carbide material come into contact, as provided in one embodiment of the present invention.

[0019] Reference numerals: 1-Drain metal layer; 2-Substrate; 3-First conductivity type buffer layer; 4-First conductivity type drift region; 5-First conductivity type conduction region; 6-Second conductivity type contact region; 7-Second conductivity type gate body region; 8-First conductivity type contact region; 9-Oxide layer; 10-First conductivity type gate polysilicon layer; 11-Source metal layer. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0021] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0023] As described in the background section, silicon carbide (SiC) possesses excellent material properties and has attracted much attention as a next-generation power semiconductor material to replace Si. With the development of power integrated circuits, the application of silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) has become increasingly mature. Compared to bipolar devices, MOSFETs have the unparalleled advantage of being able to conduct in reverse. However, the high power density characteristics of silicon carbide power MOSFETs also bring reliability challenges. When a short circuit occurs, the extremely high current density will cause a surge in instantaneous power, resulting in a rapid increase in the chip junction temperature, ultimately significantly reducing its short-circuit tolerance.

[0024] In the prior art, on the one hand, by forming a PN superjunction-like structure in the drift region of the silicon carbide semiconductor field-effect transistor, the electronic current path width of the low-doped N-type semiconductor region (N-drift region) is reduced by utilizing the depletion region of the PN junction, thereby reducing the saturation current and improving the short-circuit withstand time; on the other hand, by implementing reverse P-well doping on the source side of the silicon carbide semiconductor field-effect transistor, the current density in the junction field-effect transistor region (JFET region) is reduced, which can also extend the device withstand time.

[0025] However, existing short-circuit protection schemes for silicon carbide power metal-oxide-semiconductor field-effect transistors simultaneously increase minority carrier injection during reverse conduction, leading to increased reverse recovery losses and increased operating losses.

[0026] To solve the above problems, such as Figure 1 As shown, the present invention provides a short-circuit resistant semiconductor field-effect transistor, comprising: Substrate 2, which includes a front side and a back side disposed opposite to each other; An epitaxial layer is disposed on the front side of substrate 2; The first conductivity type conductive region 5 is disposed on the side of the epitaxial layer away from the substrate 2; The second conductivity type contact region 6 is disposed on both sides of the first conductivity type conductive region 5 and located on the side of the epitaxial layer away from the substrate 2. The second conductivity type gate body region 7 is disposed on the side of the second conductivity type contact region 6 away from the substrate 2; The first conductive contact region 8 is disposed on the side of the second conductive contact region 6 away from the substrate 2, and the upper surface of the first conductive contact region 8 is flush with the upper surfaces of the first conductive conductive region 5, the second conductive contact region 6 and the second conductive gate body region 7. A gate-source composite structure is disposed on the side of the first conductivity type conductive region 5 away from the substrate 2; Drain metal layer 1 is disposed on the back side of substrate 2.

[0027] Specifically, such as Figure 1As shown, the semiconductor field-effect transistor includes a substrate 2, which has a front side and a back side disposed opposite to each other. An epitaxial layer is disposed on the front side of the substrate 2. A first conductivity type conductive region 5 is disposed on the side of the epitaxial layer away from the substrate 2. Two second conductivity type contact regions 6 are respectively disposed on both sides of the first conductivity type conductive region 5, and each second conductivity type contact region 6 is also located on the side of the epitaxial layer away from the substrate 2. Each second conductivity type gate body region 7 is disposed on the side of the second conductivity type contact region 6 away from the substrate 2. A first conductivity type contact region 8 is disposed on the side of the second conductivity type contact region 6 away from the substrate 2, and the surface of the first conductivity type contact region 8 away from the substrate 2 has the same height as the surface of the first conductivity type conductive region 5 away from the substrate 2, the surface of the second conductivity type contact region 6 away from the substrate 2, and the surface of the second conductivity type gate body region 7. A gate-source composite structure is disposed on the side of the first conductivity type conductive region 5 away from the substrate 2, and a drain metal layer 1 is disposed on the back side of the substrate 2. The increased concentration of the P-type well region of the field-effect transistor due to the second conductivity type contact region 6 extends the device's short-circuit withstand time.

[0028] In one embodiment, a portion of the first conductivity type conductive region 5 is located between the second conductivity type contact regions 6 and a portion is located between the second conductivity type gate body regions 7 in the horizontal direction; the first conductivity type contact region 8 is located between the second conductivity type contact regions 6 and the second conductivity type gate body regions 7 in the horizontal direction, which is parallel to the substrate 2.

[0029] For example, such as Figure 1 As shown, the first conductivity type conductive region 5 is located between two second conductivity type contact regions 6 and between two second conductivity type gate body regions 7 in a direction parallel to the substrate 2; the first conductivity type contact region 8 is located between the second conductivity type contact region 6 and the second conductivity type gate body region 7 in a direction parallel to the substrate 2.

[0030] In one embodiment, the epitaxial layer includes: a first conductivity type buffer layer 3 disposed on the front side of the substrate 2; and a first conductivity type drift region 4 disposed on the side of the first conductivity type buffer layer 3 opposite to the substrate 2.

[0031] For example, such as Figure 1 As shown, the epitaxial layer includes a first conductivity type buffer layer 3 and a first conductivity type drift region 4. The first conductivity type buffer layer 3 is located on the front side of the substrate 2, and the first conductivity type drift region 4 is disposed on the side of the first conductivity type buffer layer 3 away from the substrate 2.

[0032] In one embodiment, the gate-source composite structure includes: an oxide layer 9 disposed on the side of the first conductivity type conductive region 5 away from the substrate 2, and the oxide layer 9 covers the first conductivity type conductive region 5, the second conductivity type gate body region 7, and a portion of the first conductivity type contact region 8; a first conductivity type gate polysilicon layer 10 disposed on the side of the oxide layer 9 away from the substrate 2, and encapsulated by the oxide layer 9; and a source metal layer 11 disposed on the side of the second conductivity type contact region 6 away from the substrate 2, and the source metal layer 11 covers a portion of the second conductivity type contact region 6, a portion of the first conductivity type contact region 8, and the oxide layer 9.

[0033] For example, such as Figure 1 As shown, the gate-source composite structure includes an oxide layer 9, a first conductivity type gate polysilicon layer 10, and a source metal layer 11. The oxide layer 9 is disposed on the side of the first conductivity type conductive region 5 away from the substrate 2, and the oxide layer 9 covers the entire first conductivity type conductive region 5, the two second conductivity type gate body regions 7, and part of the first conductivity type contact region 8. The first conductivity type gate polysilicon layer 10 is disposed on the side of the oxide layer 9 away from the substrate 2, and the first conductivity type gate polysilicon layer 10 is surrounded by the oxide layer 9. The source metal layer 11 is disposed on the side of the second conductivity type contact region 6 away from the substrate 2, and the source metal layer 11 covers part of the second conductivity type contact region 6, part of the first conductivity type contact region 8, and part of the oxide layer 9.

[0034] In this design, substrate 2 is of the first conductivity type, and substrate 2, second conductivity type contact region 6, first conductivity type contact region 8, and first conductivity type gate polysilicon layer 10 are heavily doped, while first conductivity type drift region 4 is lightly doped. The main body material of the field-effect transistor is made of silicon carbide.

[0035] It should be noted that the thickness of the first conductivity type drift region 4 ranges from 5 μm to 10 μm, and the thickness of the oxide layer 9 that wraps the first conductivity type gate polysilicon layer 10 ranges from 30 nm to 80 nm.

[0036] In one embodiment, the bandgap width of the second conductivity type contact region 6 is smaller than the bandgap width of the first conductivity type conductive region 5 and the bandgap width of the first conductivity type contact region 8. Specifically, the second conductivity type contact region 6 uses a newly defined material, which can be named K material, such as... Figure 2 As shown, the band gap Eg of material K is x eV, in electron volts (eV), and the band gap Eg of silicon carbide is 3.26 eV, in electron volts (eV). ΔEv = (3.26 - x) eV. The band gap difference between the two materials is that the band gap Eg of material K is smaller than that of silicon carbide. Figure 2In this context, Ec represents the rewind, Ef represents the Fermi level, and Ev represents the valence band. For example, the band gap width Eg of the second conductivity type contact region 6 is smaller than the band gap width Eg of the first conductivity type conduction region 5 and the band gap width Eg of the first conductivity type contact region 8.

[0037] In one embodiment, the second conductivity type contact region 6 and the first conductivity type conductive region 5 constitute a heterojunction diode, and the second conductivity type contact region 6 and the first conductivity type drift region 4 constitute a heterojunction diode. Specifically, as shown... Figure 1 As shown, the second conductivity type contact region 6 of material K contacts the first conductivity type conduction region 5 to form a heterojunction diode, and the second conductivity type contact region 6 of material K contacts the first conductivity type drift region 4 to form a heterojunction diode.

[0038] In one embodiment, during the reverse conduction of the field-effect transistor, the heterojunction diode forms a hole barrier. Specifically, during the reverse conduction of the field-effect transistor, the heterojunction formed by the second conductivity type contact region 6, the first conductivity type conduction region 5, and the first conductivity type drift region 4 has a large hole barrier, effectively suppressing minority carrier injection and reducing reverse recovery loss.

[0039] In one embodiment, when a short circuit occurs in the field-effect transistor, the electronic pathway of the second conductivity type gate body region 7 is compressed based on the second conductivity type contact region 6 to reduce the saturation current under short-circuit conditions. Specifically, when a short circuit occurs in the field-effect transistor, because the second conductivity type contact region 6 of the K material has a higher doping concentration, the electronic pathway of the second conductivity type gate body region 7 can be compressed, reducing the saturation current under short-circuit conditions and extending the short-circuit withstand time of the device without affecting forward conduction.

[0040] In one embodiment, the doping concentration of the second conductivity type contact region 6 ranges from 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 .

[0041] For example, the doping concentration of the first conductivity type drift region 4 ranges from 2 × 10⁻⁶. 16 cm -3 Up to 5×10 16 cm -3 The doping concentration of the first conductivity type buffer layer 3 ranges from 5 × 10⁻⁶. 17 cm -3 Up to 2×10 18 cm -3 The doping concentration of the second conductivity type contact region 6 ranges from 1×10⁶. 19 cm-3 Up to 1×10 20 cm -3 .

[0042] This invention provides a short-circuit resistant semiconductor field-effect transistor (FET). The FET includes a second conductivity type contact region that contacts a first conductivity type drift region and a first conductivity type conduction region. The second conductivity type contact region is made of a novel material and forms a heterojunction diode on different surfaces. When the FET is reverse-biased, the heterojunction has a hole barrier, suppressing minority carrier injection and reducing reverse recovery losses. When a short circuit occurs, the high doping concentration of the second conductivity type contact region reduces the saturation current under short-circuit conditions, does not affect forward conduction, and extends the short-circuit time of the device. Compared to existing silicon carbide power metal-oxide-semiconductor (MOS) FETs, the short-circuit resistant semiconductor FET provided by this invention has a longer short-circuit withstand time without degrading other operating characteristics of the device, thus exhibiting good reliability under short-circuit conditions.

[0043] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A short-circuit resistant semiconductor field-effect transistor, characterized in that, include: A substrate, comprising a front side and a back side disposed opposite to each other; An epitaxial layer disposed on the front side of the substrate; A first conductivity type conductive region is disposed on the side of the epitaxial layer away from the substrate; The second conductivity type contact region is disposed on both sides of the first conductivity type conductive region and located on the side of the epitaxial layer away from the substrate; A second conductivity type gate body region is disposed on the side of the second conductivity type contact region away from the substrate; A first conductive type contact region is disposed on the side of the second conductive type contact region away from the substrate, and the upper surface of the first conductive type contact region is flush with the upper surfaces of the first conductive type conductive region, the second conductive type contact region and the second conductive type gate body region. A gate-source composite structure is disposed on the side of the first conductivity type conductive region away from the substrate; A drain metal layer is disposed on the back side of the substrate.

2. The short-circuit resistant semiconductor field-effect transistor according to claim 1, characterized in that, The first conductive type conductive region is located in the horizontal direction, with a portion between the second conductive type contact regions and a portion between the second conductive type gate body regions; the first conductive type contact region is located in the horizontal direction between the second conductive type contact regions and the second conductive type gate body regions, and the horizontal direction is parallel to the substrate.

3. The short-circuit resistant semiconductor field-effect transistor according to claim 1, characterized in that, The epitaxial layer includes: A first conductivity type buffer layer is disposed on the front side of the substrate; A first conductivity type drift region is disposed on the side of the first conductivity type buffer layer away from the substrate.

4. The short-circuit resistant semiconductor field-effect transistor according to claim 3, characterized in that, The band gap width of the second conductivity type contact region is smaller than the band gap width of the first conductivity type conductive region and the band gap width of the first conductivity type contact region.

5. The short-circuit resistant semiconductor field-effect transistor according to claim 1, characterized in that, The gate-source composite structure includes: An oxide layer is disposed on the side of the first conductivity type conductive region away from the substrate, and the oxide layer covers the first conductivity type conductive region, the second conductivity type gate body region, and a portion of the first conductivity type contact region. A first conductivity type gate polysilicon layer is disposed on the side of the oxide layer away from the substrate and is encapsulated by the oxide layer; A source metal layer is disposed on the side of the second conductivity type contact region away from the substrate, and the source metal layer covers a portion of the second conductivity type contact region, a portion of the first conductivity type contact region, and the oxide layer.

6. The short-circuit resistant semiconductor field-effect transistor according to claim 4, characterized in that, The second conductivity type contact region and the first conductivity type conduction region constitute a heterojunction diode, and the second conductivity type contact region and the first conductivity type drift region constitute the heterojunction diode.

7. The short-circuit resistant semiconductor field-effect transistor according to claim 6, characterized in that, During the reverse conduction process of the field-effect transistor, the heterojunction diode forms a hole barrier.

8. The short-circuit resistant semiconductor field-effect transistor according to claim 4, characterized in that, When the field-effect transistor is short-circuited, the electronic path of the second conductivity type gate body region is compressed based on the second conductivity type contact region to reduce the saturation current under short-circuit conditions.

9. The short-circuit resistant semiconductor field-effect transistor according to claim 4, characterized in that, The doping concentration range of the second conductivity type contact region is 1×10. 19 cm -3 Up to 1×10 20 cm -3 .

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