LDMOS transistor in semiconductor fin

Abstract

A transistor, such as an LDMOS transistor, includes a drift region in a semiconductor fin in a carrier path between a channel region and a drain region. The transistor includes two gate dielectric structures covering different locations of the semiconductor fin. A thinner gate dielectric structure covers a portion of the channel region directly below a gate of the transistor. A thicker dielectric structure covers a portion of the drift region located directly below the gate. And a transition region between the channel region and the drift region in the semiconductor fin is located right below the gate.

Description

Technical Field

[0001] This invention generally relates to transistors having drift regions in semiconductor fins. Background Technology

[0002] LDMOS (Laterally Diffused Metal-Oxide-Semiconductor) transistors are field-effect transistors (FETs) that include a source region, a drain region, a channel region, a gate region, and a drift region. The drift region is located in the carrier path (e.g., holes, electrons) between the channel and drain regions to provide a higher breakdown voltage for the FET than a FET without a drift region. The drift region belongs to the same net conductivity doping type as the source and drain regions. Summary of the Invention

[0003] In one embodiment, a transistor includes: a drain region of a first net conductivity doping type; a source region of a first net conductivity doping type; a channel region located in a semiconductor fin in a carrier path between the drain region and the source region, the channel region being of a second net conductivity doping type opposite to the first net conductivity doping type; a drift region located in the semiconductor fin of a first net conductivity doping type, the drift region being located in the carrier path between the channel region and the drain region; and a gate located directly above a first portion of the semiconductor fin and directly transverse to the first portion of the semiconductor fin. A first gate dielectric structure of a first thickness, comprising a portion of a relative sidewall located directly above and transversely to the first portion of a channel region, the first portion of the channel region being located directly below the gate within a first portion of a semiconductor fin; a second gate dielectric structure of a second thickness, comprising a portion of a relative sidewall located directly above and transversely to the first portion of a drift region, the first portion of the drift region being located directly below the gate within a first portion of a semiconductor fin, the second thickness being a thickness designed to be greater than the first thickness.

[0004] In another embodiment, the semiconductor fin includes a transition region between the channel region and the drift region, and the second gate dielectric structure is located directly above the transition region and directly transverse to the opposite side of the transition region.

[0005] In another embodiment, the field plate and the gate are not physically adjacent, the field plate being located above the second portion of the semiconductor fin and directly transverse to the opposite sidewall of the second portion of the semiconductor fin, wherein the second gate dielectric structure is located directly between the second portion of the semiconductor fin and the field plate.

[0006] In another embodiment, the field plate is characterized as a metal field plate.

[0007] In another embodiment, the first gate dielectric structure includes a high-k dielectric material.

[0008] In another embodiment, the first gate dielectric structure and the second gate dielectric structure each comprise an oxide of the semiconductor material of the semiconductor fin.

[0009] In another embodiment, the drain region and the source region each include epitaxially grown semiconductor material, said epitaxially grown semiconductor material including at least a portion located in a semiconductor fin.

[0010] In another embodiment, the gate is characterized as a metal gate.

[0011] In another embodiment, a semiconductor fin is located on an integrated circuit; the integrated circuit includes a second semiconductor fin, the semiconductor fin and the second semiconductor fin each extending substantially parallel to each other in a first lateral direction; a gate is located directly above a first portion of the second semiconductor fin and directly lateral to the opposite sidewall of the first portion of the second semiconductor fin, the first portion of the second semiconductor fin including a second channel region and a portion of a second drift region.

[0012] In another embodiment, the second gate dielectric structure includes a portion located directly above and transverse to the opposite sidewall of the second portion of the channel region, the gate being located directly above the second portion of the channel region.

[0013] In another embodiment, a method includes forming a channel region and a drift region in a semiconductor fin, the channel region and the drift region being located in a carrier path between a source region and a drain region, the channel region being located in a carrier path between the source region and the drift region, the drift region being located in a carrier path between the channel region and the drain region, the drift region, the drain region and the source region being of a first net conductivity dopant type, and the channel region being of a second net conductivity dopant type opposite to the first net conductivity dopant type; a relative [missing information - likely a typo, should be inserted here] directly above and directly transverse to the first portion of the channel region. A first gate dielectric structure is formed on the sidewalls; a second gate dielectric structure is formed on the opposite sidewall directly above and transverse to the drift region, the thickness of the second gate dielectric structure being designed to be greater than the thickness of the first gate dielectric structure; a gate is formed directly above the first portion of the first gate dielectric structure and transverse to the sidewall of the first portion of the first gate dielectric structure and directly above the first portion of the second gate dielectric structure and transverse to the sidewall of the first portion of the second gate dielectric structure, wherein the gate is located directly above the first portion of the drift region.

[0014] In another embodiment, forming the second gate dielectric structure includes forming the second gate dielectric structure directly above and transverse to the opposite sidewall of the second portion of the channel region, wherein the gate is located directly above the second portion of the channel region.

[0015] In another embodiment, the semiconductor fin includes a transition region between the channel region and the drift region, the transition region being located directly below the second gate dielectric structure.

[0016] Another embodiment includes forming a field plate directly above and transversely to the opposite sidewall of the second portion of the second gate dielectric structure, wherein the second portion of the second gate dielectric structure is located directly above and transversely to the opposite sidewall of the second portion of the drift region.

[0017] In another embodiment, the first gate dielectric structure includes a high-k dielectric material.

[0018] In another embodiment, forming the first gate dielectric structure includes oxidizing the material at the location of the semiconductor fin in the first portion of the channel region.

[0019] In another embodiment, forming the second gate dielectric structure includes oxidizing the material of the semiconductor fins at the location of the drift region.

[0020] In another embodiment, forming the drain region includes removing material from the semiconductor fin at the location of the drain region and epitaxially growing semiconductor material on the semiconductor fin at the location of the drain region; forming the source region includes removing material from the semiconductor fin at the location of the source region and epitaxially growing semiconductor material on the semiconductor fin at the location of the source region.

[0021] In another embodiment, semiconductor fins are located on a wafer, wherein the wafer includes a second semiconductor fin, the semiconductor fin and the second semiconductor fin each extending substantially parallel to each other in a first lateral direction; forming a gate includes forming a gate directly above a second channel region located in the second semiconductor fin and directly above a first portion of a second drift region located in the second semiconductor fin; a third gate dielectric structure is formed directly above the first portion of the second channel region and directly lateral to the opposite sidewall of the first portion of the second channel region; a fourth gate dielectric structure is formed directly above the second drift region and directly lateral to the opposite sidewall of the second drift region, the thickness of the fourth gate dielectric structure being designed to be greater than the thickness of the third gate dielectric structure; the gate is located directly above a portion of the third gate dielectric structure and a portion of the fourth gate dielectric structure; the method further includes sharding the wafer into a plurality of integrated circuits, wherein the integrated circuits include semiconductor fins and second semiconductor fins.

[0022] In another embodiment, forming the gate includes: forming a sacrificial polysilicon gate; removing the sacrificial polysilicon gate; and forming a metal gate in the location of the removed polysilicon gate. Attached Figure Description

[0023] The invention will be better understood by referring to the accompanying drawings, and many of its objectives, features and advantages will become apparent to those skilled in the art.

[0024] Figure 1 A 3D view of a transistor according to at least one embodiment of the present invention.

[0025] Figure 2 This is a partial top view of a wafer during the manufacturing stage according to at least one embodiment of the present invention.

[0026] Figures 3-16 Partial cross-sectional side views at different locations on a semiconductor wafer during the manufacturing stage according to at least one embodiment of the present invention are provided.

[0027] Unless otherwise specified, the same reference numerals are used in different figures to indicate the same items. The figures are not necessarily drawn to scale. Detailed Implementation

[0028] The following is a detailed description of at least one mode for carrying out the invention. This description is intended to illustrate the invention and should not be considered limiting.

[0029] As disclosed herein, transistors such as LDMOS transistors include a drift region in a semiconductor fin located in the carrier path between the channel region and the drain region. The transistor includes two gate dielectric structures covering different locations on the semiconductor fin. A thinner gate dielectric structure covers a portion of the channel region directly below the gate of the transistor. A thicker dielectric structure covers a portion of the drift region located directly below the gate. A transition region in the semiconductor fin between the channel region and the drift region is located directly below the gate.

[0030] In one embodiment, providing a gate structure directly above both the drift region and the channel region in the semiconductor fin can improve the performance of LDMOS transistors implemented in a FinFET CMOS process. This is achieved by covering the portion of the drift region directly below the gate with a thicker gate dielectric, while the portion of the channel region directly below the gate is covered with a thinner gate dielectric. Due to the shorter channel length and lower parasitic capacitance, such transistors can exhibit good radio frequency (RF) performance with a higher cutoff frequency (Ft) without compromising reliability and breakdown voltage.

[0031] Figure 1 This is a 3D view of an LDMOS transistor 101 implemented in a semiconductor fin according to at least one embodiment of the present invention. In some embodiments, the transistor 101 is implemented in an integrated circuit (…). Figure 1(Not shown in the image). An integrated circuit may include multiple FinFET transistors in multiple semiconductor fins of the integrated circuit. Currently, FinFETs are used to fabricate integrated circuits at state-of-the-art semiconductor manufacturing nodes. In some embodiments, the processes described herein can be used to fabricate LDMOS transistors in integrated circuits with other FinFETs at these advanced nodes, thereby allowing LDMOS transistors to be implemented in integrated circuits with state-of-the-art technology.

[0032] Transistor 101 includes a source contact 105, a gate 103, a field plate 111, and a drain contact 113. Dielectric spacers 125 are located on both sides of the gate 103 and the field plate 111. Transistor 101 includes components located on semiconductor fins (…). Figure 1 The carrier path (not shown) extends laterally in the location covered by source contact 105, gate 103, field plate 111, and drain contact 113. When in a conductive state, the carrier path transports carriers (e.g., holes in P-type devices, electrons in N-type devices) from the source region (covered by source contact 105), through the channel region (covered by gate 103), through the drift region (covered by thick gate dielectric 109 and field plate 111), to the drain region (covered by drain contact 113). Figure 1 In the semiconductor fin, a thin gate dielectric 107 is covered at some locations covered by the gate 103, and a thick gate dielectric 109 is covered at other locations covered by the gate 103, at locations covered by the field plate 111, and at locations between the gate 103 and the field plate 111.

[0033] The portion of the semiconductor fin covered by source contact 105 and N+ source region 115, and the portion of the semiconductor fin covered by drain contact 113 and N+ drain region 121, each have a relatively high net N-type conductive doping concentration of N-type dopant (e.g., arsenic, phosphorus). In one embodiment, the net N-type doping concentration of these regions is 5e19 to 1e21 / cm². 3 However, in other embodiments, the concentration may be different.

[0034] P-well 117 and N-well 119 are located above the base P-substrate region 123. The portion of P-well 117 between the source contact 105 and the portion of the semiconductor fin directly below N-well 119, and the portion of the semiconductor fin directly above P-well 117, each have net P-type conductive doping (e.g., boron). In some embodiments, the doping concentration of the aforementioned portions of P-well 117 and the fin is 1-10e¹⁷ / cm². 3 Within the range, but may be other concentrations in other embodiments. A portion of the semiconductor fin covered by gate 103 with a net P-type doping concentration serves as the channel region of transistor 101.

[0035] The N-well 119 and the portion of the semiconductor fin directly above the N-well 119 each have a density of 1-10e17 / cm. 3 The net N-type doping concentration is specified, but may have other concentrations in other embodiments. This doping concentration is less than the doping concentrations of the source and drain regions. This portion of the semiconductor fin with N-type doping concentration located between the P-type channel region and the drain region acts as the drift region of transistor 101.

[0036] In some embodiments, providing a drift region including a portion directly below the gate increases transistor reliability (due to electric field modulation by the field plate) and reduces transistor overlap capacitance (due to the separation of the thicker gate dielectric and the capacitance contribution from the field plate to the gate). In some embodiments, the implementation of a separate field plate 111 helps to modulate the electric field to make it more uniform by reducing the peak field, or to diffuse the field into a deeper region away from the surface, which improves reliability. Since the field plate is separated from the gate, it does not contribute to the total gate capacitance of the device, which helps to reduce capacitance. Furthermore, in this region, using a thicker gate oxide instead of a thinner oxide can help to further reduce the overlap capacitance between the drain and the channel.

[0037] Figure 2 This is a partial top view of a semiconductor wafer 201 on which an LDMOS transistor will subsequently be formed, according to at least one embodiment of the present invention. In some embodiments, the wafer 201 includes a substrate 202 made of one or more semiconductor materials, such as single-crystal silicon, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, or other III-V semiconductor materials. In one embodiment, the substrate 202 has a bulk-semiconductor configuration. In other embodiments, the substrate 202 may have a semiconductor-on-insulator (SOI) configuration. In some embodiments, the substrate 202 is formed from a single portion of a monolithically grown semiconductor material. In other embodiments, a portion of the substrate 202 may include epitaxially grown semiconductor material. The substrate 202 may also include a dielectric structure (e.g., a shallow trench isolation structure, a buried oxide layer (not shown)).

[0038] Figure 2 The substrate 202 is shown after the formation of the P-well 212 and the N-type well 214. In one embodiment, this is achieved by using an energy of 40-500 keV and 2e12-3e13 / cm². 2 P-well 212 is formed by implanting a p-type dopant (e.g., boron) into substrate 202 at a concentration of 50-700 keV. 2An N-type dopant (e.g., arsenic, phosphorus) is implanted into substrate 202 at a certain concentration to form an N-well 214. However, in other embodiments, these implantation operations may be performed with other energies and / or other concentrations.

[0039] Figure 2 This shows the locations of subsequent structures to be formed on wafer 201. Location 207 is where the gate will subsequently be formed, and location 209 is where the field plate will subsequently be formed. See also Figure 15 The gate 1501 and field plate 1503 are in the middle. Figure 2 The locations where fins 215-219 will be formed in substrate 202 are also shown, wherein fins 216-218 are as follows: Figure 3 As shown in the image. Figure 2 It also shows that some of the subsequently formed fins (215, 217, and 219) will be formed by a thin gate dielectric structure ( Figure 10 The regions 205 covered by layers 901 and 1001 and some of the subsequently formed fins have thick gate dielectric structures. Figure 10 Region 205 of layers 701 and 1001.

[0040] Figure 2 Show Figures 3-16 The positions of the three partial cross-sectional views shown are as follows. Cross-sectional view A-A' is positioned along the subsequently formed fin 217. Cross-sectional view B-B' is located at position 207, orthogonal to cross-sectional view A-A', and cross-sectional view C-C' is located at position 209, orthogonal to cross-sectional view A-A'.

[0041] Figure 3 The chip 201 is shown in Figure 2 A cross-sectional view during the wafer manufacturing process following the previous stage. (See also...) Figure 3 As shown, a pad oxide layer 305, a low-stress nitride layer 303, and a patterned etch mask 301 are formed on wafer 201. In some embodiments, layer 305 has a thickness of 10 nm and layer 303 has a thickness of 400 nm, but in other embodiments, these layers may have other thicknesses. The patterned etch mask 301 is patterned by a photolithography process and is used to form semiconductor fins (216-218) in substrate 202. In one embodiment, the fins are formed by anisotropic etching of layers 303 and 305 and timing anisotropic etching of substrate 202, wherein the amount of time defines the depth of etching. Figure 3 As shown, fins 216-218 have net P-type conductive doping in cross section B-B' and net N-type conductive doping in cross section C-C'.

[0042] Figure 4The diagram shows a cross-sectional view of wafer 201 during a subsequent stage of its fabrication, where etch mask 301 has been removed and a second etch mask 401 has been formed by a photolithography process. Mask 401 is used to remove fins 216 and 218, leaving fin 217. In one embodiment, fins 216 and 218 are removed by an isotropic etching process. In other embodiments, fins 216 and 218 will not be formed by etching substrate 202 using mask 301 (see [link to documentation]). Figure 3 In such embodiments, etch mask 401 will not be required.

[0043] Figure 5 A cross-sectional view of wafer 201 is shown during a subsequent stage of its fabrication, where mask 401 is removed from wafer 201. A small oxide layer is grown on the exposed semiconductor surface to remove etch-damaged silicon (or, in other embodiments, other semiconductor material). An oxide layer 501 is then deposited on wafer 201. Subsequently, a nitride layer 303 is used as a stop layer to planarize wafer 201 (e.g., using a CMP process).

[0044] Figure 6 The diagram shows a cross-sectional view of wafer 201 during a later stage of its fabrication, wherein oxide layer 501 is subjected to timed etching to remove a portion of oxide layer 501, thereby exposing a portion of fin 217. Subsequently, nitride layers 303 and 305 are removed by etching using appropriate etch chemicals.

[0045] Figure 7 The diagram shows a cross-sectional view of wafer 201 during a later stage of its fabrication, where an oxide layer 701 is thermally grown on an exposed silicon surface. In one embodiment, layer 701 has a thickness in the range of 2-8 nm, but may have other thicknesses in other embodiments. Prior to forming layer 701, the exposed semiconductor surface of substrate 202 undergoes a pre-cleaning process. Layer 701 will serve as a portion of the thicker gate dielectric for the subsequently formed LDMOS transistor.

[0046] Figure 8 The diagram shows a cross-sectional view of wafer 201 during a later stage of its fabrication, where oxide layer 701 has been selectively removed from portions of fin 217 (see [link]). Figure 2 Region 203), in which a thinner gate dielectric will subsequently be formed, including over the subsequently formed channel region. A patterned etch mask 801 defines portions of layer 701 that are selectively removed.

[0047] Figure 9The diagram shows a cross-sectional view of wafer 201 during a subsequent stage of its fabrication, wherein wafer 201 undergoes another oxidation process to form a thinner oxide layer 901 (e.g., silicon oxide) on the exposed portion of the P-well 212 in region 203 of wafer 201 (see [link]). Figure 2 The oxide layer 901 is thinner than the oxide layer 701, such that the gate dielectric including the oxide layer 901 will be thinner than the gate dielectric including the oxide layer 701. In one embodiment, layer 901 has a thinner profile than the oxide layer 701. The thickness is within the range, but may have other thicknesses in other embodiments. Prior to the oxidation process, wafer 201 undergoes a pre-cleaning process.

[0048] like Figure 9 As shown, the transition region 905 between the P-well 212 and N-well 214 of fin 216 is covered by a thicker gate dielectric (including layer 701) rather than a thinner gate dielectric (including layer 901). In some embodiments, covering the transition region with a thicker gate dielectric allows the region to withstand a higher electric field. Therefore, this feature can provide a more reliable transistor that exhibits a higher breakdown voltage at the transition region subjected to a higher electric field during operation.

[0049] Figure 10 A cross-sectional view of wafer 201 is shown during a subsequent stage of its fabrication, where additional layers are formed on wafer 201. Figure 9 Following this stage, a high-k dielectric layer 1001 is deposited on wafer 201. In one embodiment, layer 1001 is made of hafnium dioxide and has a thickness of 1.5-7 nm, but in other embodiments it may be made of other high-k dielectric materials and / or have other thicknesses.

[0050] In the illustrated embodiment, the thin oxide layer 901 and the high-k dielectric layer 1001 form a thin gate dielectric for a subsequently formed transistor, while the thick oxide layer 701 and the high-k dielectric layer 1001 form a thicker gate dielectric layer for a subsequently formed transistor. However, the gate dielectric may also have other dielectric layers. In some embodiments, the high-k dielectric layer is not formed over layer 701.

[0051] A barrier metal layer 1003 is then formed over the wafer 201. In one embodiment, layer 1003 is made of titanium nitride and has a thickness of 2-10 nm, but in other embodiments it may be made of other materials and / or have other thicknesses. Some embodiments may not include a barrier metal layer.

[0052] A polysilicon layer 1007 is formed on wafer 201, followed by a low-stress nitride layer 1009. In some embodiments, layer 1007 has a thickness in the range of 80-120 nm, but in other embodiments it may have other thicknesses. Figure 10 After the phase, the wafer 201 is planarized.

[0053] Figure 11 The diagram shows a cross-sectional view of wafer 201 during a later stage of its fabrication, where openings 1103, 1105, and 1107 are formed in layers 1009, 1007, and 1003 to expose a high-k dielectric layer 1001. The openings are formed by etching layers 1009, 1007, and 1003 via an etch mask 1101 patterned by a photolithography process.

[0054] Figure 12 A cross-sectional view of wafer 201 is shown during a subsequent stage of its fabrication, in which spacers 1201 and N+ regions 1203 and 1205 are formed. Figure 11 Following the initial stage, spacers 1201 are formed in openings 1103, 1105, and 1107. In some embodiments, spacers 1201 are formed by forming a nitride thin layer over wafer 201 followed by an oxide layer. The oxide and nitride layers are then isotropically etched to form spacers 1201. In one embodiment, the nitride layer has a thickness of 1-9 nm, and the oxide layer has a thickness of 2-10 nm, but in other embodiments, these layers may have other thicknesses. After forming spacers 1103, 1105, and 1107, a nitride thin layer 1206 is formed over wafer 201, followed by an oxide thin layer 1207.

[0055] N+ regions 1205 and 1203 are formed in fin 217 through openings 1103 and 1107, respectively. In one embodiment, regions 1205 and 1203 comprise a larger extended region with a lower concentration of N-type dopant and a smaller contact region with a higher concentration of N-type dopant. In some embodiments, the energy is 0.5-10 keV and the flow rate is 1e14-1e15 / cm. 2 Dopant was injected into the extended region at a concentration of 3-40 keV and with an energy of 1e15-3e15 / cm. 2The concentration of dopant implanted into the contact regions is [not specified], but in other embodiments, these regions may be implanted with other energies and / or other concentrations. In some embodiments, regions 1203 and 1205 are formed with at least one mask (not shown). In some embodiments, regions 1205 and 1203 do not include extension regions. Similarly, in some embodiments, extension regions may be implanted before the formation of spacer 1201. In some embodiments where P-type LDMOS transistors are formed on wafer 201, P+ contact regions (not shown) similar to regions 1205 and 1203 may be formed in fins in other regions of wafer 201 by a similar ion implantation operation, wherein P-type dopant is implanted instead of N-type dopant.

[0056] Figure 13 This shows a cross-sectional view of wafer 201 after N+ epitaxial regions 1303 and 1304 have been formed on wafer 201. Regions 1303 and 1304 are formed by etching a portion of regions 1205 and 1203 of fin 217 through a mask (not shown) to create openings at those locations in fin 217. Subsequently, N-type epitaxial silicon (regions 1303 and 1304) grows in the openings and laterally outside the openings (in... Figure 13 The fins grow inwards and outwards in a cross-sectional view A-A' to increase the area of ​​the N+ region of the fins for the subsequently formed source and drain contacts. In some embodiments, portions of other fins may be removed in a similar manner to increase the size of the P+ contact region of the P-type LDMOS transistor (not shown). The wafer 201 is then annealed to activate the dopant.

[0057] Then a thin metal film (e.g., tungsten, cobalt) is formed on top of wafer 201. Figure 13 (Not shown in the image). The wafer 201 is then heated to form silicides 1307 and 1305 on regions 1303 and 1304, respectively. Unreacted metal is then removed.

[0058] Figure 14 The diagram shows a cross-sectional view of wafer 201 after the interlayer dielectric structure 1402 has been formed in openings 1103, 1105, and 1107, respectively. In some embodiments, the structure 1402 is formed by depositing an interlayer dielectric material layer (e.g., an oxide layer formed by a TEOS process) on wafer 201 and subsequently planarizing wafer 201 to remove portions of the nitride layer 1009, the polysilicon layer 1007, and the interlayer dielectric material.

[0059] Figure 15This is a cross-sectional view of wafer 201 after the remainder of polysilicon layer 1007 has been removed and metal gate 1501 and field plate 1503 have been formed in their positions. In some embodiments, the remainder of polysilicon layer 1007 is removed by etching wafer 201. A work function metal layer 1505 is selectively formed in the region of the N-type device. In one embodiment, layer 1505 may be made of aluminum and have a thickness of 2 nm, but in other embodiments it may be made of other materials and have other thicknesses. Layer 1505 is designed to set the threshold voltage of the N-type transistor. Different layers of work function material (not shown) may be selectively formed over regions of wafer 201 to set the work function of the P-type device.

[0060] Subsequently, a gate metal (e.g., tungsten) layer is formed over wafer 201. A dielectric structure 1402 is used as an etch stop to planarize wafer 201 to form gate 1501 and field plate 1503, both of which include a portion of layer 1505. In other embodiments, the gate and field plate may be polysilicon instead of metal.

[0061] Return to reference Figure 2 Gate 1501 and field plate 1503 are located at positions 207 and 209, respectively. For example... Figure 2 As shown, gate position 207 and field plate position 209 are located in Figure 4 The remaining fins (fins 215, 217, and 219) are above the stage after the previous stage. Therefore, fins 215 and 219 also include source regions, channel regions, drift regions, and drain regions (not shown). In some embodiments, the source regions of each fin are electrically connected together, and the drain regions of each fin are electrically connected together.

[0062] Figure 16 This diagram shows a cross-sectional view of the wafer 201 after the formation of gate contacts 1603 to electrically contact gate 1501, the formation of field contacts 1605 to electrically contact field plate 1503, the formation of source contacts to electrically contact source silicide 1307, and the formation of drain contacts 1607 to electrically contact drain silicide 1305. Each of contacts 1601, 1603, 1605, and 1607 includes a portion of a seed layer 1609. In some embodiments, the contacts are made of a metal such as tungsten, tungsten nitride, or copper, but in other embodiments they may be made of other metals.

[0063] In some embodiments, contacts 1601, 1603, 1605, and 1607 are formed by forming an interlayer dielectric material layer 1611 over wafer 201. In some embodiments, layer 1611 is made of oxide formed by a TEOS process. Openings are formed in layer 1611 (having one or more masks) to expose source silicide 1307, gate 1501, field plate 1503, and drain silicide 1305. After depositing a seed layer 1609, a contact metal layer is formed on wafer 201. Subsequently, wafer 201 is planarized to form individual contacts.

[0064] like Figure 16 As shown, gate 1501 covers the channel region 1621 and a portion of the drift region 1623 of the transistor located in semiconductor fin 217. The channel region 1621 at cross-section B-B' is covered by a thinner gate dielectric (made of layers 901 and 1001). The drift region 1623 at cross-section C-C' is covered by a thicker gate dielectric (made of layers 701 and 1001). As shown, gate 1501 is located directly above the channel region 1621 and a portion of the drift region 1623 and is directly transverse to the opposite sidewalls of these regions.

[0065] like Figure 16 As shown, the N-type LDMOS transistor includes a drain region (which includes regions 1303 and 1205), a channel region 1621 in fin 217, a drift region 1623 in fin 217, a source region (which includes regions 1304 and 1203), a gate 1501, and a field plate 1503. The transistor includes carrier paths from the source region through the channel region 1621, through the drift region 1623, to the drain region.

[0066] exist Figure 16 Following this stage, one or more additional interconnect layers (not shown) are formed over wafer 201, wherein the one or more interconnect layers include conductive interconnects and vias separated by an interlayer dielectric material. The conductive interconnects and vias are electrically connected to means formed in the substrate. Subsequently, external die ends (e.g., bonding pads, pillars, guide pillars) are formed on wafer 201 and electrically connected to the conductive interconnect structure of the interconnect layers. Wafer 201 is then diced into multiple integrated circuits. Each integrated circuit includes one or more transistors as shown and described in the figures above. Some integrated circuits may also include P-type LDMOS transistors. The integrated circuits are then packaged to form a packaged integrated circuit implemented in an electronic system (e.g., TV, computer, mobile phone, appliance, automobile, manufacturing equipment, or communication equipment).

[0067] Although N-type LDMOS is shown as being manufactured by the process described above, P-type transistors with drift regions can be manufactured by a similar process in which the net conductive dopant of the region is exchanged.

[0068] Transistors in other embodiments may have different structures, be made of different materials, and / or be formed using different processes. As explained above, the integrated circuit may include both N-type and P-type transistors. In some embodiments, the transistor will not include a field plate. In some embodiments, the field plate and the gate will be independently biased. In some embodiments, providing an independently biased field plate located directly above a thicker gate dielectric can provide improved reliability without degrading RF performance. In other embodiments, the field plate and the source will be electrically connected together. In some embodiments, the transistor will include a dummy gate.

[0069] In some embodiments, the LDMOS transistor described above can be used in RF power amplifiers. In simulations of some embodiments, such a transistor can have a breakdown voltage greater than 10V and a cutoff frequency (Ft) greater than 40GHz, which can exceed the performance of other existing LDMOS transistor designs implemented in semiconductor fins using FinFET technology. In some embodiments, such a transistor can eliminate the need for a separate cascode device in the power amplifier circuit. Therefore, the circuit may require a 40% reduction in area and deliver 2dB more output power compared to other conventional circuits. In other embodiments, the LDMOS transistor can be used in power converters such as DC-DC power converters.

[0070] In some embodiments, using a thinner gate dielectric to cover at least a portion of the channel region can provide a shorter channel length to improve DC and RF performance, such as providing lower on-resistance and higher cutoff frequency. In some embodiments, providing a thicker gate dielectric over the drift region below the gate can provide improved drain-to-gate breakdown voltage, thereby improving reliability. In some embodiments, providing a separate bias field plate directly above the thicker gate dielectric can provide improved reliability by reducing hot carrier injection without degrading RF performance. Furthermore, covering the channel-drift interface transition region 905 with a thicker gate dielectric can improve hot carrier degradation at this location, thereby improving transistor reliability.

[0071] As disclosed herein, if the first structure is located above the second structure on a line perpendicular to the generally flat main side of the wafer or substrate, then the first structure is "directly above" the second structure. For example, in Figure 16 In this configuration, gate contact 1603 is located directly above P-well 212. Contact 1605 is not directly above P-well 212. As disclosed herein, if the first structure is positioned below the second structure on a line oriented perpendicular to the generally flat main side of the wafer or substrate, then the first structure is "directly beneath" or "directly under" the second structure. For example, in Figure 16 In this configuration, N-well 214 is directly below contact 1607. P-well 212 is not directly below contact 1607. If two other structures are located on opposite sides of a structure along a line, then the first structure is "directly located" "between" the two structures along that line. For example, in... Figure 16 In the middle, contact 1603 is Figure 16 The line in the cross-sectional side view of section A-A' lies directly between contacts 1601 and 1605. N-well 214 does not lie directly between contacts 1603 and 1605 on a single line. If the first and second structures are located on a line having a direction parallel to the generally flat main side of the wafer or substrate, then the first structure is "directly transverse" to the second structure. For example, in... Figure 16 In this configuration, contacts 1601 and 1605 are directly transverse to each other. If two other structures lie on opposite sides of a structure on a line parallel to the generally flat main side of the wafer or substrate, then the structure is "directly transversely located" between the two structures. For example, in... Figure 16 In this configuration, contact 1603 is located directly laterally between contacts 1601 and 1605. If a surface is closer to the top of the active side of the wafer or integrated circuit on a line perpendicular to the generally flat main side of the wafer or integrated circuit, then that surface is at a "higher height" than the other surface. Figure 16 In the view, the active side of chip 201 is Figure 16 The top side of the structure. For example, contact 1603 is at a higher height than field plate 1503. As used herein, a first structure whose thickness is designed to be greater than that of the second structure means that the thickness of the first structure is greater at least in part due to specified manufacturing process parameters and not solely due to unintentional variations in manufacturing parameters.

[0072] Features specifically shown or described relative to one embodiment set forth herein may be implemented in other embodiments set forth herein.

[0073] While specific embodiments of the invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, other changes and modifications may be made without departing from the invention and its broader aspects, and therefore the appended claims are intended to cover all such changes and modifications within the true spirit and scope of the invention.

Claims

1. A transistor, characterized in that, include: The drain region is the first type of net conductive doping. The source region is the first net conductivity doping type; The channel region is located in the carrier path between the drain region and the source region in the semiconductor fin, and the channel region is a second net conductivity doping type opposite to the first net conductivity doping type. The drift region, located in the semiconductor fin, is of the first net conductivity doping type, and the drift region is located in the carrier path between the channel region and the drain region; A gate is located directly above the first portion of the semiconductor fin and is directly transverse to the opposite sidewall of the first portion of the semiconductor fin; A first gate dielectric structure of a first thickness includes portions of opposite sidewalls located directly above and transverse to the first portion of the channel region, wherein the first portion of the channel region is located directly below the gate in the first portion of the semiconductor fin. A second gate dielectric structure of a second thickness includes portions located directly above and transverse to the first portion of the drift region, the first portion of the drift region being located directly below the gate in the first portion of the semiconductor fin, the second thickness being a thickness designed to be greater than the first thickness.

2. The transistor according to claim 1, characterized in that, The semiconductor fin includes a transition region between the channel region and the drift region, and the second gate dielectric structure is located directly above the transition region and directly transverse to the opposite side of the transition region.

3. The transistor according to claim 1, characterized in that, In addition, including: A field plate, which is not physically adjacent to the gate, is located above the second portion of the semiconductor fin and directly transverse to the opposite sidewall of the second portion of the semiconductor fin, wherein the second gate dielectric structure is directly located between the second portion of the semiconductor fin and the field plate.

4. The transistor according to claim 3, characterized in that, The field plate is characterized as a metallic field plate.

5. The transistor according to claim 1, characterized in that, The first gate dielectric structure comprises a high-k dielectric material.

6. The transistor according to claim 1, characterized in that, The first gate dielectric structure and the second gate dielectric structure each comprise an oxide of the semiconductor material of the semiconductor fin.

7. The transistor according to claim 1, characterized in that, The drain region and the source region each include epitaxially grown semiconductor material, and the epitaxially grown semiconductor material includes at least a portion located in the semiconductor fin.

8. The transistor according to claim 1, characterized in that, The gate is characterized as a metal gate.

9. The transistor according to claim 1, characterized in that: The semiconductor fins are located on the integrated circuit; The integrated circuit includes a second semiconductor fin, and the semiconductor fin and the second semiconductor fin each extend substantially parallel to each other in a first lateral direction; The gate is located directly above the first portion of the second semiconductor fin and is transverse to the opposite sidewall of the first portion of the second semiconductor fin. The first portion of the second semiconductor fin includes a second channel region and a portion of a second drift region.

10. A method, characterized in that, include: A channel region and a drift region are formed in a semiconductor fin, the channel region and the drift region being located in the carrier path between the source region and the drain region, the channel region being located in the carrier path between the source region and the drift region, the drift region being located in the carrier path between the channel region and the drain region, the drift region, the drain region and the source region being of a first net conductive dopant type, and the channel region being of a second net conductive dopant type opposite to the first net conductive dopant type; A first gate dielectric structure is formed directly above the first portion of the channel region and transversely to the opposite sidewall of the first portion of the channel region; A second gate dielectric structure is formed directly above the drift region and transversely to the opposite sidewall of the drift region, and the thickness of the second gate dielectric structure is designed to be greater than the thickness of the first gate dielectric structure. A gate is formed directly above the first portion of the first gate dielectric structure and directly transverse to the sidewall of the first portion of the first gate dielectric structure, and directly above the first portion of the second gate dielectric structure and directly transverse to the opposite sidewall of the first portion of the second gate dielectric structure, wherein the gate is located directly above the first portion of the drift region.

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