Preparation method of vertical transistor, vertical transistor and semiconductor device

Abstract

The invention provides a preparation method of a vertical transistor, the vertical transistor and a semiconductor device. The method comprises the following steps: forming a dielectric fork sheet in a semiconductor substrate, the dielectric fork sheet being partially embedded in the semiconductor substrate in the vertical direction; a part of the semiconductor substrate is removed to form a pair of active structures, and the two active structures in the pair of active structures are located on the two sides of the dielectric fork piece in the first horizontal direction respectively and connected with the dielectric fork piece; the vertical direction is perpendicular to the first horizontal direction; respectively forming a gate structure and a top source drain structure corresponding to each active structure based on the pair of active structures; carrying out wafer reversing processing on the semiconductor substrate along the vertical direction, and thinning the semiconductor substrate until the dielectric forked wafer is exposed; removing the semiconductor substrate over the pair of active structures; and based on the pair of active structures, respectively forming a bottom source drain structure corresponding to each active structure. According to the invention, the transistor integration degree can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip manufacturing, and in particular to a method for fabricating a vertical transistor, a vertical transistor, and a semiconductor device. Background Technology

[0002] With Moore's Law continuing to deepen, especially after the gate-all-around (GAA) transistor technology node, exploring new transistor structures and further miniaturizing transistor size are currently hot topics in the industry's research and development.

[0003] Vertical transistors, by changing the current transport channel from parallel to the wafer to perpendicular to the wafer, can realize the transformation of transistor distribution from a two-dimensional plane to a three-dimensional space, reduce the transistor area, help to further improve transistor integration density, and improve circuit performance. They are considered one of the important technologies for continuing the miniaturization of integrated circuits. Summary of the Invention

[0004] This application provides a method for fabricating a vertical transistor, a vertical transistor, and a semiconductor device, which can reduce transistor spacing and further miniaturize integrated circuit dimensions.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a method for fabricating a vertical transistor, comprising: forming a dielectric fork in a semiconductor substrate, wherein the dielectric fork is partially embedded in the semiconductor substrate in a vertical direction; removing a portion of the semiconductor substrate to form a pair of active structures, wherein two active structures in the pair of active structures are respectively located on both sides of the dielectric fork along a first horizontal direction and are in contact with the dielectric fork; the vertical direction is perpendicular to the first horizontal direction; based on the pair of active structures, forming a gate structure and a top source / drain structure corresponding to each active structure; performing a wafer flipping process on the semiconductor substrate in a vertical direction and thinning the semiconductor substrate until the dielectric fork is exposed; removing the semiconductor substrate located above the pair of active structures; and based on the pair of active structures, forming a bottom source / drain structure corresponding to each active structure.

[0007] This application provides a vertical transistor, comprising: a dielectric fork; two transistors located on both sides of the dielectric fork along a first horizontal direction, wherein each transistor includes a top source-drain structure, a gate structure, and a bottom source-drain structure arranged sequentially along a vertical direction; and the active structure of each transistor is connected to the dielectric fork.

[0008] This application provides a semiconductor device, including: a vertical transistor provided in this application.

[0009] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0010] In this embodiment, a dielectric fork is first formed in a semiconductor substrate, partially embedded within the substrate to provide isolation in subsequent processes. Next, a pair of active structures are etched together, and the dielectric fork acts as an isolator to separate the two active structures, thus avoiding the short-circuit risk caused by insufficient spacing in traditional designs. Subsequently, a gate structure and a top source / drain structure are constructed on each active structure. The dielectric fork is then exposed through wafer flipping and thinning processes, and excess substrate material above the active structures is removed, finally forming the bottom source / drain structure and completing the transistor construction. This approach achieves effective isolation between the transistors on both sides through the dielectric fork, eliminating the need for additional transistor spacing or complex isolation structures, thereby increasing integration density. Furthermore, the step-by-step formation of the top and bottom source / drain structures makes the electrical performance of the vertical transistor more stable, which is beneficial for improving the overall device yield and reliability.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0013] Figure 1 This is a vertical transistor structure illustrated according to an exemplary embodiment. Figure 1 ;

[0014] Figure 2 This is a schematic flowchart illustrating a method for fabricating a vertical transistor according to an exemplary embodiment;

[0015] Figure 3 This is a top view schematic of a vertical transistor according to an exemplary embodiment. Figure 1 ;

[0016] Figures 4 to 20 This is a schematic diagram illustrating the fabrication process of a vertical transistor according to an exemplary embodiment;

[0017] Figure 21 This is a schematic diagram of the lead-out structure of an inverter according to an exemplary embodiment. Figure 1 ;

[0018] Figure 22 This is a schematic diagram of the lead-out structure of an inverter according to an exemplary embodiment. Figure 2 ;

[0019] Figure 23 This is a schematic diagram of the lead-out structure of an inverter according to an exemplary embodiment. Figure 3 ;

[0020] Figure 24 This is a schematic diagram of the lead-out structure of an inverter according to an exemplary embodiment. Figure 4 ;

[0021] Figure 25 This is a top view schematic of a vertical transistor according to an exemplary embodiment. Figure 2 ;

[0022] Figure 26 This is a schematic diagram of a vertical transistor structure according to an exemplary embodiment. Figure 2 .

[0023] The reference numerals and names in the figure are as follows:

[0024] 11. Gate structure; 12. Source / drain structure; 121. Top source / drain structure; 122. Bottom source / drain structure; 13. Isolation structure; 14. Dielectric fork; 15. Semiconductor substrate; 16. Hard mask structure; 17. Groove; 18. Initial dielectric fork; 19. Initial gate structure; 20. Active structure; 21. Support structure; 22. Shallow trench isolation structure; 23. Bottom isolation layer; 24. Interlayer dielectric structure; 25. Top isolation layer; 26. Top source / drain metal structure; 27. Gate interconnect structure; 28. Carrier wafer; 29. ​​Bottom source / drain metal structure. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0028] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0029] Figure 1 This is a vertical transistor structure illustrated according to an exemplary embodiment. Figure 1 . Figure 1 (a) shows a top view of the vertical transistor. For ease of understanding, only the gate structure 11 and the source / drain structure 12 are shown in the top view. The AA' section is a cross-section along the width direction (perpendicular to the channel direction) of the vertical transistor; the BB' section is a cross-section along the length direction (perpendicular to the channel direction) of the vertical transistor. Figure 1 (b) shows the vertical transistor along Figure 1 A cross-sectional view of the AA' section. Figure 1 (c) shows the vertical transistor along Figure 1 A cross-sectional view of the BB' section.

[0030] See Figure 1 As shown, a source-drain symmetrical vertical transistor is illustrated. This vertical transistor is fabricated by etching a channel on a silicon substrate and sequentially constructing a gate structure, a top source-drain structure, and a bottom source-drain structure. Due to the isolation requirements between the source-drain structure and the gate structure, at least an isolation structure 13 is formed, resulting in a larger spacing between transistors. This makes it difficult to further reduce the standard cell size, restricting the improvement of integration density and hindering the development of more advanced processes.

[0031] This application provides a method for fabricating a vertical transistor, a vertical transistor, and a semiconductor device, which can reduce transistor spacing and further miniaturize integrated circuit dimensions.

[0032] In a first aspect, embodiments of this application provide a method for fabricating a vertical transistor. Figure 2 This is a schematic flowchart illustrating a method for fabricating a vertical transistor according to an exemplary embodiment, such as... Figure 2 As shown, the fabrication method of the vertical transistor in the embodiments of this application may include steps 201 to 206.

[0033] Step 201: Form a dielectric fork in the semiconductor substrate.

[0034] In some embodiments, the semiconductor substrate may be formed of semiconductor materials such as silicon or germanium. In one embodiment, the semiconductor substrate may be a single-crystal silicon substrate.

[0035] In some embodiments, the dielectric fork can be partially embedded vertically within the semiconductor substrate. Here, partial embedding in the substrate vertically means that the height of the dielectric fork in the vertical direction is greater than the height of the active region in the vertical direction. Thus, the dielectric fork can provide isolation at both the top and bottom of the vertical transistor.

[0036] In some embodiments, the dielectric fork can be an insulating structure. The primary function of the dielectric fork is to isolate the source / drain and gate structures of adjacent transistors in subsequent processes, preventing short circuits or interference between them. In some embodiments, the dielectric fork can be made of insulating materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), or other high-dielectric-constant oxides. In some embodiments, the dielectric fork can be formed by etching a groove into a semiconductor substrate and depositing insulation within the groove. An interlayer dielectric structure is formed on top of the patterned initial gate structure, wherein the height of the interlayer dielectric structure in the vertical direction is the same as the height of the active structure in the vertical direction. The patterned initial gate structure is etched back to obtain a gate structure, wherein the height of the gate structure in the vertical direction is less than the height of the active structure in the vertical direction.

[0037] In some embodiments, gate dielectric material and gate metal material are first deposited sequentially over a bottom isolation layer, a pair of active structures, and dielectric forks to form a continuous initial gate structure. This continuous initial gate structure covers the surface of the bottom isolation layer, the sidewalls and surfaces of the active structures, and the sidewalls and surfaces of the dielectric forks, providing a good foundation for subsequent patterning and etch-back operations. The initial gate structure is then etched using a patterning process. After etching, the coverage of the initial gate structure on the surface of the bottom isolation layer changes from complete coverage to partial coverage, while the coverage of the sidewalls and surfaces of the active structures and the dielectric forks remains unchanged. Here, the patterning process isolates the gate structures between adjacent transistor units. Dielectric material is then deposited and etched back over the patterned initial gate structure to form an interlayer dielectric structure. By precisely controlling the height of the interlayer dielectric structure to match the vertical height of the active structures, it can be ensured that the active structures are not accidentally cut in subsequent processes, and the device performance is not affected. Finally, through a etch-back operation, a portion of the initial gate structure after patterning is removed, resulting in a gate structure with a height lower than the active structure. Here, after etch-back, the gate structure no longer covers the surface of the active structure, the sidewalls and surface of the dielectric fork, and the coverage of the sidewalls of the active structure changes from complete coverage to partial coverage.

[0038] In some embodiments, a back-etch operation can achieve self-aligned isolation of the gate structure, so that the gate structures of the two transistors are no longer connected, but are naturally separated by dielectric forks. Achieving self-aligned isolation of the gate structure through a back-etch operation not only reduces parasitic capacitance, but also improves the switching speed and stability of the device.

[0039] In some embodiments, the height of the gate structure obtained after etch-back is lower than the height of the active structure. In subsequent processes, this height difference allows a top isolation layer to be formed on top of the gate structure.

[0040] In some embodiments, the top isolation layer may be an insulating layer further deposited and etched back above the gate structure, typically the same as or similar to the bottom isolation layer. The top isolation layer isolates the gate structure and the top source / drain structure. In some embodiments, the material selection and deposition method of the top isolation layer may be consistent with the bottom isolation layer to ensure the stability of the overall structure and process compatibility.

[0041] In some embodiments, the formation of the top source / drain structure depends on the physical boundary provided by the top isolation layer. By forming the top source / drain structure above the top isolation layer, good electrical performance can be guaranteed for each transistor.

[0042] In some embodiments, the length of the gate structure along the first horizontal direction is greater than the length of the gate structure along the second horizontal direction; or, the length of the gate structure along the first horizontal direction is less than the length of the gate structure along the second horizontal direction, wherein the second horizontal direction is perpendicular to the vertical direction and the first horizontal direction.

[0043] In some embodiments, the first horizontal direction and the second horizontal direction are two mutually perpendicular horizontal directions that are perpendicular to the vertical direction. For example, in a wafer plane, the first horizontal direction may be the X-axis direction, and the second horizontal direction may be the Y-axis direction, forming an orthogonal coordinate system. In some embodiments, the length of the gate structure along the first horizontal direction refers to the lateral extension dimension of the gate structure in the first horizontal direction, while the length of the gate structure along the second horizontal direction is the lateral extension dimension of the gate structure in the second horizontal direction.

[0044] In some embodiments, by setting the length of the gate structure along the first horizontal direction to be greater than the length along the second horizontal direction, an exit structure (e.g., a gate interconnect structure formed subsequently) of the gate structure can be set in the first horizontal direction, thereby saving chip size in the second horizontal direction and improving device integration.

[0045] In some embodiments, by setting the length of the gate structure along the first horizontal direction to be less than the length along the second horizontal direction, the lead-out structure of the gate structure can be set in the second horizontal direction, thereby saving chip size in the first horizontal direction and improving device integration. In some embodiments, this arrangement allows the active structure and gate structure to be arranged along the second horizontal direction, thereby reducing the distance between the gate structures on both sides of the dielectric fork and further improving the adaptability and scalability of device design.

[0046] In some embodiments, the method of selecting the length ratio of the gate structure along different horizontal directions according to actual needs can achieve better device performance and layout efficiency. This not only reduces interference between adjacent devices but also improves the stability and reliability of the overall circuit, becoming an important means to promote the miniaturization of devices under advanced processes.

[0047] It should be noted that, for ease of explanation, the source / drain structures mentioned in the embodiments of this application are abbreviations, specifically referring to the source structure and / or drain structure. Furthermore, the source / drain metals are similar to the source / drain structures, where "source / drain" is an abbreviation for "source and / or drain".

[0048] Step 204: After bonding the front-side device to the carrier wafer, the semiconductor substrate is flipped in the vertical direction and thinned until the dielectric fork is exposed.

[0049] In some embodiments, after the fabrication of the front-side devices (such as the gate structure and the top source / drain structure) is completed, a carrier wafer can be bonded over the front-side devices. Then, by vertically flipping the semiconductor substrate with the completed front-side devices, the previously upward-facing front side of the semiconductor substrate is turned downwards, and the previously downward-facing back side is turned upwards. The back side of the semiconductor substrate can then be thinned until the bottom of the dielectric fork is exposed.

[0050] In some embodiments, the wafer flipping process typically involves bonding a carrier wafer to the original wafer (i.e., the semiconductor substrate with the front-side device already completed) to prevent wafer breakage or deformation during subsequent fabrication.

[0051] In some embodiments, step 204 may include: depositing an oxide material on the interlayer dielectric structure enclosing the top source / drain structure and the gate structure to form an oxide layer; and then bonding the oxide layer to a carrier wafer. Here, the oxide material may include silicon dioxide, aluminum oxide, hafnium oxide, etc.

[0052] In some embodiments, the thinning process can employ chemical mechanical polishing (CMP) or grinding techniques. In some embodiments, wafer flipping and thinning processes are key steps in realizing double-sided transistor structures, effectively freeing up space on the back side of the wafer to facilitate the subsequent formation of bottom source / drain structures and back metal leads. Wafer flipping and thinning processes also avoid mutual interference between front and back processes, thereby improving the overall device reliability and yield.

[0053] Step 205: Remove the semiconductor substrate located above the pair of active structures.

[0054] In some embodiments, the thickness of the dielectric fork inserted into the semiconductor substrate is greater than the thickness of the active structure. Therefore, removing the substrate material above the active structure after wafer flipping can expose part of the sidewalls of the dielectric fork. Exposing part of the sidewalls of the dielectric fork provides more operating space for the subsequent fabrication of the bottom source / drain structure, facilitating the separation of the bottom source / drain structure by the dielectric fork.

[0055] In some embodiments, a semiconductor substrate located above a pair of active structures is removed by a dry etching or wet etching process.

[0056] In some embodiments, step 205 may include: etching a pair of support structures above a pair of active structures; removing shallow trench isolation structures.

[0057] In some embodiments, an etching operation can remove a pair of support structures above a pair of active structures, thereby freeing up space above the active structures to facilitate the formation of bottom source / drain structures in subsequent processes. In some embodiments, the etching parameters need to be adjusted according to the material properties of the pair of support structures to ensure that only a specified area is removed without affecting other structures.

[0058] In some embodiments, after removing the pair of support structures, the previously formed shallow trench isolation structure can be removed. The removal method can be wet etching or dry etching, depending on the materials and process conditions used. After removing the shallow trench isolation structure, the previously isolated area can be reopened, thereby facilitating the formation of the bottom source / drain structure.

[0059] In some embodiments, after removing a pair of support structures and shallow trench isolation structures, the dielectric fork protrudes from the active structure. Thus, during subsequent fabrication of the bottom source / drain structures, the dielectric fork can naturally isolate the two bottom source / drain structures located on either side of the dielectric fork in the first horizontal direction.

[0060] Step 206: Based on a pair of active structures, form the bottom source-drain structure corresponding to each active structure.

[0061] In some embodiments, after exposing the dielectric fork, a bottom source / drain structure corresponding to each active structure can be formed based on the active structures on both sides of the dielectric fork. In some embodiments, the formation of the bottom source / drain structure can be achieved through epitaxial growth technology.

[0062] In some embodiments, the formation of the bottom source-drain structure is a crucial step in realizing the complete circuit function of the vertical transistor. The bottom source-drain structure, the active structure, and the top source-drain structure together constitute a complete current path. Furthermore, since the bottom source-drain structure is located on the back side of the wafer, it can be directly connected to the back metal leads, thereby further simplifying the interconnect design.

[0063] In some embodiments, by forming a bottom source-drain structure at the bottom of the active structure, and by utilizing the isolation effect of the dielectric fork, electrical isolation between the two bottom source-drain structures is ensured, preventing short circuits or interference.

[0064] In some embodiments, the top source / drain structure, gate structure, and bottom source / drain structure corresponding to each active structure constitute a vertical transistor with a vertical channel design. The channel direction is aligned with the vertical direction, thereby achieving higher integration density and smaller cell area. In some embodiments, by setting dielectric forks, two adjacent vertical transistors in the first horizontal direction are completely separated, ensuring isolation and stability between transistors.

[0065] In some embodiments, the polarities of the two vertical transistors on either side of the dielectric fork can be the same or different. For example, both vertical transistors on either side of the dielectric fork can be N-type transistors. As another example, one of the two vertical transistors on either side of the dielectric fork can be an N-type transistor, and the other can be a P-type transistor. It should be noted that the lithographic windows for the source-drain structures in N-type and P-type transistors are different.

[0066] In some embodiments, based on the type of transistors subsequently fabricated, dielectric forks can be divided into two types: one called an outer wall, used to isolate transistors of the same type; and the other called an inner wall, used to isolate transistors of different types. Both outer wall and inner wall structures can effectively reduce the spacing between transistors and improve integration density.

[0067] In some embodiments, when the two vertical transistors on opposite sides of the dielectric fork have different polarities (e.g., one is an N-type transistor and the other is a P-type transistor), the two vertical transistors can form an inverter structure. In some embodiments, the inverter structure is a basic logic gate circuit used to implement the inversion of input signals. Inverter structures are widely used in digital integrated circuits as a basic module for building more complex logic units.

[0068] In some embodiments, an inverter is formed based on two vertical transistors on both sides of a dielectric fork. The lead-out structure of the inverter may include at least one of the following: forming a gate interconnect structure on the front side of the wafer for connecting the gate structure in the inverter structure; forming a top source drain metal structure on the front side of the wafer for connecting the two top source drain structures in the inverter structure; forming a gate interconnect structure on the back side for connecting the gate structure in the inverter structure; forming a top source drain metal structure on the front side for connecting the two top source drain structures in the inverter structure; providing a gate interconnect structure on the front side for connecting the gate structure in the inverter structure; providing a bottom source drain metal structure on the back side for connecting the two bottom source drain structures in the inverter structure; forming a gate interconnect structure on the back side of the device for connecting the gate structure in the inverter structure; forming a bottom source drain metal structure on the back side of the device for connecting the two bottom source drain structures in the inverter structure.

[0069] In some embodiments, the four interconnect methods provide flexible interconnect path selection to accommodate different wiring requirements and process constraints. The choice between front-side or back-side interconnects depends on factors such as wafer processing sequence, bonding process, and thinning precision.

[0070] In some embodiments, while forming the gate interconnect structure on the front side, the gate interconnect structure also connects the top source-drain metal structures of the two transistors in the inverter structure, thereby facilitating all lead-out operations on the same side and reducing the complexity of cross-layer wiring. Backside interconnects are suitable for wafer structures that have undergone flipping and thinning to the back contact layer, and the backside interconnect structure can optimize subsequent process flows.

[0071] In some embodiments, by providing a variety of interconnection schemes, the embodiments of this application can adapt to different manufacturing processes and circuit design requirements, improve wiring flexibility, reduce parasitic resistance and capacitance, thereby improving overall circuit performance and stability.

[0072] In this embodiment, a dielectric fork is first formed in a semiconductor substrate, partially embedded within the substrate to provide isolation in subsequent processes. Next, a pair of active structures are etched together, and the dielectric fork acts as an isolator to separate the two active structures, thus avoiding the short-circuit risk caused by insufficient spacing in traditional designs. Subsequently, a gate structure and a top source / drain structure are constructed on each active structure. The dielectric fork is then exposed through wafer flipping and thinning processes, and excess substrate material above the active structures is removed, finally forming the bottom source / drain structure and completing the transistor construction. This approach achieves effective isolation between the transistors on both sides through the dielectric fork, eliminating the need for additional transistor spacing or complex isolation structures, thereby increasing integration density. Furthermore, the step-by-step formation of the top and bottom source / drain structures makes the electrical performance of the vertical transistor more stable, which is beneficial for improving the overall device yield and reliability.

[0073] In some embodiments, the method for fabricating a vertical transistor may further include at least one of the following: forming a top source-drain metal structure that connects to the top source-drain structure; forming a gate interconnect structure that connects to the gate structure; and forming a bottom source-drain metal structure that connects to the bottom source-drain structure.

[0074] In some embodiments, the top source / drain metal structure refers to a conductive path formed by a metallization process, used to connect the top source / drain structure of the transistor to subsequent wiring layers. The top source / drain metal structure is typically made of copper, aluminum, or their alloys, and is formed by processes such as photolithography, deposition, and etching.

[0075] In some embodiments, in a vertical transistor, the top source-drain metal structure can take the form of a contact via (CTT), which is filled with metal material and forms an ohmic contact with the top source-drain structure to achieve a low-resistance connection.

[0076] In some embodiments, a gate interconnect structure refers to a conductive path used to connect the gate of a transistor to a wiring layer. In some embodiments, the gate interconnect structure may take the form of a metal contact via (CTG), with one end connected to the gate structure (gate metal layer) and the other end connected to the wiring layer. In some embodiments, the gate interconnect structure is located on the periphery of the active structure.

[0077] In some embodiments, there is a synergistic relationship between the top source / drain metal structure and the gate interconnect structure, which together constitute the front interconnect network of the transistor.

[0078] In some embodiments, the bottom source / drain metal structure refers to a conductive path formed by a metallization process, used to connect the bottom source / drain structure of the transistor to subsequent wiring layers. The bottom source / drain metal structure is typically made of copper, aluminum, or their alloys, and is formed through processes such as photolithography, deposition, and etching. The bottom source / drain metal structure can be located on the back side of the wafer.

[0079] In some embodiments, in a vertical transistor, the bottom source / drain metal structure can be connected to the bottom source / drain structure via a back contact hole (CTB). The bottom source / drain metal structure configuration effectively supports double-sided wiring and three-dimensional stacking integration.

[0080] In some embodiments, the top source / drain metal structure, the gate interconnect structure, and the bottom source / drain metal structure together constitute a complete metal interconnect structure. This metal interconnect structure is responsible for the electrical connection between the front and back sides of the transistor and also enables efficient signal transmission.

[0081] In this embodiment, a top source / drain metal structure connected to the top source / drain structure, a gate interconnect structure connected to the gate structure, and a bottom source / drain metal structure connected to the bottom source / drain structure are designed and formed. The above structures enable efficient electrode lead-out and wiring operations on both the front and back sides of the transistor, thereby effectively improving the integration density and electrical performance of vertical transistors and further meeting the application requirements of next-generation advanced processes for high-performance, high-density integrated circuits.

[0082] The following is a specific example illustrating the vertical transistor and its fabrication method in the embodiments of this application.

[0083] Figure 3 This is a top view schematic of a vertical transistor according to an exemplary embodiment. Figure 1 For ease of understanding, the top view only shows the dielectric fork 14, the gate structure 11, and the source / drain structure 12. The AA' section is a section perpendicular to the length direction of the transistor (perpendicular to the channel direction); the BB' section is a section perpendicular to the width direction of the transistor (perpendicular to the channel direction). Figures 4 to 20 This is a schematic diagram illustrating the fabrication process of a vertical transistor according to an exemplary embodiment. Wherein, Figure 4 (a) to Figure 19 (a) shows the vertical transistor along Figure 3 A cross-sectional view of the AA' section. Figure 4 (b) to Figure 20 (b) shows the vertical transistor along Figure 3 A cross-sectional view of the BB' section. See also... Figures 3 to 20 The fabrication method of a vertical transistor may include the following steps.

[0084] Step 1: Taking the Outer Wall structure as an example, a hard mask structure 16 is formed on the semiconductor substrate 15 to obtain the following... Figure 4 The structure shown.

[0085] The second step involves using the hard mask structure 16 as a mask to etch the semiconductor substrate 15, thereby forming dielectric wall vacancies (i.e., grooves 17) in the semiconductor substrate 15, resulting in the following: Figure 5 The structure shown.

[0086] The third step involves depositing a dielectric material, at least within the groove 17, using an atomic layer deposition process to form the initial dielectric fork 18, resulting in... Figure 6 The structure shown.

[0087] Step 4: Etch the initial dielectric fork 18 to form the dielectric fork 14, resulting in... Figure 7 The structure shown.

[0088] In some embodiments, the height of the dielectric fork 14 in the vertical direction is greater than the height of the semiconductor substrate 15.

[0089] Step 5: Remove hard mask structure 16 to obtain the following... Figure 8 The structure shown.

[0090] Step 6: Using photolithography, the semiconductor substrate 15 is etched vertically to form a pair of active structures 20 (active nanosheet structures). Then, oxide material is deposited and etched back onto the etched semiconductor substrate 15 to form a shallow trench isolation structure 22, resulting in... Figure 9 The structure shown.

[0091] Here, a pair of support structures 21 and a pair of active structures 20 can be formed through a single etching process, with the pair of active structures 20 located above the pair of support structures 21. Here, the dielectric fork 14 passes through the pair of active structures 20 and is inserted between the pair of support structures 21.

[0092] In some embodiments, when only one pair of active structures 20 is formed by etching, the dielectric fork 14 penetrates through the pair of active structures 20 and is inserted into the unetched lower half of the semiconductor substrate 15. After wafer flipping, removing the semiconductor substrate above the pair of active structures 20 exposes the dielectric fork 14, and the vertical height of the dielectric fork 14 is greater than the height of the pair of active structures 20. Thus, the dielectric fork 14 can naturally isolate the subsequently fabricated bottom source / drain structures 122.

[0093] Step 7: Deposit and etch back the insulating material to form the bottom isolation layer 23, resulting in... Figure 10 The structure shown.

[0094] Step 8: Deposit gate dielectric material and gate metal material using atomic layer deposition process to form initial gate structure 19, resulting in... Figure 11 The structure shown.

[0095] Step 9: Pattern the initial gate structure 19 using photolithography etching. Then, deposit and etch back dielectric material to form the interlayer dielectric structure 24. Finally, etch back the patterned initial gate structure 19 to form the gate structure 11, resulting in the desired structure. Figure 12 The structure shown.

[0096] Step 10: Deposit insulating material over the gate structure 11 to form a top isolation layer 25. Then, epitaxially form a top source / drain structure 121 based on the active structure 20. Finally, form an interlayer dielectric structure 24 encapsulating the top source / drain structure 121 to obtain the desired result. Figure 13 The structure shown.

[0097] Here, the dielectric fork 14 isolates the top source and drain structures 121 on both sides.

[0098] Step 11: Based on the top source / drain structure 121 and the gate structure 11, a top source / drain metal structure 26 and a gate interconnect structure 27 are formed respectively, resulting in the following... Figure 14 The structure shown.

[0099] Step 12: Bond the front-side structure (such as interlayer dielectric structure 24) to the carrier wafer 28, then flip the wafer to obtain the following: Figure 15 The structure shown.

[0100] Step 13: Process the semiconductor substrate 15 using a chemical mechanical polishing process until the shallow trench isolation structure 22 is exposed, to obtain the desired result. Figure 16 The structure shown.

[0101] Step fourteen: Etch the support structure 21 above the active structure 20 and the shallow trench isolation structure 22 to obtain the following... Figure 17 The structure shown.

[0102] Here, after etching the support structure 21, the sidewalls of the dielectric fork 14 can be exposed.

[0103] Step 15: Based on the active structure 20, an epitaxial bottom source / drain structure 122 is formed, resulting in the following... Figure 18 The structure shown.

[0104] Here, the dielectric fork 14 isolates the bottom source and drain structures 122 on both sides.

[0105] Step 16: Based on the bottom source / drain structure 122, form the bottom source / drain metal structure 29 to obtain the following... Figure 19 The structure shown.

[0106] Here, the dielectric fork 14 isolates the bottom source and drain structures 122 on both sides.

[0107] In some embodiments, taking the Inner Wall structure as an example, based on the above preparation method, it is also possible to obtain... Figure 20 The structure shown is such that the vertical transistors on both sides of the Inner Wall have different polarities.

[0108] In this embodiment, a dielectric fork is etched and deposited before forming the active structure to isolate the source / drain and gate structures of the transistors on both sides. Next, an active nanosheet structure is etched to form, and an STI, bottom isolation, and initial gate structure are sequentially formed according to the standard process for vertical channel transistors. After patterning the initial gate structure, interlayer dielectric material is filled and etched back to expose the initial gate structure bridging the top of the dielectric fork. The initial gate structure is then etched back to achieve self-alignment and form gate structure isolation for the transistors on both sides. Next, a top isolation is formed, and a top source / drain structure and a front lead-out structure are epitaxially formed. After bonding and flipping, chemical mechanical polishing is performed on the surface of the shallow trench isolation structure. The silicon nanosheet is then etched back to the appropriate position, releasing the shallow trench isolation structure, making the dielectric fork higher than the active nanosheet structure. Finally, the bottom source / drain structure and the back lead-out structure are formed.

[0109] Furthermore, the vertical transistors provided in this application embodiment can be inspected using detection and analysis instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, this application embodiment can use TEM slicing to inspect the structure of the above-mentioned vertical transistors. On the AA' section, it can be observed that the source, drain, and gate structures of the transistors on both sides of the dielectric fork 14 are separated by the dielectric fork.

[0110] In some embodiments, inverters formed based on inner walls can have multiple lead-out methods. It is evident that the dielectric fork, while further miniaturizing the cell size, inherits the flexible lead-out advantage of double-sided vertical crystal strands.

[0111] For example, Figure 21 This is a schematic diagram of the lead-out structure of an inverter according to an exemplary embodiment. Figure 1 . Figure 22 This is a schematic diagram of the lead-out structure of an inverter according to an exemplary embodiment. Figure 2 . Figure 23This is a schematic diagram of the lead-out structure of an inverter according to an exemplary embodiment. Figure 3 . Figure 24 This is a schematic diagram of the lead-out structure of an inverter according to an exemplary embodiment. Figure 4 .

[0112] See Figure 21 As shown, the lead-out structure of the inverter can be of the first type: a gate interconnect structure 27 for connecting the gate structure 11 in the inverter structure is formed on the front side of the wafer, and a top source drain metal structure 26 for connecting the two top source drain structures 121 in the inverter structure is formed on the front side of the wafer.

[0113] Understandable. Figure 21 The gate structures 11 of the PMOS and NMOS transistors on the left and right are led out to the first metal layer on the front side of the wafer through gate vias (gate interconnect structure 27), and then led out to the second metal layer through vias in the first metal layer for lateral connection as signal input terminals (VIN), realizing the common gate function of PMOS and NMOS. Meanwhile, the source of the PMOS at the top and the source of the NMOS at the top are connected to the power supply (VDD) and power supply (VSS) on the back side of the wafer, respectively, while the drain of the PMOS at the bottom and the drain of the NMOS at the bottom are interconnected across the dielectric fork 14 through contact metal (top source-drain metal structure 26). Furthermore, the contact metal is led out to the first and second metal layers on the front side of the wafer through vias to continue completing the inter-cell interconnection.

[0114] It is important to note that Figures 21 to 24 The bottom of the image shows the front side of the wafer, and the top shows the back side.

[0115] See Figure 22 As shown, the lead-out structure of the inverter can be a second type: a gate interconnect structure 27 is formed on the back side to connect the gate structure 11 in the inverter structure, and a top source drain metal structure 26 is formed on the front side to connect the two top source drain structures 121 in the inverter structure.

[0116] Understandable. Figure 22The gate structures 11 of the PMOS and NMOS transistors on the left and right are led out to the first metal layer on the back of the wafer through gate vias (gate interconnect structure 27), and then led out to the second metal layer through vias in the first metal layer for lateral connection as signal input terminals (VIN), realizing the common gate function of PMOS and NMOS. Meanwhile, the source of the PMOS at the top and the source of the NMOS at the top are connected to the power supply (VDD) and power supply (VSS) on the back of the wafer, respectively, while the drain of the PMOS at the bottom and the drain of the NMOS at the bottom are interconnected across the dielectric fork 14 through contact metal (top source-drain metal structure 26). Furthermore, the contact metal is led out to the first and second metal layers on the front of the wafer through vias to continue completing the inter-cell interconnection.

[0117] See Figure 23 As shown, the lead-out structure of the inverter can be a third type: a gate interconnect structure 27 is formed on the front side, connecting the gate structure 11 in the inverter, and a bottom source drain metal structure 29 is formed on the back side, connecting the two bottom source drain structures 122 in the inverter.

[0118] Understandable. Figure 23 The gate structures 11 of the PMOS transistor on the left and the NMOS transistor on the right are led out to the first metal layer on the front side of the wafer through gate vias (gate interconnect structure 27), and then led out to the second metal layer through vias in the first metal layer for lateral connection as signal input terminals (VIN), realizing the common gate function of PMOS and NMOS. At the same time, the source of the PMOS at the top and the source of the NMOS at the top are interconnected across the dielectric fork 14 through contact metal (bottom source-drain metal structure 29). Furthermore, the contact metal is led out to the first and second metal layers on the back side of the wafer through vias to continue completing the inter-cell interconnection. The drain of the PMOS at the bottom and the drain of the NMOS at the bottom are connected to the power supply (VDD) and power supply (VSS) on the front side of the wafer, respectively.

[0119] See Figure 24 As shown, the lead-out structure of the inverter can be a fourth type: a gate interconnect structure 27 is formed on the back side to connect the gate structure 11 in the inverter, and a bottom source drain metal structure 29 is formed on the back side to connect the two bottom source drain structures 122 in the inverter.

[0120] Understandable. Figure 24The gate structures 11 of the PMOS and NMOS transistors on the left and right are led out to the first metal layer on the back of the wafer through gate vias (gate interconnect structure 27), and then led out to the second metal layer through vias in the first metal layer for lateral connection as signal input terminals (VIN), realizing the common gate function of PMOS and NMOS. At the same time, the source of the PMOS at the top and the source of the NMOS at the top are interconnected across the dielectric fork 14 through contact metal (bottom source-drain metal structure 29). Furthermore, the contact metal is led out to the first and second metal layers on the back of the wafer through vias to continue completing the inter-cell interconnection. The drain of the PMOS at the bottom and the drain of the NMOS at the bottom are connected to the power supply (VDD) and power supply (VSS) on the front of the wafer, respectively.

[0121] In some embodiments, Figure 25 This is a top view schematic of a vertical transistor according to an exemplary embodiment. Figure 2 For ease of understanding, the top view only shows the dielectric fork 14, the gate structure 11, and the source / drain structure 12. The AA' section is a section perpendicular to the length direction of the transistor (perpendicular to the channel direction); the BB' section is a section perpendicular to the width direction of the transistor (perpendicular to the channel direction). Figure 26 This is a schematic diagram of a vertical transistor structure according to an exemplary embodiment. Figure 2 .in, Figure 26 (a) shows the vertical transistor along Figure 25 A cross-sectional view of the AA' section. Figure 26 (b) shows the vertical transistor along Figure 25 A cross-sectional view of the BB' section. See also... Figures 25 to 26 Combined with the side grille design, the unit size can be further miniaturized.

[0122] Understandable. Figures 1 to 24 The diagram shows a scheme in which the gate structure 11 and the gate interconnect structure 27 are arranged in the first horizontal direction. Figures 25 to 26 The diagram shows a scheme where the gate structure 11 and the gate interconnect structure 27 are arranged in the second horizontal direction (also known as a side-gate design). The side-gate design can further improve the integration performance of the transistor.

[0123] Secondly, embodiments of this application provide a vertical transistor. The vertical transistor may include: a dielectric fork 14;

[0124] Two transistors are located on both sides of the dielectric fork plate 14 along the first horizontal direction. Each transistor includes a top source-drain structure 121, a gate structure 11, and a bottom source-drain structure 122 arranged sequentially along the vertical direction. The active structure 20 of each transistor is connected to the dielectric fork plate 14.

[0125] It is understood that the structure of the vertical transistor in the embodiments of this application can be referred to the description in any embodiment of the first aspect, and will not be repeated here for the sake of brevity.

[0126] Thirdly, embodiments of this application provide a semiconductor device, including: a vertical transistor as described in the above embodiments.

[0127] Fourthly, embodiments of this application provide an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device being disposed on the circuit board. The semiconductor device includes the aforementioned vertical transistor.

[0128] In summary, the dielectric fork 14 is formed by etching and deposition before forming the active structure 20 in this embodiment of the application. The dielectric fork 14 is used to isolate the transistors on both sides, thereby saving layout area, enhancing integration capability, and ensuring that the gate width does not significantly degrade. Due to the presence of the dielectric fork 14, the gate structures 11 of the transistors on both sides are naturally isolated, and the isolation characteristics of the dielectric fork 14 are beneficial for realizing gate splitting design.

[0129] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for fabricating a vertical transistor, characterized in that, The method includes: A dielectric fork is formed in a semiconductor substrate, wherein the dielectric fork is partially embedded in the semiconductor substrate in the vertical direction; A portion of the semiconductor substrate is removed to form a pair of active structures, wherein two of the active structures are located on opposite sides of the dielectric fork along a first horizontal direction and are in contact with the dielectric fork; the vertical direction is perpendicular to the first horizontal direction. Based on the pair of active structures, a gate structure and a top source / drain structure corresponding to each active structure are formed respectively; The semiconductor substrate is flipped along the vertical direction and thinned until the dielectric fork is exposed; Remove the semiconductor substrate located above the pair of active structures; Based on the pair of active structures, bottom source-drain structures corresponding to each active structure are formed.

2. The preparation method according to claim 1, characterized in that, The removal of a portion of the semiconductor substrate to form a pair of active structures includes: A portion of the semiconductor substrate is etched to form a pair of support structures and the pair of active structures, wherein the pair of support structures are located below the pair of active structures; An oxide material is deposited over the etched semiconductor substrate to form a shallow trench isolation structure, wherein the shallow trench isolation structure encloses the pair of support structures and the pair of active structures are exposed outside the shallow trench isolation structure; The removal of the semiconductor substrate located above the pair of active structures includes: Etch the pair of support structures above the pair of active structures; Remove the shallow trench isolation structure.

3. The preparation method according to claim 1, characterized in that, The process of forming a dielectric fork in a semiconductor substrate includes: A hard mask structure is formed over the semiconductor substrate, wherein the hard mask structure has an opening that exposes the semiconductor substrate; Based on the hard mask structure, the exposed semiconductor substrate is etched to form a groove; Medium material is deposited within the groove and the opening to form the medium fork plate.

4. The preparation method according to claim 1, characterized in that, The step of forming a gate structure and a top source / drain structure corresponding to each active structure based on the pair of active structures includes: An insulating material is deposited over the etched semiconductor substrate to form a bottom isolation layer; Above the bottom isolation layer, a gate structure corresponding to each active structure is formed, wherein the gate structure covers the surface of the bottom isolation layer and the sidewall of the active structure; An insulating material is deposited above the portion of the gate structure that covers the sidewall of the active structure to form a top isolation layer; Based on the pair of active structures, a top source / drain structure corresponding to each active structure is formed above the top isolation layer.

5. The preparation method according to claim 4, characterized in that, The formation of a gate structure corresponding to each active structure above the bottom isolation layer includes: A gate dielectric material and a gate metal material are sequentially deposited over the bottom isolation layer, the pair of active structures, and the dielectric fork to form an initial gate structure, wherein the initial gate structure covers the surface of the bottom isolation layer, the sidewalls and surfaces of the pair of active structures, and the sidewalls and surfaces of the dielectric fork. The initial gate structure is patterned using a photolithography etching process, wherein, compared to the state before etching where the surface of the bottom isolation layer is completely covered, the initial gate structure after etching is partially covered. An interlayer dielectric structure is formed on the initial gate structure after patterning, wherein the height of the interlayer dielectric structure in the vertical direction is the same as the height of the active structure in the vertical direction. The initial gate structure after patterning is etched back to obtain a gate structure, wherein the height of the gate structure in the vertical direction is less than the height of the active structure in the vertical direction.

6. The preparation method according to claim 4 or 5, characterized in that, The length of the gate structure along the first horizontal direction is greater than the length of the gate structure along the second horizontal direction; or... The length of the gate structure along the first horizontal direction is less than the length of the gate structure along the second horizontal direction, wherein the second horizontal direction is perpendicular to the vertical direction and the first horizontal direction.

7. The preparation method according to claim 1, characterized in that, The method further includes at least one of the following: A top source / drain metal structure is formed that connects the top source / drain structure; Forming a gate interconnect structure that connects the gate structure; A bottom source / drain metal structure is formed that connects to the bottom source / drain structure.

8. The preparation method according to claim 1, characterized in that, The top source / drain structure, gate structure, and bottom source / drain structure corresponding to each active structure constitute a transistor; The two transistors located on opposite sides of the dielectric fork along the first horizontal direction have the same or different polarities.

9. The preparation method according to claim 8, characterized in that, When the two transistors have different polarities, the two transistors form an inverter; The method further includes at least one of the following: A gate interconnect structure connecting the gate structure in the inverter is formed on the front side, and a top source drain metal structure connecting the two top source drain structures in the inverter is formed on the front side. A gate interconnect structure is formed on the back side, connecting the gate structure in the inverter, and a top source drain metal structure is formed on the front side, connecting the two top source drain structures in the inverter; A gate interconnect structure connecting the gate structure in the inverter is formed on the front side, and a bottom source drain metal structure connecting the two bottom source drain structures in the inverter is formed on the back side; The back side forms a gate interconnect structure that connects to the gate structure in the inverter, and a bottom source drain metal structure that connects to the two bottom source drain structures in the inverter.

10. A vertical transistor, characterized in that, The vertical transistor is fabricated using the method described in any one of claims 1 to 9, wherein the vertical transistor comprises: Medium fork; Two transistors are located on both sides of the dielectric fork along a first horizontal direction, wherein each transistor includes a top source-drain structure, a gate structure, and a bottom source-drain structure arranged sequentially along a vertical direction; the active structure of each transistor is connected to the dielectric fork.

11. A semiconductor device, characterized in that, include: The vertical transistor as described in claim 10.

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