Preparation method of vertical transistor, vertical transistor and semiconductor device

Abstract

The invention provides a preparation method of a vertical transistor, the vertical transistor and a semiconductor device. The method comprises the following steps: forming a dielectric fork sheet in a semiconductor substrate, wherein the dielectric fork sheet is partially embedded into the semiconductor substrate in the vertical direction; one part of the semiconductor substrate and one part of the dielectric fork piece are removed to form a pair of active structures and a dielectric cylinder, and the two active structures in the pair of active structures are located on the two sides of the dielectric cylinder in the first horizontal direction respectively and connected with the dielectric cylinder; forming a gate structure based on the pair of active structures, the gate structure surrounding the pair of active structures and the dielectric cylinders between the pair of active structures in the first horizontal plane; based on a pair of active structures, respectively forming a top source drain structure corresponding to each active structure; carrying out wafer reversing treatment, and thinning the semiconductor substrate until the dielectric cylinders are exposed; removing the semiconductor substrate over the pair of active structures; and based on the pair of active structures, respectively forming a bottom source drain structure corresponding to each active structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip manufacturing, and in particular to a method for fabricating a vertical transistor, a vertical transistor, and a semiconductor device. Background Technology

[0002] With Moore's Law continuing to deepen, especially after the gate-all-around (GAA) transistor technology node, exploring new transistor structures and further miniaturizing transistor size are currently hot topics in the industry's research and development.

[0003] Vertical transistors, by changing the current transport channel from parallel to the wafer to perpendicular to the wafer, can realize the transformation of transistor distribution from a two-dimensional plane to a three-dimensional space, reduce the transistor area, help to further improve transistor integration density, and improve circuit performance. They are considered one of the important technologies for continuing the miniaturization of integrated circuits. Summary of the Invention

[0004] This application provides a method for fabricating a vertical transistor, a vertical transistor, and a semiconductor device, which can reduce transistor spacing and further miniaturize integrated circuit dimensions.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a method for fabricating a vertical transistor, comprising: forming a dielectric fork in a semiconductor substrate, wherein the dielectric fork is partially embedded in the semiconductor substrate in a vertical direction; removing a portion of the semiconductor substrate and a portion of the dielectric fork to form a pair of active structures and a dielectric pillar, wherein two active structures in the pair of active structures are located on both sides of the dielectric pillar along a first horizontal direction and are in contact with the dielectric pillar; the vertical direction is perpendicular to the first horizontal direction; forming a gate structure based on the pair of active structures, wherein the gate structure surrounds the pair of active structures and the dielectric pillar between the pair of active structures in a first horizontal plane, the first horizontal direction being parallel to the first horizontal plane; forming a top source / drain structure corresponding to each active structure based on the pair of active structures; performing a wafer-washing process on the semiconductor substrate in a vertical direction and thinning the semiconductor substrate until the dielectric pillar is exposed; removing the semiconductor substrate above the pair of active structures; and forming a bottom source / drain structure corresponding to each active structure based on the pair of active structures.

[0007] This application provides a vertical transistor, comprising: a dielectric pillar; two transistors located on both sides of the dielectric pillar along a first horizontal direction, wherein each transistor includes a top source-drain structure, a gate structure, and a bottom source-drain structure arranged sequentially along a vertical direction; and the active structure of each transistor is connected to the dielectric pillar.

[0008] This application provides a semiconductor device, including: a vertical transistor provided in this application.

[0009] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0010] In this embodiment, dielectric pillars are first formed in a semiconductor substrate, partially embedded within the substrate to provide isolation in subsequent processes. Next, a pair of active structures are formed by etching, using the dielectric pillars as separators to separate the two active structures, thus avoiding the short-circuit risk caused by insufficient spacing in traditional designs. Subsequently, a shared gate structure is constructed around the periphery of the pair of active structures, and a top source / drain structure is constructed on each active structure. Then, the dielectric pillars are exposed through wafer flipping and thinning processes, while excess substrate material above the active structures is removed. Finally, a bottom source / drain structure is formed above the active structures, completing the transistor construction. This approach achieves effective isolation between the transistors on both sides using dielectric pillars, eliminating the need for additional transistor spacing or complex isolation structures, thereby increasing integration density. Furthermore, by forming a shared gate structure for the pair of active structures, the transistors on both sides of the dielectric pillars do not require additional metal structures for gate interconnection, thus reducing the complexity of the common-gate process.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0013] Figure 1 This is a structure of a vertical transistor according to an exemplary embodiment. Figure 1 ;

[0014] Figure 2 This is a schematic flowchart illustrating a method for fabricating a vertical transistor according to an exemplary embodiment;

[0015] Figure 3 This is a top view schematic of a vertical transistor according to an exemplary embodiment. Figure 1 ;

[0016] Figures 4 to 20 This is a schematic diagram illustrating the fabrication process of a vertical transistor according to an exemplary embodiment;

[0017] Figure 21 This is a top view schematic diagram of a semiconductor structure according to an exemplary embodiment. Figure 1 ;

[0018] Figure 22 This is a top view schematic diagram of a semiconductor structure according to an exemplary embodiment. Figure 2 ;

[0019] Figure 23 This is a top view schematic diagram of a semiconductor structure according to an exemplary embodiment. Figure 3 ;

[0020] Figure 24 This is a schematic diagram of a vertical transistor structure according to an exemplary embodiment.

[0021] The reference numerals and names in the figure are as follows:

[0022] 11-Gate structure; 12-Source / drain structure; 121-Top source / drain structure; 122-Bottom source / drain structure; 13-Isolation structure; 14-Dielectric fork; 15-Semiconductor substrate; 16-Hard mask structure; 17-Groove; 18-Initial dielectric fork; 19-Initial gate structure; 20-Active structure; 21-Support structure; 22-Shallow trench isolation structure; 23-Bottom isolation layer; 24-Interlayer dielectric structure; 25-Top isolation layer; 26-Top source / drain metal structure; 27-Gate interconnect structure; 28-Carrier wafer; 29-Bottom source / drain metal structure; 30-Dielectric pillar. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0025] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0026] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0027] Figure 1 This is a structure of a vertical transistor according to an exemplary embodiment. Figure 1 . Figure 1 (a) shows a top view of the vertical transistor. For ease of understanding, only the gate structure 11 and the source / drain structure 12 are shown in the top view. The AA' section is a cross-section along the width direction (perpendicular to the channel direction) of the vertical transistor; the BB' section is a cross-section along the length direction (perpendicular to the channel direction) of the vertical transistor. Figure 1 (b) shows the vertical transistor along Figure 1 A cross-sectional view of the AA' section. Figure 1 (c) shows the vertical transistor along Figure 1 A cross-sectional view of the BB' section.

[0028] See Figure 1 This paper illustrates a source-drain symmetrical vertical transistor. The vertical transistor is fabricated by etching a channel on a silicon substrate and sequentially constructing a gate structure, a top source-drain structure, and a bottom source-drain structure. Due to the isolation requirements between the source-drain structure and the gate structure, at least one isolation structure 13 is formed, resulting in a large spacing between transistors. This makes it difficult to further reduce the standard cell size, restricting the improvement of integration density and hindering the development of more advanced processes.

[0029] This application provides a method for fabricating a vertical transistor, a vertical transistor, and a semiconductor device, which can reduce transistor spacing and further miniaturize integrated circuit dimensions.

[0030] In a first aspect, embodiments of this application provide a method for fabricating a vertical transistor. Figure 2 This is a schematic flowchart illustrating a method for fabricating a vertical transistor according to an exemplary embodiment, such as... Figure 2 As shown, the fabrication method of the vertical transistor in the embodiments of this application may include steps 201 to 207.

[0031] Step 201: Form a dielectric fork in the semiconductor substrate.

[0032] In some embodiments, the semiconductor substrate may be formed of semiconductor materials such as silicon or germanium. In one embodiment, the semiconductor substrate may be a single-crystal silicon substrate.

[0033] In some embodiments, the dielectric fork can be partially embedded vertically within the semiconductor substrate. Here, partial embedding in the substrate vertically means that the height of the dielectric fork in the vertical direction is greater than the height of the active region in the vertical direction. Thus, the dielectric fork can provide isolation at both the top and bottom of the vertical transistor.

[0034] In some embodiments, the dielectric fork can be an insulating structure. The primary function of the dielectric fork is to isolate the source / drain and gate structures of adjacent transistors in subsequent processes, preventing short circuits or interference between them. In some embodiments, the dielectric fork can be made of insulating materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), or other high-dielectric-constant oxides. In some embodiments, the dielectric fork can be formed by processes such as etching a semiconductor substrate to form a groove and depositing an insulating material within the groove.

[0035] In some embodiments, since the dielectric forks are fabricated before the active structure is formed, physical isolation between transistors can be achieved without sacrificing additional area. This approach has a significant advantage over related technologies that require reserving a large isolation area.

[0036] In some embodiments, step 201 may include: after obtaining the semiconductor substrate, removing a portion of the semiconductor substrate to form a pair of initial active structures, then etching the middle portion of the initial active structures to form a groove and depositing insulating material to form a dielectric fork. After the middle portion of the initial active structures is removed, two active structures are formed located on both sides of the dielectric fork along a first horizontal direction.

[0037] In some embodiments, by forming dielectric forks in a semiconductor substrate, mutual interference between subsequent active structures, gate and source / drain structures can be effectively avoided, providing clear spatial boundaries for subsequent processes, while reducing the layout area increased due to isolation requirements and improving the overall integration capability of the chip.

[0038] In some embodiments, step 201 may include: forming a hard mask structure over a semiconductor substrate, wherein an opening is formed in the hard mask structure to expose the semiconductor substrate; etching the exposed semiconductor substrate based on the hard mask structure to form a groove; and depositing a dielectric material in the groove and the opening to form a dielectric fork.

[0039] In some embodiments, a hard mask structure refers to a thin film with a high etch selectivity deposited on the wafer surface, which is used to protect certain areas from etching during subsequent processes. In some embodiments, the hard mask structure is typically made of materials such as silicon dioxide, silicon nitride, or carbon-based materials. Hard mask structures exhibit good resistance to chemical etching and thermal stability. In some embodiments, through photolithography, the hard mask structure forms openings of a specific shape to expose the underlying semiconductor substrate, ensuring that only the exposed semiconductor substrate is etched, avoiding damage to the unexposed semiconductor substrate.

[0040] In some embodiments, grooves can be formed on the exposed semiconductor substrate by etching. In these embodiments, the depth and width of the grooves are precisely controlled according to design requirements. The purpose of the grooves is to provide space for subsequent deposition of dielectric materials.

[0041] In some embodiments, the dielectric material refers to a material with a high dielectric constant (k value) and good insulating properties, such as silicon oxide, silicon nitride, or other high-k dielectric materials. In some embodiments, the deposition process may include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. The dielectric material is filled into the grooves and openings via CVD or ALD, forming dielectric forks. Because the openings formed by the hard mask structure are also filled with dielectric material, the vertical height of the dielectric forks is greater than the vertical height of the semiconductor substrate.

[0042] Step 202: Remove a portion of the semiconductor substrate and a portion of the dielectric fork to form a pair of active structures and dielectric pillars, respectively.

[0043] In some embodiments, by using dry etching or wet etching processes to remove portions of the semiconductor substrate and the dielectric fork, two active structures can be formed. The active structures can be nanoscale fin-like or strip-like structures, serving as current transport channels for vertical transistors. The two active structures are located on opposite sides of the dielectric pillar along a first horizontal direction and are in contact with the dielectric pillar.

[0044] In some embodiments, step 202 may include: etching the two ends of a dielectric fork in a second horizontal direction to form dielectric pillars, wherein the second horizontal direction is perpendicular to the vertical direction and the first horizontal direction; etching a portion of a semiconductor substrate located in a sacrificial region to form a pair of active structures, wherein the sacrificial region includes the two ends of the semiconductor substrate in the first horizontal direction and the two ends in the second horizontal direction.

[0045] In some embodiments, the portions of the dielectric fork removed are located at both ends of the dielectric fork in a second horizontal direction. The second horizontal direction is perpendicular to the vertical direction and the first horizontal direction. The portions of the semiconductor substrate removed are located at both ends of the semiconductor substrate in the first horizontal direction and at both ends of the second horizontal direction. Here, both ends of the semiconductor substrate in the first and second horizontal directions belong to the sacrificial region. By removing a portion (upper half) of the semiconductor substrate within the sacrificial region, an active structure can be formed in the portion not within the sacrificial region.

[0046] In some embodiments, the first horizontal direction generally refers to a transverse direction parallel to the wafer surface, while the vertical direction is a direction perpendicular to the wafer surface. The first horizontal direction is perpendicular to the vertical direction. In some embodiments, the introduction of dielectric pillars isolates the two active structures in the horizontal direction, but maintains continuity in the vertical direction, which is beneficial for subsequent vertical current transmission.

[0047] In some embodiments, by precisely controlling the etching depth and width, it can be ensured that the dimensions of the two active structures are consistent. In some embodiments, the etching depth is less than the vertical height of the semiconductor substrate, and when etching the semiconductor substrate to form the active structure, a portion of the semiconductor substrate is retained as support for subsequent structures such as the bottom isolation layer and the gate structure.

[0048] In some embodiments, the length of the dielectric column in the second horizontal direction is approximately the same as the length of the active structure in the second horizontal direction. The second horizontal direction is perpendicular to both the first horizontal direction and the vertical direction. In some embodiments, the length of the dielectric column in the second horizontal direction is equal to the length of the active structure in the second horizontal direction.

[0049] In some embodiments, step 202 may include: etching a portion of the semiconductor substrate in the sacrificial region to form a pair of support structures and a pair of active structures, wherein the pair of support structures are located below the pair of active structures; and depositing an oxide material over the etched semiconductor substrate to form a shallow trench isolation structure, wherein the shallow trench isolation structure encloses the pair of support structures and the pair of active structures are exposed outside the shallow trench isolation structure.

[0050] In some embodiments, by precisely controlling the etching process, two symmetrical pairs of support structures and a pair of active structures located above the support structures can be formed on a semiconductor substrate. The pair of support structures are used to provide mechanical stability in subsequent processes, preventing the pair of active structures from deforming or collapsing due to external forces.

[0051] In some embodiments, a pair of support structures are structural layers located beneath a pair of active structures, typically composed of an unetched semiconductor substrate, used to support and stabilize the pair of active structures. The arrangement of the support structures can improve the overall reliability of the device, especially in vertical transistor structures, where the arrangement helps maintain the geometric accuracy of the channel.

[0052] In some embodiments, selective removal of the semiconductor substrate can be achieved by dry etching (such as reactive ion etching) or wet etching (such as using hydrofluoric acid solution). In some embodiments, etching the semiconductor substrate to a preset depth can form a pair of support structures and a pair of active structures in a single etching operation. Here, the preset depth is greater than the depth of the active structures.

[0053] In some embodiments, by providing a pair of support structures below a pair of active structures, the structural stability of the transistor during the fabrication process can be enhanced, the risk of structural failure due to thermal or mechanical stress can be reduced, and the reliability and yield of the device can be improved.

[0054] In some embodiments, shallow trench isolation (STI) structures can be formed by depositing an oxide material (such as silicon dioxide) on an etched semiconductor substrate (i.e., depositing it horizontally around the periphery of the active structure). Here, the shallow trench isolation structure is used for physical isolation between the front and back structures of the transistor.

[0055] In some embodiments, the shallow trench isolation structure surrounds a pair of support structures, which can isolate the subsequent fabrication of the gate structure from the etched semiconductor substrate. Simultaneously, a pair of active structures are exposed outside the shallow trench isolation structure, facilitating the formation of the gate structure enclosing the active structures in subsequent processes.

[0056] In some embodiments, a pair of support structures are disposed below a pair of active structures, and a shallow trench isolation structure is formed around the support structures to achieve efficient isolation between transistors and structural stability. This arrangement effectively avoids electrical interference between adjacent devices, thereby improving circuit stability and reliability, and further enhancing the overall performance and integration of the chip.

[0057] Step 203: Based on a pair of active structures, a gate structure is formed that surrounds the pair of active structures and the dielectric pillars between the pair of active structures in a first horizontal plane.

[0058] In some embodiments, the first horizontal direction is parallel to the first horizontal plane. In some embodiments, a gate structure surrounding a vertical channel structure can be formed by forming a gate structure surrounding a pair of active structures within the first horizontal plane. The height of the gate structure in the vertical direction is substantially the same as the height of the active structures in the vertical direction. The height of the dielectric pillar in the vertical direction is greater than the height of the active structures in the vertical direction, so that after the gate structure is fabricated, the subsequently grown top source / drain structures will be automatically isolated by the dielectric pillar.

[0059] In some embodiments, the gate structure may consist of a gate dielectric layer and a gate metal layer. The gate dielectric layer may be formed by a deposition process; the gate metal layer may be formed by a deposition process and a patterning process.

[0060] In some embodiments, the gate dielectric layer may include at least one of hafnium oxide, hafnium oxysilicon, aluminum oxide, or zirconium oxide; the gate metal layer may include at least one of titanium nitride, tantalum nitride, titanium aluminum carbon, tantalum aluminum carbon, tungsten, cobalt, or ruthenium.

[0061] In some embodiments, step 203 may include: sequentially depositing a gate dielectric material and a gate metal material over an etched semiconductor substrate to form an initial gate structure, wherein the initial gate structure covers the surface of the bottom isolation layer, the sidewalls and surfaces of a pair of active structures, and the sidewalls and surfaces of the dielectric pillars; patterning the initial gate structure using a photolithography etching process, wherein the etched initial gate structure partially covers the surface of the bottom isolation layer compared to the state before etching when it completely covered the surface; forming an interlayer dielectric structure over the patterned initial gate structure, wherein the height of the interlayer dielectric structure in the vertical direction is the same as the height of the active structure in the vertical direction; and etching back the patterned initial gate structure to obtain a gate structure, wherein the height of the gate structure in the vertical direction is less than the height of the active structure in the vertical direction.

[0062] In some embodiments, a gate dielectric material and a gate metal material are first deposited sequentially over a semiconductor substrate (including a bottom isolation layer, a pair of active structures, and dielectric pillars) to form a continuous initial gate structure. This continuous initial gate structure covers the surface of the bottom isolation layer, the sidewalls and surfaces of the active structures, and the sidewalls and surfaces of the dielectric pillars, providing a good foundation for subsequent patterning and etch-back operations. The initial gate structure is then etched using a patterning process. After etching, the coverage of the initial gate structure on the surface of the bottom isolation layer changes from complete coverage to partial coverage, while the coverage of the sidewalls and surfaces of the active structures and the dielectric pillars remains unchanged. Here, the patterning process isolates the gate structures between adjacent transistor units. A dielectric material is then deposited and etched back over the patterned initial gate structure to form an interlayer dielectric structure. This interlayer dielectric structure surrounds the active structures and dielectric pillars. Furthermore, the height of the interlayer dielectric structure is precisely controlled to match the vertical height of the active structures, ensuring that the active structures are not accidentally cut in subsequent processes and that device performance is not affected. Finally, through a etch-back operation, a portion of the initial gate structure after patterning is removed, resulting in a gate structure with a height lower than the active structure. Here, after etch-back, the gate structure no longer covers the surface of the active structure, the sidewalls and surface of the dielectric pillars, and the coverage of the sidewalls of the active structure changes from complete coverage to partial coverage.

[0063] In some embodiments, a etch-back operation can reserve space for the growth of a top isolation layer. In some embodiments, the height of the gate structure obtained after etch-back is lower than the height of the active structure, and this height difference allows a top isolation layer to be formed on top of the gate structure in subsequent processes.

[0064] In some embodiments, step 203 may include: depositing an insulating material over an etched semiconductor substrate to form a bottom isolation layer. Over the bottom isolation layer, a gate structure is formed, wherein the gate structure covers the surface of the bottom isolation layer, the sidewalls of the active structure, and the sidewalls of the dielectric pillars. Over the portion of the gate structure covering the sidewalls of the active structure, an insulating material is deposited to form a top isolation layer.

[0065] In some embodiments, the bottom isolation layer may be an insulating layer deposited and etched back around the active structure in a vertical transistor to isolate the gate structure and the bottom source / drain structure. In some embodiments, the bottom isolation layer may be made of silicon dioxide or other dielectric materials. In some embodiments, the bottom isolation layer may serve as a support platform for subsequent gate structures. By forming a bottom isolation layer on the etched semiconductor substrate, effective isolation of the active structure can be achieved, which helps to improve device density and performance stability.

[0066] In some embodiments, the top isolation layer may be an insulating layer further deposited and etched back above the gate structure, typically the same as or similar to the bottom isolation layer. The top isolation layer isolates the gate structure and the top source / drain structure. In some embodiments, the material selection and deposition method of the top isolation layer may be consistent with the bottom isolation layer to ensure the stability of the overall structure and process compatibility.

[0067] In some embodiments, the formation of the top source / drain structure depends on the physical boundary provided by the top isolation layer. By forming the top source / drain structure above the top isolation layer, good electrical performance can be guaranteed for each transistor.

[0068] In some embodiments, the length of the gate structure along the first horizontal direction is greater than the length of the gate structure along the second horizontal direction; or, the length of the gate structure along the first horizontal direction is less than the length of the gate structure along the second horizontal direction.

[0069] In some embodiments, the first horizontal direction and the second horizontal direction are two mutually perpendicular horizontal directions that are perpendicular to the vertical direction. For example, in a wafer plane, the first horizontal direction may be the X-axis direction, and the second horizontal direction may be the Y-axis direction, forming an orthogonal coordinate system. In some embodiments, the length of the gate structure along the first horizontal direction refers to the lateral extension dimension of the gate structure in the first horizontal direction, while the length of the gate structure along the second horizontal direction is the lateral extension dimension of the gate structure in the second horizontal direction.

[0070] In some embodiments, by setting the length of the gate structure along the first horizontal direction to be greater than the length along the second horizontal direction, an exit structure (e.g., a gate interconnect structure formed subsequently) of the gate structure can be set in the first horizontal direction, thereby saving chip size in the second horizontal direction and improving device integration.

[0071] In some embodiments, by setting the length of the gate structure along the first horizontal direction to be less than the length along the second horizontal direction, the lead-out structure of the gate structure can be set in the second horizontal direction, thereby saving chip size in the first horizontal direction and improving device integration. In some embodiments, this arrangement allows the active structure and gate structure to be arranged along the second horizontal direction, thereby reducing the distance between the gate structures on both sides of the dielectric pillar and further improving the adaptability and scalability of device design.

[0072] In some embodiments, the method of selecting the length ratio of the gate structure along different horizontal directions according to actual needs can achieve better device performance and layout efficiency. This not only reduces interference between adjacent devices but also improves the stability and reliability of the overall circuit, becoming an important means to promote the miniaturization of devices under advanced processes.

[0073] In some embodiments, the length of the gate structure along the first horizontal direction is greater than the length of the gate structure along the second horizontal direction, and the gate interconnect structure and the gate structure are arranged along the first horizontal direction. In some embodiments, the length of the gate structure along the first horizontal direction is less than the length of the gate structure along the second horizontal direction, and the gate interconnect structure and the gate structure are arranged along the second horizontal direction.

[0074] Step 204: Based on a pair of active structures, form the top source-drain structure corresponding to each active structure.

[0075] In some embodiments, for a pair of active structures, after forming a common gate structure, each top source / drain structure may be formed above the gate structure.

[0076] In some embodiments, the top source / drain structure can be formed on top of the active structure using an epitaxial growth technique.

[0077] In some embodiments, the source / drain structure can be doped silicon or germanium-doped silicon. In some embodiments, since the top source / drain structure is located above the active structure, the front-side interconnect design of the transistor can be further optimized. In some embodiments, by forming a gate structure and a top source / drain structure independently in each active structure, and with the isolation effect of the dielectric pillar, the embodiments of this application can ensure that the active structures, top source / drain structures, and gate structures on both sides of the dielectric pillar will not be short-circuited or crosstalked, thereby improving the overall stability and reliability of the device.

[0078] It should be noted that, for ease of explanation, the source / drain structures mentioned in the embodiments of this application are abbreviations, specifically referring to the source structure and / or drain structure. Furthermore, the source / drain metals are similar to the source / drain structures, where "source / drain" is an abbreviation for "source and / or drain".

[0079] Step 205: The semiconductor substrate is flipped vertically and thinned until the dielectric pillars are exposed.

[0080] In some embodiments, by vertically flipping a semiconductor substrate with completed front-side devices (such as gate structures and top source / drain structures), the previously upward-facing front side of the semiconductor substrate can be made to face down, and the previously downward-facing back side can be made to face up. The back side of the semiconductor substrate can then be thinned until the bottom of the dielectric pillars is exposed.

[0081] In some embodiments, the wafer flipping process typically involves bonding a carrier wafer to the original wafer (i.e., the semiconductor substrate with the front-side device already completed) to prevent wafer breakage or deformation during subsequent fabrication.

[0082] In some embodiments, the thinning process can employ chemical mechanical polishing (CMP) or grinding techniques. In some embodiments, wafer flipping and thinning processes are key steps in realizing double-sided transistor structures, effectively freeing up space on the back side of the wafer to facilitate the subsequent formation of bottom source / drain structures and back metal leads. Wafer flipping and thinning processes also avoid mutual interference between front and back processes, thereby improving the overall device reliability and yield.

[0083] Step 206: Remove the semiconductor substrate located above the pair of active structures.

[0084] In some embodiments, the thickness of the dielectric pillar inserted into the semiconductor substrate is greater than the thickness of the active structure. Therefore, removing the substrate material above the active structure after wafer flipping can expose part of the sidewalls of the dielectric pillar. Exposing part of the sidewalls of the dielectric pillar provides more operating space for subsequent fabrication of the bottom source / drain structure, facilitating the separation of the bottom source / drain structure by the dielectric pillar.

[0085] In some embodiments, a semiconductor substrate located above a pair of active structures is removed by a dry etching or wet etching process.

[0086] In some embodiments, step 205 may include: etching a pair of support structures above a pair of active structures; removing shallow trench isolation structures.

[0087] In some embodiments, an etching operation can remove a pair of support structures above a pair of active structures, thereby freeing up space above the active structures to facilitate the formation of bottom source / drain structures in subsequent processes. In some embodiments, the etching parameters need to be adjusted according to the material properties of the pair of support structures to ensure that only a specified area is removed without affecting other structures.

[0088] In some embodiments, after removing the pair of support structures, the previously formed shallow trench isolation structure can be removed. The removal method can be wet etching or dry etching, depending on the materials and process conditions used. After removing the shallow trench isolation structure, the previously isolated area can be reopened, thereby facilitating the formation of the bottom source / drain structure.

[0089] In some embodiments, after removing a pair of support structures and shallow trench isolation structures, the dielectric pillar protrudes from the active structure. Thus, during subsequent fabrication of the bottom source / drain structures, the dielectric pillar can naturally isolate the two bottom source / drain structures located on either side of the dielectric pillar in the first horizontal direction.

[0090] Step 207: Based on a pair of active structures, form the bottom source-drain structure corresponding to each active structure.

[0091] In some embodiments, after exposing the dielectric pillar, a bottom source / drain structure corresponding to each active structure can be formed based on the active structures on both sides of the dielectric pillar. In some embodiments, the formation of the bottom source / drain structure can be achieved through epitaxial growth techniques.

[0092] In some embodiments, the formation of the bottom source-drain structure is a crucial step in realizing the complete circuit function of the vertical transistor. The bottom source-drain structure, the active structure, and the top source-drain structure together constitute a complete current path. Furthermore, since the bottom source-drain structure is located on the back side of the wafer, it can be directly connected to the back metal leads, thereby further simplifying the interconnect design.

[0093] In some embodiments, by forming a bottom source-drain structure at the bottom of the active structure, and by utilizing the isolation effect of the dielectric pillar, electrical isolation between the two bottom source-drain structures is ensured, preventing short circuits or interference.

[0094] In some embodiments, the top source / drain structure, gate structure, and bottom source / drain structure corresponding to each active structure constitute a vertical transistor with a vertical channel design. The channel direction is aligned with the vertical direction, thereby achieving higher integration density and smaller cell area. In some embodiments, by setting dielectric pillars, two adjacent vertical transistors in the first horizontal direction are completely separated, ensuring isolation and stability between transistors.

[0095] In some embodiments, the polarities of the two vertical transistors on either side of the dielectric pillar can be the same or different. For example, both vertical transistors on either side of the dielectric pillar can be N-type transistors. As another example, one of the two vertical transistors on either side of the dielectric pillar can be an N-type transistor, and the other can be a P-type transistor. It should be noted that the lithographic windows for the growth of the source and drain structures in N-type and P-type transistors are different.

[0096] In some embodiments, based on the type of transistors subsequently fabricated, dielectric pillars can be divided into two types: one called an outer wall, used to isolate transistors of the same type; and the other called an inner wall, used to isolate transistors of different types. Both outer wall and inner wall structures can effectively reduce the spacing between transistors and improve integration density.

[0097] In some embodiments, when the two vertical transistors on either side of a dielectric pillar have different polarities (e.g., one is an N-type transistor and the other is a P-type transistor), the two vertical transistors can form an inverter structure. In some embodiments, the inverter structure is a basic logic gate circuit used to implement the inversion of input signals. Inverter structures are widely used in digital integrated circuits as a basic module for building more complex logic units.

[0098] In this embodiment, dielectric pillars are first formed in a semiconductor substrate, partially embedded within the substrate to provide isolation in subsequent processes. Next, a pair of active structures are formed by etching, using the dielectric pillars as separators to separate the two active structures, thus avoiding the short-circuit risk caused by insufficient spacing in traditional designs. Subsequently, a shared gate structure is constructed around the periphery of the pair of active structures, and a top source / drain structure is constructed on each active structure. Then, the dielectric pillars are exposed through wafer flipping and thinning processes, while excess substrate material above the active structures is removed. Finally, a bottom source / drain structure is formed above the active structures, completing the transistor construction. This approach achieves effective isolation between the transistors on both sides using dielectric pillars, eliminating the need for additional transistor spacing or complex isolation structures, thereby increasing integration density. Furthermore, by forming a shared gate structure for the pair of active structures, the transistors on both sides of the dielectric pillars do not require additional metal structures for gate interconnection, thus reducing the complexity of the common-gate process.

[0099] In some embodiments, the method for fabricating a vertical transistor may further include at least one of the following: forming a top source-drain metal structure that connects to the top source-drain structure; forming a gate interconnect structure that connects to the gate structure; and forming a bottom source-drain metal structure that connects to the bottom source-drain structure.

[0100] In some embodiments, the top source / drain metal structure refers to a conductive path formed by a metallization process, used to connect the top source / drain structure of the transistor to subsequent wiring layers. The top source / drain metal structure is typically made of titanium, nickel, cobalt, or alloys thereof, and is formed by processes such as photolithography, deposition, and etching.

[0101] In some embodiments, in a vertical transistor, the top source-drain metal structure can take the form of a contact via (CTT), which is filled with metal material and forms an ohmic contact with the top source-drain structure to achieve a low-resistance connection.

[0102] In some embodiments, a gate interconnect structure refers to a conductive path used to connect the gate of a transistor to a wiring layer. In some embodiments, the gate interconnect structure may take the form of a metal contact via (CTG), with one end connected to the gate structure (gate metal layer) and the other end connected to the wiring layer. In some embodiments, the gate interconnect structure is located on the periphery of the active structure.

[0103] In some embodiments, there is a synergistic relationship between the top source / drain metal structure and the gate interconnect structure, which together constitute the front interconnect network of the transistor.

[0104] In some embodiments, the bottom source / drain metal structure refers to a conductive path formed by a metallization process, used to connect the bottom source / drain structure of the transistor to subsequent wiring layers. The bottom source / drain metal structure is typically made of titanium, nickel, cobalt, or alloys thereof, and is formed through processes such as photolithography, deposition, and etching. The bottom source / drain metal structure can be located on the back side of the wafer.

[0105] In some embodiments, in a vertical transistor, the bottom source / drain metal structure can be connected to the bottom source / drain structure via a back contact hole (CTB). The bottom source / drain metal structure configuration effectively supports double-sided wiring and three-dimensional stacking integration.

[0106] In some embodiments, the top source / drain metal structure, the gate interconnect structure, and the bottom source / drain metal structure together constitute a complete metal interconnect structure. This metal interconnect structure is responsible for the electrical connection between the front and back sides of the transistor and also enables efficient signal transmission.

[0107] In this embodiment, a top source / drain metal structure connected to the top source / drain structure, a gate interconnect structure connected to the gate structure, and a bottom source / drain metal structure connected to the bottom source / drain structure are designed and formed. The above structures enable efficient electrode lead-out and wiring operations on both the front and back sides of the transistor, thereby effectively improving the integration density and electrical performance of vertical transistors and further meeting the application requirements of next-generation advanced processes for high-performance, high-density integrated circuits.

[0108] The following is a specific example illustrating the vertical transistor and its fabrication method in the embodiments of this application.

[0109] Figure 3 This is a top view schematic of a vertical transistor according to an exemplary embodiment. Figure 1 For ease of understanding, the top view diagram only shows the dielectric pillars, gate structure, and gate interconnect structure. The AA' section is a cross-section perpendicular to the length direction of the transistor (perpendicular to the channel direction); the BB' section is a cross-section perpendicular to the width direction of the transistor (perpendicular to the channel direction). Figures 4 to 20 This is a schematic diagram illustrating the fabrication process of a vertical transistor according to an exemplary embodiment. Wherein, Figure 4 (a) to Figure 20 (a) shows the vertical transistor along Figure 3 A cross-sectional view of the AA' section. Figure 4 (b) to Figure 20 (b) shows the vertical transistor along Figure 3 A cross-sectional view of the BB' section. See also... Figures 3 to 20 The fabrication method of a vertical transistor may include the following steps.

[0110] Step 1: Taking the Inner Wall structure as an example, a hard mask structure 16 is formed on the semiconductor substrate 15 to obtain the following... Figure 4 The structure shown.

[0111] The second step involves using the hard mask structure 16 as a mask to etch the semiconductor substrate 15, thereby forming dielectric wall vacancies (i.e., grooves 17) in the semiconductor substrate 15, resulting in the following: Figure 5 The structure shown.

[0112] The third step involves depositing a dielectric material, at least within the groove 17, using an atomic layer deposition process to form the initial dielectric fork 18, resulting in... Figure 6 The structure shown.

[0113] Step 4: Etch the initial dielectric fork 18 to form the dielectric fork 14, resulting in... Figure 7 The structure shown.

[0114] In some embodiments, the height of the dielectric fork 14 in the vertical direction is greater than the height of the semiconductor substrate 15.

[0115] Step 5: Remove hard mask structure 16 to obtain the following... Figure 8 The structure shown.

[0116] In one example, Figure 21 This is a top view schematic diagram of a semiconductor structure according to an exemplary embodiment. Figure 1 See also Figure 21 As shown, a top view is shown after the preparation of the dielectric fork 14.

[0117] Step 6: Using photolithography, the semiconductor substrate 15 and dielectric fork 14 are etched vertically to form a pair of active structures 20 (active nanosheet structures) and dielectric pillars 30. Then, oxide material is deposited and etched back onto the etched semiconductor substrate 15 to form a shallow trench isolation structure 22, resulting in... Figure 9 The structure shown.

[0118] Here, by etching a portion of the semiconductor substrate in the sacrificial region and the two ends of the dielectric fork in the second horizontal direction through a single etching process, dielectric pillars 30, a pair of support structures 21 and a pair of active structures 20 can be formed, with the pair of active structures 20 located above the pair of support structures 21.

[0119] In one example, Figure 22This is a top view schematic diagram of a semiconductor structure according to an exemplary embodiment. Figure 2 See also Figure 22 As shown, a top view is displayed after the preparation of the dielectric column 30.

[0120] Step 7: Deposit and etch back the insulating material to form the bottom isolation layer 23, resulting in... Figure 10 The structure shown.

[0121] Step 8: Deposit gate dielectric material and gate metal material using atomic layer deposition process to form initial gate structure 19, resulting in... Figure 11 The structure shown.

[0122] Step 9: Pattern the initial gate structure 19 using photolithography etching. Then, deposit and etch back dielectric material to form the interlayer dielectric structure 24. Finally, etch back the patterned initial gate structure 19 to form the gate structure 11, resulting in the desired structure. Figure 12 The structure shown.

[0123] In one example, Figure 23 This is a top view schematic diagram of a semiconductor structure according to an exemplary embodiment. Figure 3 See also Figure 23 The diagram shows a top view after the gate structure 11 has been fabricated. It can be seen that the gate structure 11 surrounds the dielectric pillar 30 and a pair of active structures 20.

[0124] Step 10: Deposit insulating material over the gate structure 11 to form a top isolation layer 25. Then, epitaxially form a top source / drain structure 121 based on the active structure 20. Finally, form an interlayer dielectric structure 24 encapsulating the top source / drain structure 121 to obtain the desired result. Figure 13 The structure shown.

[0125] Here, the dielectric column 30 isolates the top source and drain structures 121 on both sides.

[0126] Step 11: Based on the top source / drain structure 121 and the gate structure 11, a top source / drain metal structure 26 and a gate interconnect structure 27 are formed respectively, resulting in the following... Figure 14 The structure shown.

[0127] Step 12: Bond the front-side structure (such as interlayer dielectric structure 24) to the carrier wafer 28, then flip the wafer to obtain the following: Figure 15 The structure shown.

[0128] Step 13: Process the semiconductor substrate 15 using a chemical mechanical polishing process until the shallow trench isolation structure 22 is exposed, to obtain the desired result. Figure 16 The structure shown.

[0129] Step fourteen: Etch the support structure 21 above the active structure 20 and the shallow trench isolation structure 22 to obtain the following... Figure 17 The structure shown.

[0130] Here, after etching the support structure 21, the sidewalls of the dielectric pillar 30 can be exposed.

[0131] Step 15: Based on the active structure 20, an epitaxial bottom source / drain structure 122 is formed, resulting in the following... Figure 18 The structure shown.

[0132] Here, the dielectric column 30 isolates the bottom source and drain structures 122 on both sides.

[0133] Step 16: Based on the bottom source / drain structure 122, form the bottom source / drain metal structure 29 to obtain the following... Figure 19 The structure shown.

[0134] Here, the dielectric column 30 isolates the bottom source and drain structures 122 on both sides.

[0135] In some embodiments, taking the Outer Wall structure as an example, based on the above preparation method, it is also possible to obtain... Figure 20 The structure shown is such that the vertical transistors on both sides of the Outer Wall have the same polarity.

[0136] In this embodiment, a dielectric fork is etched and deposited before forming the active structure to isolate the source / drain and gate structures of the transistors on both sides. Next, an active nanosheet structure and dielectric pillars are etched to form, and an STI (Silicon-Trench Isolation) structure, a bottom isolation structure, and an initial gate structure shared by a pair of active structures are sequentially formed according to the standard process for vertical channel transistors. After patterning the initial gate structure, interlayer dielectric material is filled and etched back to expose the initial gate structure bridging the top of the dielectric pillars. The initial gate structure is then etched back to form the gate structure shared by the transistors on both sides. Next, a top isolation structure is formed, and a top source / drain structure and a front lead-out structure are epitaxially formed. After bonding and flipping, chemical mechanical polishing is performed on the surface of the shallow trench isolation structure. The silicon nanosheet is etched back to the appropriate position, and the shallow trench isolation structure is released, making the dielectric pillar higher than the active nanosheet structure. Finally, a bottom source / drain structure and a back lead-out structure are formed.

[0137] Furthermore, the vertical transistor provided in this application embodiment can be detected using detection and analysis instruments, such as scanning electron microscope (SEM), transmission electron microscope (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, this application embodiment can use TEM slicing to detect the structure of the above-mentioned vertical transistor. On the AA' section, it can be observed that the source and drain of the transistor on both sides of the dielectric pillar 30 are separated from the active structure by the dielectric pillar 30.

[0138] In some embodiments, inverters formed based on inner walls can have multiple lead-out methods. It is evident that while further miniaturizing the cell size, the dielectric pillars retain the flexible lead-out advantage of double-sided vertical crystal strands.

[0139] In some embodiments, Figure 24 This is a schematic diagram illustrating the structure of a vertical transistor according to an exemplary embodiment. Wherein, Figure 24 (a) shows the vertical transistor along Figure 3 A cross-sectional view of the AA' section. Figure 24 (b) shows the vertical transistor along Figure 3 A cross-sectional view of the BB' section. See also... Figure 24 Combined with the side grille design,

[0140] Understandable. Figures 1 to 23 The diagram shows a scheme in which the gate structure 11 and the gate interconnect structure 27 are arranged in the first horizontal direction. Figure 24 The diagram shows a scheme where the gate structure 11 and the gate interconnect structure 27 are arranged in the second horizontal direction (also known as a side-gate design). The side-gate design can further improve the integration performance of the transistor.

[0141] Secondly, embodiments of this application provide a vertical transistor. The vertical transistor may include: a dielectric pillar 30;

[0142] Two transistors are located on both sides of the dielectric pillar 30 along the first horizontal direction. Each transistor includes a top source-drain structure 121, a gate structure 11, and a bottom source-drain structure 122 arranged sequentially along the vertical direction. The active structure 20 of each transistor is connected to the dielectric pillar 30.

[0143] It is understood that the structure of the vertical transistor in the embodiments of this application can be referred to the description in any embodiment of the first aspect, and will not be repeated here for the sake of brevity.

[0144] Thirdly, embodiments of this application provide a semiconductor device, including: a vertical transistor as described in the above embodiments.

[0145] Fourthly, embodiments of this application provide an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device being disposed on the circuit board. The semiconductor device includes the aforementioned vertical transistor.

[0146] In summary, the dielectric pillars 30 are formed by etching and deposition before the formation of the active structure 20 in this embodiment of the application. These dielectric pillars 30 are used to isolate the transistors on both sides, thereby saving layout area, enhancing integration capability, and ensuring that the gate width does not significantly degrade. Due to the presence of the dielectric pillars 30, the gate structures 11 of the transistors on both sides are naturally isolated, and the isolation characteristics of the dielectric pillars 30 are beneficial for realizing gate separation design.

[0147] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for fabricating a vertical transistor, characterized in that, The method includes: A dielectric fork is formed in a semiconductor substrate, wherein the dielectric fork is partially embedded in the semiconductor substrate in the vertical direction; A portion of the semiconductor substrate and a portion of the dielectric fork are removed to form a pair of active structures and a dielectric pillar, wherein two of the active structures in the pair are located on both sides of the dielectric pillar along a first horizontal direction and are in contact with the dielectric pillar; the vertical direction is perpendicular to the first horizontal direction. A gate structure is formed based on the pair of active structures, wherein the gate structure surrounds the pair of active structures and the dielectric pillar between the pair of active structures in a first horizontal plane, and the first horizontal direction is parallel to the first horizontal plane; Based on the pair of active structures, a top source-drain structure corresponding to each active structure is formed; The semiconductor substrate is flipped along the vertical direction and thinned until the dielectric pillars are exposed; Remove the semiconductor substrate located above the pair of active structures; Based on the pair of active structures, bottom source-drain structures corresponding to each active structure are formed respectively.

2. The preparation method according to claim 1, characterized in that, The removal of a portion of the semiconductor substrate and a portion of the dielectric fork to form a pair of active structures and dielectric pillars, respectively, includes: The dielectric fork is etched at both ends in a second horizontal direction to form the dielectric pillar, wherein the second horizontal direction is perpendicular to the vertical direction and the first horizontal direction; A portion of the semiconductor substrate located in the sacrificial region is etched to form the pair of active structures, wherein the sacrificial region includes both ends of the semiconductor substrate in the first horizontal direction and both ends in the second horizontal direction.

3. The preparation method according to claim 2, characterized in that, The etching of a portion of the semiconductor substrate located in the sacrificial region to form the pair of active structures includes: A portion of the semiconductor substrate located in the sacrificial region is etched to form a pair of support structures and the pair of active structures, wherein the pair of support structures are located below the pair of active structures; An oxide material is deposited over the etched semiconductor substrate to form a shallow trench isolation structure, wherein the shallow trench isolation structure encloses the pair of support structures and the pair of active structures are exposed outside the shallow trench isolation structure; The removal of the semiconductor substrate located above the pair of active structures includes: Etch the pair of support structures above the pair of active structures; Remove the shallow trench isolation structure.

4. The preparation method according to claim 1, characterized in that, The formation of a gate structure based on the pair of active structures includes: A gate dielectric material and a gate metal material are sequentially deposited over the etched semiconductor substrate to form an initial gate structure, wherein the initial gate structure covers the surface of the bottom isolation layer, the sidewalls and surfaces of the pair of active structures, and the sidewalls and surfaces of the dielectric pillars; The initial gate structure is patterned using a photolithography etching process, wherein, compared to the state before etching where the surface of the bottom isolation layer is completely covered, the initial gate structure after etching is partially covered. An interlayer dielectric structure is formed on the initial gate structure after patterning, wherein the height of the interlayer dielectric structure in the vertical direction is the same as the height of the active structure in the vertical direction. The initial gate structure after patterning is etched back to obtain a gate structure, wherein the height of the gate structure in the vertical direction is less than the height of the active structure in the vertical direction.

5. The preparation method according to claim 4, characterized in that, The method of forming a gate structure based on the pair of active structures further includes: An insulating material is deposited over the etched semiconductor substrate to form a bottom isolation layer; The gate structure is formed above the bottom isolation layer, wherein the gate structure covers the surface of the bottom isolation layer, the sidewall of the active structure, and the sidewall of the dielectric pillar; An insulating material is deposited over the portion of the gate structure that covers the sidewall of the active structure to form a top isolation layer.

6. The preparation method according to claim 1, characterized in that, The process of forming a dielectric fork in a semiconductor substrate includes: A hard mask structure is formed over the semiconductor substrate, wherein the hard mask structure has an opening that exposes the semiconductor substrate; Based on the hard mask structure, the exposed semiconductor substrate is etched to form a groove; A medium material is deposited within the groove and the opening to form the medium fork.

7. The preparation method according to claim 1, characterized in that, The length of the gate structure along the first horizontal direction is greater than the length of the gate structure along the second horizontal direction; or... The length of the gate structure along the first horizontal direction is less than the length of the gate structure along the second horizontal direction.

8. The preparation method according to claim 1, characterized in that, The method further includes at least one of the following: A top source / drain metal structure is formed that connects the top source / drain structure; Forming a gate interconnect structure that connects the gate structure; A bottom source / drain metal structure is formed that connects to the bottom source / drain structure.

9. A vertical transistor, characterized in that, The vertical transistor is fabricated using the method described in any one of claims 1 to 8, and comprises: Medium column; Two transistors are located on both sides of the dielectric pillar along a first horizontal direction, wherein each transistor includes a top source-drain structure, a gate structure, and a bottom source-drain structure arranged sequentially along a vertical direction; the active structure of each transistor is connected to the dielectric pillar.

10. A semiconductor device, characterized in that, include: The vertical transistor as described in claim 9.

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