A parallel siC mosfet device and a method of manufacturing the same

Abstract

The application discloses a parallel SiC MOSFET device and a preparation method thereof. The preparation method comprises the following steps: dividing a device epitaxial layer into a cell region and an auxiliary current sharing region, and the auxiliary current sharing region is located at one side edge of the cell region; performing groove etching treatment on the device epitaxial layer through a first preset process to etch a plurality of main grooves in the cell region; performing groove etching treatment on the device epitaxial layer again through a second preset process to etch a plurality of shallow grooves in the auxiliary current sharing region, and the groove depth of the shallow grooves is smaller than the groove depth of the main grooves; performing light doping treatment on the bottom of each shallow groove to form a dynamic current sharing structure; and preparing a gate, a source and a drain on the device epitaxial layer in sequence through a third preset process to obtain the parallel SiC MOSFET device. According to the technical scheme, when the parallel SiC MOSFET device is used in parallel, the dynamic current sharing effect can be achieved through adjustment of the internal structure of the device, and a complex external circuit does not need to be designed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a parallel SiC MOSFET device and a preparation method thereof. BACKGROUND

[0002] In related technologies, when multiple SiC MOSFET devices (i.e. silicon carbide metal oxide semiconductor field effect transistor) are used in parallel, in order to ensure that the current can be evenly distributed to each SiC MOSFET device in the dynamic process of high-speed switching of each SiC MOSFET device, a special circuit layout, topology and auxiliary element configuration are designed to suppress the problem of uneven dynamic current caused by parameter differences and parasitic parameter asymmetry of each SiC MOSFET device. However, it is found in actual application that this way needs to design a complex external circuit, which not only increases the design difficulty, volume and cost of the system, but also introduces additional parasitic parameters (i.e. inconsistency of external elements themselves), weakens the current sharing effect, and even brings new mismatch problems, making it difficult to guarantee the reliability of the overall solution. SUMMARY

[0003] The purpose of the present application is to provide a parallel SiC MOSFET device and a preparation method thereof, aiming to improve the problem that when multiple SiC MOSFET devices are used in parallel, a complex external circuit needs to be designed to perform dynamic current sharing, which not only increases the design difficulty, volume and cost of the system, but also makes it difficult to guarantee the reliability of the overall solution.

[0004] To achieve this purpose, the embodiments of the present application provide a preparation method of a parallel SiC MOSFET device, which comprises:

[0005] The device epitaxial layer is divided into a cell region and an auxiliary current sharing region, and the auxiliary current sharing region is located at one side edge of the cell region;

[0006] A first preset process is performed on the device epitaxial layer to etch a plurality of main grooves in the cell region;

[0007] A second preset process is performed again on the device epitaxial layer to etch a plurality of shallow grooves in the auxiliary current sharing region, and the groove depth of the shallow grooves is smaller than the groove depth of the main grooves;

[0008] The bottom of each shallow groove is subjected to light doping treatment, so that the plurality of shallow grooves form a dynamic current sharing structure;

[0009] The preparation of the gate, the source and the drain is sequentially completed on the device epitaxial layer by a third preset process, so as to obtain the parallel SiC MOSFET device.

[0010] Optionally, in some embodiments of the present application, the trench etching treatment is performed on the device epitaxial layer by the first preset process to etch a plurality of main trenches in the cell region, which comprises:

[0011] A hard mask layer is deposited on the surface of the device epitaxial layer by a chemical vapor deposition process;

[0012] A first photoresist layer is spin-coated on the side of the hard mask layer away from the device epitaxial layer;

[0013] The first mask information containing the main trench region information is sequentially transferred to the first photoresist layer, the hard mask layer and the device epitaxial layer by the combination of the photolithography process and the dry etching process, so as to etch a plurality of the main trenches in the cell region.

[0014] Optionally, in some embodiments of the present application, the first mask information containing the main trench region information is sequentially transferred to the first photoresist layer, the hard mask layer and the device epitaxial layer by the combination of the photolithography process and the dry etching process to etch a plurality of the main trenches in the cell region, which comprises: the first mask information is transferred to the first photoresist layer by the photolithography process; after the first mask information on the first photoresist layer is transferred to the hard mask layer by the dry etching process, the remaining part of the first photoresist layer is removed; and after the first mask information on the hard mask layer is transferred to the device epitaxial layer by the dry etching process to etch a plurality of the main trenches in the cell region, the hard mask layer is removed; and / or,

[0015] The thickness of the hard mask layer is 2 μm ~ 10 μm; and / or,

[0016] The depth of the main trench is 0.8 μm ~ 2 μm.

[0017] Optionally, in some embodiments of the present application, the trench etching treatment is performed again on the device epitaxial layer by the second preset process to etch a plurality of shallow trenches in the auxiliary current equalization region, which comprises:

[0018] A second photoresist layer is spin-coated on the surface of the device epitaxial layer;

[0019] The second mask information containing the shallow trench region information is sequentially transferred to the second photoresist layer and the device epitaxial layer by the combination of the photolithography process and the dry etching process, so as to etch a plurality of the shallow trenches in the auxiliary current equalization region.

[0020] Optionally, in some embodiments of the present application, the second mask information containing the shallow trench region information is sequentially transferred to the second photoresist layer and the device epitaxial layer by the combination of the photolithography process and the dry etching process to etch a plurality of shallow trenches in the auxiliary uniform current area, including: transferring the second mask information to the second photoresist layer by the photolithography process; transferring the second mask information on the second photoresist layer to the device epitaxial layer by the dry etching process to etch a plurality of shallow trenches in the auxiliary uniform current area; and / or,

[0021] The depth of the shallow trench is 0.6 μm ~ 1 μm.

[0022] Optionally, in some embodiments of the present application, the bottom of each shallow trench is subjected to light doping treatment to form a dynamic uniform current structure, including:

[0023] The bottom of each shallow trench is subjected to light doping treatment by ion implantation process to form a dynamic uniform current structure.

[0024] Optionally, in some embodiments of the present application, the preparation of the gate, the source and the drain is sequentially completed on the device epitaxial layer by the third preset process to obtain the parallel SiC MOSFET device, including:

[0025] The plurality of main trenches and the plurality of shallow trenches are sequentially subjected to gate oxide layer growth treatment and gate metal filling treatment by the combination of the thermal oxidation process and the chemical vapor deposition process to complete the preparation of the gate at the plurality of main trenches and the filling treatment of the plurality of shallow trenches at the same time;

[0026] The preset position of the cell area is subjected to preset doping treatment by the combination of the photolithography process and the ion implantation process to define the body injection area and the source area at the preset position;

[0027] The insulating layer and a plurality of source contact holes are formed on the surface of the device epitaxial layer by the combination of the chemical vapor deposition process, the photolithography process and the dry etching process;

[0028] After depositing a metal layer on the surface of the insulating layer and in a plurality of source contact holes by the physical vapor deposition process, the preparation of the source and the drain is completed by continuing the passivation, device thinning and back metallization treatment to obtain the parallel SiC MOSFET device.

[0029] Optionally, in some embodiments of the present application, the filling process of the plurality of shallow trenches is completed at the same time as the preparation of the gate at the plurality of main trenches, including: growing a gate oxide layer on the sidewalls of the plurality of main trenches and the sidewalls of the plurality of shallow trenches by a thermal oxidation process; filling the interiors of the plurality of main trenches and the interiors of the plurality of shallow trenches with a gate metal by a chemical vapor deposition process, so as to complete the filling process of the plurality of shallow trenches at the same time as the preparation of the gate at the plurality of main trenches; and / or,

[0030] The definition of the body injection region and the source region at the preset positions includes: performing first doping treatment on the first preset position of the cell region by the combination of a photolithography process and an ion implantation process, to obtain the body injection region; performing second doping treatment on the second preset position of the cell region by the combination of a photolithography process and an ion implantation process, to obtain the source region; and / or,

[0031] The formation of the insulating layer and the plurality of source contact holes on the surface of the device epitaxial layer includes: depositing the insulating layer on the surface of the device epitaxial layer by a chemical vapor deposition process; spin-coating a third photoresist layer on the surface of the insulating layer; transferring third mask information containing contact hole area information to the third photoresist layer and the insulating layer in sequence by the combination of a photolithography process and a dry etching process, to etch the plurality of source contact holes on the insulating layer.

[0032] Optionally, in some embodiments of the present application, the thickness of the insulating layer is 40 nm-1000 nm; and / or,

[0033] The thickness of the metal layer is 4 μm-10 μm.

[0034] In addition, for this purpose, the embodiments of the present application also provide a parallel SiC MOSFET device, which is prepared by any one of the preparation methods described above.

[0035] The parallel SiC MOSFET device and the preparation method thereof provided by the embodiment of the present application, through the above method steps, the parallel SiC MOSFET device prepared by the method has a dynamic current sharing structure formed by a shallow trench and light doping added at the edge of the device compared with the traditional structure. The structure design can play a buffering role of a capacitor between the gate and the source when an external voltage is suddenly applied (that is, in a transient state, the rate of change of voltage with time dv / dt is a higher value), thereby reducing the influence of the too large rate of change of voltage with time dv / dt when the voltage suddenly changes. That is, the parallel SiC MOSFET device is provided with additional charge regulation capability, thereby relieving the direct influence of voltage mutation on the cell region structure of the parallel SiC MOSFET device, that is, avoiding the problems caused by the early reaching of the threshold voltage and the early opening of the channel, so that the opening time of each parallel SiC MOSFET device is more uniform when the parallel SiC MOSFET device is used in parallel. It can be seen that the parallel SiC MOSFET device prepared by the technical solution can achieve the effect of dynamic current sharing by adjusting the internal structure of the device when used in parallel, without the need to design a complex external circuit. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0037] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the specification, to enable those skilled in the art to understand and read, and do not define the limiting conditions for the implementation of the present application, so they do not have technical significance. Any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0038] Figure 1 The flowchart of the preparation method of the parallel SiC MOSFET device of the embodiment of the present application.

[0039] Figure 2 The preparation process diagram of the parallel SiC MOSFET device of the embodiment of the present application Figure 1 .

[0040] Figure 3 The preparation process diagram of the parallel SiC MOSFET device of the embodiment of the present application Figure 2 .

[0041] Figure 4 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 3 .

[0042] Figure 5 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 4 .

[0043] Figure 6 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 5 .

[0044] Figure 7 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 6 .

[0045] Figure 8 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 7 .

[0046] Figure 9 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 8 .

[0047] Figure 10 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 9 .

[0048] Figure 11 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 10 .

[0049] Figure 12 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 10 .

[0050] Figure 13 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 10 .

[0051] Figure 14 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 10 .

[0052] Figure 15 Preparation process of parallel SiC MOSFET devices for the embodiment of the present application Figure 10 .

[0053] Figure 16 for Figure 1 The flowchart shows the specific steps of S120 in the fabrication method of the parallel SiC MOSFET device.

[0054] Figure 17 for Figure 1 The flowchart shows the specific steps of S130 in the fabrication method of the parallel SiC MOSFET device.

[0055] Figure 18 for Figure 1 The flowchart shows the specific steps of step S150 in the fabrication method of the parallel SiC MOSFET device.

[0056] Figure label:

[0057] 10. Device epitaxial layer; 11. Cell region; 111. Main trench; 12. Auxiliary current equalization region; 121. Shallow trench; 122. Semiconductor thin layer; 20. Hard mask layer; 21. Second notch; 31. First photoresist layer; 311. First notch; 32. Second photoresist layer; 321. Third notch; 33. Third photoresist layer; 331. Fourth notch; 34. Fourth photoresist layer; 341. Fifth notch; 35. Fifth photoresist layer; 351. Sixth notch; 41. Gate oxide layer; 42. Gate metal; 51. Body injection region; 52. Source region; 60. Insulating layer; 61. Source contact hole; 70. Metal layer. Detailed Implementation

[0058] To make the inventive objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0059] In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0060] The technical solution of this application will be further described below with reference to the accompanying drawings and specific embodiments.

[0061] Referring to Figures 1 to 15 As shown in the drawings, in one embodiment, the application provides a preparation method of a parallel SiC MOSFET device, which can specifically include:

[0062] Step S110: dividing the device epitaxial layer into a cell region and an auxiliary current sharing region, the auxiliary current sharing region being located at one side edge of the cell region.

[0063] It should be noted that the preparation method of the parallel SiC MOSFET device of the application is mainly applied in the production and manufacturing of the parallel SiC MOSFET device, that is, the parallel SiC MOSFET device prepared by the preparation method is mainly applied in the scene of parallel use of multiple SiC MOSFET devices.

[0064] The parallel SiC MOSFET device prepared by the preparation method is still essentially a SiC MOSFET device, so its specific preparation process is basically the same as that of a general SiC MOSFET device, and a SiC substrate wafer also needs to be provided to grow a device epitaxial layer 10 on the SiC substrate wafer by a chemical vapor deposition (CVD) process. Different from a general SiC MOSFET device, the entire device epitaxial layer 10 is taken as a cell region 11, and after obtaining the device epitaxial layer 10, the device epitaxial layer 10 is divided into the cell region 11 and an auxiliary current sharing region 12, the auxiliary current sharing region 12 being located at one side edge of the cell region 11, that is, the auxiliary current sharing region 12 is divided at one side edge of the entire device epitaxial layer 10 to set a dynamic current sharing structure in subsequent method steps. It can be understood that the region division in the method steps is a virtual division based on the subsequent device function partition, rather than a physical division actually performed on the device epitaxial layer 10.

[0065] Step S120: performing groove etching treatment on the device epitaxial layer by a first preset process to etch a plurality of main grooves in the cell region.

[0066] It should be noted that after the device epitaxial layer 10 is divided into the cell region 11 and the auxiliary current sharing region 12 by the above method steps, groove etching treatment can be performed on the device epitaxial layer 10 by a first preset process to etch a plurality of main grooves 111 in the cell region 11. The method step is basically consistent with the method step of manufacturing main grooves 111 of a general SiC MOSFET device, that is, groove etching treatment can be performed on the device epitaxial layer 10 by a conventional etching process to complete the preparation of the plurality of main grooves 111. Generally, the number of the plurality of main grooves 111 is preferably three, and the depth of the main grooves 111 is preferably 0.8 μm ~ 2 μm.

[0067] Step S130: again perform trench etching treatment on the device epitaxial layer by a second preset process to etch a plurality of shallow trenches in the auxiliary current sharing region.

[0068] It should be noted that after the preparation of the plurality of main trenches 111 is completed through the above method steps, the device epitaxial layer 10 can be further subjected to trench etching treatment by a second preset process to etch a plurality of shallow trenches 121 in the auxiliary current sharing region 12. The purpose of this method step is to etch a plurality of shallow trenches 121 in the auxiliary current sharing region 12. The shallow trenches 121 differ from the main trenches 111 mainly in the difference in the opening region and the trench depth, that is, the shallow trenches 121 are opened in the auxiliary current sharing region 12 on one side edge of the device epitaxial layer 10, and the trench depth of the shallow trenches 121 is smaller than the trench depth of the main trenches 111. Therefore, the same or similar etching process can be used to perform trench etching treatment on the device epitaxial layer 10 to complete the preparation of the plurality of shallow trenches 121. Generally, the number of the plurality of shallow trenches 121 is preferably two, and the depth of the shallow trenches 121 is preferably 0.6 μm ~ 1 μm.

[0069] Step S140: perform light doping treatment on the bottom of each shallow trench to form a dynamic current sharing structure for the plurality of shallow trenches.

[0070] It should be noted that after the preparation of the plurality of main trenches 111 is completed through the above method steps, the device epitaxial layer 10 can be further subjected to trench etching treatment by a second preset process to etch a plurality of shallow trenches 121 in the auxiliary current sharing region 12. The purpose of this method step is to etch a plurality of shallow trenches 121 in the auxiliary current sharing region 12. The shallow trenches 121 differ from the main trenches 111 mainly in the difference in the opening region and the trench depth, that is, the shallow trenches 121 are opened in the auxiliary current sharing region 12 on one side edge of the device epitaxial layer 10, and the trench depth of the shallow trenches 121 is smaller than the trench depth of the main trenches 111. Therefore, the same or similar etching process can be used to perform trench etching treatment on the device epitaxial layer 10 to complete the preparation of the plurality of shallow trenches 121. Generally, the number of the plurality of shallow trenches 121 is preferably two, and the depth of the shallow trenches 121 is preferably 0.6 μm ~ 1 μm.

[0071] Step S150: sequentially complete the preparation of the gate, the source and the drain on the device epitaxial layer by a third preset process to obtain a parallel SiC MOSFET device.

[0072] It should be noted that after the bottom of each shallow trench 121 is subjected to the light doping treatment through the above method steps, the preparation of the gate, the source and the drain can be continued in the device epitaxial layer 10 through the third preset process to obtain the parallel SiC MOSFET device. The purpose of this method step is to complete the preparation of the main structure of the parallel SiC MOSFET device, i.e. the gate, the source and the drain in the device epitaxial layer 10. This process is roughly the same as the general SiC MOSFET device, i.e. the preparation of the gate, the source and the drain in the device epitaxial layer 10 can be completed through the conventional process to finally obtain the parallel SiC MOSFET device.

[0073] In this way, the preparation method of the parallel SiC MOSFET device of the embodiment of the application, through the above method steps, the parallel SiC MOSFET device prepared has a dynamic current sharing structure formed by the shallow trench 121 and the light doping added at the edge of the device compared with the traditional structure. The structure design can play a buffering role of the capacitor between the gate and the source when the external voltage is suddenly applied (i.e. in the transient state, the rate of change of voltage with time dv / dt is a higher value), which reduces the influence of the too large rate of change of voltage with time dv / dt when the voltage suddenly changes, i.e. provides additional charge regulation capability for the parallel SiC MOSFET device, thereby relieving the direct influence of the voltage sudden change on the cell region structure of the parallel SiC MOSFET device, i.e. avoiding the problem of the channel being turned on in advance due to the threshold voltage being reached in advance, so that the turn-on time of each parallel SiC MOSFET device is more uniform when the parallel SiC MOSFET device is used in parallel. It can be seen that the parallel SiC MOSFET device prepared by the technical solution can achieve dynamic current sharing through the adjustment of the internal structure of the device when used in parallel, without the need to design a complex external circuit.

[0074] In some examples, as shown in Figure 2 , Figure 3 , Figure 4 and Figure 16 , the specific process of performing the above method step of "performing trench etching treatment on the device epitaxial layer through the first preset process to etch a plurality of main trenches in the cell region" can be as follows:

[0075] Step S121: depositing a hard mask layer on the surface of the device epitaxial layer through a chemical vapor deposition process.

[0076] Step S122: spin coating a first photoresist layer on the side of the hard mask layer away from the device epitaxial layer.

[0077] Step S123: by the combination of the photolithography process and the dry etching process, the first mask information containing the main trench area information is sequentially transferred to the first photoresist layer, the hard mask layer and the device epitaxial layer, so as to etch a plurality of main trenches in the cell region.

[0078] It should be noted that when the hard mask layer 20 is deposited on the surface of the device epitaxial layer 10 by the chemical vapor deposition process, the above method step can specifically deposit a hard mask layer 20 with a thickness of preferably 2 μm ~ 10 μm on the upper surface of the device epitaxial layer 10, so as to ensure that the hard mask layer 20 can provide good etching protection in the subsequent etching process of the main trench 111. The first mask information containing the main trench area information mentioned in the above method step specifically refers to that the planar pattern, size and position distribution of all the main trenches 111 that need to be etched in the cell region 11 of the device epitaxial layer 10 can be accurately defined by the first mask information. The first mask information takes the light-shielding / transmissive pattern on the mask as the carrier, and is the direct basis and spatial positioning template for the subsequent photolithography and etching process to physically and sequentially transfer the design blueprint of the main trench 111 to the first photoresist layer 31, the hard mask layer 20 and the device epitaxial layer 10.

[0079] In this way, by the above method steps, a corresponding number of main trenches 111 located at corresponding positions can be etched in the cell region 11.

[0080] In some examples, the specific process of performing the above method step "by the combination of the photolithography process and the dry etching process, the first mask information containing the main trench area information is sequentially transferred to the first photoresist layer, the hard mask layer and the device epitaxial layer, so as to etch a plurality of main trenches in the cell region" can be as follows: first, the first mask information is transferred to the first photoresist layer 31 by the photolithography process (i.e. to make the first photoresist layer 31 form a structure with a plurality of first notches 311 as shown in FIG. 11B). Then, the first mask information on the first photoresist layer 31 is transferred to the hard mask layer 20 by the dry etching process (i.e. to make the hard mask layer 20 form a structure with a plurality of second notches 221 as shown in FIG. 11C). Finally, the first mask information on the hard mask layer 20 is transferred to the device epitaxial layer 10 by the dry etching process (i.e. to make the device epitaxial layer 10 form a structure with a plurality of main trenches 111 as shown in FIG. 11D). Figure 2 Figure 3 ​After the structure with several second notches 21 is shown, the remaining part of the first photoresist layer 31 is removed. Finally, the first mask information on the hard mask layer 20 is transferred to the device epitaxial layer 10 again through the dry etching process, so as to etch a plurality of main trenches 111 in the cell region 11, and then remove the hard mask layer 20. In this way, through the precise combination of photolithography and dry etching process, the pattern of the first mask information is first copied to the first photoresist layer 31 with high fidelity, and then the pattern is accurately transferred to the hard mask layer 20 with the first photoresist layer 31 as a mask. Finally, the etching of the device epitaxial layer 10 is completed by the hard mask layer 20 as a durable mask. This process of layer-by-layer transfer effectively ensures the uniformity of the depth of the main trench 111 etching and the vertical regularity of the side wall shape by using the excellent etching resistance of the hard mask layer 20, thereby providing a key process guarantee for the consistency and reliability of the device performance.

[0081] It should be noted that in the process of removing the hard mask layer 20 after the above method steps etch a plurality of main trenches 111 in the cell region 11, the hard mask layer 20 can be removed by wet etching, so that it can realize the fast, uniform and selective removal of the hard mask layer 20, while avoiding physical damage or erosion to the main trench 111 structure formed. This process is simple and efficient, which helps to clean the surface after the formation of the key structure, provides a flat and residue-free starting interface for the subsequent shallow trench 121 etching and dynamic current sharing structure preparation, and guarantees the smooth connection of the process flow and the stability of the device performance.

[0082] In some examples, as shown in Figure 5 , Figure 6 and Figure 17 , the specific process of performing the above method step "etching a plurality of shallow trenches in the auxiliary current sharing region through a second preset process again" can be as follows:

[0083] Step S131: spin-coating a second photoresist layer on the surface of the device epitaxial layer.

[0084] Step S132: through the combination of photolithography and dry etching process, the second mask information containing the shallow trench area information is sequentially transferred to the second photoresist layer and the device epitaxial layer, so as to etch a plurality of shallow trenches in the auxiliary current sharing region 12.

[0085] It should be noted that the second mask information containing the shallow trench region information mentioned in the above method steps specifically refers to the planar pattern, size and position distribution of all shallow trenches 121 that need to be etched in the auxiliary current uniformization area 12 of the device epitaxial layer, which can be accurately defined by the second mask information. The second mask information is carried by the light-shielding / transmissive pattern on the mask, and is the direct basis and spatial positioning template for the subsequent photolithography and etching process to physically transfer the design blueprint of the shallow trenches 121 to the second photoresist layer 32 and the device epitaxial layer in sequence.

[0086] In this way, through the above method steps, the corresponding number and position of the shallow trenches 121 can be well etched in the auxiliary current uniformization area 12.

[0087] In some examples, the specific process of performing the above method step "transferring the second mask information containing the shallow trench region information to the second photoresist layer and the device epitaxial layer in sequence by the combination of photolithography and dry etching process, to etch a plurality of shallow trenches in the auxiliary current uniformization area" can be as follows: transferring the second mask information to the second photoresist layer 32 by photolithography (i.e. making the second photoresist layer 32 form a structure with a plurality of third openings 321 as shown in Figure 5 transferring the second mask information on the second photoresist layer 32 to the device epitaxial layer 10 by dry etching, to etch a plurality of shallow trenches 121 in the auxiliary current uniformization area 12 (at this time, the remaining part of the second photoresist layer 32 is not removed yet, so as to facilitate the subsequent light doping treatment for the bottom of each shallow trench 121 by shielding of the second photoresist layer 32). In this way, the accurate transfer of the second mask information to the second photoresist layer 32 by photolithography defines the pattern position of the shallow trenches 121 on the auxiliary current uniformization area 12. Subsequently, the pattern is accurately etched to the auxiliary current uniformization area 12 of the device epitaxial layer 10 by dry etching, so as to form a shallow trench 121 structure with controllable groove depth and consistent topography. This process combination realizes the precise processing of the size and distribution of the shallow trenches 121, lays a reliable physical foundation for the subsequent formation of the dynamic current uniformization functional area, and ensures the controllability and consistency of the current uniformization effect.

[0088] In some examples, as shown in Figure 7 and Figure 8 the specific process of performing the above method step "light doping treatment is performed on the bottom of each shallow trench, so as to form a plurality of shallow trenches 121 into a dynamic current uniformization structure" can be as follows: light doping treatment is performed on the bottom of each shallow trench 121 by ion implantation process, so as to form a plurality of shallow trenches 121 into a dynamic current uniformization structure, which can be specifically performed under the shielding of the second photoresist layer 32. When the corresponding light doping treatment is completed, the remaining part of the second photoresist layer 32 can be removed, so as to form Figure 8The shallow trench 121 is subjected to a light doping process by an ion implantation process. In this way, the impurity type, dose and depth can be precisely controlled, and a semiconductor thin layer 122 with an engineered resistance is formed at the bottom of the trench. This step is the core of the construction of the dynamic current sharing function area. The controlled resistance introduced can automatically adjust the potential and current distribution of each parallel branch during switching, thereby achieving efficient and adaptive dynamic current sharing inside the device, and significantly improving the stability and reliability of parallel operation.

[0089] In some examples, as shown in FIG. 1 1, the specific process of performing the above method step of "preparing the gate, source and drain of the device in sequence on the device epitaxial layer by the third preset process to obtain the parallel SiC MOSFET device" can be as follows: Figures 9 to 15 、 Figure 18 In some examples, as shown in FIG. 1 1, the specific process of performing the above method step of "preparing the gate, source and drain of the device in sequence on the device epitaxial layer by the third preset process to obtain the parallel SiC MOSFET device" can be as follows:

[0090] Step S151: By the combination of thermal oxidation process and chemical vapor deposition process, the gate oxide layer growth process and the gate metal filling process are performed on the plurality of main trenches and the plurality of shallow trenches in sequence, so as to complete the preparation of the gate at the plurality of main trenches and complete the filling process of the plurality of shallow trenches.

[0091] It should be noted that the purpose of this method step is to complete the preparation of the gate while completing the filling process of the plurality of shallow trenches 121. The specific process can be as follows: first, the gate oxide layer 41 is grown on the sidewalls of the plurality of main trenches 1 1 1 and the sidewalls of the plurality of shallow trenches 121 by a thermal oxidation process. Then, the gate metal 42 is filled into the plurality of main trenches 1 1 1 and the plurality of shallow trenches 121 by a chemical vapor deposition process, so as to complete the preparation of the gate (i.e., the gate metal 42 located in the cell area 1 1 ) at the plurality of main trenches 1 1 1 while completing the filling process of the plurality of shallow trenches 121. Since the thermal oxidation process has no area selectivity, the gate oxide layer 41 will also grow on the surface of the device epitaxial layer 10. Similarly, since the chemical vapor deposition process also has no area selectivity, a layer of gate metal 42 will also be deposited on the surface of the device epitaxial layer 10. After the corresponding process is completed, the gate metal 42 on the surface of the device epitaxial layer 10 can be removed by chemical mechanical polishing, so that it only exists in the trench. Since the main trench 1 1 1 and the shallow trench 121 are not connected in design, the gate metal 42 filled in the two is also insulated from each other. After the gate metal 42 on the surface of the device epitaxial layer 10 is removed, a wet etching process (for example, using a diluted hydrofluoric acid solution) is used to selectively remove the gate oxide layer 41 on the surface of the device epitaxial layer 10. This is because the etching rate of hydrofluoric acid on silicon oxide (gate oxide) is much higher than that on single crystal silicon carbide (epitaxial layer) or metal, so that the oxide layer on the surface of the device epitaxial layer 10 can be accurately removed without damaging the underlying SiC material or the gate structure in the trench.

[0092] Step S152: The pre-set positions of the cell region are subjected to pre-set doping treatment by the combination of the photolithography process and the ion implantation process, so as to define the body injection region and the source region at the pre-set positions.

[0093] It should be noted that the purpose of the method step is to complete the preparation of the source electrode, and the specific process can be as follows: first, the first pre-set position of the cell region 11 is subjected to first doping treatment (which can be P-type doping treatment in particular) by the combination of the photolithography process and the ion implantation process, to obtain the body injection region 51, that is, as shown in Figure 11 After the fourth mask information containing the first pre-set position region information is transferred to the fourth photoresist layer 34 by the photolithography process (i.e., so that the fourth photoresist layer 34 forms a structure having a plurality of fifth openings 341 as shown in Figure 11 ), the first pre-set position of the cell region 11 is subjected to corresponding doping treatment by the ion implantation process using the shielding of the fourth photoresist layer 34, to obtain the body injection region 51. Then, the second pre-set position of the cell region 11 is subjected to second doping treatment (which can be N-type doping treatment in particular) by the combination of the photolithography process and the ion implantation process, to obtain the source region 52 (i.e., the source electrode heavily doped region), that is, as shown in Figure 12 After the fifth mask information containing the second pre-set position region information is transferred to the fifth photoresist layer 35 by the photolithography process (i.e., so that the fifth photoresist layer 35 forms a structure having a plurality of sixth openings 351 as shown in Figure 12 ), the second pre-set position of the cell region 11 is subjected to corresponding doping treatment by the ion implantation process using the shielding of the fifth photoresist layer 35, to obtain the source region 52.

[0094] Step S153: The insulating layer and a plurality of source electrode contact holes are formed on the surface of the device epitaxial layer by the combination of the chemical vapor deposition process, the photolithography process and the dry etching process.

[0095] It should be noted that the purpose of the method step is to complete the preparation of the insulating layer 60, and the specific process can be as follows: first, the insulating layer 60 is deposited on the surface of the device epitaxial layer 10 by the chemical vapor deposition process. The third photoresist layer 33 is spin-coated on the surface of the insulating layer 60. Then, the third mask information containing the contact hole region information is transferred to the third photoresist layer (i.e., so that the third photoresist layer 33 forms a structure having a plurality of fourth openings 331 as shown in Figure 14 ) and the insulating layer 60 in sequence by the combination of the photolithography process and the dry etching process, to etch a plurality of source electrode contact holes 61 in the insulating layer 60. Generally, the thickness of the insulating layer 60 is preferably 40 nm ~ 1000 nm.

[0096] Step S154: After the metal layer is deposited on the surface of the insulating layer and in the source contact holes by the physical vapor deposition process, the preparation of the drain is completed by continuing the passivation, device thinning and back metallization processes, and a parallel SiC MOSFET device is obtained.

[0097] It should be noted that the method step deposits a metal layer 70 with a thickness preferably of 4-10 μm on the surface of the insulating layer 60 by the physical vapor deposition process, and at the same time, the metal layer 70 fills the source contact holes 61, so as to realize the extraction of the source region 52, and then complete the preparation of the source (i.e. the metal layer 70) on the front surface (i.e. the upper surface as shown) of the device. Subsequently, the conventional passivation process is performed to protect the surface of the device from the environment, and after the device thickness and thermal resistance are optimized by the conventional device thinning process, the low-resistance and reliable drain ohmic contact is formed by the back metallization, i.e. the preparation of the drain (not shown) is completed on the back surface (i.e. the lower surface as shown) of the device. This series of processes completely constructs the electrode system and physical structure of the device, and ensures that the parallel SiC MOSFET device has good heat dissipation capacity, electrical performance and long-term working reliability. Figure 15 Figure 15 In this way, by the above method steps, not only the preparation of the main trench 111 gate is completed, but also the shallow trench 121 of the auxiliary current sharing region 12 is filled with the gate material at the same time, simplifying the process steps. The accurate patterning of the source region 52 and the insulating layer 60 ensures the function and isolation of the key regions of the device. Finally, by the combination of the front metal layer deposition and the back metallization process, the complete source and drain electrodes are efficiently constructed, thereby realizing the synchronous manufacturing of the high-performance parallel SiC MOSFET device and the built-in dynamic current sharing structure, and improving the overall performance and production efficiency of the device.

[0098] In this way, by the above method steps, not only the preparation of the main trench 111 gate is completed, but also the shallow trench 121 of the auxiliary current sharing region 12 is filled with the gate material at the same time, simplifying the process steps. The accurate patterning of the source region 52 and the insulating layer 60 ensures the function and isolation of the key regions of the device. Finally, by the combination of the front metal layer deposition and the back metallization process, the complete source and drain electrodes are efficiently constructed, thereby realizing the synchronous manufacturing of the high-performance parallel SiC MOSFET device and the built-in dynamic current sharing structure, and improving the overall performance and production efficiency of the device.

[0099] In one embodiment, as shown in Figure 15 the parallel SiC MOSFET device prepared by the preparation method of the above embodiment. In this way, since the parallel SiC MOSFET device of the embodiment of the application is prepared by the preparation method of the above embodiment, it can achieve the effect of dynamic current sharing through the adjustment of the internal structure of the device when used in parallel, without the need to design a complex external circuit.

[0100] ​The above-described embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for fabricating a parallel SiC MOSFET device, characterized in that, The preparation method includes: The epitaxial layer of the device is divided into a cell region and an auxiliary current sharing region, wherein the auxiliary current sharing region is located at one edge of the cell region; A trench etching process is performed on the epitaxial layer of the device using a first preset process to etch a number of main trenches in the cell region. The device epitaxial layer is subjected to trench etching again through a second preset process to etch several shallow trenches in the auxiliary current equalization region. The depth of the shallow trenches is less than the depth of the main trench. The bottom of each of the shallow trenches is lightly doped to form a dynamic flow-equalizing structure in the shallow trenches. The parallel SiC MOSFET device is obtained by sequentially fabricating the gate, source, and drain on the device epitaxial layer through a third preset process, including: sequentially growing gate oxide layers and filling gate metals in a plurality of main trenches and a plurality of shallow trenches through a combination of thermal oxidation and chemical vapor deposition processes, so as to complete the fabrication of the gate in a plurality of main trenches and the filling process of a plurality of shallow trenches at the same time.

2. The preparation method according to claim 1, characterized in that, The process of performing trench etching on the epitaxial layer of the device through a first preset process to etch a plurality of main trenches in the cell region includes: A hard mask layer is deposited on the surface of the epitaxial layer of the device using a chemical vapor deposition process. A first photoresist layer is spin-coated on the side of the hard mask layer away from the epitaxial layer of the device. By combining photolithography and dry etching processes, the first photomask information containing the main trench region information is sequentially transferred to the first photoresist layer, the hard mask layer, and the device epitaxial layer to etch a plurality of the main trenches in the cell region.

3. The preparation method according to claim 2, characterized in that, The method of transferring first photomask information containing information about the main trench region sequentially to the first photoresist layer, the hard mask layer, and the device epitaxial layer through a combination of photolithography and dry etching processes to etch a plurality of the main trenches in the cell region includes: transferring the first photomask information to the first photoresist layer through photolithography; transferring the first photomask information on the first photoresist layer to the hard mask layer through dry etching, and then removing the remaining portion of the first photoresist layer; transferring the first photomask information on the hard mask layer to the device epitaxial layer through dry etching, and then removing the hard mask layer after etching a plurality of the main trenches in the cell region; and / or, The thickness of the hard mask layer is 2μm~10μm; and / or, The depth of the main trench is 0.8μm to 2μm.

4. The preparation method according to claim 1, characterized in that, The second preset process is used to perform trench etching on the epitaxial layer of the device again to etch several shallow trenches in the auxiliary current equalization region, including: A second photoresist layer is spin-coated onto the surface of the epitaxial layer of the device; By combining photolithography and dry etching processes, the second photomask information containing information about the shallow trench region is sequentially transferred to the second photoresist layer and the device epitaxial layer, so as to etch a plurality of the shallow trenches in the auxiliary current equalization region.

5. The preparation method according to claim 4, characterized in that, The method of transferring second photomask information containing shallow trench region information sequentially to the second photoresist layer and the device epitaxial layer through a combination of photolithography and dry etching processes to etch a plurality of shallow trenches in the auxiliary current equalization region includes: transferring the second photomask information to the second photoresist layer through photolithography; transferring the second photomask information on the second photoresist layer to the device epitaxial layer through dry etching processes to etch a plurality of shallow trenches in the auxiliary current equalization region; and / or, The depth of the shallow trench is 0.6μm to 1μm.

6. The preparation method according to claim 1, characterized in that, The step of lightly doping the bottom of each of the shallow trenches to form a dynamic flow-equalizing structure in the shallow trenches includes: The bottom of each of the shallow trenches is lightly doped using an ion implantation process to create a dynamic flow-equalizing structure in the shallow trenches.

7. The preparation method according to any one of claims 1-6, characterized in that, The process of sequentially fabricating the gate, source, and drain on the epitaxial layer of the device using a third preset process to obtain the parallel SiC MOSFET device further includes: By combining photolithography and ion implantation, a preset doping process is performed on a preset position of the cell region to define the bulk implantation region and the source region at the preset position. An insulating layer and several source contact holes are formed on the surface of the epitaxial layer of the device by combining chemical vapor deposition, photolithography and dry etching processes. After depositing a metal layer on the surface of the insulating layer and in several source contact holes using a physical vapor deposition process, passivation, device thinning, and back-side metallization are performed to complete the fabrication of the source and drain, thus obtaining the parallel SiC MOSFET device.

8. The preparation method according to claim 7, characterized in that, The process of simultaneously fabricating the gate at the main trenches and filling the shallow trenches includes: growing a gate oxide layer on the sidewalls of the main trenches and the sidewalls of the shallow trenches using a thermal oxidation process; and filling the interiors of the main trenches and the shallow trenches with gate metal using a chemical vapor deposition process, so as to simultaneously fabricate the gate at the main trenches and fill the shallow trenches; and / or, The step of defining the body implantation region and the source region at the preset positions includes: performing a first doping treatment on a first preset position of the cell region using a combination of photolithography and ion implantation processes to obtain the body implantation region; performing a second doping treatment on a second preset position of the cell region using a combination of photolithography and ion implantation processes to obtain the source region; and / or, The process of forming an insulating layer and a plurality of source contact holes on the surface of the epitaxial layer of the device includes: depositing the insulating layer on the surface of the epitaxial layer of the device by chemical vapor deposition; spin-coating a third photoresist layer on the surface of the insulating layer; and sequentially transferring third photomask information containing information about the contact hole region to the third photoresist layer and the insulating layer by a combination of photolithography and dry etching processes, so as to etch a plurality of the source contact holes on the insulating layer.

9. The preparation method according to claim 7, characterized in that, The thickness of the insulating layer is 40 nm to 1000 nm; and / or, The thickness of the metal layer is 4μm to 10μm.

10. A parallel SiC MOSFET device, characterized in that, The parallel SiC MOSFET device is prepared by the preparation method described in any one of claims 1-9.

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