Semiconductor device and data storage system including the same

Abstract

The invention provides a semiconductor device, a data storage system including the semiconductor device, and a manufacturing method. In one aspect, a semiconductor device includes: a substrate including an upper surface and a lower surface; a gate structure having a first length in a first direction and disposed on the substrate; a drain region extending from an upper surface of the substrate at a first side of the gate structure; a source region extending from the upper surface of the substrate and located on the second side of the gate structure; the channel region extends from the upper surface of the substrate, is positioned below the gate structure, and is positioned between the drain region and the source region; and a first separation trench structure extending in the second direction from the lower surface of the substrate, disposed in a boundary region between the channel region and the drain region, and spaced apart from the upper surface of the substrate.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and data storage systems including such semiconductor devices. Background Technology

[0002] In data storage systems, semiconductor devices capable of storing large amounts of data are required. Therefore, methods to increase the data storage capacity of semiconductor devices have been investigated. For example, as one method to increase the data storage capacity of semiconductor devices, semiconductor devices comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells have been proposed. Furthermore, the circuit elements driving the memory cells include complementary metal-oxide-semiconductor (CMOS) transistors and high-voltage transistors to which several to tens of volts are applied. Summary of the Invention

[0003] One aspect of this disclosure is to provide a semiconductor device in which drain-induced barrier lowering (DiBL) is prevented by forming a separation structure in a high-voltage transistor that blocks the lower part of the drain region from the channel region, thereby improving cutoff characteristics.

[0004] One aspect of this disclosure is to provide a data storage system including a semiconductor device that has improved cutoff characteristics by blocking current from flowing from the drain region to a region other than the channel region in a high-voltage transistor.

[0005] A semiconductor device according to one or more embodiments includes: a substrate including an upper surface and a lower surface; a gate structure located on the upper surface of the substrate and having a first length in a first direction parallel to the upper surface of the substrate; a drain region disposed in the substrate and extending from the upper surface of the substrate on a first side of the gate structure in the first direction; a source region disposed in the substrate and extending from the upper surface of the substrate on a second side of the gate structure in the first direction, the second side of the gate structure being opposite to the first side of the gate structure in the first direction; a channel region disposed in the substrate and extending from the upper surface of the substrate, located below the gate structure and between the drain region and the source region; and a first separating trench structure extending from the lower surface of the substrate in a second direction perpendicular to the first direction, disposed in a boundary region between the channel region and the drain region, and spaced apart from the upper surface of the substrate.

[0006] A semiconductor device according to one or more embodiments includes: a cell structure including a gate electrode, a channel structure extending through the gate electrode, and a contact plug connected to the gate electrode; and a peripheral circuit structure including: a substrate electrically connected to the cell structure, the substrate having an upper surface and a lower surface; a first element region and a second element region located in the substrate; an N-type first circuit element and a P-type second circuit element located in the first element region; and an N-type third circuit element and a P-type fourth circuit element located in the second element region, wherein at least one of the N-type third circuit elements includes: a gate structure located on the upper surface of the substrate, the gate structure including a gate dielectric layer and a gate conductive layer located on the gate dielectric layer, the thickness of the gate dielectric layer of the gate structure being greater than that of the N-type first circuit element and the P-type second circuit element. The thickness of the gate dielectric layer; a drain region disposed in the substrate and extending from the upper surface of the substrate on a first side of the gate structure in a first direction parallel to the upper surface of the substrate; a source region disposed in the substrate and extending from the upper surface of the substrate on a second side of the gate structure opposite to the first side of the gate structure in the first direction; a channel region disposed in the substrate and extending from the upper surface of the substrate, located below the gate structure and between the drain region and the source region; and a partition trench structure extending from the lower surface of the substrate in a second direction perpendicular to the first direction and spaced apart from the upper surface of the substrate, the partition trench structure being disposed in the boundary region between the channel region and the drain region.

[0007] A data storage system includes: a semiconductor memory device, the semiconductor memory device comprising: a substrate; a first substrate structure including a first circuit element, a second circuit element, a third circuit element, and a fourth circuit element located on the substrate; and a second substrate structure including memory cells and input and output pads electrically connected to the first circuit element to the fourth circuit element; and a controller electrically connected to the semiconductor memory device via the input and output pads and controlling the semiconductor memory device, wherein the first circuit element includes an NMOS transistor for low-voltage driving, the second circuit element includes a PMOS transistor for low-voltage driving, the third circuit element includes an NMOS transistor for high-voltage driving, and the fourth circuit element includes a PMOS transistor for high-voltage driving, and each of the third circuit elements includes: a gate structure located on the upper surface of the substrate, the gate structure including a gate dielectric layer and a gate conductive layer located on the gate dielectric layer, the... The thickness of the gate dielectric layer of the gate structure is greater than the thickness of the gate dielectric layers of the first circuit element and the second circuit element; a drain region is disposed in the substrate and extends from the upper surface of the substrate on a first side of the gate structure in a first direction, the first direction being parallel to the upper surface of the substrate; a source region is disposed in the substrate and extends from the upper surface of the substrate on a second side of the gate structure, the second side of the gate structure being opposite to the first side of the gate structure in the first direction; a channel region is disposed in the substrate and extends from the upper surface of the substrate, located below the gate structure and between the drain region and the source region; and a partition trench structure extends from the lower surface of the substrate in a second direction perpendicular to the first direction, the partition trench structure being disposed in the boundary region between the channel region and the drain region, and the partition trench structure having an upper end spaced apart from the upper surface of the substrate.

[0008] To prevent the diffusion of the depletion region of the drain region in a high-voltage NMOS transistor, the cutoff characteristics can be improved by forming a separation structure between the drain region and the channel region, physically isolating the drain region from the lower substrate of the channel region. This improves device reliability.

[0009] The aspects to be addressed by this disclosure are not limited to those described above, and those skilled in the art will clearly understand from the following description. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic plan view of an example semiconductor device; Figure 2 It is based on Figure 1 A partial enlarged view of a semiconductor device according to one or more embodiments.

[0011] Figures 3A to 3D It is based on Figure 1 A cross-sectional view of a semiconductor device according to one or more embodiments; Figure 4 and Figure 5 This is a schematic cross-sectional view of an example semiconductor device; Figure 6A This is a plan view of an example semiconductor device, and Figure 6B yes Figure 6A A cross-sectional view of an example semiconductor device; Figure 7 This is a schematic cross-sectional view of an example semiconductor device; Figure 8 This is a schematic cross-sectional view of an example semiconductor device used as a memory device; Figure 9A and Figure 9B yes Figure 8 A magnified view of a portion of a semiconductor device; Figure 10 This is a cross-sectional view of an example semiconductor device; Figures 11A to 11K This is a schematic cross-sectional view illustrating an example method of manufacturing a semiconductor device; Figure 12 This is a schematic view illustrating an example data storage system including semiconductor devices; and Figure 13 This is a schematic perspective view of an example data storage system including semiconductor devices. Detailed Implementation

[0012] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. It will be understood that expressions such as “on,” “above,” “upper,” “below,” “under,” “lower,” and “side surface” are used only in light of the drawings unless they are indicated by the drawings and individually referenced.

[0013] Figure 1 It is a schematic plan view of a semiconductor device according to one or more embodiments. Figure 2 It is based on Figure 1 A partial enlarged view of a semiconductor device according to one or more embodiments.

[0014] Figures 3A to 3D It is based on Figure 1 A cross-sectional view of a semiconductor device according to one or more embodiments, and Figure 3A It is along Figure 1 A cross-sectional view of a semiconductor device taken along line I-I'. Figure 3B It is along Figure 1 A cross-sectional view of a semiconductor device taken along line II-II'. Figure 3C It is along Figure 1 A cross-sectional view of the semiconductor device taken from line III-III', and Figure 3D It is along Figure 1 A cross-sectional view of a semiconductor device taken along line IV-IV'.

[0015] Semiconductor device 10 may include an NMOS region NR and a PMOS region PR. Semiconductor device 10 may include a substrate 1, a device isolation layer 21 located in the substrate 1, and a first circuit element TR disposed in the NMOS region NR on the substrate 1 as an NMOS transistor. N and a second circuit element TR, which serves as a PMOS transistor, disposed on substrate 1 in the PMOS region PR. P .

[0016] The substrate 1 may have an upper surface Sf extending in the X and Y directions and a lower surface Sr opposite to the upper surface Sf. A device isolation layer 21 may be formed on the substrate 1 to define an active region. First and second source / drain regions D including impurities. N S N D P and S P It can be disposed in some active regions. The substrate 1 can include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, the substrate 1 can be provided as a single-crystal silicon wafer.

[0017] When both the NMOS region NR and the PMOS region PR are disposed in the substrate 1, and the substrate 1 is a P-type substrate, a well region 5 can be disposed in the substrate 1 to define the PMOS region PR. The well region 5 can be a region doped with N-type impurities. However, this disclosure is not limited to this, and a well region doped with P-type impurities can also be disposed in the substrate 1 to define the NMOS region NR. Substrate pad regions 3 for applying body voltage to the NMOS region NR and the PMOS region PR can be disposed, and multiple substrate pad regions 3 can be disposed mainly in the edge regions. When the substrate pad region 3 includes a well region, the substrate pad region 3 can be disposed in the well region 5, and can be a highly doped region.

[0018] The device isolation layer 21 can define an active region in the substrate 1. The device isolation layer 21 can be disposed in the NMOS region NR and the PMOS region PR, respectively, and when the NMOS region NR and / or the PMOS region PR includes a well region 5, the NMOS region NR and / or the PMOS region PR can be configured to define the active region of each transistor in the well region 5. For example, the device isolation layer 21 can be formed in a shallow trench isolation (STI) process. In some embodiments, the arrangement shape and depth of the device isolation layer 21 can be varied. The device isolation layer 21 can be formed of an insulating material. The device isolation layer 21 can be, for example, an oxide, a nitride, or a combination thereof.

[0019] In the NMOS region NR, the first circuit element TR N It can be arranged in a matrix. The first circuit element TR N It can be disposed on the upper surface Sf of substrate 1 and can include planar transistors. Each first circuit element TR N It may include a first gate structure GS N First source / drain region D N and S N and the first gate spacer 40, the first gate structure GS N Including the first gate electrode structure GE N and the first gate dielectric layer 20.

[0020] First circuit element TR N Gate structure GS N Second circuit element TR P Gate structure GS P The stacked structures can be identical to each other.

[0021] As a planar transistor, the first circuit element TR N It may include a first gate structure GS having a first height h1 at a distance of 1 from the upper surface Sf of the substrate 1. N .

[0022] First gate structure GS N It may include a first gate electrode structure GE N and the first gate dielectric layer 20, the first gate structure GS N It has a first width Wg in the X direction and a first length L1 in the Y direction. First gate electrode structure GE N It may include a lower conductive layer 35 and an upper conductive layer 37.

[0023] The first gate dielectric layer 20 may include a low-k material, such as an oxide or nitride, and may preferably include a silicon oxide film (SiO2). The first gate dielectric layer 20 may have a first thickness T1, and the first thickness T1 may be approximately 40 nm to 50 nm, but this disclosure is not limited thereto.

[0024] First gate electrode structure GE N It can be disposed on the first gate dielectric layer 20, and can include at least two layers, but this disclosure is not limited thereto. First gate electrode structure GE N It may include a lower conductive layer 35 and an upper conductive layer 37.

[0025] The lower conductive layer 35 may include polycrystalline silicon, but this disclosure is not limited thereto, and the upper conductive layer 37 may include a metal such as tungsten or aluminum. An ohmic contact layer 38 may be further included between the lower conductive layer 35 and the upper conductive layer 37, and the ohmic contact layer 38 may include titanium nitride (TiN) and tantalum nitride (TaN), but this disclosure is not limited thereto. The thickness of the ohmic contact layer 38 may be significantly less than the thicknesses of the lower conductive layer 35 and the upper conductive layer 37.

[0026] Mask layer 39 can be further included in the first gate electrode structure GE N The upper part. Mask layer 39 may include silicon nitride and silicon oxynitride.

[0027] Gate spacer 40 can be disposed in the first gate structure GS in the Y direction. N On both side surfaces. The gate spacer 40 can be formed of at least one of oxide, nitride or oxynitride, and can be formed of a low-k film.

[0028] First source / drain region D N and S N It is possible to have a gate structure GS in the Y direction N The two sides are disposed on the upper surface Sf of substrate 1. The first source / drain region D N and S N The first gate structure GS can be disposed in the Y direction from the upper surface Sf of the substrate 1 inward to a first depth d1. N Both sides include impurities. First source / drain region D N and S N It can have a second width Wd in the X direction, and the second width Wd can be equal to or less than the first gate structure GS. N The first width Wg, and can be included within the first width Wg. Therefore, the first source / drain region D N and S N It can be connected to the first gate structure GS in the Y direction. N alignment.

[0029] First source / drain region D N and S N Each of these can include a low-concentration doped region 2 and a high-concentration doped region 4. The low-concentration doped region 2 can be configured to extend from the first gate structure GS in the Z direction. N The region is offset and can be doped with a low concentration of impurities up to a first depth d1. The first depth d1 can be approximately 40 nm to 50 nm in length. The doping depth of the high-concentration doped region 4 can be shallower than the first depth d1 of the low-concentration doped region 2, and the depth of the high-concentration doped region 4 can be 10 nm to 12 nm, but this disclosure is not limited thereto.

[0030] First source region S N The low-concentration doped region 2 and the high-concentration doped region 4 are doped with impurities of the same conductivity type, and only their doping concentrations can differ from each other. The area of ​​the high-concentration doped region 4 can be smaller than the area of ​​the low-concentration doped region 2, and the high-concentration doped region 4 can be connected to the first gate structure GS. N Spacing them apart so as not to interact with the first gate structure GS in the XY plane. N Overlapping. Therefore, the highly doped region 4 can essentially be used as the first source region S. N Furthermore, the low-concentration doped region 2 can be a diffusion region of the high-concentration doped region 4, but this disclosure is not limited thereto.

[0031] First drain region D N The low-concentration doped region 2 and the high-concentration doped region 4 are doped with impurities of the same conductivity type, and only their doping concentrations can differ from each other. The area of ​​the high-concentration doped region 4 can be smaller than the area of ​​the low-concentration doped region 2, and the high-concentration doped region 4 and the low-concentration doped region 2 can be connected to the first gate structure GS. N Spacing them apart so as not to interact with the first gate structure GS in the XY plane. N Overlap. The low-concentration doped region 2 can have the same characteristics as the first source region S. N The low-concentration doped region 2 has the same first depth d1, and the high-concentration doped region 4 can also be doped at a shallower depth than the low-concentration doped region 2. Therefore, the high-concentration doped region 4 is essentially used as the drain region, and the low-concentration doped region 2 can be the diffusion region of the high-concentration doped region 4, but this disclosure is not limited thereto.

[0032] First source / drain region D N and S NThe doping concentration of the high-concentration doped regions 4 in each of the structures can be the same, and the doping concentration of the low-concentration doped regions 2 can also be the same, but this disclosure is not limited thereto. Furthermore, the separation distance between the high-concentration doped regions 4 can be greater than the separation distance between the low-concentration doped regions 2, and the separation distance between the low-concentration doped regions 2 can be substantially equal to that of the first gate structure GS. N The first length L1 can be defined as the channel length and can be approximately 1 μm to 1.2 μm, but this disclosure is not limited thereto. The first depth d1 of the low-concentration doped region 2 can have a depth shallower than the depth of the device isolation layer 21.

[0033] Channel area ACT N It can be in the first source / drain region D N and S N Between the first gate structure GS N The lower part Sf is disposed in the substrate 1 from the upper surface of the substrate 1. According to the first gate structure GS applied... N The magnitude of the gate voltage, where the region where the inversion layer is formed can be considered as the channel region ACT. N .

[0034] At the same time, each first circuit element TR N This can include the ACT located in the channel region N The lower part and the first drain region D N The dividing groove structure 30 between them.

[0035] The separation trench structure 30 can extend from the lower surface Sr of the substrate 1 along the Z direction toward the first drain region D. N Low concentration doped region 2 and channel region ACT N The boundary between them extends, and can extend in the X direction to a region equal to or greater than the first drain region D. N The length L2 of the second width Wd in the X direction, as follows Figure 1 and Figure 2 As shown.

[0036] It has a first drain region D equal to or greater than the first drain region D N The length of the dividing trench structure 30 can be defined as being along the first drain region D in the X direction. N The edge extends so as to connect with the first drain region D. N and the ACT area N All boundaries overlap between them. Therefore, the dividing trench structure 30 can have a length equal to or greater than the second width Wd in the X direction, and can have an upper surface width W1 in the Y direction, and the first sub-width W3 of the upper surface width W1 can be set to be the same as the trench area ACT. N The overlap, and the second sub-width W4 can be set to the same as the first drain region D.N Overlap. The upper surface width W1 can be approximately 100 nm or less, and can satisfy, for example, the first gate structure GS. N The first length L1 is 1 / 10 or less.

[0037] The partition trench structure 30 has a shape similar to a wall extending along the Z direction from the lower surface Sr of the substrate 1, and can be configured to have a partition distance such that the partition trench structure 30 can be spaced apart from the upper surface Sf of the substrate 1 by a second distance d2. Therefore, the upper surface of the partition trench structure 30 can be positioned at a height lower than the upper surface Sf of the substrate 1 by the second distance d2, and the lower surface of the partition trench structure 30 can be coplanar with the lower surface Sr of the substrate 1. The second distance d2 can be equal to or greater than the channel region ACT. N The thickness of the inversion layer can be, for example, about 9 nm to 11 nm, preferably about 10 nm. The upper surface of the separating trench structure 30 can be considered to be disposed on the upper surface Sf of the substrate 1 and the first drain region D. N At the height between the lower surfaces.

[0038] Therefore, the separating trench structure 30 can extend from a point spaced apart from the upper surface Sf of the substrate 1 by the trench depth to the lower surface Sr of the substrate 1, and can simultaneously extend into the trench region ACT. N Below will be the channel area ACT N The lower substrate 1 and the first drain region D N Physical and electrical separation.

[0039] The partition trench structure 30 may include an insulating material, and may include silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride, and may also include a high-k material. The high-k material may refer to a dielectric material having a higher dielectric constant than silicon oxide (SiO2), and may include at least one of hafnium oxide, hafnium silicon oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium titanium oxide, lithium oxide, aluminum oxide, or lead zinc niobate. The partition trench structure 30 may be applied to block charge carriers from passing through the channel region ACT. N The lower substrate 1 from the first drain region D N Move to source pole region S N Any insulating material.

[0040] The dividing trench structure 30 may include a first part and a second part that divide its upper surface width W1 in the Y direction, the first part being connected to the trench region ACT. N Overlapping and the second part with the first drain region D N The two parts overlap, and the first sub-width W3 of the upper surface of the first part can be equal to or greater than the second sub-width W4 of the upper surface of the second part.

[0041] Therefore, the first portion of the partition trench structure 30 may include a section that bends from the upper surface and faces the first source region S. N The first portion may have a first side surface Ss, and the first portion may have both an upper surface and a first side surface Ss that are in direct contact with the substrate 1. Therefore, the first portion may be configured to span the substrate 1 from the lower surface to the upper surface of the first portion. The second portion of the separating trench structure 30 may include a portion connected to the first portion in the Y direction and bent from its upper surface to face the first drain region D. N The second side surface Sd. The second part of the separating trench structure 30 may have a connection with the first drain region D. N The upper surface of the low-concentration doped region 2 is in contact with the upper surface, and the upper region of the second side surface Sd, which curves from the upper surface, can be in contact with the first drain region D. N The low-concentration doped region 2 contacts the substrate 1, and the lower region of the second side surface Sd can contact the substrate 1. The second portion can be formed without bending, but this disclosure is not limited thereto, and through the second portion, the first drain region D... N The low-concentration doped region 2 may have a concave stepped portion in the edge connecting from the lower end to the side surface (e.g., as shown in the image). Figure 3A (See corner 33). The depth of the step portion can be approximately 30 nm to 40 nm, but this disclosure is not limited thereto.

[0042] In this way, the separating trench structure 30 can be set in the first drain region D N Low concentration doped region 2 and channel region ACT N The first drain region D is in contact with the N Simultaneous penetration of the channel area ACT in its surrounding region N The area of ​​the lower substrate 1 makes the first drain region D N Can be used with ACT except for the channel area N ACT (Active Channel) outside the upper region N The lower substrate 1 is physically and electrically separated.

[0043] When the first circuit element TR N When driven by a high voltage ranging from a few volts to tens of volts, it is applied to the first drain region D. N The drain voltage can be a high voltage of tens of volts, for example, 10V to 30V, and the gate voltage can also be a high voltage of tens of volts. First drain region D N This high drain voltage may be present in the first drain region D. N A deep depletion region forms below, and this deep depletion region may extend into the channel region ACT. N The lower part and may be connected to the first source region S N This could lead to unintended penetration. Specifically, in the case of a cutoff state, i.e., even when the channel region ACT...N Even without a gate voltage, current may still flow through the channel region ACT. N The lower substrate 1 may generate a very large cutoff current, which could reduce the reliability of the device.

[0044] In one or more embodiments, in the high-voltage element, the first circuit element TR, which is an NMOS transistor, can be used. N Set in the ACT area of ​​the trench N The upper part below the first drain region D N and the ACT area N The space between them is separated by a trench structure 30, thereby eliminating punch-through. Specifically, the trench structure 30 can prevent the depletion region from penetrating the first drain region D. N The lower part along the channel area ACT N The lower extension is therefore minimized in the channel region ACT. N ACT flows outside the channel area N The leakage current of the lower substrate 1.

[0045] Therefore, from the first drain region D N Charge carriers can flow only through the channel region ACT N The upper part, and the channel area ACT N The upper part can form an inversion layer only when a gate voltage is applied, thereby minimizing the cutoff current.

[0046] The separating trench structure 30 can be formed to penetrate the substrate 1 from the lower surface Sr toward the upper surface Sf of the substrate 1 while being spaced apart from the upper surface Sf of the substrate 1 by a second distance d2, thereby physically defining the channel region ACT. N The width of the lower surface of the dividing groove structure 30 may be the same as or different from the width W1 of the upper surface, but this disclosure is not limited thereto.

[0047] Meanwhile, the second circuit element TR P It can be arranged in a matrix in the PMOS region PR, and the second circuit element TR P This may include a planar transistor located in a well region 5 of the substrate 1, specifically a well region 5 containing a first conductive impurity. The first conductive impurity may be an N-type impurity, and the second circuit element TR P It can be a PMOS transistor.

[0048] Each second circuit element TR P It can have the same characteristics as the first circuit element TR N Same gate structure.

[0049] Specifically, the second gate structure GS PIt may include the first circuit element TR N Those identical second gate electrode structures GE P and gate dielectric layer 20, second gate electrode structure GE P This includes a lower conductive layer 35, an upper conductive layer 37, and a mask layer 39. The configuration of each of the gate dielectric layer 20, the lower conductive layer 35, the upper conductive layer 37, the mask layer 39, and the ohmic contact layer 38 can be configured with the first gate structure GS. N The configurations are the same.

[0050] Gate spacer 40 can be disposed in the second gate structure GS P On the two side surfaces. Second source / drain region D P and S P It can be in the second gate structure GS P The two sides are disposed on the upper surface of the substrate 1.

[0051] The gate spacer 40 may be formed of at least one of oxide, nitride or oxynitride, and may be formed of, for example, a low-κ film.

[0052] Second source / drain region D P and S P It can be in the second gate structure GS P Both sides are formed from the upper surface of the substrate 1 inward to a first depth d1, and include impurities.

[0053] Second source / drain region D P and S P It can include a low-concentration doped region 2 and a high-concentration doped region 4, respectively. The low-concentration doped region 2 can be configured to extend from the gate structure GS in the Z direction. P The region is offset and can be doped with a low concentration of impurities up to a first depth d1. The first depth d1 can be 40 nm to 50 nm in length, and the high-concentration doped region 4 can be shallower than the first depth d1 of the low-concentration doped region 2, and can be, for example, about 10 nm to 12 nm, but this disclosure is not limited thereto.

[0054] Second source / drain region D P and S P The low-concentration doped region 2 and the high-concentration doped region 4 can be doped with impurities of the same conductivity type, and only the doping concentration of the impurities can differ from each other. The area of ​​the high-concentration doped region 4 can be smaller than the area of ​​the low-concentration doped region 2, and the high-concentration doped region 4 and the low-concentration doped region 2 can be configured to not be adjacent to the gate structure GS in the XY plane. P Overlapping. Therefore, the high-concentration doped region 4 is essentially used as the source region, and the low-concentration doped region 2 can be the diffusion region of the high-concentration doped region 4, but this disclosure is not limited thereto.

[0055] Second circuit element TR P It can be used as a PMOS transistor in substrate 1, and even the second circuit element TR P Driven by high-voltage components, the separating trench structure 30 may not be required. That is, in the case of a PMOS transistor, since the depletion region is not located in the second drain region D... P The diffusion occurs below, so the separation trench structure 30 may not be necessary.

[0056] On substrate 1, the first circuit element TR N An NMOS transistor can be configured in the NMOS region NR, and the second circuit element TR... P PMOS transistors can be arranged in the PMOS region PR, and various circuits can be connected to the gate structure GS respectively. N and GS P and source / drain region D N S N D P and S P Electrical connections are implemented through plugs and interconnections.

[0057] In the following text, reference will be made to Figures 4 to 7 Describe an example implementation method. Figure 4 and Figure 5 It is a schematic cross-sectional view of a semiconductor device according to one or more embodiments.

[0058] refer to Figure 4 Except for the partition trench structure 30 being formed only by the first part, the semiconductor device 10a can be with Figures 1 to 3D The semiconductor device 10 is the same.

[0059] Each partition trench structure 30 of the semiconductor device 10a may have a lower surface coplanar with the lower surface Sr of the substrate 1, and may be configured such that its upper surface is spaced apart from the upper surface Sf of the substrate 1 by a second distance d2 through the lower surface Sr of the substrate 1. The partition trench structure 30 may have a first source / drain region D in the X direction that is equal to or greater than the first source / drain region D. N and S N The length L2, and may have an upper surface width W1 in the Y direction starting from the upper surface. The partition trench structure 30 may only include the trench area ACT. N The first overlapping portion, excluding the portion with the first drain region D. N The overlapping second part. That is, the separating trench structure 30 can be configured to face the trench area ACT. N The first part is shifted so that it has an upper surface width W1.

[0060] The first portion of the partition trench structure 30 may include a section that bends from the upper surface and faces the first source region S. N The first side surface Ss and the curve from the top surface facing the first drain region D N The second side surface Sd. In the first part, both the upper surface and the first side surface Ss can be in direct contact with the substrate 1, and in the second side surface Sd, the upper region can be in contact with the first drain region D. N The low-concentration doped region 2 is the contact.

[0061] The first part can be formed without bending, and the second side surface Sd can be configured to be aligned with the first drain region D. N Edge, i.e., side surface SD N Contact, causing the first drain region D N It can be formed without steps.

[0062] In this way, the separating trench structure 30 can be in the first drain region D N Low concentration doped region 2 and channel region ACT N The first drain region D is in contact with the N Edges and side surfaces SD N Simultaneously penetrates substrate 1 and can extend to the channel region ACT N The lower part, so that the first drain region D N Can be used with ACT except for the channel area N ACT (Active Channel) outside the upper region N The lower substrate 1 is physically and electrically isolated.

[0063] refer to Figure 5 In addition to the tilt of the separating trench structure 30, the semiconductor device 10b can be coupled with... Figures 1 to 3D The semiconductor device 10 is the same.

[0064] Each partition trench structure 30 of the semiconductor device 10b may have a lower surface coplanar with the lower surface Sr of the substrate 1, and may be configured such that its upper surface is spaced apart from the upper surface Sf of the substrate 1 by a second distance d2 through the lower surface Sr of the substrate 1.

[0065] In each dividing trench structure 30, the width W2 of its lower surface in the X direction is greater than the width W1 of its upper surface, and for example, the width can gradually increase from the upper surface to the lower surface. Therefore, the side surfaces Sd and Ss connecting the upper and lower surfaces can have an inclination at least in some portions, and for example, can have a continuous inclination from the upper surface to the lower surface. The inclination of the side surfaces can also be applied to their length in the Y direction, and it is understood that their area can increase towards the lower surface.

[0066] Figure 6A It is a plan view of a semiconductor device according to one or more embodiments, and Figure 6B yes Figure 6A A cross-sectional view of a semiconductor device taken along line V-V'.

[0067] refer to Figure 6A and Figure 6B Except for the first source polar region S N and the ACT area N In addition to the additional separation trench structure 30 between them, the semiconductor device 10c can be with Figures 1 to 3D The semiconductor device 10 is the same.

[0068] The semiconductor device 10c may include a first separating trench structure 30a and a second separating trench structure 30b.

[0069] Each first circuit element TR of the NMOS transistor in semiconductor device 10c N This may include setting the first drain region D N and the ACT area N The first separating trench structure 30a between and the first source pole region S N and the ACT area N The second dividing trench structure 30b between them.

[0070] The first dividing trench structure 30a and the second dividing trench structure 30b can have the same shape. Because the first dividing trench structure 30a has the same shape as... Figures 1 to 3D The partition trench structure 30 described herein has the same shape and arrangement, therefore its description will be omitted.

[0071] The second separating trench structure 30b may also have a lower surface coplanar with the lower surface Sr of the substrate 1, and may be configured such that its upper surface is spaced apart from the upper surface Sf of the substrate 1 by a second distance d2 by penetrating the substrate 1 from the lower surface Sr. The second separating trench structure 30b may have a first portion and a second portion, and the first portion may penetrate the trench region ACT. N The substrate 1 below, and the second portion adjacent to the first portion, can penetrate the first source region S in the upper region. N That is, the first part may include a portion that is bent from the upper surface to contact the substrate 1 and faces the first drain region D. N The first side surface Sd, and the second portion may include a bend from the upper surface to contact the first source region S in the upper region. N The second side surface Ss. Therefore, through the second separating trench structure 30b, the first source region S N It may have a concave stepped portion in the region that curves from its lower end to its side surface. First source region SN and the first drain region D N The steps may be symmetrical to each other, but this disclosure is not limited thereto.

[0072] The side surface Ss of the first separating trench structure 30a and the side surface Sd of the second separating trench structure 30b can face each other, the substrate 1 is located between them, and the separation distance d3 between the two first side surfaces Ss and Sd can be shorter than the channel region ACT. N The length of the channel.

[0073] In this way, the second partition trench structure 30b can be located in the first source region S. N Low concentration doped region 2 and channel region ACT N The first source pole region S is in contact with the N Simultaneously penetrating the edge of substrate 1 to the channel region ACT N The lower region, thus preventing the flow from the first drain region D N The flowing leakage current is injected into the first source region S. N middle.

[0074] refer to Figure 7 In addition to the protruding region included in the separating trench structure 30, the semiconductor device 10d can be connected with... Figure 6A and Figure 6B The semiconductor device 10c is the same.

[0075] Each first circuit element TR of the NMOS transistor in semiconductor device 10d N This may include setting the first drain region D N and the ACT area N The first separating trench structure 30a between them, and the first source pole region S N and the ACT area N The second dividing trench structure 30b between them.

[0076] The first dividing trench structure 30a and the second dividing trench structure 30b may have the same shape. Each of the first dividing trench structure 30a and the second dividing trench structure 30b may include a base region and an ACT extending from both ends of the base region toward the trench region. N The prominent protruding regions 31a and 31b. The base region can be connected with... Figure 6A and Figure 6B The first separating trench structure 30a and the second separating trench structure 30b of the semiconductor device 10c are the same.

[0077] The first dividing trench structure 30a may include two protruding regions 31a, which extend from the first side surface Ss toward the trench region ACT at both ends of the base region in the X direction (i.e., the length direction) along the Y direction. N (That is, protruding toward the second dividing trench structure 30b).

[0078] The two protruding regions 31a may have the same width as the base region, and their protruding length may be equal to or less than their width. The protruding regions 31a may also extend in the Z direction to have the same height as the base region.

[0079] The second dividing trench structure 30b may include two protruding regions 31b, which extend from the first side surface Sd toward the trench region ACT at both ends of the base region in the X direction (i.e., the length direction) along the Y direction. N (That is, protruding toward the first dividing trench structure 30a).

[0080] The two protruding regions 31b may have the same width as the base region, and their protruding length may be equal to or less than their width. The protruding regions 31b may also extend in the Z direction to have the same height as the base region.

[0081] Therefore, the protruding regions 31a of the first separating trench structure 30a and 31b of the second separating trench structure 30b can be spaced apart by a fourth distance d4 and can face each other. In this case, the fourth distance d4 can be smaller than the third distance d3, which is the separation distance between the base regions. Through the separation space of the fourth distance d4, the substrate voltage applied from the substrate pad region 3 can be transmitted to the channel region ACT. N The substrate region below. When the first separating trench structure 30a and the second separating trench structure 30b include protruding regions 31a and 31b, they can block the flow along the first drain region D. N Leakage current flowing at the interface between the component isolation layer 21 and the component.

[0082] Figures 1 to 7 The various first circuit elements TR shown N and various second circuit elements TR P It is applicable to circuit design for various semiconductor devices.

[0083] In the following text, see references Figures 8 to 9B , will describe Figures 1 to 5 An example of a semiconductor device being used as part of the peripheral circuitry of a memory device.

[0084] Figures 8 to 9B Semiconductor devices according to one or more embodiments are shown. Figure 8 It is a cross-sectional view of a semiconductor device according to one or more embodiments, and Figure 9A and Figure 9B It is based on Figure 8 A partial enlarged view of a semiconductor device according to one or more embodiments, and Figure 9A It shows Figure 8 The "C" part and the "D" part, and Figure 9B It shows Figure 8 The "E" part.

[0085] refer to Figures 8 to 9B The semiconductor device 100 includes a first substrate structure S1 and a second substrate structure S2 that are vertically bonded to each other. The first substrate structure S1 may include a peripheral circuit region, and the second substrate structure S2 may include a memory cell region.

[0086] The first substrate structure S1 may have a low-voltage element region LR and a high-voltage element region HR. The low-voltage element region LR may be defined as a region where circuit elements capable of being controlled with a relatively low drive voltage are disposed, and the high-voltage element region HR may be defined as a region where circuit elements capable of being controlled with a relatively high drive voltage are disposed.

[0087] The first substrate structure S1 may include a substrate 201, component isolation layers 210a and 210b located in the substrate 201, a first circuit element TR1 and a second circuit element TR2 disposed on the substrate 201 in a low-voltage component region LR, a third circuit element TR3 and a fourth circuit element TR4 disposed on the substrate 201 in a high-voltage component region HR, a peripheral region insulating layer 290 located on the upper surface of the substrate 201, a contact plug 285 located on the substrate 201, a circuit interconnect 280, a first bonding passage 295, a first bonding pad 298, and a first bonding insulating layer 299.

[0088] The first substrate structure S1 may include a first well region 206L, a first source / drain region 205aL and a second source / drain region 205bL disposed in the low voltage element region LR, a second well region 206H disposed in the high voltage element region HR, and a third source / drain region 205aH and a fourth source / drain region 205bH.

[0089] The substrate 201 may have upper surfaces Sa and Sb extending in the X and Y directions, and a lower surface Sr opposite to the upper surfaces Sa and Sb.

[0090] The substrate 201 may include a first upper surface Sa disposed in the low-voltage element region LR and a second upper surface Sb disposed in the high-voltage element region HR, and the second upper surface Sb may be disposed in the Z direction at a position where the height of the substrate step portion hs is lower than the height of the first upper surface Sa. Therefore, the gate structure GS of the high-voltage element region HR H The starting point can be set lower overall.

[0091] The substrate 201 may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, the substrate 201 may be provided as a single-crystal silicon wafer.

[0092] CMOS transistors can be disposed in each of the low-voltage element region LR and the high-voltage element region HR, and the first well region 206L and the second well region 206H can be disposed in the substrate 201 such that transistors of different conductivity types can be disposed in each element region LR and HR. When the substrate 201 is a P-type semiconductor, the first well region 206L and the second well region 206H can be N-type wells doped with N-type impurities.

[0093] Therefore, the portion other than the first well region 206L and the second well region 206H can be defined as first element regions NR1 and NR2 in which NMOS transistors are disposed, and the portion in which the first well region 206L and the second well region 206H are disposed as second element regions PR1 and PR2 in which PMOS transistors are disposed. When the conductivity type of the substrate 201 is opposite, the conductivity type of each region can be opposite.

[0094] The low-voltage component region LR and the high-voltage component region HR can be defined by forming component isolation layers 210a and 210b, respectively. For example, component isolation layers 210a and 210b can be formed in a shallow trench isolation (STI) process. In some embodiments, the arrangement shape and depth of component isolation layers 210a and 210b can be varied. Component isolation layers 210a and 210b can be formed of an insulating material. Component isolation layers 210a and 210b can be, for example, oxides, nitrides, or combinations thereof.

[0095] The first source / drain region 205aL, the second source / drain region 205bL, the third source / drain region 205aH, and the fourth source / drain region 205bH, which include impurities, can be located in the active region.

[0096] The low-voltage component region LR may include a first component region NR1 and a second component region PR1, and the high-voltage component region HR may include a first component region NR2 and a second component region PR2.

[0097] Therefore, the first source / drain region 205aL and the second source / drain region 205bL in the low-voltage element region LR can be regions respectively disposed in the first element region NR1 and the second element region PR1 and doped with impurities of different conductivity types, and the third source / drain region 205aH and the fourth source / drain region 205bH in the high-voltage element region HR can be regions respectively disposed in the first element region NR2 and the second element region PR2 and doped with impurities of different conductivity types.

[0098] The first source / drain region 205aL in the first element region NR1 of the low-voltage element region LR and the third source / drain region 205aH in the first element region NR2 of the high-voltage element region HR can be doped with the same impurities, and the second source / drain region 205bL in the second element region PR1 of the low-voltage element region LR and the fourth source / drain region 205bH in the second element region PR2 of the high-voltage element region HR can be doped with the same impurities.

[0099] In the first substrate structure S1 of the semiconductor device 100, the first element region NR2 and the second element region PR2 of the high-voltage element region HR can respectively correspond to the above-mentioned... Figures 1 to 3D The first element region NR and the second element region PR of the semiconductor device 10.

[0100] Therefore, as Figures 1 to 3D The first circuit element TR of the NMOS transistor N It can be the third circuit element TR3 in the high-voltage element region HR, and as... Figures 1 to 3D The second circuit element TR of the PMOS transistor P It can be the fourth circuit element TR4 in the high-voltage element region HR.

[0101] The first circuit element TR1 of the low voltage element region LR can be disposed on the upper surface of the substrate 201 and can be a planar transistor. It can include a first gate structure GS1, a first source / drain region 205aL and a first gate spacer 240. The first gate structure GS1 includes first gate dielectric structures 224 and 225 and first gate electrode layers 232, 235, 238 and 237.

[0102] The first gate dielectric structures 224 and 225 may include a first interface insulating layer 224 and a first gate dielectric layer 225.

[0103] The first interface insulating layer 224 may be disposed on the first upper surface Sa of the substrate 201 and may include silicon oxide having a low κ dielectric constant, and the first gate dielectric layer 225 may include a high κ dielectric material. A high κ dielectric material may refer to a dielectric material having a higher dielectric constant than the silicon oxide film (SiO2). The first gate dielectric layer 225 may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0104] The first gate electrode layers 232, 235, 238 and 237 can be disposed on the first gate dielectric layer 225.

[0105] The first gate electrode layers 232, 235, 238, and 237 may include at least two layers, but this disclosure is not limited thereto. The first gate electrode layers 232, 235, 238, and 237 may include a first conductive layer 233, a second conductive layer 235, and a third conductive layer 237 stacked in a vertical direction.

[0106] The first conductive layer 232 is a metal substrate and may include metal or metal nitride. The first conductive layer 232 may include tungsten, titanium nitride, tantalum nitride, titanium silicon nitride (TiSiN), silicon-doped titanium nitride (Si-doped TiN, TSN), or combinations thereof. The first conductive layer 232 may preferably include titanium nitride (TiN) or TSN (Ti-Si-N).

[0107] The second conductive layer 233 may include polysilicon, but this disclosure is not limited thereto. The third conductive layer 237 may include a metallic material different from the first conductive layer 232, and may include, for example, tungsten (W), but this disclosure is not limited thereto.

[0108] The ohmic contact layer 238 may be further included between the second conductive layer 233 and the third conductive layer 237, and the ohmic contact layer 238 may include, but is not limited to, titanium nitride (TiN) or tantalum nitride (TaN). The thickness of the ohmic contact layer 238 may be significantly smaller than the thickness of the second conductive layer 233 and the third conductive layer 237.

[0109] The mask layer 239 may be further included in the upper portion of the first gate electrode layers 232, 235, 238, and 237. The mask layer 239 may include silicon nitride and silicon oxynitride. The vertical length from the upper surface of the first gate structure GS1 to the substrate 201 may have a second height h2.

[0110] The first gate spacer 240 may be disposed on both side surfaces of the first gate structure GS1. The first gate spacer 240 may insulate the first source / drain region 205aL from the first gate structure GS1. The first gate spacer 240 may be formed of at least one of oxide, nitride, or oxynitride, and may be made of, for example, a low-k film.

[0111] The first source / drain region 205aL can be disposed on both sides of the first gate structure GS1 in the substrate 201. The first source / drain region 205aL can include multiple impurity regions with different doping concentrations, and can include a high-concentration doped region 4 and a low-concentration doped region 2, respectively.

[0112] The second circuit element TR2 in the low-voltage element region LR can be a PMOS transistor, which is a planar transistor in the well region 206L of the substrate 201.

[0113] Each second circuit element TR2 may include a channel structure 223, second gate dielectric structures 224 and 225, a second gate structure GS2 including a second gate electrode layer, a second source / drain region 205bL, and a gate spacer 240.

[0114] The channel structure 223 may include a semiconductor material on the first upper surface Sa of the substrate 201, having a band gap smaller than that of the substrate 201. For example, when the substrate 201 includes silicon, the channel structure may include silicon germanium (SiGe).

[0115] The second gate dielectric structures 224 and 225 may include a second interface insulating layer 224 and a second gate dielectric layer 225, and may be the same as the second interface insulating layer 224 and the first gate dielectric layer 225 of the first gate dielectric structures 224 and 225, but this disclosure is not limited thereto.

[0116] The second gate electrode layers 232, 235, 238 and 237 can be disposed on the second gate dielectric layer 225.

[0117] The second gate electrode layers 232, 235, 238, and 237 may include at least two layers, but this disclosure is not limited thereto. The second gate electrode layers 232, 235, 238, and 237 may include a first conductive layer 233, a second conductive layer 235, and a third conductive layer 237 stacked vertically. The second gate electrode layers 232, 235, 238, and 237 may correspond to each of the first gate electrode layers 232, 235, 238, and 237, and their description is omitted.

[0118] The mask layer 239 may be further included in the upper portion of the second gate electrode layers 232, 235, 238, and 237. The mask layer 239 may include silicon nitride and silicon oxynitride. The second gate structure GS2 may have a third height h3, and the third height h3 may be greater than the second height h2 of the first gate structure GS1.

[0119] The second gate spacer 240 can be disposed on both side surfaces of the second gate structure GS2. The second source / drain region 205bL can be disposed on both sides of the second gate structure GS2 in the first well region 206L of the substrate 201.

[0120] Meanwhile, the third circuit element TR3 and the fourth circuit element TR4 can be further disposed in the high-voltage element region HR of the semiconductor device 100.

[0121] The third circuit element TR3 can be used as an NMOS transistor in the second upper surface Sb of the high-voltage element region HR, and the fourth circuit element TR4 can be used as a PMOS transistor in the second upper surface Sb of the high-voltage element region HR.

[0122] exist Figure 8 and Figure 9A In the high-voltage element region HR, the dimensions (e.g., channel length, etc.) of circuit elements TR3 and TR4 are shown to be the same as or similar to the dimensions of circuit elements TR1 and TR2 in the low-voltage element region LR, but this disclosure is not limited thereto, and the dimensions (e.g., channel length, etc.) of circuit elements TR3 and TR4 in the high-voltage element region HR may be larger than the dimensions of circuit elements TR1 and TR2.

[0123] The third circuit element TR3 and the fourth circuit element TR4 can be disposed in their respective conductive regions, and at least one of them can be disposed in the well region 206H. Figure 8 The diagram shows that the substrate 201 is a P-type substrate 201 and the fourth circuit element TR4 is disposed in the well region 206H doped with N-type impurities, but this disclosure is not limited thereto.

[0124] Except that the regions where the third circuit element TR3 and the fourth circuit element TR4 are located have different conductivity types, the third circuit element TR3 and the fourth circuit element TR4 can have the same characteristics as the gate structure GS. H Same stacking structure.

[0125] In other words, the third circuit element TR3 and the fourth circuit element TR4 are planar transistors and may include a gate structure GS. H With gate spacer 240, third source / drain region 205aH, and fourth source / drain region 205bH, gate structure GS HThe second upper surface Sb has a first height h1 at a distance from the substrate 201, and the second upper surface Sb is lower than the substrate step portion hs by the first upper surface Sa of the substrate 201.

[0126] Gate structure GS H It may include a gate dielectric layer 222, a lower conductive layer 235, and an upper conductive layer 237.

[0127] The gate dielectric layer 222 may include a low-k material, such as an oxide or nitride, and may preferably include a silicon oxide film (SiO2). The thickness T1 of the gate dielectric layer 222 may be greater than the thickness of the interface insulating layer 224 of the first circuit element TR1 and the second circuit element TR2 or the thickness of the first and second gate dielectric layers 225, and may preferably have a thickness substantially equal to that of the substrate step portion hs, but this disclosure is not limited thereto.

[0128] Gate electrode layers 235, 238, and 237 may be disposed on gate dielectric layer 222 and may include at least two layers, but are not limited thereto. Gate electrode layers 235, 238, and 237 may include a lower conductive layer 235 and an upper conductive layer 237. The lower conductive layer 235 may include polysilicon, but this disclosure is not limited thereto, and may be formed of substantially the same material and thickness as the second conductive layer 235 of the second circuit element TR2. The upper conductive layer 237 may include a metal such as tungsten or aluminum, and may be formed of substantially the same material and thickness as the third conductive layer 237 of the second circuit element TR2. An ohmic contact layer 238 may be further included between the lower conductive layer 235 and the upper conductive layer 237, and the ohmic contact layer 238 may include titanium nitride (TiN) or tantalum nitride (TaN), but is not limited thereto. The thickness of the ohmic contact layer 238 may be significantly less than the thickness of the lower conductive layer 235 and the upper conductive layer 237.

[0129] The mask layer 239 may be further included in the upper portion of the gate electrode layers 235, 238, and 237. The mask layer 239 may include silicon nitride or silicon oxynitride.

[0130] Therefore, in the third circuit element TR3 and the fourth circuit element TR4, the lower conductive layer 235, the ohmic contact layer 238, the upper conductive layer 237 and the mask layer 239 can be disposed on the first upper surface Sa of the substrate 201, and the height of the upper surface of the third circuit element TR3 and the fourth circuit element TR4 can be set to be lower than the height of the upper surface of the first circuit element TR1 and the second circuit element TR2.

[0131] However, the first upper surface Sa and the second upper surface Sb of the substrate 201 are not required, and the low voltage element region LR and the high voltage element region HR can be disposed on the upper surface at the same height.

[0132] Gate spacer 240 can be disposed in gate structure GS H On both side surfaces. The gate spacer 240 can be formed of at least one of oxide, nitride or oxynitride, and can be formed of, for example, a low-κ film.

[0133] The third source / drain region 205aH and the fourth source / drain region 205bH can be disposed in the gate structure GS in the substrate 201. H Both sides include impurities.

[0134] Each of the third source / drain region 205aH and the fourth source / drain region 205bH includes a source region S and a drain region D, and the source region S and the drain region D may each include a low-concentration doped region 2 and a high-concentration doped region 4, and their configuration may be consistent with... Figures 1 to 3D The configuration is the same as in [the previous section].

[0135] exist Figure 8 In the semiconductor device 100 serving as a memory device, each third circuit element TR3 (i.e., an NMOS transistor) in the high-voltage element region HR may include a third drain region 205aH(D) and a channel region ACT. N The dividing groove structure 230 between them.

[0136] The partition trench structure 230 can have the same as Figures 1 to 3D The same configuration as the partition trench structure 30, and the low-concentration doped region 2 and the channel region ACT from the lower surface Sr of the substrate 201 along the Z direction toward the third drain region 205aH(D). N The boundary between them extends to a length equal to or greater than the entire length of the third drain region 205aH(D).

[0137] The dividing trench structure 230 has an upper surface width W1, and a first portion of the upper surface width W1 can be configured to overlap with the third drain region 205aH(D), and a second portion of it can be arranged to overlap with the channel region ACT. N overlap.

[0138] The partition trench structure 230 can be formed with a wall shape extending along the Z direction from the lower surface Sr of the substrate 201, and can be formed with a partition distance such that the partition trench structure 230 is spaced apart from the second upper surface Sb of the substrate 201 by a second distance d2. Therefore, the upper surface of the partition trench structure 230 can be positioned at a height lower than the height of the second upper surface Sb of the substrate 201 by the second distance d2, and the surface of the partition trench structure 230 can be coplanar with the lower surface Sr of the substrate 201. The second distance d2 can be defined as a trench depth of 9 nm to 11 nm, preferably approximately 10 nm.

[0139] Therefore, the separating trench structure 230 can extend from a point spaced apart from the second upper surface Sb of the substrate 201 by the trench depth to the lower surface Sr of the substrate 201, and can simultaneously extend in the trench region ACT N In the lower part, the substrate 201 and the third drain region 205aH(D) are physically and electrically separated.

[0140] The partition trench structure 230 may include an insulating material and may include silicon oxide or silicon nitride.

[0141] Figure 8 The semiconductor device 100 is shown having a partitioned trench structure 230 disposed therein for ACT in the channel region by corresponding to each NMOS transistor in the high-voltage element region. N In the lower part, the third drain region 205aH(D) is separated from the substrate 201, and the high voltage drain voltage can be not applied to the fourth circuit element TR4 of the PMOS transistor in the high voltage element region HR or the first circuit element TR1 and the second circuit element TR2 in the low voltage element region LR, so that the separation trench structure 230 of this disclosure can be omitted.

[0142] Interconnect structures and a lower surface insulating layer may be further disposed on the lower surface of substrate 201, and at least a portion of the lower surface interconnect structure may form a back-side power delivery network (BSPDN), but this disclosure is not limited thereto. A passivation layer may be disposed to cover the lower surface Sr of substrate 201 and the lower surface of the separating trench structure 230.

[0143] Simultaneously, a peripheral region insulating layer 290 may be disposed on the upper surfaces Sa and Sb of the substrate 201 on the first circuit element TR1 to the fourth circuit element TR4. The peripheral region insulating layer 290 may include multiple insulating layers formed by different process operations. The peripheral region insulating layer 290 may be formed of an insulating material and may include at least one of, for example, oxides, nitrides, or oxynitrides.

[0144] The contact plug 285 can penetrate the peripheral region insulating layer 290 and can be connected to the highly doped regions 4 of the first to fourth source / drain regions 205aL, 205bL, 205aH and 205bH. A portion of the contact plug 285 can penetrate the peripheral region insulating layer 290 and can be connected to the gate structure.

[0145] Each contact plug 285 may have an inclined side surface such that the width of its upper surface is greater than the width of its lower surface. The upper ends of the contact plugs 285 may be positioned at substantially the same height, but this disclosure is not limited thereto.

[0146] Each contact plug 285 may have a cylindrical shape. The contact plug 285 may include a conductive material and may include at least one of, for example, a semiconductor material, a metal-semiconductor compound, or a metallic material such as tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), ruthenium (Ru), or aluminum (Al), each of which may further include a diffusion barrier. The contact plugs 285 and the circuit interconnects 280 may be disposed on the upper surfaces Sa and Sb of the substrate 201 and may be connected to each other.

[0147] A first bonding path 295, a first bonding pad 298, and a first bonding insulating layer 299 may be included in a first bonding structure and may be disposed on the uppermost circuit interconnect 280. The first bonding path 295 may have a cylindrical shape, and the first bonding pad 298 may have a linear shape. The upper surfaces of the first bonding pad 298 and the first bonding insulating layer 299 may be exposed to the upper surface of the first substrate structure S1. The first bonding path 295 and the first bonding pad 298 may provide an electrical connection path between the first substrate structure S1 and the second substrate structure S2. A portion of the first bonding pad 298 may not be connected to the lower circuit interconnect 280 and may be configured for bonding only. The first bonding path 295 and the first bonding pad 298 may include a conductive material, such as copper (Cu). The first bonding insulating layer 299 may be disposed around the first bonding pad 298. The first bonding insulating layer 299 can also be used as a diffusion barrier layer for the first bonding pad 298, and may include at least one of, for example, SiN, SiON, SiCN, SiOC, SiOCN or SiO2.

[0148] The second substrate structure S2 may include a plate layer 101, a gate electrode 130 stacked on the lower surface of the plate layer 101, an interlayer insulating layer 120 stacked alternately with the gate electrode 130, a channel structure CH penetrating the gate electrode 130, a partition region MS penetrating the gate electrode 130 and extending in one direction, a first cell contact plug 152 connected to the gate electrode 130, and a second cell contact plug 154 electrically connected to the plate layer 101. The second substrate structure S2 may also include a covering insulating layer 105, a passivation layer 106, a contact insulating layer 125, a cell on-contact 170, a cell interconnect 180, and a cell region insulating layer 190. The second substrate structure S2 may also include a second bonding passage 195, a second bonding pad 198, and a second bonding insulating layer 199 as a second bonding structure.

[0149] Layer 101 may have an upper surface extending in both the X and Y directions. Layer 101 may serve as a common source line for semiconductor device 100. Layer 101 may include a conductive material. For example, layer 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Layer 101 may also include impurities. Layer 101 may be provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer. In some example embodiments, layer 101 may include a plurality of vertically stacked conductive layers.

[0150] The gate electrodes 130 may be vertically spaced apart and stacked on the lower surface of the plate layer 101, thereby forming a stacked structure together with the interlayer insulating layer 120. The stacked structure may include a lower stacked structure and an upper stacked structure that are vertically stacked and surround the first channel structure CH1 and the second channel structure CH2, respectively. However, according to one or more embodiments, the stacked structure may be formed as a single stacked structure.

[0151] The gate electrode 130 may include: at least one lower gate electrode 130L, which is included in the gate of a ground select transistor; a memory gate electrode 130M, which is included in a plurality of memory cells; and an upper gate electrode 130U, which is included in the gate of a string select transistor. Here, the lower and upper stacked structures, the lower gate electrode 130L and the upper gate electrode 130U may be referred to as “lower” and “upper” based on the orientation during the manufacturing process. The number of memory gate electrodes 130M included in the memory cells may be determined according to the capacity of the semiconductor device 100. According to one or more example embodiments, the number of upper gate electrodes 130U and lower gate electrodes 130L may be 1 to 4 or more, and may have the same or different structures as the memory gate electrode 130M. In some embodiments, the gate electrode 130 may also include a gate electrode 130 disposed below the upper gate electrode 130U and / or disposed above the lower gate electrode 130L and included in an erase transistor for erasing operations utilizing the gate-induced drain leakage (GIDL) phenomenon. In addition, some gate electrodes 130, such as memory gate electrodes 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L, may be dummy gate electrodes.

[0152] Gate electrodes 130 may be stacked vertically and spaced apart from each other, and may extend to different lengths in at least one direction, such as the X direction, thereby forming a stepped structure. Gate electrodes 130 may also be configured to have a stepped structure relative to each other in the Y direction. With the stepped structure, gate electrodes 130 may be configured such that the upper gate electrode 130 extends longer than the lower gate electrode 130. Each gate electrode 130 may have a region in which its lower surface is exposed downwards from the interlayer insulating layer 120 and other gate electrodes 130, and this region may be referred to as pad region 130P. Gate electrodes 130 may be connected to the first cell contact plug 152 in pad region 130P. Gate electrodes 130 may have increased thickness in pad region 130P.

[0153] The gate electrode 130 may include a metallic material, such as tungsten (W). According to one or more example embodiments, the gate electrode 130 may include polycrystalline silicon or a metal silicide material. In some embodiments, the gate electrode 130 may also include a diffusion barrier and may include, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0154] Interlayer insulating layers 120 may be disposed between gate electrodes 130. Similar to gate electrodes 130, interlayer insulating layers 120 may also be spaced apart from each other in a direction perpendicular to the lower surface of plate layer 101 and may extend in the Y direction. Interlayer insulating layers 120 may comprise insulating materials such as silicon oxide or silicon nitride.

[0155] Each channel structure CH can be included in a single memory cell string and can be spaced apart from each other in rows and columns on the lower surface of layer 101. The channel structures CH can be configured to form a grid pattern in a plan view, or they can be configured to form a zigzag shape in one direction. The channel structures CH can have a columnar shape and can have sloping side surfaces such that, depending on the aspect ratio, the width of the channel structures CH becomes narrower as it gets closer to layer 101 along the channel structures CH.

[0156] Each channel structure CH can be in the form of a first channel structure CH1 and a second channel structure CH2 connected to the lower stacked structure and the upper stacked structure penetrating the gate electrode 130, and can have a curved portion due to differences or variations in the width of the connection region. However, according to one or more embodiments, the number of channel structures stacked along the Z direction can be varied differently.

[0157] Each channel structure CH may include a channel layer 140, a gate dielectric layer 145, a channel-fill insulating layer 147, and channel pads 149 disposed in a channel via. The channel layer 140 may be formed in an annular shape surrounding the inner channel-fill insulating layer 147, but according to one or more embodiments, it may also have a columnar shape, such as a cylinder or prism, without the channel-fill insulating layer 147. The channel layer 140 may include a semiconductor material such as polysilicon or monocrystalline silicon. The channel layer 140 may be exposed at its upper end and may be connected to the substrate layer 101.

[0158] like Figure 9B As shown, in the upper end of the channel structure CH, the upper end of the channel layer 140 can be exposed from the gate dielectric layer 145. The upper end of the channel layer 140 may include an upper surface and an upper region of a side surface connected to the upper surface. The upper end of the channel layer 140 can be in direct contact with the board layer 101 and can be surrounded by the board layer 101. With this arrangement, the channel layer 140 can be physically and electrically connected to the board layer 101.

[0159] A gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a barrier layer stacked sequentially from the channel layer 140. The tunneling layer can tunnel charge into the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The barrier layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. In some embodiments, at least a portion of the gate dielectric layer 145 may extend horizontally along the gate electrode 130.

[0160] The channel pad 149 may be provided only at the lower end of the second channel structure CH2. The channel pad 149 may include, for example, doped polysilicon.

[0161] The channel layer 140, the gate dielectric layer 145, and the channel-filling insulating layer 147 can be interconnected between the first channel structure CH1 and the second channel structure CH2. A relatively thick interlayer insulating layer 120 can be further disposed between the first channel structure CH1 and the second channel structure CH2. However, the shape of the interlayer insulating layer 120 can be varied in the example embodiment.

[0162] The separating region MS can be configured to extend through the gate electrode 130 in one direction, such as the X direction. Although in Figure 1Only one partition region MS is shown, but multiple partition regions MS can be provided that extend parallel to each other in the X direction and are spaced apart from each other in the Y direction. The partition regions MS can penetrate all the gate electrodes 130 stacked on the plate 101 and can be connected to the plate 101.

[0163] The partition region MS may have a shape in which its width decreases toward the board layer 101 due to a high aspect ratio, but this disclosure is not limited thereto. The partition region MS may include an insulating material and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0164] The first unit contact plug 152 and the second unit contact plug 154 may extend in the Z direction and may have inclined side surfaces such that the width of the first unit contact plug 152 and the second unit contact plug 154 becomes narrower as they approach the substrate 101. The upper ends of the first unit contact plug 152 and the second unit contact plug 154 may be disposed on the lower surface of the substrate 101, for example, in or within the lower surface of the substrate 101. The first unit contact plug 152 and the second unit contact plug 154 may be included in a portion of the second interconnect structure in the second substrate structure S2.

[0165] The first unit contact plug 152 can electrically connect the gate electrode 130 to a first interconnect structure in the first substrate structure S1. The first unit contact plug 152 can be physically and electrically connected to the gate electrode 130 at its corresponding pad region 130P, thereby applying an electrical signal to the gate electrode 130. The first unit contact plug 152 can penetrate the pad region 130P of the gate electrode 130. The first unit contact plug 152 can be configured to extend into the board layer 101 by penetrating the region of the gate electrode 130 that forms a stepped structure. The first unit contact plug 152 can be electrically isolated from the board layer 101 by covering with an insulating layer 105. However, in some example embodiments, the first unit contact plug 152 can have a form that does not penetrate the gate electrode 130. In this case, the first unit contact plug 152 can extend to connect to the lower surface or lower portion of each gate electrode 130.

[0166] The first cell contact plug 152 may have a shape that extends horizontally within the pad region 130P. The first cell contact plug 152 may be separated from the gate electrode 130 on the pad region 130P by a contact insulating layer 125. The contact insulating layer 125 may surround a side surface of one of the first cell contact plugs 152 and may be configured to be spaced apart from each other in the Z direction. The contact insulating layer 125 may be disposed at a height substantially the same as the height of the gate electrode 130. The contact insulating layer 125 may comprise an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0167] The second unit contact plug 154 can be disposed in a region where the gate electrode 130 is not disposed, for example, outside the gate electrode 130. The second unit contact plug 154 can electrically connect the first circuit element TR1 and the second circuit element TR2 of the first substrate structure S1 to the board layer 101. The second unit contact plug 154 can extend into the board layer 101 by penetrating a portion of the unit region insulating layer 190.

[0168] The first unit contact plug 152 and the second unit contact plug 154 may include metallic materials, and may include, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0169] A covering insulating layer 105 may be disposed between the first unit contact plug 152 and the plate layer 101. The covering insulating layer 105 may cover the upper end of the first unit contact plug 152. The covering insulating layer 105 may not extend above the channel structure CH and the second unit contact plug 154. The upper surface of the covering insulating layer 105 may have a curve along the upper end of the first unit contact plug 152, but the shape of the upper surface of the covering insulating layer 105 is not limited thereto. The covering insulating layer 105 may include an insulating material, such as at least one of silicon oxide, silicon nitride, or silicon carbide. In some example embodiments, the covering insulating layer 105 may be configured to have multiple layers spaced apart from each other between the first unit contact plugs 152. In some example embodiments, the covering insulating layer 105 may be configured to penetrate the plate layer 101.

[0170] The cell contact 170 and cell interconnect 180 can be included in a part of the second interconnect structure, and the second substrate structure S2 can be electrically connected to the first substrate structure S1.

[0171] The cell top contact 170 may include first to third cell top contacts 172, 174, and 176, and the cell interconnect 180 may include first cell interconnect 182 and second cell interconnect 184. The channel pad 149 and the first cell contact plug 152 and second cell contact plug 154 may be connected from their lower ends to the first cell top contact 172. The first cell top contact 172 may be connected from its lower end to the second cell top contact 174, and the second cell top contact 174 may be connected from its lower end to the first cell interconnect 182. The third cell top contact 176 may be vertically connected to the first cell interconnect 182 and the second cell interconnect 184. The cell top contact 170 may have a cylindrical shape. In some embodiments, the cell top contact 170 may have sloping side surfaces such that, depending on the aspect ratio, its width decreases as it approaches the board layer 101 and increases towards the first substrate structure S1.

[0172] The first unit interconnect 182 may include a bit line connected to the channel structure CH and an interconnect disposed at the same height level as the bit line. The second unit interconnect 184 may be an interconnect disposed below the first unit interconnect 182. The unit interconnect 180 may have a linear shape extending in at least one direction. In some embodiments, the thickness of the second unit interconnect 184 may be greater than the thickness of the first unit interconnect 182. The unit interconnect 180 may have a sloped side surface such that its width decreases toward the board layer 101.

[0173] The cell contacts 170 and cell interconnects 180 may include, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0174] The second bonding path 195 of the second bonding structure can be disposed below and connected to the second unit interconnect 184, and the second bonding pad 198 of the second bonding structure can be connected to the second bonding path 195. The second bonding pad 198 can have a lower surface exposed to the lower surface of the second substrate structure S2. The second bonding pad 198 can be bonded and connected through the first bonding pad 298 of the first substrate structure S1, and the second bonding insulating layer 199 can be bonded and connected through the first bonding insulating layer 299 of the first substrate structure S1. The second bonding path 195 and the second bonding pad 198 can include a conductive material, such as copper (Cu). The second bonding insulating layer 199 can include at least one of, for example, SiO2, SiN, SiCN, SiOC, SiON, or SiOCN.

[0175] The first substrate structure S1 and the second substrate structure S2 can be bonded to each other by bonding the first bonding pad 298 and the second bonding pad 198, and by bonding the first bonding insulating layer 299 and the second bonding insulating layer 199. The bonding of the first bonding pad 298 and the second bonding pad 198 can be, for example, copper (Cu)-copper (Cu) bonding, and the bonding of the first bonding insulating layer 299 and the second bonding insulating layer 199 can be, for example, dielectric-dielectric bonding, such as SiCN-SiCN bonding. The first substrate structure S1 and the second substrate structure S2 can be bonded to each other by a hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

[0176] The cell region insulating layer 190 can be configured to cover the lower surface of the board layer 101 and the gate electrode 130 on the lower surface of the board layer 101. The passivation layer 106 can be disposed on the upper surface of the board layer 101 and can have openings that expose the input / output pad regions (IOP). The passivation layer 106 can be used as a layer to protect the semiconductor device 100.

[0177] According to one or more embodiments, the unit region insulating layer 190 and passivation layer 106 may include at least one of insulating materials (e.g., silicon oxide, silicon nitride, or silicon carbide) and may be formed from multiple insulating layers.

[0178] Figure 10 It is a cross-sectional view of a semiconductor device according to one or more embodiments.

[0179] refer to Figure 10 The semiconductor device 100a may include a peripheral circuit region (PERI) and a memory cell region (CELL). The PERI includes a substrate 1, and the CELL includes a board layer 101. The CELL may be disposed on the PERI. In some embodiments, conversely, the CELL may be disposed below the PERI.

[0180] The above reference Figures 8 to 9A The description of the first semiconductor structure S1 can be applied to the peripheral circuit region PERI. However, unlike the first semiconductor structure S1, the peripheral circuit region PERI may not include the first bonding path 295, the first bonding pad 298, and the first bonding insulating layer 299 included in the bonding structure.

[0181] For the cell area, unless otherwise described, the above references to Figure 6 to 12 can be applied. Figure 8 The description of the second semiconductor structure S2 is as follows. However, unlike the second semiconductor structure S2, the memory cell region CELL may not include the second bonding path 195, the second bonding pad 198, and the second bonding insulating layer 199 included in the bonding structure, and may not include the passivation layer 106. The memory cell region CELL may also include a first horizontal conductive layer 102 and a second horizontal conductive layer 104, a horizontal insulating structure 110, and a substrate-penetrating insulating layer 121 located on the plate layer 101.

[0182] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be stacked sequentially and disposed on the upper surface of the plate layer 101. The first horizontal conductive layer 102 may be used as part of the common source line of the semiconductor device 100f, and may be used as the common source line together with the plate layer 101, for example. The first horizontal conductive layer 102 may be directly connected to the channel layer 140 at the periphery of each channel structure CH. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may include semiconductor materials, and may include, for example, polysilicon.

[0183] The horizontal insulating structure 110 may be disposed on the plate layer 101 parallel to the first horizontal conductive layer 102. The horizontal insulating structure 110 may include three horizontal insulating layers stacked sequentially on the plate layer 101. The horizontal insulating structure 110 may be a layer remaining after a portion of the semiconductor device 100a has been replaced with the first horizontal conductive layer 102 during the manufacturing process. The horizontal insulating structure 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0184] The substrate penetrating insulating layer 121 can be configured to penetrate the plate layer 101, the horizontal insulating structure 110, and the second horizontal conductive layer 104. The upper surface of the substrate penetrating insulating layer 121 can be coplanar with the upper surface of the second horizontal conductive layer 104, but this disclosure is not limited thereto. The substrate penetrating insulating layer 121 can include an insulating material, such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0185] In one or more embodiments, the first unit contact plug 152 and the second unit contact plug 154 can penetrate the gate electrode 130 and then penetrate the substrate and the insulating layer 121 to connect to the circuit interconnect 280 of the peripheral circuit region PERI.

[0186] Figures 11A to 11K This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device 100 according to one or more embodiments. Figures 11A to 11K It shows the corresponding Figure 8 The area.

[0187] refer to Figure 11A Substrate 201 can be prepared.

[0188] The substrate 201 may have an initial thickness Ti from the upper surface Sa to the lower surface Sr, and may be a semiconductor substrate, such as a silicon wafer. On the upper surface of the circuit elements on which the substrate 201 is disposed, regions for forming a high-voltage element region HR and a low-voltage element region LR may be defined and etched such that the upper surface of the high-voltage element region HR has a substrate step hs from the upper surface of the low-voltage element region LR. Therefore, the substrate 201 may have a first upper surface Sa in the low-voltage element region LR and a second upper surface Sb in the high-voltage element region HR, the second upper surface Sb being disposed at a height reduced by the substrate step hs. The initial thickness Ti, which is the length in the Z direction from the first upper surface Sa to the lower surface Sr of the substrate 201, may be greater than [a certain value]. Figure 8 The substrate thickness TS.

[0189] Impurities can be doped into the second element regions PR1 and PR2, where PMOS transistors are disposed in the high-voltage element region HR and the low-voltage element region LR, to form the first well region 206L and the second well region 206H, and element isolation layers 210a and 210b can be formed respectively. The element isolation layers 210a and 210b can be formed by forming shallow trenches and stacking oxides, but this disclosure is not limited thereto.

[0190] A preliminary gate dielectric layer 220p can be formed on the substrate 201 in the high-voltage element region HR with the same thickness T7 as the substrate step portion hs. The preliminary gate dielectric layer 220p can be formed with a large thickness using a material with a low dielectric constant (such as silicon oxide or silicon oxynitride).

[0191] An etch mask layer M can be further formed on the initial gate dielectric layer 220p. The etch mask layer M can be formed of polysilicon with a relatively thin thickness and can be selectively formed only in the high-voltage device region HR.

[0192] In the low-voltage element region LR, a channel structure 223 may be further formed on the substrate 201 of the second element region PR1 in the region formed by the second gate structure GS2. The channel structure 223 may include a semiconductor material with a band gap smaller than that of the substrate 201 material, and may include silicon germanium.

[0193] refer to Figure 11B A preliminary interface insulating layer 224p, a preliminary gate dielectric layer 225p, and a preliminary first conductive layer 233p can be sequentially formed in the entire low-voltage element region LR and the high-voltage element region HR.

[0194] The preliminary interface insulating layer 224p can be formed by stacking the materials included in the first and second interface insulating layers 224 as a whole on the first upper surface Sa and the second upper surface Sb of the substrate 201, and can be formed by depositing silicon oxide. The preliminary gate dielectric layer 225p can include a high-κ material, can be deposited to have a thickness greater than that of the preliminary interface insulating layer 224p, and can be formed by depositing hafnium oxide (HfO) on the preliminary interface insulating layer 224p, but this disclosure is not limited thereto.

[0195] The initial first conductive layer 233p may include a metal nitride and can be formed by depositing titanium nitride.

[0196] like Figure 11C As shown, the stacked material layer of the high-voltage component region HR can be etched to expose the etch mask layer M.

[0197] In other words, only the material layer stacked in the low-voltage element region LR can be retained, and the other layers in the high-voltage element region HR, from the initial interface insulating layer 224p stacked on the etch mask layer M to the initial first conductive layer 233p, can be completely removed.

[0198] refer to Figure 11D The initial second conductive layer 235p, the initial ohmic contact layer 238p, and the initial third conductive layer 237p can be stacked sequentially throughout the entire low-voltage component region LR and the high-voltage component region HR.

[0199] The initial second conductive layer 235p may include polysilicon and may be formed without boundary with the etch mask layer M by including the same material as the etch mask layer M.

[0200] The initial ohmic contact layer 238p can be formed using materials such as tantalum nitride or titanium nitride to have a relatively thin thickness. A preliminary third conductive layer 237p can be formed on the initial ohmic contact layer 238p. The preliminary third conductive layer 237p can include a metallic material such as tungsten or aluminum.

[0201] refer to Figure 11E The gate structures GS1, GS2, and GS4 of the first to fourth circuit elements TR1 to TR4 are specified. H A mask layer 239 is formed in the region, and then the mask layer 239 is etched to form gate structures GS1, GS2 and GS3 respectively. H .

[0202] Mask layer 239 may be silicon nitride or silicon oxynitride, and may be patterned as a mask to form gate structures GS1, GS2 and GS3 that define each circuit element TR1 to TR4. H .

[0203] Regarding the gate structures GS1, GS2 and GS H In terms of height, the second circuit element TR2 can be the highest, and the third circuit element TR3 and the fourth circuit element TR4 can be the lowest.

[0204] Then, by using gate structures GS1, GS2 and GS H Using a mask to perform ion implantation processes, ion implantation can be performed on the corresponding gate structures GS1, GS2, and GS3. H Source / drain regions 205aL, 205bL, 205aH, and 205bH are formed on both sides of the substrate 201. The source / drain regions 205aL, 205bL, 205aH, and 205bH may include those located on the gate structures GS1, GS2, and GS3, respectively. H The source region S and drain region D are located on both sides, and a low-concentration doped region 2 and a high-concentration doped region 4 can be formed on each of the source region S and drain region D.

[0205] Then, the gate structures GS1, GS2 and GS3 of each circuit element TR1 to TR4 can be configured. H Gate spacers 240 are formed on the two sidewalls, thereby forming gate structures GS1, GS2 and GS3. H Therefore, the first circuit element TR1 to the fourth circuit element TR4 can be completed.

[0206] Then, refer to Figure 11F A circuit structure can be formed on the first circuit element TR1 to the fourth circuit element TR4. The contact plug 285 can be formed by partially forming a peripheral insulating layer 290, then partially etching and removing the peripheral insulating layer, and then filling the removed portion with a conductive material. For example, the circuit interconnect 280 can be formed by depositing a conductive material and then patterning the conductive material.

[0207] Then, a first bonding insulating layer 299 can be formed on the circuit interconnect 280. After partially removing the first bonding insulating layer 299 and the peripheral region insulating layer 290, a first bonding passage 295 and a first bonding pad 298 of the first bonding structure can be formed.

[0208] This operation prepares the first substrate structure S1.

[0209] Next, refer to Figure 11G This allows for the fabrication of a second substrate structure S2.

[0210] The second substrate structure S2 can alternately stack sacrificial insulating layers and interlayer insulating layers 120 on the substrate Sub.

[0211] The substrate Sub is a layer removed by subsequent processes and can be a semiconductor substrate such as undoped silicon (Si). The sacrificial insulating layer can be removed by subsequent processes using gate electrode 130 (see [link to documentation]). Figure 8 The sacrificial insulating layer can be formed of a material that is etchable and has etch selectivity relative to the interlayer insulating layer 120. For example, the interlayer insulating layer 120 can be formed of at least one of silicon oxide or silicon nitride, and the sacrificial insulating layer can be formed of a material selected from silicon, silicon oxide, silicon carbide, and silicon nitride, different from the material of the interlayer insulating layer 120. In some embodiments, the thickness of the interlayer insulating layer 120 and the number of films included in the interlayer insulating layer 120 can be varied from those illustrated.

[0212] Then, in the region including the end of the sacrificial insulating layer, photolithography and etching processes can be repeated to form a stepped shape. The sacrificial insulating layer can be formed to have a relatively thick thickness at the end, and further processes can be performed on it. A portion of the cell region insulating layer 190 of the lower stacked structure covering the sacrificial insulating layer and the interlayer insulating layer 120 can be formed.

[0213] The vertical sacrificial layer can be formed corresponding to each channel structure, and the vertical sacrificial layer can include, for example, polysilicon.

[0214] A channel structure CH can be formed that penetrates the stacked structure of the sacrificial insulation layer and the interlayer insulation layer 120.

[0215] First, the vertical sacrificial layer can be removed to form a channel via. Next, a gate dielectric layer 145, a channel layer 140, a channel-filling insulating layer 147, and a channel pad 149 can be sequentially formed in each channel via to form a channel structure CH including a first channel structure CH1 and a second channel structure CH2. The channel layer 140 can be formed on the gate dielectric layer 145 in the channel structure CH. The channel-filling insulating layer 147 can be formed to fill the channel structure CH and can be an insulating material. However, according to one or more embodiments, the space between the channel layers 140 can be filled with a conductive material instead of the channel-filling insulating layer 147. The channel pad 149 can be formed of a conductive material and can be formed, for example, polysilicon.

[0216] Next, in the region corresponding to the separating region MS, an opening extending to the board layer 101 through the sacrificial insulating layer and the interlayer insulating layer 120 can be formed, and the sacrificial insulating layer can be removed by applying an etchant through the opening. The sacrificial insulating layer can be selectively removed relative to the interlayer insulating layer 120, for example, using wet etching.

[0217] The gate electrode 130 can be formed by depositing a conductive material in the region where the sacrificial insulating layer has been removed. The conductive material may include a metal, polysilicon, or a metal silicide. After forming the gate electrode 130, an insulating material may be deposited in the opening to form the separation region MS.

[0218] The first cell contact plug 152 can then be formed by depositing conductive material in the contact hole. A portion of the insulating material can also be removed when the contact sacrificial layer previously formed in the area forming the contact hole is removed. In this case, the insulating material can be completely removed from the pad region 130P, and the insulating material can be retained below it, thereby forming the contact insulating layer 125. The first cell contact plug 152 can be formed having a region extending horizontally from the pad region 130P, and thus can be physically and electrically connected to the gate electrode 130. The second cell contact plug 154 can be formed by forming a separate contact hole extending into the substrate Sub through the cell region insulating layer 190 outside the gate electrode 130 and depositing conductive material into the contact hole. The conductive material deposition process can be performed simultaneously with the deposition process for the first cell contact plug 152, but this disclosure is not limited thereto.

[0219] A second interconnect structure and a second bonding structure can be formed on the gate electrode 130. In the second interconnect structure, the cell contact 170 can be formed by etching the cell region insulating layer 190 on the channel pad 149 and the first cell contact plug 152 and the second cell contact plug 154 and depositing conductive material thereon. The cell interconnect line 180 can be formed by a conductive material deposition and patterning process, or by partially forming the cell region insulating layer 190, then patterning the cell region insulating layer 190 and depositing conductive material thereon.

[0220] In the second bonding structure, a second bonding insulating layer 199 can be formed on the cell region insulating layer 190. Then, the second bonding insulating layer 199 and the cell region insulating layer 190 can be partially removed, and a conductive material can be deposited to form a second bonding path 195, on which a second bonding pad 198 can then be formed. In some example embodiments, the vertically arranged second bonding path 195 and the second bonding pad 198 can be integrally formed with each other. The upper surface of the second bonding pad 198 can be exposed from the cell region insulating layer 190.

[0221] refer to Figure 11HThe first substrate structure S1 and the second substrate structure S2 can be connected to each other by joining the first bonding pad 298 and the second bonding pad 198 in an annealing and / or pressurizing process. Simultaneously, the first bonding insulating layer 299 and the second bonding insulating layer 199 can also be joined. At this time, the first substrate structure S1 on the second substrate structure S2 can be flipped so that the first bonding pad 298 faces downwards, and then bonding can be performed. The first substrate structure S1 and the second substrate structure S2 can be directly bonded to each other without the intervention of an adhesive such as a separate adhesive layer.

[0222] In the bonding structure of the first substrate structure S1 and the second substrate structure S2, a portion of the substrate 201 can be removed to reduce the thickness of the substrate 201 from the initial thickness Ti to the substrate thickness TS. In this case, a portion of the substrate 201 can be removed by a polishing process such as a grinding process.

[0223] refer to Figure 11I An opening OP1 can be formed in the area where the partition trench structure 230 is provided on the polished lower surface Sr of the exposed substrate 201.

[0224] The opening OP1 can be formed by performing laser etching or plasma etching, and can be formed in the third drain region 205aH(D) and channel region ACT of the third circuit element TR3. N The boundary between them is a groove extending in the Z direction from the lower surface Sr of the substrate 201 to a degree corresponding to a second distance d2 from the upper surface Sb of the substrate 201. The shape of the opening OP1 can be a strip shape in the XY plane, but it can also be a wall shape by extending along the Z direction.

[0225] In this case, the opening OP1 can be formed by using a stop to etch the lower surface of the component isolation layer 210b in one go until the lower surface of the component isolation layer 210b, and then sequentially etching the component isolation layer 210b to the target depth, but this disclosure is not limited thereto.

[0226] In each NMOS transistor in the polymer element region HR, there can be a third drain region 205aH(D) and a channel region ACT. N An opening OP1 is formed in the boundary between them, thereby preventing charge carriers from passing from the third drain region 205aH(D) through the channel region ACT. N The substrate 201 below is transferred.

[0227] refer to Figure 11J Insulating material can be filled into the opening OP1 to form a partition trench structure 230.

[0228] The insulating material may include silicon oxide, silicon nitride, and silicon oxynitride, and may be formed by depositing a high-κ material and then planarizing the high-κ material such that the lower surface of the separating trench structure 230 and the lower surface Sr of the substrate 201 are coplanar with each other.

[0229] refer to Figure 11K When the first substrate structure S1 and the second substrate structure S2, which are joined together, are flipped and placed on the carrier substrate 300, and the base substrate Sub of the second substrate structure S2 is exposed on its upper surface, the base substrate Sub can be removed.

[0230] For example, a portion of the substrate Sub can be removed from the upper surface in a polishing process such as a grinding process, and the remaining portion of the substrate Sub can be removed in an etching process such as a wet etching process. By removing the substrate Sub of the second substrate structure S2, the total thickness of the semiconductor device can be minimized. By removing the substrate Sub, the channel structure CH and the upper ends of the first cell contact plug 152 and the second cell contact plug 154 can be exposed. The gate dielectric layer 145 (see [reference]) can be partially removed from the upper part of the exposed channel structure CH. Figure 9B ).

[0231] Then, as Figure 8 As shown, a plate layer 101 can be formed on the upper part of the channel structure CH, and an insulating material can be deposited on the upper part of the exposed first unit contact plug 152 to form a covering insulating layer 105.

[0232] The plate layer 101 can be formed by depositing a semiconductor material. For example, the plate layer 101 can be formed by depositing amorphous silicon (Si) and then crystallizing the amorphous silicon (Si). A passivation layer 106 can be formed on the plate layer 101.

[0233] Therefore, it is possible to manufacture Figure 8 Semiconductor device 100.

[0234] Figure 12 This is a schematic diagram illustrating a data storage system including semiconductor devices according to one or more embodiments.

[0235] refer to Figure 12 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0236] Semiconductor device 1100 may be a non-volatile memory device, and may be, for example, the one referenced above. Figures 8 to 10 The NAND flash memory device described herein. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In some embodiments, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR located between the bit line BL and the common source line CSL.

[0237] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary in one or more embodiments.

[0238] In some implementations, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be the gate electrode of memory cell transistor MCT, and gate upper lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0239] In some embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 or the upper erase control transistor UT2 can be used for an erase operation to erase data stored in the memory cell transistor MCT by utilizing the GIDL phenomenon.

[0240] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the first structure 1100F to the second structure 1100S.

[0241] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output interconnects 1135 extending from the first structure 1100F to the second structure 1100S.

[0242] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to an example embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0243] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 for handling communication with semiconductor device 1100. Through NAND interface 1221, control commands for controlling semiconductor device 1100, data to be recorded in memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When receiving control commands from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control commands.

[0244] Figure 13 This is a perspective view schematically illustrating a data storage system including semiconductor devices according to one or more embodiments.

[0245] refer to Figure 13A data storage system 2000 according to one or more embodiments of the present disclosure may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be interconnected with the controller 2002 via interconnect patterns 2005 formed on the motherboard 2001.

[0246] The motherboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In some embodiments, the data storage system 2000 may communicate with the external host via, for example, an interface such as Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Memory (UFS). In some embodiments, the data storage system 2000 may be operated by power supplied from the external host through the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0247] The controller 2002 can record data to or read data from the semiconductor package 2003, or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0248] DRAM 2004 can be a buffer memory used to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 can also operate as a type of cache memory and can provide space for temporarily storing data during control operations of the semiconductor package 2003. When the data storage system 2000 includes DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0249] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 located on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0250] The package substrate 2100 may be a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 12 Input / output pads 1101. Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include the above-referenced... Figures 8 to 10 The semiconductor device described.

[0251] In some embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input / output pads 2210 and the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding wires and may be electrically connected to the on-package pads 2130 of the package substrate 2100. According to an example embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including silicon vias (TSVs) instead of a bonding wire connection structure 2400.

[0252] In some embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In one or more embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate, different from the motherboard 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected with each other via interconnects formed on the interposer substrate.

[0253] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims. Certain features described in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from the combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate, the substrate including an upper surface and a lower surface; A gate structure located on the upper surface of the substrate, the gate structure having a first length in a first direction parallel to the upper surface of the substrate; A drain region is disposed in the substrate and extends from the upper surface of the substrate on a first side of the gate structure in the first direction; A source region is disposed in the substrate and extends from the upper surface of the substrate on a second side of the gate structure, the second side of the gate structure being opposite to the first side of the gate structure in the first direction; A channel region is disposed in the substrate and extends from the upper surface of the substrate, located below the gate structure, and between the drain region and the source region; as well as A first separating trench structure extends from the lower surface of the substrate in a second direction perpendicular to the first direction, is disposed in the boundary region between the channel region and the drain region, and is spaced apart from the upper surface of the substrate.

2. The semiconductor device according to claim 1, in, The drain region has a first width in a third direction parallel to the upper surface of the substrate and perpendicular to the first direction, and Wherein, the length of the first separating trench structure in the third direction is equal to or greater than the first width of the drain region in the third direction.

3. The semiconductor device according to claim 1, in, The separation distance between the first separating trench structure and the upper surface of the substrate in the second direction is equal to or greater than the thickness of the inversion layer in the trench region.

4. The semiconductor device according to claim 1, in, The first dividing trench structure has an upper surface, and the upper surface of the first dividing trench structure has a second length in the first direction. Wherein, the second length of the upper surface of the first separating trench structure is less than the first length of the gate structure.

5. The semiconductor device according to claim 4, in, The upper surface of the first separating trench structure includes: The first portion, which is in contact with the drain region; and The second part extends from the first part along the first direction and contacts the channel region.

6. The semiconductor device according to claim 5, in, The length of the second portion of the upper surface of the first dividing groove structure in the first direction is equal to or greater than the length of the first portion of the upper surface of the first dividing groove structure in the first direction.

7. The semiconductor device according to claim 5, in, The drain region has a corner defined by at least the lower surface of the drain region and the side surface of the drain region, and the corner has a concave surface that contacts the first portion of the first separating trench structure.

8. The semiconductor device according to claim 4, in, The upper surface of the first separating trench structure is disposed at a height between the upper surface of the substrate and the lower surface of the drain region.

9. The semiconductor device according to claim 1, in, The lower surface of the first separating trench structure is coplanar with the lower surface of the substrate.

10. The semiconductor device according to claim 1, in, The width of the lower surface of the first dividing groove structure is greater than the width of the upper surface of the first dividing groove structure.

11. The semiconductor device according to claim 1, in, The first dividing groove structure includes a first side surface and a second side surface located between the upper surface and the lower surface of the first dividing groove structure and opposite to each other in the first direction. Wherein, the first side surface contacts the drain region at the upper part of the first separating trench structure, and the second side surface contacts the substrate at the upper part of the first separating trench structure.

12. The semiconductor device according to claim 11, in, The first separating trench structure contacts the side surface of the drain region at the upper part of the first side surface.

13. The semiconductor device according to claim 1, further comprising: A second separating trench structure extends from the lower surface of the substrate in the second direction and is spaced apart from the upper surface of the substrate, the second separating trench structure being disposed in the boundary region between the channel region and the source region.

14. The semiconductor device according to claim 13, in, The separation distance between the first separation trench structure and the second separation trench structure along the first direction is less than the first length of the gate structure.

15. The semiconductor device according to claim 1, in, The semiconductor device includes an NMOS transistor.

16. The semiconductor device according to claim 1, in, The drain region is configured to receive a drain voltage of 10V to 30V.

17. A semiconductor device, said semiconductor device comprising: A unit structure, the unit structure including a gate electrode, a channel structure extending through the gate electrode, and a contact plug connected to the gate electrode; as well as The peripheral circuit structure includes: A substrate electrically connected to the unit structure, the substrate having an upper surface and a lower surface; The first element region and the second element region are located in the substrate; The N-type first circuit element and the P-type second circuit element located in the first element region; and The N-type third circuit element and the P-type fourth circuit element are located in the second element region. Wherein, at least one of the N-type third circuit elements includes: A gate structure is located on the upper surface of the substrate. The gate structure includes a gate dielectric layer and a gate conductive layer located on the gate dielectric layer. The thickness of the gate dielectric layer of the gate structure is greater than the thickness of the gate dielectric layers of the N-type first circuit element and the P-type second circuit element. A drain region is disposed in the substrate and extends from the upper surface of the substrate on a first side of the gate structure in a first direction parallel to the upper surface of the substrate. A source region is disposed in the substrate and extends from the upper surface of the substrate on a second side of the gate structure, the second side of the gate structure being opposite to the first side of the gate structure in the first direction; A channel region, disposed in the substrate and extending from the upper surface of the substrate, located below the gate structure and between the drain region and the source region; and A separating trench structure extends from the lower surface of the substrate in a second direction perpendicular to the first direction and is spaced apart from the upper surface of the substrate, the separating trench structure being disposed in the boundary region between the channel region and the drain region.

18. The semiconductor device according to claim 17, in, The lower surface of the partition trench structure is coplanar with the lower surface of the substrate, and the upper surface of the partition trench structure is disposed at a height lower than the height of the upper surface of the substrate.

19. The semiconductor device according to claim 17, in, The drain region has a first length in a third direction parallel to the upper surface of the substrate, and the length of the separating trench structure in the third direction is equal to or greater than the first length of the drain region.

20. A data storage system, the data storage system comprising: A semiconductor memory device, the semiconductor memory device comprising: substrate; A first substrate structure, the first substrate structure including a first circuit element, a second circuit element, a third circuit element, and a fourth circuit element located on the substrate; and A second substrate structure, the second substrate structure including a memory cell and input and output pads electrically connected to the first circuit element to the fourth circuit element; and A controller, electrically connected to and controlling the semiconductor memory device via the input and output pads, Wherein, the first circuit element includes an NMOS transistor for low-voltage driving, the second circuit element includes a PMOS transistor for low-voltage driving, the third circuit element includes an NMOS transistor for high-voltage driving, and the fourth circuit element includes a PMOS transistor for high-voltage driving. Each of the third circuit elements includes: A gate structure is located on the upper surface of the substrate. The gate structure includes a gate dielectric layer and a gate conductive layer located on the gate dielectric layer. The thickness of the gate dielectric layer of the gate structure is greater than the thickness of the gate dielectric layers of the first circuit element and the second circuit element. A drain region is disposed in the substrate and extends from the upper surface of the substrate on a first side of the gate structure in a first direction parallel to the upper surface of the substrate. A source region is disposed in the substrate and extends from the upper surface of the substrate on a second side of the gate structure, the second side of the gate structure being opposite to the first side of the gate structure in the first direction; A channel region, disposed in the substrate and extending from the upper surface of the substrate, located below the gate structure and between the drain region and the source region; and A separating trench structure extends from the lower surface of the substrate in a second direction perpendicular to the first direction, the separating trench structure is disposed in the boundary region between the channel region and the drain region, and the upper end of the separating trench structure is spaced apart from the upper surface of the substrate.

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