Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes: a first lower epitaxial pattern on one side of a gate structure, where the first lower epitaxial pattern is connected to a lower active pattern; a first upper epitaxial pattern on the other side of the gate structure, where the first upper epitaxial pattern is connected to the upper active pattern; a cutting pattern spaced apart from the lower and upper active patterns, adjacent to the gate structure, and extending in the first direction; and a via structure connected to the first lower epitaxial pattern and the first upper epitaxial pattern in the dicing pattern, in which the via structure includes: a first pillar portion overlapping the first upper epitaxial pattern in the second direction; a second pillar portion overlapping the first lower epitaxial pattern in the second direction; and a connecting portion extending in the first direction to connect the first pillar portion and the second pillar portion.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0112902, filed on August 22, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to electronic devices, such as semiconductor devices and methods for manufacturing such semiconductor devices. More specifically, this invention may relate to semiconductor devices comprising stacked multi-gate transistors and methods for manufacturing such semiconductor devices. Background Technology

[0003] As one of the scaling techniques for increasing the density of integrated circuit devices, a multi-gate transistor is proposed, wherein a silicon body with a fin shape or nanowire shape is formed on a substrate, and a gate is formed on the surface of the silicon body.

[0004] Because this multi-gate transistor uses a three-dimensional channel, scaling can be performed relatively easily. Furthermore, current control capability can be improved even without increasing the gate length of the multi-gate transistor. Additionally, the short-channel effect (SCE), where the channel region potential is affected by the drain voltage, can be effectively suppressed.

[0005] In addition, in order to realize more components in the same area, semiconductor devices using stacked multi-gate transistors are being investigated, in which multi-gate transistors in the upper region are stacked on top of multi-gate transistors in the lower region. Summary of the Invention

[0006] Various aspects of the present invention can provide semiconductor devices with improved performance and integration.

[0007] Various aspects of the present invention can provide methods for manufacturing semiconductor devices with improved performance and integration.

[0008] However, the inventive concept is not limited to the aspects set forth herein. These and other aspects of the inventive concept will become more apparent to those skilled in the art upon reference to the following detailed description of the inventive concept.

[0009] According to aspects of the present invention, a semiconductor device is provided, comprising: a substrate; an upper active pattern extending on the substrate along a first direction; a lower active pattern located between the upper surface of the substrate and the upper active pattern in a second direction intersecting the first direction and the upper surface of the substrate, wherein the lower active pattern extends along the first direction; a gate structure extending on the lower and upper active patterns along a third direction intersecting the first and second directions; a first lower epitaxial pattern on a first side of the gate structure, wherein the first lower epitaxial pattern is connected to the lower active pattern; and a first upper epitaxial pattern. On the second side of the gate structure, a first upper epitaxial pattern is connected to an upper active pattern; a diced pattern, spaced apart from the lower and upper active patterns in a third direction, is adjacent to the gate structure and extends along a first direction; and a via structure, in the diced pattern, is connected to the first lower and first upper epitaxial patterns, wherein the via structure includes: a first pillar portion overlapping the first upper epitaxial pattern in a third direction; a second pillar portion overlapping the first lower epitaxial pattern in a third direction; and a connecting portion extending along the first direction and connecting the first pillar portion and the second pillar portion.

[0010] According to an aspect of the present invention, a semiconductor device is provided, comprising: a substrate; an upper active pattern extending on the substrate along a first direction; a lower active pattern located between the upper surface of the substrate and the upper active pattern in a second direction intersecting the first direction and an upper surface of the substrate, wherein the lower active pattern extends along the first direction; a gate structure extending on the lower active pattern and the upper active pattern in a third direction intersecting the first and second directions; a first lower epitaxial pattern on a first side of the gate structure, wherein the first lower epitaxial pattern is connected to the lower active pattern; a second lower epitaxial pattern on a second side of the gate structure, wherein the second lower epitaxial pattern is connected to the lower active pattern; and a first upper epitaxial pattern extending on the gate structure. A first side of the gate structure, wherein a first upper epitaxial pattern is connected to an upper active pattern; a second upper epitaxial pattern, on a second side of the gate structure, wherein the second upper epitaxial pattern is connected to the upper active pattern; a diced pattern, spaced apart from the lower active pattern and the upper active pattern in a third direction, adjacent to the gate structure, and extending along a first direction; and a via structure, in the diced pattern, connected to the second lower epitaxial pattern and the first upper epitaxial pattern, wherein the via structure includes: a first via recess extending from the upper surface of the via structure and overlapping the second upper epitaxial pattern in a third direction; and a second via groove extending from the lower surface of the via structure and overlapping the first lower epitaxial pattern in a third direction.

[0011] According to an aspect of the present invention, a semiconductor device is provided, comprising: a substrate including a first surface and a second surface opposite to the first surface in a first direction; a lower active pattern and an upper active pattern sequentially stacked along the first direction, and each of the lower active pattern and the upper active pattern extending along a second direction intersecting the first direction; an intermediate insulating pattern between the lower active pattern and the upper active pattern; a gate structure extending along a third direction intersecting the first and second directions, wherein each of the lower active pattern and the upper active pattern penetrates the gate structure; a first lower epitaxial pattern on a first side of the gate structure, wherein the first lower epitaxial pattern is connected to the lower active pattern; a second lower epitaxial pattern on a second side of the gate structure, wherein the second lower epitaxial pattern is connected to the lower active pattern; a first upper epitaxial pattern on a second side of the gate structure, wherein the first upper epitaxial pattern is connected to the upper active pattern; and a second upper epitaxial pattern on a gate junction. The second side of the structure includes a second upper epitaxial pattern connected to an upper active pattern; a diced pattern spaced apart from the lower active pattern and the upper active pattern in a third direction, adjacent to the gate structure, and extending along a first direction; and a via structure in the diced pattern, wherein the via structure includes: a connecting portion overlapping the intermediate insulating pattern and the gate structure in a third direction; a first pillar portion overlapping the first upper epitaxial pattern and not overlapping the second upper epitaxial pattern in a third direction; and a second pillar portion overlapping the second lower epitaxial pattern and not overlapping the first lower epitaxial pattern in a third direction; a first connecting pattern extending along a third direction on the upper surface of the first upper epitaxial pattern and connecting the first upper epitaxial pattern to the first pillar portion; and a second connecting pattern extending along a third direction on the lower surface of the second lower epitaxial pattern and connecting the second lower epitaxial pattern to the second pillar portion. Attached Figure Description

[0012] The above and other aspects and features of the inventive concept will become clearer by referring to the accompanying drawings, which describe embodiments of the inventive concept in detail, in which:

[0013] Figure 1 It is a layout diagram used to illustrate a semiconductor device according to some embodiments.

[0014] Figure 2 It is along Figure 1 A schematic cross-sectional view of section A-A'.

[0015] Figure 3 It is along Figure 1 A schematic cross-sectional view of the section taken from B-B'.

[0016] Figure 4 It is along Figure 1 A schematic cross-sectional view of the section cut from C-C'.

[0017] Figure 5 It is along Figure 1 A schematic cross-sectional view of the D-D' section.

[0018] Figure 6 It is along Figure 1 A schematic cross-sectional view taken from E-E'.

[0019] Figure 7 It is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments.

[0020] Figures 8 to 11 These are schematic cross-sectional views used to illustrate various semiconductor devices according to some embodiments.

[0021] Figure 12 It is a layout diagram used to illustrate a semiconductor device according to some embodiments.

[0022] Figures 13 to 45 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0023] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, without departing from the teachings of the inventive concept, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part.

[0024] Figure 1 It is a layout diagram used to illustrate a semiconductor device according to some embodiments. Figure 2 It is along Figure 1 A schematic cross-sectional view of section A-A'. Figure 3 It is along Figure 1 A schematic cross-sectional view of the section taken from B-B'. Figure 4 It is along Figure 1 A schematic cross-sectional view of the section cut from C-C'. Figure 5 It is along Figure 1 A schematic cross-sectional view of the D-D' section. Figure 6 It is along Figure 1 A schematic cross-sectional view taken from E-E'.

[0025] Reference Figures 1 to 6 According to some embodiments, a semiconductor device may include a first region I and a second region II.

[0026] The first region I and the second region II can be stacked (sequentially) along the first direction Z. Transistors of the same conductivity type can be formed in the first region I and the second region II, or transistors of different conductivity types can be formed. In the following description, it will be primarily assumed that the first region I is a PFET (p-type field-effect transistor) region and the second region II is an NFET (n-type field-effect transistor) region. However, this is merely an example, and those skilled in the art will understand that the first region I can be an NFET region and the second region II can be a PFET region, or both the first region I and the second region II can be NFET regions, or both the first region I and the second region II can be PFET regions.

[0027] The semiconductor device according to some embodiments may include a substrate 102, lower active patterns A11 and A12, upper active patterns A21 and A22, intermediate insulating pattern 115, gate structures G11, G12, G21, G22, G31 and G32, diced pattern 150, lower source / drain patterns 160A and 160B, a first etch stop layer 165, a first interlayer insulating film 190, upper source / drain patterns 260A and 260B, a second etch stop layer 265, a second interlayer insulating film 290, a front source / drain contact FCA, a front wiring structure FS, a rear source / drain contact BCA, a rear connection contact BCM, a rear wiring structure BS, and a via structure 180.

[0028] Substrate 102 may be bulk silicon or silicon-on-insulator (SOI). In some embodiments, substrate 102 may be a silicon substrate, or may include other materials, such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and / or gallium antimonide. In some embodiments, substrate 102 may be an epitaxial layer formed on a base substrate. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] In some embodiments, substrate 102 may be an insulating substrate comprising an insulating material. For example, substrate 102 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon oxycarbonitride, and / or combinations thereof. As an example, substrate 102 may include a silicon oxide film.

[0030] The substrate 102 may include a first surface 102a and a second surface 102b that are opposite each other (in a first direction Z). In this specification, the first surface 102a is also referred to as the front side (e.g., the upper side) of the substrate 102, and the second surface 102b is also referred to as the rear side (e.g., the lower side) of the substrate 102.

[0031] Lower active patterns A11 and A12 may be disposed in the first region I. Lower active patterns A11 and A12 may be spaced apart from the substrate 102 in a first direction Z. Lower active patterns A11 and A12 may be spaced apart from each other (in a third direction Y intersecting the first direction Z) and extend side-by-side along a second direction X intersecting the first direction Z. For example, lower active patterns A11 and A12 may each comprise a first lower active pattern A11 and a second lower active pattern A12 extending along the second direction X. The first lower active pattern A11 and the second lower active pattern A12 may be spaced apart from each other in a third direction Y intersecting the first direction Z and the second direction X. The first direction Z may be perpendicular to the first surface 102a and / or the second surface 102b. The second direction X and the third direction Y may be parallel to the first surface 102a and / or the second surface 102b. The second direction X and the third direction Y may intersect each other.

[0032] In some embodiments, each of the lower active patterns A11 and A12 may include a plurality of lower bridging patterns 111 and 112 that are sequentially stacked and spaced apart from each other (in the first direction Z). The lower bridging patterns 111 and 112 can be used as an MBCFET including a multi-bridge channel in the first region I. The channel region. The number of bridging patterns included in each of the active patterns A11 and A12 in the figure is an example embodiment and is not limited to the number shown in the figure.

[0033] Upper active patterns A21 and A22 may be disposed in the second region II. Upper active patterns A21 and A22 may be spaced apart from lower active patterns A11 and A12 in the first direction Z. Upper active patterns A21 and A22 may be spaced apart from each other (in the third direction Y) and may extend side-by-side along the second direction X. For example, each of the upper active patterns A21 and A22 may include a first upper active pattern A21 and a second upper active pattern A22 extending longer along the second direction X. The first upper active pattern A21 may be spaced apart from the first lower active pattern A11 in the first direction Z. The second upper active pattern A22 may be spaced apart from the second lower active pattern A12 in the first direction Z. The first upper active pattern A21 may overlap with the first lower active pattern A11 in the first direction Z, and the second upper active pattern A22 may overlap with the second lower active pattern A12 in the first direction Z.

[0034] In some embodiments, each of the active patterns A21 and A22 may include a plurality of upper bridging patterns 211 and 212 that are sequentially stacked and spaced apart from each other (in the first direction Z). The upper bridging patterns 211 and 212 may serve as channel regions for an MBCFET® that includes a multi-bridge channel in a second region II. The number of bridging patterns included in each of the active patterns A21 and A22 in the figure is an example embodiment and is not limited to the number shown in the figure.

[0035] Each of the lower active patterns A11 and A12 and the upper active patterns A21 and A22 may include silicon (Si) and / or germanium (Ge) as elemental semiconductor materials. In some embodiments, each of the lower active patterns A11 and A12 and the upper active patterns A21 and A22 may include a compound semiconductor, such as a group IV-IV compound semiconductor and / or a group III-V compound semiconductor. A group IV-IV compound semiconductor may be, for example, a binary or ternary compound comprising at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound formed by doping these elements with group IV elements. A group III-V compound semiconductor may be, for example, a binary, ternary, or quaternary compound formed by combining aluminum (Al), gallium (Ga), and / or indium (In), which are group III elements, with phosphorus (P), arsenic (As), and / or antimony (Sb), which are group V elements.

[0036] The intermediate insulating pattern 115 may lie between the lower active patterns A11 and A12 and the upper active patterns A21 and A22 in the first direction Z. For example, the intermediate insulating pattern 115 may lie between the first lower active pattern A11 and the first upper active pattern A21, and may lie between the second lower active pattern A12 and the second upper active pattern A22. In some embodiments, the intermediate insulating pattern 115 may extend relatively long along the second direction X.

[0037] The intermediate insulating pattern 115 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon carbonitride, and / or combinations thereof. As an example, the intermediate insulating pattern 115 may include a silicon nitride film.

[0038] Gate structures G11, G12, G21, G22, G31, and G32 may be formed on lower active patterns A11 and A12 and upper active patterns A21 and A22. Gate structures G11, G12, G21, G22, G31, and G32 may intersect with (e.g., overlap in the first direction Z) the lower active patterns A11 and A12 and the upper active patterns A21 and A22. For example, gate structures G11, G12, G21, G22, G31, and G32 may include a first gate structure G11, a second gate structure G12, a third gate structure G21, a fourth gate structure G22, a fifth gate structure G31, and a sixth gate structure G32, each extending in the third direction Y.

[0039] The first gate structure G11 may intersect with the first lower active pattern A11 and the first upper active pattern A21 (e.g., overlap in the first direction Z). The first gate structure G11 may be located between the third gate structure G21 and the fifth gate structure G31 in the second direction X. The second gate structure G12 may intersect with the second lower active pattern A12 and the second upper active pattern A22. The second gate structure G12 may be arranged together with the first gate structure G11 in the third direction Y. For example, the second gate structure G12 may overlap with the first gate structure G11 in the third direction Y. The second gate structure G12 may be located between the fourth gate structure G22 and the sixth gate structure G32 in the second direction X.

[0040] The third gate structure G21 may intersect with the first lower active pattern A11 and the first upper active pattern A21 (e.g., overlap in the first direction Z). The third gate structure G21 may be spaced apart from the first gate structure G11 in the second direction X. The fourth gate structure G22 may intersect with the second lower active pattern A12 and the second upper active pattern A22 (e.g., overlap in the first direction Z). The fourth gate structure G22 may be arranged together with the third gate structure G21 in the third direction Y. For example, the fourth gate structure G22 may overlap with the third gate structure G21 in the third direction Y.

[0041] The fifth gate structure G31 may intersect with the first lower active pattern A11 and the first upper active pattern A21 (e.g., overlap in the first direction Z). The fifth gate structure G31 may be spaced apart from the first gate structure G11 in the second direction X. The sixth gate structure G32 may intersect with the second lower active pattern A12 and the second upper active pattern A22 (e.g., overlap in the first direction Z). The sixth gate structure G32 may be arranged together with the fifth gate structure G31 along the third direction Y. For example, the sixth gate structure G32 may overlap with the fifth gate structure G31 in the third direction Y.

[0042] In some embodiments, each of the gate structures G11, G12, G21, G22, G31 and G32 may include a gate dielectric film 120, a first gate electrode 130, a second gate electrode 230, a gate spacer 140 and a gate capping film 145.

[0043] The gate dielectric film 120 may be located between the lower active patterns A11 and A12 and the first gate electrode 130, and between the upper active patterns A21 and A22 and the second gate electrode 230. The gate dielectric film 120 may include a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, a high dielectric constant material with a dielectric constant higher than that of silicon oxide, and / or combinations thereof. The high dielectric constant material may include, for example, but not limited to, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and / or combinations thereof.

[0044] Although the gate dielectric film 120 is shown as a single layer only, this is merely an example, and it is self-evident that the gate dielectric film 120 can also be a multilayer film formed by stacking multiple dielectric films. For example, the gate dielectric film 120 may include an interface film and a high-dielectric film sequentially stacked on the lower active patterns A11 and A12 and the upper active patterns A21 and A22. The interface film may include, for example, an oxide film formed by oxidizing the surfaces of the lower active patterns A11 and A12 and the surfaces of the upper active patterns A21 and A22. The high-dielectric-constant film may include, for example, a high-dielectric-constant material with a dielectric constant higher than silicon oxide.

[0045] In some embodiments, a portion of the gate dielectric film 120 may be located between the substrate 102 and the first gate electrode 130. For example, the gate dielectric film 120 may also extend along a first surface 102a of the substrate 102. In some embodiments, a portion of the gate dielectric film 120 may be located between the intermediate insulating pattern 115 and the first gate electrode 130 and / or between the intermediate insulating pattern 115 and the second gate electrode 230. For example, the gate dielectric film 120 may also extend along the periphery of the intermediate insulating pattern 115.

[0046] The first gate electrode 130 may be disposed in the first region I. The first gate electrode 130 may intersect with the lower active patterns A11 and A12 (e.g., overlap in the first direction Z). For example, each of the lower bridging patterns 111 and 112 may extend along the second direction X and penetrate (extend into) the first gate electrode 130. The first gate electrode 130 may extend around (e.g., around) the periphery of each of the lower bridging patterns 111 and 112.

[0047] The second gate electrode 230 may be disposed in the second region II. The second gate electrode 230 may intersect with the upper active patterns A21 and A22 (e.g., overlap in the first direction Z). For example, each of the upper bridging patterns 211 and 212 may extend along the second direction X and penetrate (extend into) the second gate electrode 230. The second gate electrode 230 may extend around (e.g., around) the periphery of each of the upper bridging patterns 211 and 212.

[0048] Each of the first gate electrode 130 and the second gate electrode 230 may include a conductive material, such as, but not limited to, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al and / or combinations thereof. Each of the first gate electrode 130 and the second gate electrode 230 may be formed by a substitution process, but is not limited thereto.

[0049] Although each of the first gate electrode 130 and the second gate electrode 230 is shown as a single-layer film in the figure, this is merely an example, and it is self-evident that they can each be formed by stacking multiple conductive films. For example, each of the first gate electrode 130 and the second gate electrode 230 may include a work function adjustment film for adjusting the work function, and a filling conductive film for filling the space formed by the work function adjustment film. The work function adjustment film may include, for example, TiN, TaN, TiC, TaC, TiAlC, and / or combinations thereof. The filling conductive film may include, for example, W and / or Al.

[0050] In some embodiments, each of the first gate electrode 130 and the second gate electrode 230 may comprise different conductive materials. For example, each of the first gate electrode 130 and the second gate electrode 230 may comprise a work function adjustment film with a different conductivity type. As an example, the first gate electrode 130 may comprise a p-type work function adjustment film, and the second gate electrode 230 may comprise an n-type work function adjustment film.

[0051] Despite Figure 4 The diagram shows the first gate electrode 130 and the second gate electrode 230 in direct contact with each other, but this is only an example. If desired, the first gate electrode 130 and the second gate electrode 230 can be electrically separated. For example, unlike the example shown, the intermediate insulating pattern 115 can extend along a third direction Y and (electrically) separate the first gate electrode 130 from the second gate electrode 230.

[0052] Gate spacer 140 may extend along the side surface of the first gate electrode 130 and the side surface of the second gate electrode 230. Each of the lower active patterns A11 and A12 and the upper active patterns A21 and A22 may extend along the second direction X and penetrate (extend into) gate spacer 140. Gate spacer 140 may include an insulating material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and / or combinations thereof.

[0053] In some embodiments, a portion of the gate dielectric film 120 may be located between the second gate electrode 230 and the gate spacer 140. For example, the gate dielectric film 120 may also extend along the inner surface of the gate spacer 140.

[0054] The gate capping film 145 may extend along the upper surface of the second gate electrode 230. The gate capping film 145 may include an insulating material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and / or combinations thereof.

[0055] The cutting pattern 150 can extend relatively long along the second direction X. The cutting pattern 150 can be spaced apart from the lower active patterns A11 and A12 and the upper active patterns A21 and A22 in the third direction Y. Multiple cutting patterns 150 can be spaced apart from each other in the third direction Y.

[0056] Gate structures G11, G12, G21, G22, G31, and G32 can be cut by a cutting pattern 150. For example, the cutting pattern 150 can extend along a second direction X between the first lower active pattern A11 and the second lower active pattern A12, and between the first upper active pattern A21 and the second upper active pattern A22. Such a cutting pattern 150 can separate the first gate structure G11 from the second gate structure G12 in the third direction Y, can separate the third gate structure G21 from the fourth gate structure G22 in the third direction Y, and can separate the fifth gate structure G31 from the sixth gate structure G32 in the third direction Y.

[0057] In some embodiments, the cutting pattern 150 may include a padding insulating film 152 and a filling insulating film 154 sequentially stacked on the side surfaces of each gate structure G11, G12, G21, G22, G31 and G32.

[0058] The pad insulating film 152 may be situated between each gate structure G11, G12, G21, G22, G31, and G32 and the filling insulating film 154. In some embodiments, the first gate electrode 130 and the second gate electrode 230 may be in direct contact with the pad insulating film 152. The pad insulating film 152 may include, for example, but not limited to, silicon oxide, silicon oxynitride, silicon carbonitride, and / or combinations thereof. As an example, the pad insulating film 152 may include a silicon nitride film.

[0059] The filler insulating film 154 can fill the area remaining after the cut pattern 150 is formed following the formation of the backing insulating film 152. The filler insulating film 154 may include, for example, but not limited to, silicon oxide, silicon oxynitride, silicon carbonitride, and / or combinations thereof. As an example, the filler insulating film 154 may include a silicon oxide film.

[0060] Lower source / drain patterns 160A and 160B can be formed within (above) the lower active patterns A11 and A12 on the side surfaces of the gate structures G11, G12, G21, G22, G31, and G32. Lower source / drain patterns 160A and 160B can include a first lower source / drain pattern 160A and a second lower source / drain pattern 160B. The first lower active pattern A11 can penetrate (extend into) the first gate electrode 130 and can be (electrically) connected to the first lower source / drain pattern 160A. The second lower active pattern A12 can penetrate (extend into) the first gate electrode 130 and can be (electrically) connected to the second lower source / drain pattern 160B. Lower source / drain patterns 160A and 160B can be spaced apart from the first gate electrode 130 by a gate spacer 140 and / or a gate dielectric film 120.

[0061] In some embodiments, each of the lower source / drain patterns 160A and 160B may include an epitaxial layer doped with impurities. For example, the first lower source / drain pattern 160A may include an epitaxial pattern grown from a first lower active pattern A11 by an epitaxial growth method. For example, the second lower source / drain pattern 160B may include an epitaxial pattern grown from a second lower active pattern A12 by an epitaxial growth method.

[0062] When the current active patterns A11 and A12 are the channel regions of the PFET, each of the lower source / drain patterns 160A and 160B may include P-type impurities (e.g., B, In, Ga and / or Al) and / or impurities to prevent the diffusion of P-type impurities.

[0063] In some embodiments, the first lower source / drain pattern 160A may include a first lower epitaxial pattern 1601 on one side of the first gate structure G11 and a second lower epitaxial pattern 1602 on the other side of the first gate structure G11 (e.g., on opposite sides in the second direction X). For example, the first lower epitaxial pattern 1601 may be located between the first gate structure G11 and the third gate structure G21 (in the second direction X). For example, the second lower epitaxial pattern 1602 may be located between the first gate structure G11 and the fifth gate structure G31 (in the second direction X).

[0064] A first etch stop layer 165 may be formed on the lower source / drain patterns 160A and 160B. The first etch stop layer 165 may extend along the contour of the surface of each of the lower source / drain patterns 160A and 160B. In some embodiments, the first etch stop layer 165 may also extend along a first surface 102a of the substrate 102 (on the first surface 102a of the substrate 102). The first etch stop layer 165 may include, for example, but not limited to, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and / or combinations thereof.

[0065] A first interlayer insulating film 190 may be formed on the first etch stop layer 165. The first interlayer insulating film 190 may be formed to fill the space on the first etch stop layer 165. The first interlayer insulating film 190 may include, for example, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, low dielectric constant materials with a dielectric constant less than that of silicon oxide, and / or combinations thereof. Low dielectric constant materials may include, for example, but not limited to, FOX (flowable oxide), TOSZ (Torene SilaZene), USG (undoped silica glass), BSG (borosilicate glass), PSG (phosphorus silica glass), BPSG (borosilicate glass), PETEOS (plasma-reinforced tetraethyl orthosilicate), FSG (fluorosilicate glass), CDO (carbon-doped silica), degelatin, aerogel, amorphous fluorocarbon, OSG (organosilicate glass), parylene, BCB (bisbenzocyclobutene), SiLK, polyimide, porous polymer materials, and / or combinations thereof.

[0066] Upper source / drain patterns 260A and 260B can be formed within (on top) upper active patterns A21 and A22 on the side surfaces of gate structures G11, G12, G21, G22, G31, and G32. Upper source / drain patterns 260A and 260B can include a first upper source / drain pattern 260A and a second upper source / drain pattern 260B. The first upper active pattern A21 can penetrate (extend into) the second gate electrode 230 and can be (electrically) connected to the first upper source / drain pattern 260A. The second upper active pattern A22 can penetrate (extend into) the second gate electrode 230 and can be (electrically) connected to the second upper source / drain pattern 260B. Upper source / drain patterns 260A and 260B can be spaced apart from the second gate electrode 230 by gate spacer 140 and / or gate dielectric film 120.

[0067] In some embodiments, each of the upper source / drain patterns 260A and 260B may include an epitaxial layer doped with impurities. For example, the first upper source / drain pattern 260A may include an epitaxial pattern grown from a first upper active pattern A21 by an epitaxial growth method. For example, the second upper source / drain pattern 260B may include an epitaxial pattern grown from a second upper active pattern A22 by an epitaxial growth method.

[0068] When the active patterns A21 and A22 are the channel regions of an NFET, each of the upper source / drain patterns 260A and 260B may include N-type impurities (e.g., P, Sb, and / or As) and / or impurities to prevent the diffusion of N-type impurities.

[0069] In some embodiments, the first upper source / drain pattern 260A may include a first upper epitaxial pattern 2601 on one side of the first gate structure G11 and a second upper epitaxial pattern 2602 on the other side of the first gate structure G11 (e.g., on the opposite side in the second direction X). For example, the first upper epitaxial pattern 2601 may be located between the first gate structure G11 and the third gate structure G21 (in the second direction X). For example, the second upper epitaxial pattern 2602 may be located between the first gate structure G11 and the fifth gate structure G31 (in the second direction X).

[0070] A second etch stop layer 265 may be formed on the upper source / drain patterns 260A and 260B. The second etch stop layer 265 may extend along the contour of the surface of each of the upper source / drain patterns 260A and 260B. In some embodiments, the second etch stop layer 265 may also extend along the upper surface of the first interlayer insulating film 190. The second etch stop layer 265 may be configured as an etch stop layer in an etching process for forming the front source / drain contact FCA. The second etch stop layer 265 may include, for example, but not limited to, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOCN), silicon boron nitride (SiBN), silicon boron oxycarbide (SiOBN), silicon oxycarbide (SiOC), and / or combinations thereof.

[0071] The second interlayer insulating film 290 may be formed on the second etch stop layer 265. The second interlayer insulating film 290 may be formed to fill the space above the second etch stop layer 265. The second interlayer insulating film 290 may include, for example, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon carbonitride, low dielectric constant materials with a dielectric constant less than that of silicon oxide, and / or combinations thereof.

[0072] A front source / drain contact FCA can be formed on the upper surfaces of the upper source / drain patterns 260A and 260B. The front source / drain contact FCA can be (electrically) connected to the upper source / drain patterns 260A and 260B. For example, the front source / drain contact FCA can extend along a first direction Z and penetrate (extend into) the second interlayer insulating film 290 and the second etch stop layer 265, respectively. In some embodiments, the front source / drain contact FCA can extend into the upper source / drain patterns 260A and 260B.

[0073] The front wiring structure FS can be formed on the first surface 102a of the substrate 102. For example, the front wiring structure FS can be formed on the upper surface of the second interlayer insulating film 290. The front wiring structure FS may include an interlayer insulating film FID, a multilayer front wiring pattern FM inside the interlayer insulating film FID, and a front via pattern FV (electrically) connected to the front wiring pattern FM. The number, quantity, and position of the interlayer insulating film FID, the front wiring pattern FM, and the front via pattern FV shown in the figure are merely examples and are not limited to the number, quantity, and position shown in the figure.

[0074] Although not specifically shown, each of the front wiring pattern FM and the front via pattern FV may include a barrier conductive film and a fill conductive film. The barrier conductive film may include a metal and / or a metal nitride for preventing diffusion of the fill conductive film. The barrier conductive film may include, for example, but not limited to, titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and / or their nitrides. The fill conductive film may include, for example, but not limited to, aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and / or their alloys.

[0075] The front wiring structure FS can provide signal lines and / or power lines for electronic components (e.g., field-effect transistors) on the first surface 102a of the substrate 102. For example, the front wiring structure FS can be electrically connected to the upper source / drain patterns 260A and 260B and / or the second gate electrode 230. As an example, such as Figure 6 As shown, the second upper epitaxial pattern 2602 can be electrically connected to at least one front via pattern FV via at least one front source / drain contact FCA.

[0076] In some embodiments, such as Figure 4 As shown, the gate contact CB can be formed on the second gate electrode 230. The gate contact CB penetrates (extends into) the gate capping film 145 and can electrically connect the second gate electrode 230 to some front wiring pattern FM.

[0077] The back source / drain contact BCA can be formed on the lower surface of the lower source / drain patterns 160A and 160B. The back source / drain contact BCA can be (electrically) connected to the lower source / drain patterns 160A and 160B. For example, each back source / drain contact BCA can extend along the first direction Z and penetrate (extend into) the substrate 102.

[0078] In some embodiments, a contact spacer 108 may be formed between the substrate 102 and each downstream source / drain contact BCA. The contact spacer 108 may extend along a side surface of each downstream source / drain contact BCA. The contact spacer 108 may include an insulating material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon carbonitride, and / or combinations thereof.

[0079] The back connection contact portion BCM can be formed on the second surface 102b of the substrate 102. The back connection contact portion BCM can be (electrically) connected to the back source / drain contact portion BCA. For example, a third interlayer insulating film 109 can be formed on the second surface 102b of the substrate 102. The back connection contact portion BCM can extend along the first direction Z and penetrate (extend into) the third interlayer insulating film 109.

[0080] The back wiring structure BS can be formed on the second surface 102b of the substrate 102. For example, the back wiring structure BS can be formed on the lower surface of the third interlayer insulating film 109. The back wiring structure BS may include a back interlayer insulating film BID, a multilayer back wiring pattern BM inside the back interlayer insulating film BID, and a back via pattern BV (electrically) connected to the back wiring pattern BM. The number, quantity, and position of the back interlayer insulating film BID, the back wiring pattern BM, and the back via pattern BV shown in the figure are merely examples and are not limited to the number, quantity, and position shown in the figure.

[0081] Although not specifically shown, each of the back wiring pattern BM and the back via pattern BV may include a barrier conductive film and a fill conductive film. The barrier conductive film may include a metal and / or metal nitride for preventing diffusion of the fill conductive film. The barrier conductive film may include, for example, but not limited to, titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and / or their nitrides. The fill conductive film may include, for example, but not limited to, aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and / or their alloys.

[0082] The back wiring structure BS can provide signal lines and / or power lines for electronic components (e.g., field-effect transistors) on the second surface 102b of the substrate 102. For example, the back wiring structure BS can be electrically connected to the lower source / drain patterns 160A and 160B and / or the first gate electrode 130. As an example, such as Figure 5 As shown, the first lower epitaxial pattern 1601 can be electrically connected to at least one rear via pattern BV via at least one rear source / drain contact BCA and at least one rear connection contact BCM.

[0083] The via structure 180 can be formed inside the cut pattern 150. The via structure 180 can be spaced apart from the upper and lower active patterns A11 and A12 and the upper active patterns A21 and A22 in the third direction Y. The via structure 180 may include a connecting portion 182, a first pillar portion 184, and a second pillar portion 186. The connecting portion 182, the first pillar portion 184, and the second pillar portion 186 can be integrally formed to form the via structure 180. For example, the connecting portion 182, the first pillar portion 184, and the second pillar portion 186 can be connected to each other without a (visible) boundary.

[0084] The connection portion 182 may overlap with the first gate structure G11 in the third direction Y. The connection portion 182 may extend along the second direction X and connect the first pillar portion 184 and the second pillar portion 186. In some embodiments, the connection portion 182 may overlap with the intermediate insulating pattern 115 in the third direction Y.

[0085] The first pillar portion 184 may overlap with the first upper epitaxial pattern 2601 in the third direction Y. For example, the first pillar portion 184 may extend upward (e.g., along the direction toward the front wiring structure FS) from the upper surface of one side of the connection portion 182 (the first side in the second direction X). In some embodiments, the first pillar portion 184 may not overlap with the second upper epitaxial pattern 2602 in the third direction Y. In some embodiments, the first pillar portion 184 may not overlap with the second gate electrode 230 of the first gate structure G11 in the third direction Y.

[0086] The connecting portion 182 and the first pillar portion 184 may define a first via recess 180r1 of the via structure 180. The first via recess 180r1 may extend downward from the upper surface of the via structure 180 (e.g., toward the rear wiring structure BS). The side surface of the first via recess 180r1 may be defined by the inner surface (side surface) of the first pillar portion 184, and the lower surface of the first via recess 180r1 may be defined by the upper surface of the connecting portion 182. In some embodiments, the first via recess 180r1 may overlap with the second upper epitaxial pattern 2602 in the third direction Y. In some embodiments, the first via recess 180r1 may overlap with the second gate electrode 230 of the first gate structure G11 in the third direction Y.

[0087] In some embodiments, such as Figure 3 As shown, the first through-hole recess 180r1 may include a curved surface connecting the lower surface of the first through-hole recess 180r1 to the side surface of the first through-hole recess 180r1. For example, in the region adjacent to the connecting portion 182, the width of the first pillar portion 184 in the second direction X may gradually decrease as it moves away from the connecting portion 182. This may be due to the characteristics of the recessing process used to form the first through-hole recess 180r1.

[0088] The second pillar 186 may overlap with the second lower epitaxial pattern 1602 in the third direction Y. For example, the second pillar 186 may extend downward (e.g., in the direction toward the rear wiring structure BS) from the lower surface of the other side of the connector 182 (the second side opposite to the first side in the second direction X). In some embodiments, the second pillar 186 may not overlap with the first lower epitaxial pattern 1601 in the third direction Y. In some embodiments, the second pillar 186 may not overlap with the first gate electrode 130 of the first gate structure G11 in the third direction Y.

[0089] The connecting portion 182 and the second pillar portion 186 may define a second via recess 180r2 of the via structure 180. The second via recess 180r2 may extend upward from the lower surface of the via structure 180 (e.g., along the direction of the forward wiring structure FS). The side surface of the second via recess 180r2 may be defined by the inner surface (side surface) of the second pillar portion 186, and the upper surface of the second via recess 180r2 may be defined by the lower surface of the connecting portion 182. In some embodiments, the second via recess 180r2 may overlap with the first lower epitaxial pattern 1601 in the third direction Y. In some embodiments, the second via recess 180r2 may overlap with the first gate electrode 130 of the first gate structure G11 in the third direction Y.

[0090] In some embodiments, such as Figure 3 As shown, the second through-hole recess 180r2 may include a curved surface connecting the upper surface of the second through-hole recess 180r2 to the side surface of the second through-hole recess 180r2. For example, in the region adjacent to the connecting portion 182, the width of the second pillar portion 186 in the second direction X may gradually decrease as it moves away from the connecting portion 182. This may be due to the characteristics of the recessing process used to form the second through-hole recess 180r2.

[0091] The insulating filling film 154 can fill the first via recess 180r1 and the second via recess 180r2. For example, the insulating filling film 154 may include a main filling film 154a, a first recess filling film 154b, and a second recess filling film 154c. The first recess filling film 154b may be located between the main filling film 154a and the first pillar portion 184 in the second direction X. The first recess filling film 154b can fill the first via recess 180r1. The second recess filling film 154c may be located between the main filling film 154a and the second pillar portion 186 in the second direction X. The second recess filling film 154c can fill the second via recess 180r2. Figure 3 Although the diagram shows the boundaries between the main filling film 154a and the first recessed filling film 154b, as well as the boundaries between the main filling film 154a and the second recessed filling film 154c, this is merely an example. In some cases, the boundaries between the main filling film 154a and the first recessed filling film 154b and / or the boundaries between the main filling film 154a and the second recessed filling film 154c may not exist (may be invisible).

[0092] In some embodiments, the height of the lower surface of the first via recess 180r1 may be the same as or lower than the height of the upper surface of the intermediate insulating pattern 115. In some embodiments, the lower surface of the first via recess 180r1 may be coplanar with the lower surface of the second upper epitaxial pattern 2602. In this document, the terms "horizontal," "vertical horizontal," "height," etc., may refer to a relative position relative to a reference element in the first direction Z. For example, horizontal, vertical horizontal, height, etc., may be the distance from the lower surface of the rear wiring inter-insulating film BID in the first direction Z. For example, a higher level may indicate a greater distance from the lower surface of the rear wiring inter-insulating film BID in the first direction Z, and a lower level may indicate a closer distance from the lower surface of the rear wiring inter-insulating film BID in the first direction Z.

[0093] In some embodiments, the height of the upper surface of the second via recess 180r2 may be the same as or higher than the height of the lower surface of the intermediate insulating pattern 115. In some embodiments, the upper surface of the second via recess 180r2 may be coplanar with the upper surface of the first lower extension pattern 1601.

[0094] In some embodiments, the first post portion 184 and the second post portion 186 may not overlap in the first direction Z. For example, as Figure 3 As shown, the portion of the first through hole recess 180r1 adjacent to the first pillar portion 184 and the portion of the second through hole recess 180r2 adjacent to the second pillar portion 186 can overlap in the first direction Z.

[0095] The via structure 180 can electrically connect the first region I to the second region II across at least one of the gate structures G11, G12, G21, G22, G31, and G32. For example, as shown, the via structure 180 can electrically connect the first upper epitaxial pattern 2601 to the second lower epitaxial pattern 1602 across the first gate structure G11. For example, a first connection pattern FCA1 can be formed extending in the third direction Y and electrically connecting the first upper epitaxial pattern 2601 to the first pillar 184. Furthermore, for example, a second connection pattern BCM1 can be formed extending in the third direction Y and electrically connecting the second lower epitaxial pattern 1602 to the second pillar 186. Accordingly, the first upper epitaxial pattern 2601 and the second lower epitaxial pattern 1602 can be electrically connected.

[0096] In some embodiments, the first connecting pattern FCA1 may directly contact the side surface of the first column portion 184, such as Figure 5As shown. In some embodiments, the first connection pattern FCA1 may be included in the front source / drain contact FCA. For example, the first connection pattern FCA1 may be formed at the same level as other front source / drain contact FCAs that are not connected to the first upper epitaxial pattern 2601. In this specification, the term "same level" (e.g., elements at the same level) may refer to a level (e.g., an element) formed by the same manufacturing process.

[0097] In some embodiments, such as Figure 6 As shown, the second connection pattern BCM1 can directly contact the lower surface of the second column portion 186. In some embodiments, the second connection pattern BCM1 can be included in the rear connection contact portion BCM. For example, the second connection pattern BCM1 can be formed at the same level as other rear connection contact portions BCMs that are not connected to the second lower extension pattern 1602.

[0098] In some embodiments, the via structure 180 may be electrically connected to the front wiring structure FS. For example, the first connection pattern FCA1 may be (electrically) connected to some front via patterns FV.

[0099] As semiconductor devices become increasingly integrated, individual circuit patterns are becoming more and more intricate to accommodate more components within the same area. To this end, semiconductor devices using stacked multi-gate transistors are being investigated, where multi-gate transistors in an upper region (e.g., second region II) are stacked on top of multi-gate transistors in a lower region (e.g., first region I). However, such semiconductor devices suffer from difficulties in achieving high integration density due to the complexity of their circuit patterns.

[0100] For example, depending on the design, a via may be needed to connect the lower and upper regions across the gate. However, such a via can degrade the performance of the semiconductor device by increasing the parasitic capacitance of the gate and / or source / drain patterns opposite the via.

[0101] Conversely, in a semiconductor device according to some embodiments, a via structure 180 that electrically connects a first region I and a second region II across a first gate structure G11 can reduce parasitic capacitance. Specifically, as described above, the via structure 180 may include a first via recess 180r1 overlapping the first gate structure G11 and / or the second upper epitaxial pattern 2602 in a third direction Y. Furthermore, as described above, the via structure 180 may include a second via recess 180r2 overlapping the first gate structure G11 and / or the first lower epitaxial pattern 1601 in a third direction Y. This via structure 180 can reduce parasitic capacitance by reducing the relative area with the first gate structure G11, the second upper epitaxial pattern 2602, and / or the first lower epitaxial pattern 1601.

[0102] Furthermore, the via structure 180 may have a connection portion 182, a first pillar portion 184, and a second pillar portion 186 defined by a first via recess 180r1 and a second via recess 180r2. Since the connection portion 182, the first pillar portion 184, and the second pillar portion 186 can be integrally formed, resistance degradation due to interface resistance can be reduced (e.g., prevented). Accordingly, a semiconductor device with improved performance and integration can be provided.

[0103] exist Figures 1 to 6 In the above description, the via structure 180 spans only one row of gate structures (i.e., the first gate structure G11 and the second gate structure G12), but this is merely an example. Those skilled in the art to which this invention pertains will understand that the connection portion 182 of the via structure 180 may also intersect with two or more rows of gate structures to connect the first region I to the second region II.

[0104] Figure 7 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the description may be brief or omitted. Figures 1 to 6 The repeated parts of the description. For reference, Figure 7 It is along Figure 1 Another schematic cross-sectional view taken from A-A'.

[0105] Reference Figure 1 and Figure 7 In a semiconductor device according to some embodiments, via structure 180 may be electrically connected to a back wiring structure BS. For example, a second connection pattern BCM1 may be (electrically) connected to some back via patterns BV.

[0106] Figures 8 to 11 These are schematic cross-sectional views used to illustrate various semiconductor devices according to some embodiments. For ease of explanation, the descriptions may be brief or omitted. Figures 1 to 7 The repeated parts of the description. For reference, Figures 8 to 11 They are along Figure 1 Another schematic cross-sectional view of the B-B' section.

[0107] Reference Figure 1 and Figure 8 In a semiconductor device according to some embodiments, the first pillar 184 and / or the second pillar 186 may have an inclined surface (inclined side surface).

[0108] For example, the outer surface of the first pillar 184 facing the main filler film 154a may form a non-right-angled first exterior angle θ11 with the upper surface of the main filler film 154a. Similarly, the outer surface of the second pillar 186 facing the main filler film 154a may form a non-right-angled second exterior angle θ12 with the lower surface of the main filler film 154a. In some embodiments, the first exterior angle θ11 may be an obtuse angle, and the second exterior angle θ12 may be an acute angle. This may be due to the characteristics of the etching process used to form the via structure 180.

[0109] For example, the inner surface of the first pillar portion 184 facing the first recessed filling film 154b may form a third external angle θ21, which is not perpendicular to the upper surface of the first recessed filling film 154b. In some embodiments, the third external angle θ21 may be an acute angle. This may be due to the characteristics of the recessing process used to form the first through-hole recess 180r1.

[0110] For example, the inner surface of the second pillar 186 facing the second recessed filling film 154c may form a non-right-angled fourth exterior angle θ22 with the lower surface of the second recessed filling film 154c. In some embodiments, the fourth exterior angle θ22 may be an acute angle. This may be due to the characteristics of the recessing process used to form the second through-hole recess 180r2.

[0111] Reference Figure 1 , Figure 2 and Figure 9 In a semiconductor device according to some embodiments, the height of the lower surface of the first via recess 180r1 may be lower than the height of the lower surface of the second upper epitaxial pattern 2602, and / or the height of the upper surface of the second via recess 180r2 may be higher than the height of the upper surface of the first lower epitaxial pattern 1601.

[0112] For example, the height of the lower surface of the first via recess 180r1 can be lower than the height of the upper surface of the intermediate insulating pattern 115, or the height of the upper surface of the second via recess 180r2 can be lower than the upper surface of the intermediate insulating pattern 115. Figure 3 Compared to the via structure 180, this via structure 180 can also reduce parasitic capacitance by reducing the relative area with the first gate structure G11, the second upper epitaxial pattern 2602 and / or the first lower epitaxial pattern 1601.

[0113] Reference Figure 1 , Figure 2 and Figure 10 In a semiconductor device according to some embodiments, the connection portion 182 may overlap with the second upper epitaxial pattern 2602 and / or the first lower epitaxial pattern 1601 in a third-direction Y.

[0114] For example, the height of the lower surface of the first via recess 180r1 may be higher than the height of the lower surface of the second upper epitaxial pattern 2602. In some embodiments, the height of the lower surface of the first via recess 180r1 may be higher than the height of the upper surface of the intermediate insulating pattern 115. Figure 3 Compared to the via structure 180, this via structure 180 can have a larger volume, and therefore, can have a further reduced resistance.

[0115] For example, the height of the upper surface of the second via recess 180r2 may be lower than the height of the upper surface of the first lower epitaxial pattern 1601. In some embodiments, the height of the upper surface of the second via recess 180r2 may be lower than the height of the lower surface of the intermediate insulating pattern 115. Figure 3 Compared to the via structure 180, this via structure 180 can have a larger volume, and therefore, can have a further reduced resistance.

[0116] Reference Figure 1 and Figure 11 In a semiconductor device according to some embodiments, the first pillar 184 and / or the second pillar 186 may overlap with the first gate structure G11 in the third direction Y.

[0117] For example, the inner surface of the first pillar portion 184, opposite to the first recessed filling film 154b, can overlap with the second gate electrode 230 of the first gate structure G11 in the third direction Y. Figure 3 Compared to the via structure 180, this first pillar 184 can have a larger volume, and therefore can have a further reduced resistance.

[0118] For example, the inner surface of the second pillar 186, facing the second recessed filling film 154c, can overlap with the first gate electrode 130 of the first gate structure G11 in the third direction Y. Figure 3 Compared to the via structure 180, this second pillar 186 can have a larger volume, and therefore, can have a further reduced resistance.

[0119] Figure 12 This is a layout diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the description may be brief or omitted. Figures 1 to 11 The repeated parts of the description.

[0120] Reference Figure 12 In a semiconductor device according to some embodiments, a via structure 180 may electrically connect a first upper source / drain pattern 260A to a second lower source / drain pattern 160B across at least one of gate structures G11, G12, G21, G22, G31 and G32.

[0121] For example, the second lower source / drain pattern 160B may include a third lower epitaxial pattern 1603 on one side of the first gate structure G11 (e.g., the first side in the second direction X) and a fourth lower epitaxial pattern 1604 on the other side of the first gate structure G11 (e.g., the second side in the second direction X opposite to the first side). Furthermore, for example, a third connection pattern BCM2 may be formed extending along the third direction Y and (electrically) connecting the fourth lower epitaxial pattern 1604 to the second pillar portion 186. Accordingly, the first upper epitaxial pattern 2601 and the fourth lower epitaxial pattern 1604 may be electrically connected.

[0122] In the following text, reference will be made to Figures 1 to 45 A method for manufacturing a semiconductor device according to an example embodiment is described.

[0123] Figures 13 to 45 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments. For ease of description, the above descriptions may be brief or omitted. Figures 1 to 12 The repeated parts of the description.

[0124] Reference Figure 13 and Figure 14 A fin structure FP and a dummy gate structure DG are formed on a substrate 100.

[0125] The fin structure FP can extend relatively long along the second direction X. The fin structure FP may include fin pattern 110, lower bridging patterns 111 and 112, first sacrificial pattern 310, sacrificial separation pattern 115S, upper bridging patterns 211 and 212, and second sacrificial pattern 320.

[0126] The fin pattern 110 may protrude from the upper surface of the substrate 100 and extend along the second direction X. Lower bridging patterns 111 and 112 and a first sacrificial pattern 310 may be alternately stacked on the fin pattern 110. A sacrificial separation pattern 115S may be stacked on the lower bridging patterns 111 and 112 and the first sacrificial pattern 310. Upper bridging patterns 211 and 212 and a second sacrificial pattern 320 may be alternately stacked on the sacrificial separation pattern 115S.

[0127] The first sacrificial pattern 310 and the second sacrificial pattern 320 may include materials that are etch-selective relative to the lower bridging patterns 111 and 112 and the upper bridging patterns 211 and 212. As an example, each of the lower bridging patterns 111 and 112 and the upper bridging patterns 211 and 212 may include a silicon film, and each of the first sacrificial pattern 310 and the second sacrificial pattern 320 may include a silicon-germanium film.

[0128] The sacrificial separation pattern 115S may include a material having etch selectivity relative to the lower bridging patterns 111 and 112, the first sacrificial pattern 310, the upper bridging patterns 211 and 212, and the second sacrificial pattern 320. As an example, each of the first sacrificial pattern 310 and the second sacrificial pattern 320 may include a silicon-germanium film containing a first concentration of germanium (Ge), and the sacrificial separation pattern 115S may include a silicon-germanium film containing a second concentration of germanium (Ge) that is different from (e.g., greater than) the first concentration.

[0129] A dummy gate structure DG can be formed on the fin structure FP. The dummy gate structure DG can intersect with the fin structure FP (e.g., overlap in the first direction Z). For example, the dummy gate structure DG can extend relatively long along the third direction Y.

[0130] The dummy gate structure (DG) may include a dummy gate electrode 330, a gate spacer 140, and a gate mask pattern 350. For example, a material film may be formed on a fin structure (FP). Next, a gate mask pattern 350 extending in a third direction (Y) may be formed on the material film. Next, a patterning process may be performed using the gate mask pattern 350 as an etching mask to pattern the material film, and the dummy gate electrode 330 may be formed from the material film. Next, a gate spacer 140 extending along the side surface of the dummy gate electrode 330 may be formed.

[0131] The dummy gate electrode 330 may include a material that has etch selectivity relative to the lower bridging patterns 111 and 112 and the upper bridging patterns 211 and 212. For example, the dummy gate electrode 330 may include a polysilicon film.

[0132] Reference Figure 15 This can form an intermediate insulating pattern 115.

[0133] For example, the sacrificial separation pattern 115S can be selectively removed. Next, an intermediate insulating pattern 115 can be formed to replace the area where the sacrificial separation pattern 115S was removed. Accordingly, a fin structure FP including the intermediate insulating pattern 115 can be provided.

[0134] Reference Figure 16 Using the dummy gate structure DG, a recess process can be performed on the upper bridging patterns 211 and 212 and the second sacrificial pattern 320.

[0135] As the recessing process is performed, upper source / drain recesses 210r can be formed in the upper bridging patterns 211 and 212 and the second sacrificial pattern 320. In some embodiments, the lower surface of the upper source / drain recess 210r may be lower than the upper surface of the intermediate insulating pattern 115.

[0136] A spacer membrane 142 can then be formed. The spacer membrane 142 can extend conformally along the contour of the upper source / drain recess 210r. The spacer membrane 142 may include an insulating material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon carbonitride, and / or combinations thereof.

[0137] Reference Figure 17 The spacer membrane 142 can be used to perform a recessing process on the lower bridging patterns 111 and 112 and the first sacrificial pattern 310.

[0138] As the recessing process is performed, a lower source / drain recess 110r can be formed inside the lower bridging patterns 111 and 112 and the first sacrificial pattern 310. In some embodiments, the lower surface of the lower source / drain recess 110r may be lower than the upper surface of the fin pattern 110.

[0139] Reference Figure 18 This can form source / drain patterns 160A and 160B.

[0140] Lower source / drain patterns 160A and 160B can be formed by an epitaxial growth process using lower bridging patterns 111 and 112 as seed layers. Accordingly, lower source / drain patterns 160A and 160B connected to lower active patterns A11 and A12 can be formed.

[0141] In some embodiments, a holding pattern 360 may be formed within the fin pattern 110. Lower source / drain patterns 160A and 160B may be formed on the holding pattern 360. The holding pattern 360 may comprise a material having etch selectivity relative to the substrate 100 and / or the fin pattern 110. As an example, the substrate 100 may be a silicon substrate, the fin pattern 110 may be a silicon pattern, and the holding pattern 360 may be a silicon-germanium pattern. In some embodiments, unlike the example shown, the holding pattern 360 may be omitted.

[0142] Reference Figure 19 A first etch stop layer 165 and a first interlayer insulating film 190 can be formed on the spacer film 142 and the lower source / drain patterns 160A and 160B.

[0143] The first etch stop layer 165 and the first interlayer insulating film 190 may cover the lower source / drain patterns 160A and 160B. In some embodiments, the upper surface of the first interlayer insulating film 190 may be formed below the lower surface of the upper active patterns A21 and A22.

[0144] After the first etch stop layer 165 and the first interlayer insulating film 190 are formed, the bridging patterns 211 and 212 and the second sacrificial pattern 320 can be exposed from the spacer film 142.

[0145] Reference Figure 20 This can form source / drain patterns 260A and 260B.

[0146] The upper source / drain patterns 260A and 260B can be formed by an epitaxial growth process using upper bridging patterns 211 and 212 as seed layers. Accordingly, upper source / drain patterns 260A and 260B connected to the upper active patterns A21 and A22 can be formed.

[0147] Reference Figure 21 and Figure 22 This forms the initial gate structures PG1, PG2 and PG3.

[0148] For example, a second etch stop layer 265 and a second interlayer insulating film 290 can be formed on the upper source / drain patterns 260A and 260B. Next, the gate mask pattern 350, the dummy gate electrode 330, the first sacrificial pattern 310, and the second sacrificial pattern 320 can be removed sequentially. The dummy gate electrode 330, the first sacrificial pattern 310, and the second sacrificial pattern 320 can be selectively removed relative to the lower bridging patterns 111 and 112 and the upper bridging patterns 211 and 212. Next, a gate dielectric film 120, a first gate electrode 130, and a second gate electrode 230 can be formed, replacing the areas where the dummy gate electrode 330, the first sacrificial pattern 310, and the second sacrificial pattern 320 were removed. Next, a gate capping film 145 can be formed covering the upper surface of the second gate electrode 230. Accordingly, multiple initial gate structures PG1, PG2 and PG3 can be provided, including gate dielectric film 120, first gate electrode 130, second gate electrode 230, gate spacer 140 and gate capping film 145.

[0149] Reference Figure 23 and Figure 24 It can form a cutting pattern of 150.

[0150] The cutting pattern 150 can be spaced apart from the active patterns A11 and A12 above and below in the third direction Y, and from the active patterns A21 and A22 above. The cutting pattern 150 can extend along the second direction X and cut... Figure 21 and Figure 22 The initial gate structures are PG1, PG2, and PG3. Correspondingly, gate structures G11, G12, G21, G22, G31, and G32 can be provided.

[0151] In some embodiments, the dicing pattern 150 may include sequentially stacked pad insulating film 152 and sacrificial dicing film 153. The pad insulating film 152 may be located between each of the gate structures G11, G12, G21, G22, G31 and G32 and the sacrificial dicing film 153.

[0152] Reference Figure 25 The sacrificial cutting membrane 153 can be patterned.

[0153] For example, a patterned sacrificial dicing film 153 can be formed using a via mask pattern MP1 formed on the sacrificial dicing film 153. In some embodiments, the patterned sacrificial dicing film 153 may overlap with a first gate structure G11, a first lower epitaxial pattern 1601, a second lower epitaxial pattern 1602, a first upper epitaxial pattern 2601, and a second upper epitaxial pattern 2602 in a third-direction Y. Next, a filling insulating film 154 may be formed to replace the area where the sacrificial dicing film 153 is removed.

[0154] Reference Figure 26 and Figure 27 It can form a through-hole structure of 180°.

[0155] For example, the patterned sacrificial cleaving film 153 can be selectively removed relative to the filling insulating film 154. Next, a via structure 180 can be formed to replace the area where the sacrificial cleaving film 153 has been removed. Accordingly, a via structure 180 can be provided in the third direction Y that overlaps with the first gate structure G11, the first lower epitaxial pattern 1601, the second lower epitaxial pattern 1602, the first upper epitaxial pattern 2601, and the second upper epitaxial pattern 2602.

[0156] Reference Figure 28 and Figure 29 A recessed process can be performed on a portion of the via structure 180.

[0157] As the recess process is performed, a first via recess 180r1 extending downward from the upper surface of the via structure 180 can be formed. In some embodiments, the first via recess 180r1 may overlap with the second upper epitaxial pattern 2602 in the third direction Y. In some embodiments, the first via recess 180r1 may overlap with the second gate electrode 230 of the first gate structure G11 in the third direction Y. Accordingly, a via structure 180 including a first pillar portion 184 can be provided.

[0158] Reference Figure 30 A first recess filling film 154b can be formed to fill at least a portion of the first through-hole recess 180r1. Accordingly, a filling insulating film 154 including the first recess filling film 154b can be provided.

[0159] Reference Figures 31 to 33 This can form the first connection pattern FCA1 and / or the front source / drain contact FCA.

[0160] The first connecting pattern FCA1 can extend along a third direction Y and connect the first upper extension pattern 2601 to the first column portion 184 (electrically).

[0161] The front source / drain contact FCA penetrates (extends into) the second interlayer insulating film 290 and the second etch stop layer 265, and can be (electrically) connected to the upper source / drain patterns 260A and 260B. In some embodiments, the front source / drain contact FCA may include a first connection pattern FCA1.

[0162] Reference Figure 34 This can form a front wiring structure (FS).

[0163] The front wiring structure FS can be electrically connected to the upper source / drain patterns 260A and 260B and / or the second gate electrode 230.

[0164] Reference Figure 35 The front wiring structure FS can be attached to the carrier substrate 400.

[0165] For example, the carrier substrate 400 can be attached to Figure 34 The resulting product. After attaching the carrier substrate 400, it can be... Figure 34 The result is a reversed product.

[0166] Reference Figure 36 This can form substrate 102.

[0167] For example, the base substrate 100 and the fin pattern 110 can be removed. Next, a substrate 102 can be formed in the area where the base substrate 100 and the fin pattern 110 have been removed. In some embodiments, the base substrate 100 and the fin pattern 110 can be selectively removed relative to the retained pattern 360.

[0168] Reference Figures 37 to 39 This forms the source / drain contact section BCA.

[0169] The back source / drain contact BCA penetrates (extends into) the substrate 102 and can be (electrically) connected to the lower source / drain patterns 160A and 160B.

[0170] Reference Figure 40 and Figure 41 A recessed process can be performed on a portion of the via structure 180.

[0171] As the recess process is performed, a second via recess 180r2 extending downward from the upper surface of the via structure 180 can be formed. In some embodiments, the second via recess 180r2 may overlap with the first lower epitaxial pattern 1601 in the third direction Y. In some embodiments, the second via recess 180r2 may overlap with the first gate electrode 130 of the first gate structure G11 in the third direction Y. Accordingly, a via structure 180 including a second pillar 186 can be provided.

[0172] Reference Figure 42 A second recess filling film 154c can be formed to fill at least a portion of the second through-hole recess 180r2. Accordingly, a filling insulating film 154 including the second recess filling film 154c can be provided.

[0173] Reference Figures 43 to 45 This can form a second connection pattern BCM1 and / or a rear connection contact BCM.

[0174] The second connecting pattern BCM1 can extend along the third direction Y and connect the second lower extension pattern 1602 to the second column portion 186 (electrically).

[0175] The rear connection contact BCM penetrates (extends into) the third interlayer insulating film 109 and can be (electrically) connected to the rear source / drain contact BCA. In some embodiments, the rear connection contact BCM may include a second connection pattern BCM1.

[0176] Next, refer to Figures 1 to 3 This can form a back wiring structure (BS).

[0177] The rear wiring structure BS can be electrically connected to the lower source / drain patterns 160A and 160B and / or the first gate electrode 130. Accordingly, the above can be configured for use... Figures 1 to 6 Explanation of semiconductor devices.

[0178] Although the inventive concept has been specifically shown and described in conjunction with exemplary embodiments thereof, those skilled in the art will understand that various modifications in form and detail may be made therein without departing from the scope of the inventive concept as defined by the appended claims. Therefore, it is intended that these embodiments be considered illustrative rather than restrictive in all respects, and that the scope of the invention be indicated by reference to the appended claims rather than the foregoing description.

Claims

1. A semiconductor device, comprising: Substrate; An active pattern is present on the substrate and extends along a first direction. The lower active pattern is located between the upper surface of the substrate and the upper active pattern in a second direction that intersects the first direction and the upper surface of the substrate, wherein the lower active pattern extends along the first direction; A gate structure extends along a third direction intersecting the first direction and the second direction on the lower active pattern and the upper active pattern; A first lower epitaxial pattern is located on a first side of the gate structure, wherein the first lower epitaxial pattern is connected to the lower active pattern; A first upper epitaxial pattern is located on the second side of the gate structure, wherein the first upper epitaxial pattern is connected to the upper active pattern; A diced pattern, spaced apart from the lower active pattern and the upper active pattern in the third direction, adjacent to the gate structure, and extending along the first direction; and The via structure, in the cutting pattern, connects the first lower epitaxial pattern and the first upper epitaxial pattern. The via structure includes: a first pillar portion that overlaps with the first upper extension pattern in the third direction; a second pillar portion that overlaps with the first lower extension pattern in the third direction; and a connecting portion that extends along the first direction and connects the first pillar portion and the second pillar portion.

2. The semiconductor device according to claim 1, in, The first column, the second column, and the connecting part are integrally connected to each other.

3. The semiconductor device according to claim 1, further comprising: An intermediate insulating pattern is located between the lower active pattern and the upper active pattern. The connecting portion overlaps with the gate structure and the intermediate insulating pattern in the third direction.

4. The semiconductor device according to claim 1, further comprising: A second upper epitaxial pattern is connected to the upper active pattern on the first side of the gate structure. Wherein, the first column portion does not overlap with the second upper extension pattern in the third direction.

5. The semiconductor device according to claim 1, further comprising: The second lower epitaxial pattern is connected to the lower active pattern on the second side of the gate structure. Wherein, the second column portion does not overlap with the second lower extension pattern in the third direction.

6. The semiconductor device according to claim 1, further comprising: The first connecting pattern is on the upper surface of the first upper extensional pattern. The first connecting pattern extends along the third direction and connects the first upper extension pattern to the first column portion.

7. The semiconductor device according to claim 1, further comprising: The second connecting pattern is on the lower surface of the first lower extensional pattern. The second connecting pattern extends along the third direction and connects the first lower extension pattern to the second column portion.

8. The semiconductor device according to claim 1, in, The first lower epitaxial pattern includes impurities of a first conductivity type, and The first epitaxial pattern includes impurities of a second conductivity type that are different from the first conductivity type.

9. The semiconductor device according to claim 1, in, The cutting pattern includes a pad insulating film and a fill insulating film sequentially stacked on the side surface of the gate structure, and The insulating film is located between the via structure and the gate structure.

10. A semiconductor device, comprising: Substrate; An active pattern is present on the substrate and extends along a first direction. The lower active pattern is located between the upper surface of the substrate and the upper active pattern in a second direction that intersects the first direction and the upper surface of the substrate, wherein the lower active pattern extends along the first direction; A gate structure extends along a third direction intersecting the first direction and the second direction on the lower active pattern and the upper active pattern; A first lower epitaxial pattern is located on a first side of the gate structure, wherein the first lower epitaxial pattern is connected to the lower active pattern; A second lower epitaxial pattern is provided on a second side of the gate structure, wherein the second lower epitaxial pattern is connected to the lower active pattern; A first upper epitaxial pattern is located on the first side of the gate structure, wherein the first upper epitaxial pattern is connected to the upper active pattern; A second upper epitaxial pattern is located on the second side of the gate structure, wherein the second upper epitaxial pattern is connected to the upper active pattern; A diced pattern, spaced apart from the lower active pattern and the upper active pattern in the third direction, adjacent to the gate structure, and extending along the first direction; and The via structure, in the cut pattern, connects the second lower epitaxial pattern and the first upper epitaxial pattern. The via structure includes: a first via recess extending from the upper surface of the via structure and overlapping with the second upper epitaxial pattern in the third direction; and a second via recess extending from the lower surface of the via structure and overlapping with the first lower epitaxial pattern in the third direction.

11. The semiconductor device according to claim 10, in, The first through-hole recess includes a curved surface that connects the lower surface of the first through-hole recess to the side surface of the first through-hole recess.

12. The semiconductor device according to claim 10, in, The second via recess includes a curved surface that connects the upper surface of the second via recess to the side surface of the second via recess.

13. The semiconductor device according to claim 10, in, The first distance between the lower surface of the first via recess and the upper surface of the substrate is equal to or less than the second distance between the lower surface of the second upper epitaxial pattern and the upper surface of the substrate.

14. The semiconductor device according to claim 10, in, The first distance between the upper surface of the second via recess and the upper surface of the substrate is equal to or greater than the second distance between the upper surface of the first lower epitaxial pattern and the upper surface of the substrate.

15. The semiconductor device according to claim 10, in, The cutting pattern includes a pad insulating film and a fill insulating film sequentially stacked on the side surface of the gate structure. The insulating film is located between the via structure and the gate structure, and The insulating filling film is located in the first through-hole recess and the second through-hole recess.

16. A semiconductor device, comprising: The substrate includes a first surface and a second surface opposite to the first surface in a first direction; A lower active pattern and an upper active pattern are stacked sequentially along the first direction, and each of the lower active pattern and the upper active pattern extends along a second direction intersecting the first direction; An intermediate insulating pattern is located between the lower active pattern and the upper active pattern; A gate structure extends along a third direction intersecting the first direction and the second direction, wherein each of the lower active pattern and the upper active pattern penetrates the gate structure; A first lower epitaxial pattern is located on a first side of the gate structure, wherein the first lower epitaxial pattern is connected to the lower active pattern; A second lower epitaxial pattern is provided on a second side of the gate structure, wherein the second lower epitaxial pattern is connected to the lower active pattern; A first upper epitaxial pattern is located on the first side of the gate structure, wherein the first upper epitaxial pattern is connected to the upper active pattern; A second upper epitaxial pattern is located on the second side of the gate structure, wherein the second upper epitaxial pattern is connected to the upper active pattern; A diced pattern, spaced apart from the lower active pattern and the upper active pattern in the third direction, adjacent to the gate structure, and extending along the second direction; and A via structure in the dicing pattern, wherein the via structure includes: a connecting portion that overlaps with the intermediate insulating pattern and the gate structure in the third direction; a first pillar portion that overlaps with the first upper epitaxial pattern and does not overlap with the second upper epitaxial pattern in the third direction; and a second pillar portion that overlaps with the second lower epitaxial pattern and does not overlap with the first lower epitaxial pattern in the third direction. A first connecting pattern extends along the third direction on the upper surface of the first upper extension pattern and connects the first upper extension pattern to the first column portion; and The second connecting pattern extends along the third direction on the lower surface of the second lower extension pattern and connects the second lower extension pattern to the second column portion.

17. The semiconductor device according to claim 16, in, The first connecting pattern is in contact with the side surface of the first column.

18. The semiconductor device according to claim 16, in, The second connecting pattern contacts the lower surface of the second column.

19. The semiconductor device of claim 16, further comprising: The front wiring structure is electrically connected to the second upper epitaxial pattern on the first surface of the substrate.

20. The semiconductor device of claim 16, further comprising: The back wiring structure is electrically connected to the first lower epitaxial pattern on the second surface of the substrate.

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