Semiconductor component and forming method thereof

Abstract

A semiconductor device includes an image sensor device including a capacitor structure including an amorphous component as a dielectric material, the amorphous component including a metal oxide mixture. The amorphous component replaces a crystalline metal oxide dielectric layer stack used in other methods. The amorphous composition reduces or prevents interface defects and electron capture compared to a crystalline metal oxide dielectric layer stack. The single amorphous layer avoids interface between metal oxides and crystal defects of the metal oxides, in which electron capture is readily formed. The resulting image sensor components exhibit reduced latency compared to other methods using crystalline metal oxide dielectric layer stacks. Further, using a single amorphous layer comprising a metal oxide mixture increases the capacitance of the corresponding capacitive structure compared to other methods using a crystalline metal oxide dielectric layer stack.

Description

Technical Field

[0001] This invention relates to a semiconductor component and a method for forming the same. Background Technology

[0002] Complementary metal oxide semiconductor (CMOS) image sensors may include multiple pixel sensors arranged in a pixel sensor array. The pixel sensors of a CMOS image sensor may include photodiodes configured to convert photons of incident light into an electronic photocurrent. The magnitude of the photocurrent is at least partially based on the intensity of the incident light. Therefore, if the pixel sensors in the pixel sensor array are capable of sensing a wide range of incident light intensities, the images and / or videos produced by a CMOS image sensor can achieve a high range of brightness and contrast. Summary of the Invention

[0003] Some embodiments of the present invention provide a method for forming a semiconductor component. The method includes forming a trench in a dielectric layer. The method includes depositing a first electrode layer of a semiconductor layer stack in the trench. The method includes depositing an insulating layer of the semiconductor layer stack on the first electrode layer in the trench. The method includes depositing a second electrode layer of the semiconductor layer stack on the insulating layer in the trench, wherein the semiconductor layer stack extends along the sidewalls and bottom surface of the trench, and wherein the insulating layer is an amorphous layer comprising a combination of metal and oxygen.

[0004] Some embodiments of the present invention provide a method for forming a semiconductor component. The method includes depositing a first conductive layer within a trench formed in a dielectric layer, wherein the first conductive layer extends along the sidewalls and bottom surface of the trench. The method includes performing processing operations to transform a portion of the first conductive layer into a buffer layer. The method includes depositing an insulating layer on the buffer layer, wherein the insulating layer is an amorphous composition comprising a mixture of a first metallic material, a second metallic material, and oxygen. The method includes depositing a second conductive layer on the insulating layer.

[0005] Some embodiments of the present invention provide a semiconductor component. The semiconductor component includes a first electrode layer extending along the sidewalls and bottom surface of a trench. The semiconductor component includes a second electrode layer within the trench. The semiconductor component includes an insulating layer between the first and second electrode layers, wherein the insulating layer extends along the sidewalls and bottom surface of the trench, and wherein the insulating layer has an amorphous structure comprising a mixture of multiple high-k dielectric oxide materials. Attached Figure Description

[0006] The best understanding of various aspects of the invention can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various feature components are not drawn to scale. In fact, for clarity, the dimensions of the various feature components can be arbitrarily increased or decreased.

[0007] Figure 1A and Figure 1B This is an example circuit diagram of the pixel sensor described in this article.

[0008] Figure 2A and Figure 2B This is a diagram of the example semiconductor component described in this article.

[0009] Figures 3A to 3E This is an example diagram of the semiconductor component formation described in this article.

[0010] Figures 4A to 4Q This is an example diagram of the trench capacitor structure described in this article.

[0011] Figure 5A and Figure 5B This is an example diagram of the insulating layer of the capacitor structure described in this article.

[0012] Figure 6 Describe the elemental composition of the insulating layer of the capacitor structure described in this article.

[0013] Figure 7 This is a diagram of the example semiconductor component described in this article.

[0014] Figure 8 This is a diagram of the example semiconductor component described in this article.

[0015] Figure 9 This is a diagram of the example semiconductor component described in this article.

[0016] Figure 10 This is an example process flow diagram related to the formation of semiconductor components as described in this article.

[0017] Figure 11 This is an example process flow diagram related to the formation of semiconductor components as described in this article. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances of various features for implementing the provided protected objectives. Specific examples of components and configurations are described below to simplify the content of the invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the invention. This repetition is for the sake of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to facilitate the description of the relationship between one component or feature shown in the figure and another component or feature. These spatially relative terms are intended to also encompass orientations shown in the figure other than those of the component in use or operation. Components may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0020] In some cases, the number of incident photons a pixel sensor can absorb before reaching saturation may be limited. "Saturation" refers to a point beyond which a pixel sensor can no longer absorb additional photons. Pixel sensor saturation limits its dynamic range because it cannot obtain additional brightness and color information from further photon absorption.

[0021] The amount of photocurrent charge a pixel sensor can store before reaching saturation is called its full-well capacity (FWC). The FWC of a pixel sensor can be based at least in part on the size (e.g., depth, width, volume) and / or shape of its photodiode. While increasing the size of the photodiode can increase the FWC, doing so may sacrifice the pixel density in the pixel sensor array, potentially reducing the array's resolution.

[0022] To increase the full-well capacity of a pixel sensor, an image sensor assembly (e.g., a complementary metal-oxide-semiconductor (CMOS) image sensor assembly) may include a capacitor structure configured to store the charge associated with the photocurrent generated by the pixel sensor before the charge is transferred to a floating diffusion node associated with the pixel sensor. The photocurrent can be transferred from the pixel sensor to the capacitor structure, allowing the pixel sensor to generate more charge for the photocurrent instead of storing it entirely in the photodiode and / or floating diffusion node. Therefore, the capacitor structure increases the full-well capacity of the pixel sensor, potentially enabling a wider range of brightness and / or contrast in images and / or videos produced by the pixel sensor array. The capacitor structure is designed to achieve a small lateral footprint and may include a metal-insulator-metal (MIM) layer stack, where bottom and top electrode layers are arranged alternately and separated by insulating layers.

[0023] However, some high-density MIM capacitors may suffer from degraded imaging performance when their insulating layers contain stacks of crystalline material. For example, those made of zirconium oxide (ZrO2) x (e.g., ZrO2) and aluminum oxide (Al) x O y Crystalline insulating layer stacks composed of materials such as Al2O3 (e.g., ZrO2 / Al2O3 / ZrO2 (ZAZ) dielectric layer stacks) are prone to charge trapping, which can lead to discharge delays in MIM capacitors containing such crystalline insulating layer stacks. In ZrO2 / Al2O3 / ZrO2 (ZAZ) arrangements, the interface between the zirconium oxide and alumina layers, as well as crystal defects within the zirconium oxide layer, can contribute to current leakage paths and electron traps. More specifically, oxygen can migrate from the crystalline zirconium oxide within the zirconium oxide layer (particularly at the interface between the zirconium oxide and alumina layers), resulting in crystal defects known as oxygen vacancies. These oxygen vacancies can act as electron traps, trapping electrons in the MIM capacitor (e.g., from the electrode layers of the MIM capacitor), which increases the discharge time of the MIM capacitor and causes delays in the generation of images and / or videos.

[0024] In some embodiments described herein, the image sensor assembly (e.g., a CMOS image sensor assembly) includes a capacitor structure (e.g., a MIM capacitor) comprising an insulating layer with an amorphous composition comprising a mixture of zirconium, aluminum, and oxygen. Compared to crystalline insulating layer stacks (such as a zirconium dioxide / aluminum oxide / zirconium dioxide (ZrO2 / Al2O3 / ZrO2) (ZAZ) dielectric layer stack), the amorphous composition reduces or prevents interface defects and electron trapping. In particular, the amorphous composition of the insulating layer avoids interfaces between different zirconium dioxide and aluminum oxide layers, which reduces and / or prevents the formation of crystal defects (such as oxygen vacancies) in the insulating layer. Because charge trapping in the capacitor structure is reduced, minimized, and / or prevented due to the reduction and / or prevention of crystal defects, the resulting image sensor assembly exhibits reduced latency when generating images and / or videos. For example, in some embodiments, the image sensor assembly may exhibit a latency reduction of more than 20% when generating images and / or videos compared to other capacitor structures including a ZAZ dielectric layer stack. Furthermore, the amorphous composition of the insulating layer may increase the capacitance of the capacitor structure compared to other capacitor structures that include a ZAZ dielectric layer stack. For example, in some embodiments, the capacitance of the capacitor structure can be increased by approximately 30% compared to other methods.

[0025] Figure 1A and Figure 1B This is an example circuit diagram of the pixel sensor 100 described herein. The pixel sensor 100 may include a front-side pixel sensor (e.g., a pixel sensor configured to receive photons from the front side of the sensor die), a rear-side pixel sensor (e.g., a pixel sensor configured to receive photons from the back side of the sensor die), and / or other types of pixel sensors.

[0026] like Figure 1A As shown in the example circuit, pixel sensor 100 includes a photodiode 102, which can be configured to sense and / or accumulate incident light (e.g., light directed toward pixel sensor 100) and convert photons of the incident light into a photocurrent. The magnitude of the photocurrent may be based on the number of photons collected in photodiode 102 (e.g., the intensity of the incident light). Therefore, the accumulation of photons in photodiode 102 produces an accumulation of charge, representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a larger intensity or brightness, while a smaller amount of charge may correspond to a lower intensity or brightness).

[0027] Photodiode 102 is electrically connected to transfer gate 104. Transfer gate 104 is configured to control the transfer of photocurrent from photodiode to floating diffusion node 106. Transfer gate 104 can be selectively switched by applying a transfer voltage (Vtx) to transfer gate 104. In some embodiments, the transfer voltage applied to transfer gate 104 causes a leakage path (e.g., a buried trench) to be formed across transfer gate 104 between photodiode 102 and floating diffusion node 106, allowing photocurrent to travel along the leakage path to floating diffusion node 106. In some embodiments, removing the transfer voltage from transfer gate 104 (or the absence of the transfer voltage) causes the leakage path to be removed, preventing photocurrent from traveling from photodiode 102 to floating diffusion node 106.

[0028] The circuitry of pixel sensor 100 may further include a reset gate 108. The reset gate 108 is electrically connected to a voltage source 110. The reset gate 108 may be controlled to selectively apply a reset voltage (Vrst) from the voltage source 110 to the floating diffusion node 106. The transfer gate 104 and the reset gate 108 may be electrically coupled to the floating diffusion node 106 such that the reset voltage is applied to the floating diffusion node 106 to “reset” the floating diffusion node 106 (e.g., by draining any residual charge in the floating diffusion node 106), which occurs before activating the transfer gate 104 to transfer photocurrent from the photodiode 102 to the floating diffusion node 106.

[0029] Pixel sensor 100 may be a lateral overflow integration capacitor (LOFIC) pixel sensor with an overflow gate 112 and an overflow capacitor 114. The overflow capacitor 114 can be electrically coupled to a floating diffusion node 106 via the overflow gate 112, allowing photocurrent to be transferred from the floating diffusion node 106 to the overflow capacitor 114 for temporary storage. The overflow gate 112 can selectively control the flow of photocurrent to and / or from the overflow capacitor 114. This allows additional photocurrent to be transferred from the photodiode 102 to the floating diffusion node 106 without causing pixel sensor 100 to saturate, thereby increasing the full-well capacity and dynamic range of pixel sensor 100.

[0030] The photocurrent can be used to apply a floating diffusion voltage (Vfd) to the source follower gate 116 of the pixel sensor 100 circuitry. This allows the photocurrent to be observed without removing or discharging it from the floating diffusion node 106 and / or the overflow capacitor 114. A reset gate 108 can be used instead to remove or discharge the photocurrent from the floating diffusion node 106 and / or the overflow capacitor 114.

[0031] In order to apply the floating diffusion voltage to the source follower gate 116, the transfer gate 104 can be turned off (e.g., to prevent photocurrent from flowing back to the photodiode 102) and the overflow gate 112 can be turned on. This configuration allows the photocurrent stored in the floating diffusion node 106 and the overflow capacitor 114 to be used to apply the floating diffusion voltage to the source follower gate 116.

[0032] The source follower gate 116 acts as a high impedance amplifier for the pixel sensor 100. The source follower gate 116 provides voltage-to-current conversion for the floating diffuse voltage. The output of the source follower gate 116 is electrically connected to the row select gate 118, which is configured to control the flow of photocurrent to external circuitry. The row select gate 118 is controlled by selectively applying a selection voltage (Vdi) to its gate. This allows photocurrent to flow to the output of the pixel sensor 100.

[0033] like Figure 1B As shown in another example circuit, pixel sensor 100 may include multiple sub-circuits. These sub-circuits may include small pixel sub-circuits and large pixel sub-circuits. The small pixel sub-circuit may include a small photodiode 102a, a transmission gate 104a, a floating diffusion node 106a, an overflow gate 112a, and an overflow capacitor 114a. The large pixel sensor sub-circuit may include a large photodiode 102b, a transmission gate 104b, a floating diffusion node 106b, an overflow gate 112b, and an overflow capacitor 114b. Both the small and large pixel sub-circuits may be connected to a reset gate 108, a voltage source 110, a source follower gate 116, and a row select gate 118. The large photodiode 102b may be physically larger than the small photodiode 102a, thereby allowing pixel sensor 100 to have different photon sensitivities in different regions.

[0034] As shown above, with Figure 1A and Figure 1B For example. Other examples may be related to... Figure 1A and Figure 1B The descriptions are different.

[0035] Figure 2A and Figure 2BThe image is an icon for the example semiconductor component 200 described herein. Semiconductor component 200 may include a system-on-chip (SoC) component, logic components such as a central processing unit (CPU) or graphics processing unit (GPU), memory components (e.g., high-bandwidth memory (HBM) components), image sensor components (e.g., complementary metal-oxide-semiconductor (CMOS) image sensor components), and / or other types of semiconductor components. With respect to the image sensor component, semiconductor component 200 may include an example structural embodiment of the overflow capacitor 114 of the pixel sensor 100 described herein.

[0036] Figure 2A A cross-sectional view of semiconductor component 200 is depicted. (e.g.) Figure 2A As shown, the semiconductor component 200 may include a component layer 202 and an interconnect layer 204, wherein the interconnect layer 204 is arranged in the semiconductor component 200 along the z-direction relative to the component layer 202. For example, the interconnect layer 204 may be located above the component layer 202. In another example, the interconnect layer 204 may be located below the component layer 202.

[0037] Interconnect layer 204 may include conductive structures arranged to transmit signals and / or provide power distribution throughout the semiconductor component 200. In some embodiments, the semiconductor component 200 includes interconnect layers 204 located above and below component layer 202. A first interconnect layer 204 located on a first side of component layer 202 may be used for signal propagation throughout the semiconductor component 200, while a second interconnect layer 204 located on a opposite second side of component layer 202 may be used for power distribution within the semiconductor component 200.

[0038] Component layer 202 includes a substrate 206 of semiconductor component 200. Substrate 206 may correspond to a portion of the semiconductor wafer forming semiconductor component 200. Substrate 206 may include a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or other types of substrates. Substrate 206 may extend in semiconductor component 200 along the x-direction and / or y-direction such that the top and bottom surfaces of substrate 206 are substantially perpendicular to the z-direction in semiconductor component 200.

[0039] Integrated circuit component 208 may be contained within and / or on substrate 206 in component layer 202 of semiconductor component 200. Integrated circuit component 208 may include front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (FinFET) structures, front-end gate allaround (GAA) transistor structures), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuitry, and / or other types of front-end semiconductor components.

[0040] The front-end transistor structure may include multiple source / drain regions that may correspond to doped regions of substrate 206 and are separated by channel regions in substrate 206. In some embodiments, the source / drain regions are doped with a first type of dopant (e.g., p-type dopant such as boron (B) and / or gallium (Ga), n-type dopant such as phosphorus (P) and / or arsenic (As)), while the channel regions are doped with a second type of dopant different from the first type of dopant. The front-end transistor structure may include a gate structure located above and / or around the channel regions. The gate dielectric layer of the front-end transistor structure may be located between the gate structure and the channel regions. The gate structure may include a polysilicon gate and a high-dielectric gate dielectric layer (e.g., hafnium oxide (HfO)). x Metal gates such as HfO2, and / or other types of gate structures.

[0041] A dielectric layer 210 is disposed on the substrate 206. The dielectric layer 210 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric layer 210 includes a dielectric material that allows for selective etching or protects various portions of the substrate 206 and / or the integrated circuit assembly 208 from etching, and / or electrically isolates the integrated circuit assembly 208 within the assembly layer 202. The dielectric layer 210 includes silicon nitride (Si). x N y ), oxides (e.g., silicon dioxide (SiO2) xThe dielectric layer 210 may extend in the semiconductor assembly 200 along the x-direction and / or y-direction. Contacts 212 (e.g., source / drain contacts, gate contacts) may pass through the dielectric layer 210 and extend between the integrated circuit assembly 208 and the interconnect layer 204. The contacts may electrically connect the integrated circuit assembly 208 to the interconnect layer 204. Contacts 212 may include vias, plugs, and / or other types of elongated conductive structures. Contacts 212 may include conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au).

[0042] Interconnect layer 204 includes multiple dielectric layers (e.g., back-end dielectric layers) arranged in one direction (e.g., the z-direction) approximately perpendicular to the top surface of substrate 206. The dielectric layers may include interlayer dielectric layers 214 and etch stop layers 216, which are alternately arranged in the z-direction. Interlayer dielectric layers 214 and etch stop layers 216 may extend in the semiconductor assembly 200 along the x-direction and / or y-direction.

[0043] Interlayer dielectric layers 214 may each comprise a low-dielectric oxide material, such as silicon oxide (SiO2). xAlternatively, the interlayer dielectric layer 214 may comprise borosilicate glass (BSG), fluorine-containing silicate glass (FSG), tetraethylorthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 214 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of materials with extremely low dielectric properties include carbon-doped silicon oxide (C-SiOx), amorphous fluorinated carbon (a-CxFy), parylene, bis-benzocyclobutenes (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbide (SiOC) polymers, porous HSQ, porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silicon oxide (SiO). x )wait.

[0044] The etch stop layers 216 may each include silicon nitride (Si). x N y The interlayer dielectric layer 214 and the etch stop layer 216 comprise different dielectric materials to provide etch selectivity, thereby enabling the formation of various structures in the interconnect layer 204. For example, the interlayer dielectric layer 214 may each comprise a low dielectric material, such as borosilicate glass (USG), while the etch stop layer 216 may each comprise a high dielectric material, such as silicon nitride (SiO2). x N y Alternatively, the two or more etch stop layers 216 may comprise different materials. For example, one or more first etch stop layers 216 may comprise silicon nitride (SiC). x N yOne or more second etch stop layers 216 may include silicon carbide (SiC).

[0045] Interconnect layer 204 includes multiple conductive structures arranged across multiple layers. These conductive structures may be electrically coupled and / or physically coupled to one or more integrated circuit components 208 in component layer 202. The conductive structures provide electrical wiring, enabling signals and / or power to be supplied to and / or transmitted from integrated circuit components 208.

[0046] The conductive structure may include multiple layers 218a to 218e arranged in a vertical direction and alternating with multiple layers 220a to 220d in the z-direction (e.g., vertically alternating). Each of layers 218a to 218e includes a metallization structure 222, while each of layers 220a to 220d includes an interconnection structure 224.

[0047] Layers 218a to 218e of the metallization structure 222 may be referred to as M layers. For example, layer 218a of the metallization structure 222 (referred to as the metal-0 (M0) layer) may be located at the bottom of the interconnect layer 204 and may be coupled to the component layer 202. In particular, the metallization structure 222 in the M0 layer may be coupled to the contact 212 (e.g., a contact layer referred to as the "CO" layer) of the integrated circuit component 208 in the component layer 202. Layer 218b of the metallization structure 222 (referred to as the metal-1 (M1) layer) may be located above layer 218a of the metallization structure 222 in the interconnect layer 204, layer 218c of the metallization structure 222 (referred to as the metal-2 (M2) layer) may be located above layer 218b of the metallization structure 222, and so on.

[0048] Layer 220a of interconnect structure 224 (referred to as via-1 (V0) layer) may be included between M0 layer and M1 layer to interconnect M0 layer and M1 layer, layer 220b of interconnect structure 224 (referred to as via-2 (V1) layer) may be included between M1 layer and M2 layer to interconnect M1 layer and M2 layer, and so on.

[0049] Metallization structure 222 may include trenches, metallization layers, conductive traces, and / or combinations of other types of conductive structures. Interconnect structure 224 may include vias, interconnects, and / or combinations of other types of conductive structures. Metallization structure 222 and interconnect structure 224 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as examples of other conductive materials. In some embodiments, one or more pad layers are contained between the dielectric layer of interconnect layer 204 and metallization structure 222, and / or between the dielectric layer of interconnect layer 204 and interconnect structure 224. One or more pad layers may include barrier pads, adhesive pads, and / or other types of pads. Example materials for one or more pads include tantalum nitride (TaN) and / or titanium nitride (TiN), as well as other examples.

[0050] In some embodiments, the top layer of the conductive structure (e.g., the top layer of the metallization structure 222, the top layer of the interconnect structure 224) may be coupled to a connection structure on top of the semiconductor component 200. The connection structure may include solder balls, solder bumps, contact pads (e.g., land grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), under-bump metallization (UBM) connections, microbumps, ball grid array (BGA) balls, control collapse chip connection (C4) bumps, and / or other types of connection structures. In some embodiments, the top layer of the conductive structure (e.g., the top layer of the metallization structure 222, the top layer of the interconnect structure 224) may be coupled to bonding structures, such as bonding pads and / or bonding vias.

[0051] like Figure 2A As further shown, the trench capacitor structure 226 is included in the interconnect layer 204 of the semiconductor component 200. The trench capacitor structure 226 is an example structural embodiment of the overflow capacitor 114 of the pixel sensor 100.

[0052] Generally, a capacitor structure may include a metal-in-metal (MIM) structure, in which an insulating layer is sandwiched between two conductive electrode layers. The capacitance of a capacitor structure (e.g., the amount of charge it can store) depends directly on the geometry of the conductive electrode layers. The larger the area of ​​the conductive electrode layers, the larger the capacitance of the capacitor structure. Therefore, increasing the size of the metal electrode layers can increase the capacitance of the capacitor structure.

[0053] Increasing the lateral dimensions of the capacitor structure directly contradicts the semiconductor industry's design principle of minimizing semiconductor component size. The goal of minimizing semiconductor component size is to reduce power consumption, improve operational performance and efficiency, and / or enable semiconductor components for increasingly smaller form factor applications. Therefore, in some cases, the size of the capacitor structure can be increased vertically within the semiconductor component, allowing the capacitor structure to extend through multiple layers. Deep trench capacitors (DTCs) are a type of capacitor structure formed in trenches within a semiconductor component, with the electrode and insulating layers extending along and conforming to the trench's contour. This allows for an increase in the area of ​​the conductive electrode layer (thus increasing capacitance) while minimizing the increase in the lateral dimensions of the capacitor structure. The trenches in a deep trench capacitor structure are typically formed with a high aspect ratio between the trench depth and trench width.

[0054] Reference Figure 2A The trench capacitor structure 226 may include a deep trench capacitor structure extending through and / or contained in one or more dielectric layers in the interconnect layer 204, such as one or more interlayer dielectric layers 214 and / or one or more etch stop layers 216. In some embodiments, the trench capacitor structure 226 is configured to store charge (e.g., photocurrent) from an integrated circuit component 208 (e.g., a pixel sensor) in the semiconductor component 200. In some embodiments, the integrated circuit component 208 is electrically coupled to the trench capacitor structure 226 to form a memory cell (e.g., a dynamic random access memory (DRAM) cell or another type of capacitor-based memory cell) in the semiconductor component 200. In some embodiments, the trench capacitor structure 226 is configured to provide charge decoupling for one or more integrated circuit components 208. In some embodiments, the trench capacitor structure 226 is configured to perform another function in the semiconductor component 200.

[0055] The trench capacitor structure 226 may be electrically coupled and / or physically coupled to the bottom contact 228 and to the top contact 230. Alternatively, the trench capacitor structure 226 may be electrically coupled and / or physically coupled to multiple top contacts. The bottom contact 228 and the top contact 230 may each include one or more conductive structures in the interconnect layer 204, such as one or more metallized structures 222 and / or one or more interconnect structures 224, etc.

[0056] Figure 2B This describes a detailed cross-sectional view of trench capacitor structure 226. (See attached image.) Figure 2BAs shown, the trench capacitor structure 226 includes one or more trenches 232 on a bottom contact 228. The bottom contact 228 may be contained in an interlayer dielectric layer 214a in the interconnect layer 204 of the semiconductor component 200. The trenches 232 of the trench capacitor structure 226 may extend through one or more dielectric layers in the interconnect layer 204 of the semiconductor component 200, including through etch stop layers 216a, 214a, 216b, 214c, and / or 214d. In some embodiments, the trenches 232 may have a high aspect ratio, i.e., the ratio of the depth (or height) of the trenches 232 to the lateral width (or critical dimension) of the trenches 232. Therefore, the trench capacitor structure 226 may be referred to as a deep trench capacitor structure. In some embodiments, the aspect ratio of the trenches 232 may be approximately 10:1 or greater. In some embodiments, trench 232 may have an aspect ratio ranging from about 20:1 to about 50:1. However, other values ​​and ranges are also within the scope of this invention.

[0057] like Figure 2B As further shown, the trench capacitor structure 226 includes multiple conformal layers that conform to the contour of the trench 232. The conformal layers may include an adhesive layer 234, a bottom electrode layer 236 on the adhesive layer 234, a buffer layer 238 on the bottom electrode layer 236, and an insulating layer 240 on the buffer layer 238. The adhesive layer 234, bottom electrode layer 236, buffer layer 238, and insulating layer 240 may each conform to the contour of the trench 232 such that they conform to the sidewalls and bottom surface of the trench 232. The trench capacitor structure 226 also includes a top electrode layer 242 on the insulating layer 240. In some embodiments, the top electrode layer 242 is a filler layer that fills the remaining area of ​​the trench 232. Alternatively, the top electrode layer 242 may be conformal to the sidewalls and bottom surface of the trench 232, and may further include a dielectric plug layer or a fill layer in the remaining area of ​​the trench 232.

[0058] The adhesive layer 234, also referred to as a glue layer, can be used to promote adhesion between the bottom electrode layer 236 and the dielectric layers (e.g., interlayer dielectric layers 214b, 214c, and 214d, etch stop layers 216a, 216b, and 216c) and / or the bottom contact 228. The adhesive layer 234 can also serve as a barrier layer to prevent conductive material (e.g., copper (Cu)) from the bottom contact 228 from migrating upwards into the bottom electrode layer 236. The adhesive layer 234 may include tantalum (Ta), tantalum nitride (TaN), and / or other suitable adhesive materials.

[0059] The bottom electrode layer 236, insulating layer 240, and top electrode layer 242 correspond to the metal-insulator-metal (MIM) structure of the trench capacitor structure 226. Therefore, the trench capacitor structure 226 can also be referred to as a MIM capacitor structure. The bottom electrode layer 236 (also called capacitor bottom metal (CBM)) and the top electrode layer 242 (also called capacitor top metal (CTM)) may each include one or more conductive metals, one or more conductive metal-containing materials, one or more conductive ceramic materials, and / or other types of conductive materials. For example, these include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), and / or tantalum nitride (TaN). In some embodiments, the bottom electrode layer 236 and the top electrode layer 242 include the same material or the same material composition. In some embodiments, the bottom electrode layer 236 and the top electrode layer 242 include different materials or different material compositions.

[0060] The buffer layer 238 may include one or more materials. For example, the buffer layer 238 may include a material that promotes or facilitates lattice matching between the bottom electrode layer 236 and the buffer layer 238, and / or may include a material that promotes or facilitates lattice matching between the insulating layer 240 and the buffer layer 238.

[0061] The bottom electrode layer 236 contains nitrogen-containing materials or nitride-containing materials (such as titanium nitride (Ti)). x In embodiments containing N, such as Ti₂N), the material of the buffer layer 238 may also include nitrogen-containing materials or nitride-containing materials, such as titanium nitride (TiN) and / or titanium oxynitride (TiO₂). x N y This facilitates or helps achieve lattice matching through chemical bonding between the bottom electrode layer 236 and the buffer layer 238.

[0062] In embodiments where the insulating layer 240 comprises an oxygen-containing material or an oxide-containing material (such as alumina or zirconium oxide), the material of the buffer layer 238 may also comprise an oxygen-containing material or an oxide-containing material, such as titanium oxide (TiO2). x (e.g., TiO2), which can promote or contribute to lattice matching between buffer layer 238 and insulating layer 240.

[0063] Surface treatment chemicals can be used to perform a surface treatment operation on the bottom electrode layer 236. The surface treatment chemicals may include nitrous oxide (N₂O) and / or other types of surface treatment chemicals that react with the material of the bottom electrode layer 236. The surface treatment operation forms a buffer layer 238 in and / or on the bottom electrode layer 236. In particular, nitrous oxide (N₂O) in the surface treatment chemicals may react with materials in the bottom electrode layer 236, such as titanium nitride (e.g., Ti). x N, such as Ti₂N), reacts to form a mixture containing titanium oxide (such as TiO₂). x A buffer layer 238, such as TiO2 and titanium nitride (TiN). The reaction between the material of the bottom electrode layer 236 and nitrous oxide (N2O) in the surface treatment chemicals may include:

[0064] The bottom electrode layer 236 contains titanium nitride (such as Ti). x N, such as Ti₂N, reacts with nitrous oxide (N₂O) in surface treatment chemicals to form titanium oxide (such as TiO₂) in buffer layer 238. x Examples of titanium dioxide (TiO2) and titanium nitride (TiN) are titanium oxides. Additional reactions of nitrous oxide (N2O) with titanium oxide can also form titanium oxynitride (TiO2). x N y It is a component of buffer layer 238.

[0065] The insulating layer 240 comprises an amorphous mixture or composition of various materials and is an electrically insulating layer overall. As used herein, the term "amorphous" refers to a mixture or composition of molecules and atoms in a variable arrangement. In other words, the molecules and atoms of an amorphous structure are in an amorphous disordered arrangement. Although short-range ordered molecules and atoms may exist in the amorphous composition, the entire amorphous composition lacks a regular arrangement of its elements. In some embodiments, the amorphous composition is a disordered structure comprising oxygen and one or more metals (e.g., aluminum and / or zirconium). In some portions of the amorphous composition, the metal may be bonded to oxygen in the form of metal oxides (e.g., highly dielectric metal oxides). For example, the amorphous composition may comprise an amorphous component containing two or more highly dielectric oxide materials, such as zirconium oxide (ZrO2). x For example, ZrO2) and aluminum oxide (Al) x O y For example, Al2O3).

[0066] In some embodiments, the insulating layer 240 comprises an amorphous composition of zirconium, aluminum, and oxygen (ZrAlO). In the amorphous composition of zirconium, aluminum, and oxygen, molecules with Zr-O bonds, Al-O bonds, Zr-O-Al bonds, and / or Zr-Al bonds may be present, forming an amorphous thin film. For example, the insulating layer 240 may be an amorphous thin film comprising two or more highly dielectric oxides, such as zirconium oxide (ZrO). x For example, ZrO2) and aluminum oxide (Al) x O y For example, amorphous components such as Al2O3.

[0067] In some embodiments, the trench capacitor structure 226 includes a plurality of trenches 232, and the MIM structure of the trench capacitor structure 226 (e.g., bottom electrode layer 236, insulating layer 240, and top electrode layer 242) may extend along the sidewalls and bottom surface of the plurality of trenches 232 and extend between the plurality of trenches 232. The trenches 232 may be laterally arranged in the x-direction and spaced at a certain distance (in Figure 2B The trenches are spaced apart (indicated by dimension D1). In this way, the trench capacitor structure 226 includes a plurality of trenches 232, which extends the length (and therefore the area) of the MIM structure (e.g., bottom electrode layer 236, insulating layer 240 and top electrode layer 242) of the trench capacitor structure 226, thereby increasing the capacitance of the trench capacitor structure 226.

[0068] like Figure 2B As further shown, the trench capacitor structure 226 may include one or more capping layers located above the trench 232 and above the MIM structure of the trench capacitor structure 226. The one or more capping layers may include an oxide capping layer 244, an oxide nitride capping layer 246, and / or a nitride capping layer 248, etc. The capping layers may provide electrical isolation for the MIM structure of the trench capacitor structure 226, and / or may also serve as a hard mask layer stack forming the top contact 230. The oxide capping layer 244 may contain an oxide-containing dielectric material, such as silicon oxide (SiO2). x For example, SiO2). The oxynitride capping layer 246 may contain an oxynitride-containing dielectric material, such as silicon oxynitride (SiON). The nitride capping layer 248 may contain a nitride-containing dielectric material, such as silicon nitride (SiO2). x N y For example, Si3N4, etc.

[0069] like Figure 2BAs further shown, the trench capacitor structure 226 may include one or more sidewall spacers 250 and / or 252 located on the sidewalls of the capping layers 244-248 and / or on the sidewalls of the top electrode layer 242 above the trench 232. The combination of the capping layers 244-248 and the sidewall spacers 250 and 252 can be used as a self-aligned mask when etching the adhesive layer 234, the bottom electrode layer 236, the buffer layer 238, the insulating layer 240, and / or the top electrode layer 242 to define the MIM structure of the trench capacitor structure 226. The sidewall spacers 250 may contain an oxide-containing dielectric material, such as silicon oxide (SiO2). x For example, SiO2). The sidewall spacer 252 may contain a nitride-containing dielectric material, such as silicon nitride (SiO2). x N y For example, Si3N4, etc.

[0070] As mentioned above, providing Figure 2A and 2B As an example. Other examples may differ. Figure 2A and 2B The example shown.

[0071] Figures 3A to 3E This is an illustration of embodiment 300 forming the semiconductor component 200 described herein. In some embodiments, one or more semiconductor process tools may be used to perform [processing / deployment]. Figures 3A to 3E One or more related semiconductor process operations, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0072] Go to Figure 3A A substrate 206 is provided. The substrate 206 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and / or other types of semiconductor wafers. The semiconductor component 200 may be formed on the semiconductor wafer together with other semiconductor components.

[0073] like Figure 3BAs shown, integrated circuit component 208 may be formed in component layer 202 and / or on substrate 206 of semiconductor component 200. One or more portions of integrated circuit component 208 may be formed using one or more semiconductor process tools. For example, ion implantation tools may be used to dope one or more regions in substrate 206 with one or more types of dopant to form wells, implantation regions, and / or other types of doped regions of integrated circuit component 208 in substrate 206. Alternatively, deposition tools may be used to perform various deposition operations to deposit layers and / or structures of integrated circuit component 208, and / or deposit photoresist layers to etch substrate 206 and / or portions of the deposited layers. Alternatively, exposure tools may be used to expose photoresist layers to form patterns in the photoresist layers. Alternatively, development tools may be used to develop patterns in the photoresist layers. Alternatively, etching tools may be used to etch substrate 206 and / or portions of the deposited layers to form integrated circuit component 208. Alternatively, planarization tools may be used to planarize portions of integrated circuit component 208. Alternatively, electroplating tools may be used to deposit metal structures and / or layers of integrated circuit component 208.

[0074] like Figure 3B As further shown, a dielectric layer 210 is deposited on and / or above the substrate 206 and on and / or above the integrated circuit assembly 208 using a deposition tool. The dielectric layer 210 can be deposited using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. In some embodiments, a planarization operation, such as chemical mechanical planarization (CMP), can be performed using a planarization tool to planarize the dielectric layer 210 after deposition.

[0075] like Figure 3BAs further shown, contacts 212 of the integrated circuit component 208 can be formed through a dielectric layer 210. Contacts 212 can be formed in grooves within the dielectric layer 210. In some embodiments, the dielectric layer 210 is etched using a pattern in a photoresist layer to form grooves. In these embodiments, a photoresist layer can be formed on the dielectric layer 210 using a deposition tool. The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A portion of the photoresist layer can be developed and removed using a development tool to expose the pattern. The dielectric layer can be etched based on the pattern using an etching tool to form grooves. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, the remaining portion of the photoresist layer can be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to etch the dielectric layer 210 based on the pattern to form grooves.

[0076] Contact 212 may be formed in a recess. In some embodiments, contact 212 (e.g., a gate contact) is formed on the gate structure of integrated circuit assembly 208. In some embodiments, contact 212 (e.g., a source / drain contact) is formed on the source / drain region of integrated circuit assembly 208. Material of contact 212 may be deposited in the recess using deposition tools via chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques. Material of contact 212 may be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then material of contact 212 is deposited on the seed layer. In some embodiments, a planarization operation (e.g., a chemical mechanical planarization operation) is performed using a planarization tool to planarize contact 212 after deposition, such that the top of contact 212 is substantially coplanar with the top of dielectric layer 210.

[0077] like Figure 3CAs shown, a first portion of the interconnect layer 204 of the semiconductor component 200 is formed on the dielectric layer 210. Alternating interlayer dielectric layers 214 and etch stop layers 216 are deposited in the first portion of the interconnect layer 204 of the semiconductor component 200 using one or more deposition tools. In this manner, the interlayer dielectric layers 214 and etch stop layers 216 can be arranged along the z-direction in the semiconductor component 200. Each interlayer dielectric layer 214 and each etch stop layer 216 can be deposited using one or more deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, the interlayer dielectric layers 214 and / or etch stop layers 216 can be planarized using a planarization tool after deposition.

[0078] like Figure 3C As further shown, various operations can be performed using deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor process tools to form a metallization structure 222 and an interconnect structure 224 in a first portion of the interconnect layer 204 of the semiconductor component 200. The bottom contact 228 of the trench capacitor structure 226 can also be formed in the first portion of the interconnect layer 204.

[0079] In some embodiments, a first portion of interconnect layer 204 may be formed in multiple layers. For example, an interlayer dielectric layer 214 and an etch stop layer 216 may be formed (e.g., using one or more deposition tools and / or one or more planarization tools), grooves may be formed in and / or through the interlayer dielectric layer 214 and the etch stop layer 216 (e.g., using an exposure tool, a development tool, and / or an etching tool), and a layer 218a (e.g., an M0 layer) of metallization structure 222 may be formed in the interlayer dielectric layer 214 and the etch stop layer 216 (e.g., using one or more deposition tools and / or one or more planarization tools). Another interlayer dielectric layer 214 and another etch stop layer 216 may be formed, and a layer 220a (e.g., a V0 layer) of interconnect structure 224 may be formed in the interlayer dielectric layer 214 and the etch stop layer 216. Layers 218b, 218c, 220b, and 220c may be formed in a similar manner.

[0080] The metallized structure 222, interconnect structure 224, and / or bottom contact 228 can be deposited using one or more deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. In some embodiments, the metallized structure 222, interconnect structure 224, and / or bottom contact 228 can be planarized using a planarization tool after deposition.

[0081] like Figure 3D As shown, a trench capacitor structure 226 can be formed in one or more dielectric layers in interconnect layer 204. The trench capacitor structure 226 can be formed such that the trenches 232 of the trench capacitor structure 226 fall on the bottom contacts 228 in interconnect layer 204. An example process for forming the trench capacitor structure 226 is described in... Figures 4A-4Q The explanation and description are as follows.

[0082] like Figure 3E As shown, a second portion of the interconnect layer 204 of the semiconductor component 200 is formed over the first portion of the interconnect layer 204, including over the trench capacitor structure 226. The second portion of the interconnect layer 204 can be similar to... Figure 3C The first portion of the interconnect layer 204 is formed in the manner described. The top contact 230 of the trench capacitor structure 226 may be formed in the second portion of the interconnect layer 204.

[0083] As mentioned above, Figures 3A to 3E This is provided as an example. Other examples may be provided. Figures 3A to 3E The descriptions are different.

[0084] Figures 4A to 4Q This is a diagram of embodiment 400 of the formation of trench capacitor structure 226 described herein. In some embodiments, one or more semiconductor process tools can be used to perform the process... Figures 4A to 4Q The related description includes one or more semiconductor process operations, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, wafer / die transfer tools, and / or other types of semiconductor process tools. In some embodiments, they can be used as... Figures 3A to 3E The process described above for forming semiconductor component 200 is performed in part with Figures 4A to 4Q One or more semiconductor process operations described in relation to this.

[0085] like Figure 4AAs shown, a mask layer can be formed on the interlayer dielectric layer 214d in the interconnect layer 204 of the semiconductor component 200. For example, a dielectric mask layer 402 can be formed on the interlayer dielectric layer 214d. The dielectric mask layer 402 may comprise silicon oxynitride (SiON) and / or other suitable dielectric materials.

[0086] The dielectric mask layer 402 can be deposited using deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) is performed using a planarization tool after deposition of the dielectric mask layer 402 to planarize the dielectric mask layer 402.

[0087] like Figure 4B As shown, a photoresist layer 404 can be formed over the dielectric mask layer 402, and a pattern 406 can be formed in the photoresist layer 404. The photoresist layer can be formed on the dielectric mask layer 402 using a deposition tool (e.g., using spin coating or other suitable deposition techniques). In some embodiments, a bottom anti-reflective coating (BARC) is first deposited on the dielectric mask layer 402, and then the photoresist layer 404 is deposited on the bottom anti-reflective coating. The photoresist layer 404 can be exposed to a radiation source using an exposure tool to pattern the photoresist layer 404. A portion of the photoresist layer 404 can be developed and removed using a development tool to expose the pattern 406.

[0088] like Figure 4C As shown, an etching tool can be used to etch the dielectric mask layer 402 based on the pattern 406 in the photoresist layer 404 to transfer the pattern 406 to the dielectric mask layer 402. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). The etchant may have a higher etching rate on the dielectric mask layer 402 compared to the material of the underlying interlayer dielectric layer 214d. Therefore, the etching operation can be stopped on the interlayer dielectric layer 214d, minimizing the etching of the interlayer dielectric layer 214d.

[0089] like Figure 4DAs shown, another etching operation is performed to etch through the interlayer dielectric layers 214b, 214c, and 214d, and through the etch stop layers 216b and 216c, to form the trench 232 of the trench capacitor structure 226. This etching operation can include, for example, a gas-based etching operation using a different type of etchant, compared to the etchant used to transfer the pattern 406 to the dielectric mask layer 402. Therefore, a wafer / die transfer tool can be used to transfer the semiconductor component 200 from the first etching tool (where the pattern 406 is transferred to the dielectric mask layer 402) to the second etching tool (where the interlayer dielectric layers 214b, 214c, and 214d, as well as ESL 216b and 216c, are etched), reducing the possibility of cross-contamination between the first and second etching tools. Alternatively, an etching tool with multiple process chambers (such as a cluster tool) can be used, and the semiconductor component 200 can be transferred between the process chambers of the etching tool to etch using different types of etchants.

[0090] The gas-based etchant used for etching the interlayer dielectric layers 214b, 214c, 214d and the etch stop layers 216b, 216c may include a fluorine-based gas etchant that exhibits a higher etching rate for the dielectric material of the interlayer dielectric layers 214b, 214c, 214d and the etch stop layers 216b, 216c compared to the etching rate of the dielectric mask layer 402. This allows the interlayer dielectric layers 214b, 214c, 214d and the etch stop layers 216b, 216c to be etched while minimizing the etching of the dielectric mask layer 402 (therefore, the width or critical dimension of the trench 232 top is hardly increased). The fluorine-based etchant may include a fluoride-based fluorine (CF3) etchant. x Gas etchants, such as carbon tetrafluoride (CF4) gas etchant.

[0091] In some embodiments, multiple etching operations (e.g., multiple gas-based etching operations using a fluorine-based etchant) are performed to form the trench 232 of the trench capacitor structure 226. For example, a first etching operation (referred to as a "master etching" operation) may be performed to form the trench 232 extending to an etch stop layer 216a. In other words, the etching of the first etching operation stops at the etch stop layer 216a, such that the etch stop layer 216a remains between the bottom of the trench 232 and the bottom contact 228 at the bottom. The etch stop layer 216a remains above the bottom contact 228 to prevent the bottom contact 228 from being exposed to oxygen and other contaminants that may cause the bottom contact 228 to oxidize. After the first etching operation, the trench 232 may have tapered sidewalls, resulting in the lateral width of the trench 232 gradually decreasing from the top to the bottom of the trench 232.

[0092] A second etching operation (referred to as an "over-etching" operation) may be performed after the first etching operation to shape the bottom of trench 232. Specifically, the second etching operation may be performed to increase the verticality of the sidewalls of trench 232, thereby reducing the taper of the sidewalls of trench 232. During both the first and second etching operations, the dielectric mask layer 402 remains on the interlayer dielectric layer 214d to form and shape trench 232, such that the dielectric mask layer 402 protects the interlayer dielectric layer 214d from etching, which reduces the likelihood of critical dimension widening and the likelihood of rounded corners at the top of trench 232.

[0093] like Figure 4E As shown, a third etching operation (referred to as a "linear removal" etching operation) is performed to etch through the ESL 216a to the bottom of the trench 232, extending the trench 232 through the ESL 216a and reaching the bottom contact 228. Therefore, after the third etching operation, the bottom contact 228 is exposed through the trench 232. The third etching operation can use a second etching tool and a fluorine-based etchant, such as a fluorocarbon (CF3)-based etchant. x A gas etchant, such as CF4, is used. During the third etching operation, the dielectric mask layer 402 remains on the interlayer dielectric layer 214d to etch through the etch stop layer 216a, thus protecting the interlayer dielectric layer 214d from etching, which reduces the likelihood of critical dimension reduction. After the bottom contact 228 is exposed in the trench 232, the dielectric mask layer 402 is removed from the interlayer dielectric layer 214d.

[0094] like Figure 4F As shown, adhesive layer 234 can be deposited on the sidewalls and bottom surface of trench 232. The bottom surface of trench 232 corresponds to the top surface of bottom contact 228, so adhesive layer 234 can physically contact the top surface of bottom contact 228. Adhesive layer 234 can also be deposited on the top surface of interlayer dielectric layer 214d between adjacent trenches 232, such that adhesive layer 234 can physically contact the top surface of interlayer dielectric layer 214d. In some embodiments, adhesive layer 234 is conformally deposited using a deposition tool so that adhesive layer 234 conforms to the contour of trench 232. In some embodiments, adhesive layer 234 is deposited using conformal chemical vapor deposition and / or atomic layer deposition techniques.

[0095] like Figure 4GAs shown, the bottom electrode layer 236 can be deposited on the adhesive layer 234. Therefore, the bottom electrode layer 236 is deposited on the sidewalls and bottom surface of the trench 232 (corresponding to the top surface of the bottom contact 228). The bottom electrode layer 236 can also be deposited on the top surface of the adhesive layer 234 between adjacent trenches 232. In some embodiments, the bottom electrode layer 236 is conformally deposited using a deposition tool, such that the bottom electrode layer 236 conforms to the contour of the trench 232. In some embodiments, the bottom electrode layer 236 is deposited using conformal chemical vapor deposition and / or atomic layer deposition techniques.

[0096] like Figure 4H As shown, a surface treatment operation is performed on the bottom electrode layer 236 using surface treatment chemicals. The surface treatment chemicals may include nitrous oxide (N₂O) and / or other types of surface treatment chemicals that react with the material of the bottom electrode layer 236. The surface treatment operation forms a buffer layer 238 in and / or on the bottom electrode layer 236. As a result, the external portion of the bottom electrode layer 236 exposed to nitrous oxide (N₂O) is transformed into the buffer layer 238. The nitrous oxide (N₂O) in the surface treatment chemicals reacts with, for example, titanium nitride (such as Ti) in the bottom electrode layer 236. x N, such as Ti₂N), reacts to form titanium oxide (such as TiO₂). x Buffer layers 238 of nitrous oxide (TiO2) and titanium nitride (TiN) are used. Additional reactions of nitrous oxide (N2O) with titanium oxide may also form titanium oxynitride (TiO2). x N y It is a component of buffer layer 238.

[0097] like Figure 4I As shown, insulating layer 240 can be deposited on buffer layer 238. Therefore, insulating layer 240 is deposited on the sidewalls and bottom surface of trench 232 (corresponding to the top surface of bottom contact 228). Insulating layer 240 can also be deposited on the top surface of buffer layer 238 between adjacent trenches 232. In some embodiments, insulating layer 240 is conformally deposited using a deposition tool so that insulating layer 240 conforms to the contour of trench 232. In some embodiments, insulating layer 240 is deposited using conformal chemical vapor deposition and / or atomic layer deposition techniques.

[0098] In some embodiments, multiple atomic layer deposition cycles are performed to deposit the insulating layer 240. For example... Figure 5A As described in more detail below, performing an atomic layer deposition cycle may include depositing zirconium oxide (ZrO2) using a first material precursor. x (e.g., ZrO2), and alumina (Al) is deposited on zirconium oxide using a second material precursor. x O y(e.g., Al₂O₃). A first material precursor is oxidized to form zirconium oxide, and a second material precursor is oxidized to form aluminum oxide. Multiple atomic layer deposition cycles are performed to deposit alternating zirconium oxide and aluminum oxide atomic layers. The alternating zirconium oxide and aluminum oxide atomic layers are mixed together to form an insulating layer 240. The insulating layer 240 comprises an amorphous composition of zirconium, aluminum, and oxygen (ZrAlO), wherein molecules having Zr-O bonds, Al-O bonds, Zr-O-Al bonds, and / or Zr-Al bonds may be present in the amorphous film. The insulating layer 240 may be an amorphous film containing an amorphous composition of zirconium oxide and aluminum oxide.

[0099] like Figure 4J As shown, a top electrode layer 242 may be deposited on an insulating layer 240. The top electrode layer 242 may be deposited to fill the remaining area of ​​the trench 232. The top electrode layer 242 may also be deposited on the top surface of the insulating layer 240 between adjacent trenches 232. In some embodiments, the top electrode layer 242 is conformally deposited using a deposition tool employing physical vapor deposition, chemical vapor deposition, atomic layer deposition, and / or other suitable deposition techniques.

[0100] like Figure 4K As shown, a capping layer is formed over the trench 232 of the trench capacitor structure 226. For example, an oxide capping layer 244 may be formed over and / or on the top electrode layer 242, an oxynitride capping layer 246 may be formed over and / or on the oxide capping layer 244, and / or a nitride capping layer 248 may be formed over and / or on the oxynitride capping layer 246, and other examples.

[0101] An oxide capping layer 244, an oxynitride capping layer 246, and / or a nitride capping layer 248 can be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. The oxide capping layer 244, the oxynitride capping layer 246, and / or the nitride capping layer 248 may be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., a chemical mechanical planarization operation) can be performed using a planarization tool to planarize the oxide capping layer 244, the oxynitride capping layer 246, and / or the nitride capping layer 248 after deposition.

[0102] like Figure 4LAs shown, capping layers (e.g., oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248) can be used to etch and define the top electrode layer 242 of the trench capacitor structure 226. In some embodiments, the oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248 are etched using a pattern in a photoresist layer to form a hard mask on the top electrode layer 242. In these embodiments, a photoresist layer can be formed on the nitride capping layer 248 using a deposition tool. The photoresist layer can be exposed to a radiation source using an exposure tool to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248 can be etched based on the pattern using an etching tool to define the hard mask layer. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, the remaining portion of the photoresist layer may be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques). The top electrode layer 242 may then be etched using an etching tool based on a hard mask layer (e.g., based on a pattern in oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248) to define the top electrode layer 242.

[0103] like Figure 4M As shown, spacer layers 408 and 410 are formed on a capping layer (e.g., oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248). Spacer layers 408 and 410 extend along the ends of the capping layers (e.g., along the ends of oxide capping layer 244, oxynitride capping layer 246, and / or nitride capping layer 248) and along the ends of the top electrode layer 242. Furthermore, spacer layers 408 and 410 are formed on exposed portions of the insulating layer 240.

[0104] Spacer layers 408 and / or 410 can be deposited using deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. Spacer layers 408 and / or 410 may be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) may be performed after the deposition of spacer layers 408 and / or 410 to planarize the spacer layers 408 and / or 410.

[0105] like Figure 4NAs shown, spacer layers 408 and 410 are etched together with portions of insulating layer 240, buffer layer 238, bottom electrode layer 236, and adhesive layer 234 to define the bottom electrode layer 236 of the MIM structure of trench capacitor structure 226. This etching operation may be referred to as a CBM etching operation. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. Etching of spacer layers 408 and 410 removes portions of spacer layers 408 and 410 from the top of nitride capping layer 248, resulting in the formation of sidewall spacers 250 and 252 at the ends of oxide capping layer 244, oxynitride capping layer 246, nitride capping layer 248, and top electrode layer 242. Furthermore, the etching of spacer layers 408 and 410 results in the sidewall spacer 252 having a circular outer surface.

[0106] Anisotropic etching of spacer layers 408 and 410 can be achieved using etchants (e.g., gas-based etchants, plasma-based etchants). Spacer layers 408 and 410 can be etched together with portions of insulating layer 240, buffer layer 238, bottom electrode layer 236, and adhesive layer 234. This anisotropic etching primarily occurs along the z-direction in the semiconductor assembly 200, enabling minimal lateral etching of the bottom electrode layer 236 and insulating layer 240.

[0107] like Figure 4O As shown, additional material can be formed in the interlayer dielectric layer 214d to encapsulate the trench capacitor structure 226. The additional material in the interlayer dielectric layer 214d can be deposited using deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, epitaxy, oxidation, and / or other suitable deposition techniques. The additional material in the interlayer dielectric layer 214d can be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) can be performed on the interlayer dielectric layer 214d after the deposition of the additional material in the interlayer dielectric layer 214d to planarize the interlayer dielectric layer 214d.

[0108] like Figure 4P As shown, a groove 412 can be formed in the interlayer dielectric layer 214d, passing through the cap layers 244-248 and extending to the top electrode layer 242 of the trench capacitor structure 226. Therefore, the top electrode layer 242 can be exposed through the groove 412.

[0109] In some embodiments, the pattern in the photoresist layer is used to etch the interlayer dielectric layer 214d, the oxide capping layer 244, the oxynitride capping layer 246, and / or the nitride capping layer 248 to form a recess 412. In these embodiments, a deposition tool can be used to form the photoresist layer on the interlayer dielectric layer 214d. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the interlayer dielectric layer 214d, the oxide capping layer 244, the oxynitride capping layer 246, and / or the nitride capping layer 248 based on the pattern to form the recess 412. In some embodiments, one or more etching operations are performed to etch the interlayer dielectric layer 214d, the oxide capping layer 244, the oxynitride capping layer 246, and / or the nitride capping layer 248. In some embodiments, one or more etching operations may include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, the remaining portion of the photoresist layer may be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative to pattern-forming groove 412.

[0110] like Figure 4Q As shown, a top contact 230 can be formed in the groove 412. The material of the top contact 230 can be deposited using deposition tools via chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques. The top contact 230 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then the top contact 230 is deposited on the seed layer. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) is performed after the deposition of the top contact 230 using a planarization tool to planarize the top contact 230.

[0111] As mentioned above, providing Figures 4A to 4Q As an example. Other examples may be similar. Figures 4A to 4Q The descriptions are different.

[0112] Figure 5A and Figure 5B Example 500 illustrates the insulating layer 240 described herein. Example 500 includes an atomic layer deposition technique in which atomic layers of zirconium oxide 502 and aluminum oxide 504 are alternately deposited on a buffer layer 238. These alternating atomic layers are mixed together to form an amorphous structure of the insulating layer 240. Multiple operations in the atomic layer deposition technique are performed over time.

[0113] Multiple atomic layer deposition cycles are performed to form an insulating layer 240. The atomic layer deposition cycle in Example 500 includes the use of a sequence of gaseous precursors (or reactants). The semiconductor component 200 is placed in the process chamber of the deposition tool, and oxygen-containing gas is pulsed during the atomic layer deposition cycle to oxygenate the semiconductor component 200. The oxygen-containing gas may include ozone (O3), oxygen (O2), water vapor (H2O), and / or other oxygen-containing gases. The pulse duration of the oxygen-containing gas may range from about 0.1 seconds to about 3 seconds. However, other range values ​​are included within the scope of this invention.

[0114] The pulse of oxygen-containing gas may be followed by the first pulse of a first metallic material precursor, which is provided into the process chamber of the deposition tool. The first metallic material precursor may include a zirconium vapor precursor for the zirconium oxide layer 502. Examples of zirconium precursors include tetratetra(tert-butoxy)zirconium(IV)(Zr(OC(CH3)3)4), zirconium tetraiodide(IV)(ZrI4), zirconium tetrachloride(IV)(ZrCl4), and tetratetra(dimethylamino)zirconium(IV)(Zr(NMe2)4), among others. The duration of the first pulse of the first metallic material precursor may range from about 0.1 seconds to about 3 seconds. However, other range values ​​are included within the scope of this invention.

[0115] The first metallic material precursor is then removed from the process chamber, and a pulse of oxygen-containing gas may be supplied to the process chamber again. This pulse of oxygen-containing gas may be followed by a pulse of a second metallic material precursor, which is supplied to the process chamber of the deposition tool. The second metallic material precursor may include an aluminum vapor precursor for the alumina layer 504. Examples of aluminum precursors include trimethylaluminum (TMA) (C3H9Al), dimethylaluminum hydride (DMAH) ((CH3)2AlH), and dimethylethylamine (DMEAA) (AIH3:N(CH3)2(CH2CH3)), among others. The pulse duration of the second metallic material precursor may range from about 0.1 seconds to about 3 seconds. However, other range values ​​are included within the scope of this invention.

[0116] The first pulse of the first metallic material precursor may react with oxygen-containing gas to form a first zirconium oxide layer 502 of the insulating layer 240. The first zirconium oxide layer 502 includes an oxygen-containing metallic material (e.g., a metal oxide material) containing the metal of the first metallic material precursor (e.g., zirconium). The first pulse of the second metallic material precursor may react with oxygen-containing gas to form a first aluminum oxide layer 504 of the insulating layer 240 on the first zirconium oxide layer 502. The first aluminum oxide layer 504 includes an oxygen-containing metallic material (e.g., a metal oxide material) containing the metal of the second metallic material precursor (e.g., aluminum).

[0117] Additional atomic layer deposition cycles can be performed to form repeating alternating atomic layers (e.g., zirconium oxide layer 502 and aluminum oxide layer 504) on the first zirconium oxide layer 502 and the first aluminum oxide layer 504, such as Figure 5A As shown. The number of atomic layer deposition cycles performed may be based on the desired insulation layer thickness of 240.

[0118] In some embodiments, multiple atomic layer deposition cycles are performed to deposit alternating layers of zirconium oxide and alumina at the same or different deposition rates. In particular, in one atomic layer deposition cycle, a layer of a first high-dielectric metal oxide (e.g., zirconium oxide) may be deposited with a layer of a second high-dielectric metal oxide (e.g., alumina) at approximately the same rate, a faster rate, or a slower rate.

[0119] In some embodiments, the deposition rate per atomic layer deposition cycle is in the range of about 0.5 angstroms to about 2 angstroms per atomic layer deposition cycle. However, other range values ​​are included within the scope of the invention.

[0120] The duration of each atomic layer deposition cycle may range from about 3 seconds to about 6 seconds. However, other range values ​​are included within the scope of the invention. In some embodiments, the amount of time for the first metal precursor pulse to react with oxygen-containing gas and / or the amount of the first metal precursor are controlled to increase or decrease the concentration and / or deposition thickness of the zirconium oxide layer 502. Similarly, the amount of time for the second metal precursor pulse to react with oxygen-containing gas and / or the amount of the second metal precursor are controlled to increase or decrease the concentration and / or deposition thickness of the alumina layer 504.

[0121] In some embodiments, in one or more atomic layer deposition cycles, each cycle may contain a greater number of first metal material precursor pulses than the number of second metal material precursor pulses, to achieve a higher concentration and a greater deposition thickness of the first metal oxide (e.g., zirconium oxide) in the insulating layer 240. For example, an atomic layer deposition cycle may contain three zirconium pulses and one aluminum pulse to achieve a thickness ratio of approximately 3:1 between the zirconium oxide layer 502 thickness and the aluminum oxide layer 504 thickness.

[0122] Alternatively, in one or more atomic layer deposition cycles, each cycle may contain a greater number of second metal precursor pulses than the number of first metal precursor pulses, to achieve a higher concentration and greater deposition thickness of the second metal oxide (e.g., alumina) in the insulating layer 240. For example, an atomic layer deposition cycle may contain 3 zirconium pulses and 4 aluminum pulses to achieve a thickness ratio of approximately 3:4 between the zirconium oxide layer 502 and the alumina layer 504.

[0123] In some embodiments, one or more atomic layer deposition cycles may contain the same number of first metal precursor pulses and second metal precursor pulses to achieve approximately the same concentration and approximately the same deposition thickness of the first and second metal oxides. As used herein, “concentration” refers to the amount of a given substance relative to volume (e.g., atoms per cubic centimeter).

[0124] The combined deposition thickness of the zirconia layer 502 in the z-direction can be greater than, less than, or approximately equal to the combined deposition thickness of the alumina layer 504 in the z-direction. Similarly, the thickness of the individual zirconia layer 502 and alumina layer 504 in the z-direction can be increased or decreased by varying the reaction time and / or the amount of precursor during a given atomic layer deposition cycle.

[0125] In some embodiments, atomic layer deposition cycles are repeated until the thickness of the insulating layer 240 in the z-direction is approximately 50 to approximately 80 angstroms. However, other range values ​​are included within the scope of the invention.

[0126] Reference Figure 5B In some embodiments, Figure 5A The repeating alternating atomic layers shown (e.g., zirconium oxide layer 502 and aluminum oxide layer 504) are not visible in the final structure of the semiconductor component 200. Figure 5B As shown, due to subsequent heat treatment, the zirconium oxide layer 502 and the aluminum oxide layer 504 are mixed together to form an insulating layer 240 containing an amorphous composition of zirconium, aluminum, and oxygen (ZrAlO). This insulating layer may contain molecules with Zr-O bonds, Al-O bonds, Zr-O-Al bonds, and / or Zr-Al bonds, forming an amorphous thin film. The insulating layer 240 may be an amorphous thin film containing amorphous components of zirconium oxide and aluminum oxide.

[0127] The amorphous structure of insulating layer 240 exhibits higher stability compared to other methods using a ZrO2 / Al2O3 / ZrO2 (ZAZ) dielectric layer stack as the insulating layer. In particular, the amorphous structure of insulating layer 240 can withstand high-temperature conditions better than crystals containing a ZAZ stack, resulting in lower oxygen migration. However, in some cases, the amorphous structure of insulating layer 240 may contain multiple phases, such as a tetragonal phase and / or a cubic phase, which are more stable than other phases.

[0128] As mentioned above, Figure 5A and Figure 5B Provided as an example. Other examples may be related to... Figure 5A and Figure 5B The descriptions are different.

[0129] Figure 6 The elemental composition 600 of the insulating layer 240 along the depth profile 602 in Example 500 is illustrated. The elemental composition is described as the atomic percentage 604 of one or more elements in the insulating layer 240 as a function of the depth 606 of the insulating layer 240. In particular, the atomic percentage 604 of one or more elements is described from the top surface to the bottom surface of the insulating layer 240.

[0130] like Figure 6 As shown in the depth profile 602, the insulating layer 240 may include aluminum oxide (Al). x O y ) and zirconium oxide (ZrO) x Aluminum (e.g., aluminum oxide (Al)) x O y The atomic percentage (or concentration) of zirconium (e.g., zirconium oxide (ZrO)) is 604. x The atomic percentage 604 (or concentration) of the insulating layer 240 increases along the depth 606, reaches a peak, and then decreases, such that the concentration of aluminum and zirconium in or near the middle portion of the insulating layer 240 in the z direction is greater than the concentration on or near the top and bottom surfaces of the insulating layer 240.

[0131] Because the curves of alumina and zirconium oxide have approximately the same parabolic shape, and there are approximately parallel line segments along the depth 606 of the insulating layer 240, in some embodiments, aluminum (e.g., alumina (Al)) x O y The atomic percentage (or concentration) of zirconium (e.g., zirconium oxide (ZrO)) is 604. x The ratio of atomic percentage 604 (or concentration) of the insulating layer 240 is substantially uniform (e.g., remains constant) along a depth 606 of the insulating layer 240.

[0132] As can be seen from the higher peaks and higher points of the alumina curve compared to the lower peaks and lower points of the zirconium oxide curve, in some embodiments, along the depth 606 of the insulating layer 240, the insulating layer 240 may contain elements relative to zirconium (e.g., zirconium oxide (ZrO)). x Aluminum with an atomic percentage (or concentration) higher than 604 (e.g., aluminum oxide (Al₂O₃)) has a higher atomic percentage (or concentration). x O y Atomic percentage 604 (or concentration).

[0133] In some embodiments, the ratio of the atomic percentage 604 (or concentration) of zirconium oxide 604 to the atomic percentage 604 (or concentration) of aluminum oxide 604 in insulating layer 240 may range from approximately 3:4 to approximately 9:2. As described herein, insulating layer 240, as a single amorphous layer, avoids the interface between zirconium oxide and aluminum oxide, as well as the formation of easily trapped crystal defects in zirconium oxide. The resulting image sensor assembly exhibits reduced latency. For example, in some embodiments, when using a single amorphous insulating layer, latency can be reduced by more than 20% compared to other methods using a ZrO2 / Al2O3 / ZrO2 (ZAZ) dielectric layer stack as the insulating layer. With a zirconium oxide atomic percentage 604 (or concentration) to aluminum oxide atomic percentage 604 (or concentration) ratio of approximately 3:4 in insulating layer 240, latency is reduced by approximately 5% compared to other methods. When the ratio of the atomic percentage 604 (or concentration) of zirconium oxide to the atomic percentage 604 (or concentration) of aluminum oxide in insulating layer 240 is approximately 3:2, the delay is reduced by approximately 10% compared to other methods. When the ratio of the atomic percentage 604 (or concentration) of zirconium oxide to the atomic percentage 604 (or concentration) of aluminum oxide in insulating layer 240 is approximately 3:1, the delay is reduced by approximately 21% compared to other methods. When the ratio of the atomic percentage 604 (or concentration) of zirconium oxide to the atomic percentage 604 (or concentration) of aluminum oxide in insulating layer 240 is approximately 9:2, the delay is reduced by approximately 23% compared to other methods.

[0134] Figure 7 The image is an icon for the example semiconductor component 700 described herein. Semiconductor component 700 may include examples of three-dimensional image sensors (e.g., 3D CMOS image sensors). Semiconductor component 700 may be configured to be deployed in various embodiments, such as digital cameras, video recorders, night vision cameras, automotive sensors, and cameras and / or other types of light-sensing embodiments.

[0135] like Figure 7As shown, the semiconductor component 700 may include a pixel sensor array 702. The semiconductor component 700 may also include a black level correction (BLC) region 704, a bonding pad region 706, and / or a sealing ring region 708, etc. The pixel sensor array 702 may include a plurality of pixel sensors 100 arranged in an array. Pixel sensors 100 may be configured to sense incident light and convert photons of the incident light into photocurrent. Pixel sensors 100 may be included in a component layer 710 of the semiconductor component 700. Each pixel sensor 100 may include one or more photodiodes 102 configured to generate photocurrent based on photons of the incident light. Pixel sensors 100 may also include floating diffusion nodes 106 in the component layer 710 configured to temporarily store the photocurrent generated by the associated pixel sensors 100, and may each include a transfer gate 104 configured to control the flow of photocurrent from the photodiodes 102 to the floating diffusion nodes 106. The pixel sensor 100 can be formed by one or more semiconductor process tools using various semiconductor process technologies, such as photolithography, etching, deposition, chemical mechanical planarization and / or ion implantation.

[0136] The black level correction region 704 includes a metal shielding layer over a portion of the component layer 710 to allow baseline current measurements to be performed within the component layer 710 of the black level correction region 704 to determine the dark current of the pixel sensor array 702 (e.g., current generated in the component layer 710 by non-incident light sources such as heat), thereby allowing the black level of the pixel sensor array 702 to be adjusted to compensate for the dark current. The bonding pad region 706 may include one or more conductive bonding pads (or electronic pads) and / or metallization layers through which electrical connections can be established between the semiconductor component 700 and external components and / or external packages. The sealing ring region 708 may include an arrangement of metallization and interconnect structures to provide structural rigidity to the semiconductor component 700 and protect it from moisture and other contaminants.

[0137] like Figure 7 As further shown, the semiconductor component 700 may include an interconnect layer 712 located below the component layer 710. The interconnect layer 712 may include a dielectric region 714, which includes one or more dielectric layers (e.g., an interlayer dielectric layer, an interlayer metal dielectric layer, an etch stop layer) and an arrangement of metallization structures 716 and interconnect structures 718 in the dielectric region 714. A passivation layer 720 may be included below the interconnect layer 712.

[0138] like Figure 7As further shown, one or more overflow capacitors 114 may be included in the interconnect layer 712. The overflow capacitor 114 may be structurally implemented as the trench capacitor structure 226 shown and described herein. The overflow capacitor 114 may be electrically coupled to the floating diffusion node 106 of the pixel sensor 100 and may be configured to store the overflow photocurrent from the floating diffusion node 106.

[0139] As mentioned above, providing Figure 7 As an example. Other examples may be related to... Figure 7 The descriptions are different.

[0140] Figure 8 This is a diagram of an example semiconductor component 800 described herein. Semiconductor component 800 may include an example of a three-dimensional image sensor (e.g., a 3D CMOS image sensor). Semiconductor component 800 may be configured to be deployed in various implementations, such as digital cameras, video recorders, night vision cameras, automotive sensors, and cameras and / or other types of light-sensing implementations.

[0141] like Figure 8 As shown, semiconductor component 800 includes a combination of structures and / or layers similar to those of semiconductor component 700. For example, semiconductor component 800 may include elements 802 to 818, which are similar to elements 702 to 718 of semiconductor component 700.

[0142] However, the semiconductor component 800 includes multiple semiconductor dies, including a first semiconductor die 820a and a second semiconductor die 820b. The first semiconductor die 820a and the second semiconductor die 820b can be directly bonded together at a bonding interface 822, such that the first semiconductor die 820a and the second semiconductor die 820b are stacked and vertically arranged along the z-direction in the semiconductor component 800. The first semiconductor die 820a may be referred to as an image sensor die and may include a pixel sensor array 802 (including a pixel sensor 100), a black level correction region 804, and a bonding pad region 806. The first semiconductor die 820a may also include a photodiode 102, a transmission gate 104, a floating diffusion node 106, a component layer 810, and an interconnect layer 812 (including a dielectric region 814, a metallization structure 816, and an interconnect structure 818). Figure 8 In the example, the overflow capacitor 114 is contained in the interconnect layer 812 of the first semiconductor die 820a. The sealing ring region 808 may extend through the first semiconductor die 820a and the second semiconductor die 820b.

[0143] like Figure 8As further shown, the second semiconductor die 820b of the semiconductor component 800 may include a component layer 824, one or more integrated circuit components 826 contained in the component layer 824, and an interconnect layer 828 located above the component layer 824. The interconnect layer 828 may include a dielectric region 830, which includes one or more dielectric layers (e.g., interlayer dielectric layers, etch stop layers) and an arrangement of metallization structures 832 and interconnect structures 834 in the dielectric region 830 of the interconnect layer 828 of the second semiconductor die 820b.

[0144] The first semiconductor die 820a and the second semiconductor die 820b can be joined at the bonding interface 822 via a dielectric-to-dielectric bonding between the dielectric region 814 of the first semiconductor die 820a and the dielectric region 830 of the second semiconductor die 820b. Furthermore, the first semiconductor die 820a and the second semiconductor die 820b can be joined at the bonding interface 822 via a metal-to-metal bonding between a bonding pad 836 contained in the interconnect layer 812 of the first semiconductor die 820a and a bonding pad 838 contained in the interconnect layer 828 of the second semiconductor die 820b. The bonding pad 836 can be electrically connected to the metallization structure 816 and the interconnect structure 818 in the interconnect layer 812 via a bonding via 840, while the bonding pad 838 can be electrically connected to the metallization structure 832 and the interconnect structure 834 in the interconnect layer 828 via a bonding via 842.

[0145] As mentioned above, providing Figure 8 As an example. Other examples may be related to... Figure 8 The descriptions are different.

[0146] Figure 9 This is a diagram of an example semiconductor component 900 described herein. Semiconductor component 900 may include examples of a three-dimensional image sensor (e.g., a three-dimensional complementary metal-oxide-semiconductor image sensor). Semiconductor component 900 may be configured to be deployed in various embodiments, such as digital cameras, video recorders, night vision cameras, automotive sensors and cameras, and / or other types of light-sensing embodiments.

[0147] like Figure 9 As shown, semiconductor component 900 includes a combination of structures and / or layers similar to those of semiconductor component 800. For example, semiconductor component 900 may include elements 902 to 942, which are similar to elements 802 to 842 of semiconductor component 800. Semiconductor component 900 may also include pixel sensor 100, photodiode 102, transfer gate 104, floating diffusion node 106, and one or more overflow capacitors 114.

[0148] However, in semiconductor component 900, one or more overflow capacitors 114 are included in a second semiconductor die 920b (e.g., an application-specific integrated circuit (ASIC) die) and not (or except) included in a first semiconductor die 920a (e.g., a sensor die). Including one or more overflow capacitors 114 in the second semiconductor die 920b instead of the first semiconductor die 920a allows a larger area in the first semiconductor die 920a to be used for the photodiode 102 (which provides the photodiode 102 with increased full-well capacity) and / or for control circuitry for the pixel sensor 100 (e.g., for the transfer gate 104, reset gate 108, overflow gate 112), which may increase the performance of semiconductor component 900.

[0149] As mentioned above, providing Figure 9 As an example. Other examples may be related to... Figure 9 The descriptions are different.

[0150] Figure 10 This is a flowchart of an example process 1000 associated with the formation of a semiconductor component. In some embodiments, Figure 10 One or more process blocks are executed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0151] like Figure 10 As shown, process 1000 may include forming trenches in a dielectric layer (block 1010). For example, one or more semiconductor process tools may be used to form trenches (e.g., trench 232) in a dielectric layer (e.g., interlayer dielectric layer 214 and / or etch stop layer 216), as described herein.

[0152] like Figure 10 As further shown, process 1000 may include a first electrode layer (block 1020) deposited in a trench of a semiconductor layer stack. For example, a first electrode layer (e.g., bottom electrode layer 236) of a semiconductor layer stack of a capacitor structure (e.g., trench capacitor structure 226) may be deposited in a trench using one or more semiconductor process tools, as described herein.

[0153] like Figure 10 As further shown, process 1000 may include depositing an insulating layer of a semiconductor layer stack in a trench onto a first electrode layer (block 1030). For example, one or more semiconductor process tools may be used to deposit an insulating layer (e.g., insulating layer 240) of a semiconductor layer stack onto a first electrode layer in a trench, as described herein.

[0154] like Figure 10 As further shown, process 1000 may include depositing a second electrode layer of a semiconductor layer stack on an insulating layer in a trench (block 1040). For example, one or more semiconductor process tools may be used to deposit the second electrode layer (e.g., top electrode layer 242) of the semiconductor layer stack on an insulating layer in a trench, as described herein. In some embodiments, the semiconductor layer stack extends along the sidewalls and bottom surface of the trench. In some embodiments, the insulating layer is an amorphous layer comprising a combination of metal and oxygen.

[0155] Process 1000 may include additional embodiments, such as any single embodiment or combination of any embodiments described below and / or one or more other related processes described elsewhere herein.

[0156] In a first embodiment, depositing an insulating layer includes performing multiple atomic layer deposition cycles to deposit the insulating layer, wherein performing one atomic layer deposition cycle includes depositing zirconium oxide (e.g., zirconium oxide layer 502) using a first material precursor and depositing alumina (e.g., alumina layer 504) on the zirconium oxide using a second material precursor.

[0157] In the second embodiment, the atomic layer deposition cycle, performed alone or in combination with the first embodiment, further includes oxidizing a first material precursor to form zirconium oxide and oxidizing a second material precursor to form aluminum oxide.

[0158] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the thickness of the deposited zirconium oxide is greater than the thickness of the deposited alumina.

[0159] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the thickness of the deposited zirconium oxide is less than the thickness of the deposited alumina.

[0160] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the thickness of the deposited zirconium oxide is approximately equal to the thickness of the deposited alumina.

[0161] In the sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, multiple atomic layer deposition cycles are performed to deposit alternating zirconium oxide and alumina atomic layers.

[0162] In the seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, process 1000 includes performing a surface treatment operation on the first electrode layer to transform a portion of the first electrode layer into a buffer layer (e.g., buffer layer 238) on the first electrode layer, wherein the surface treatment operation is performed prior to the deposition of an insulating layer, and the insulating layer is deposited on the buffer layer.

[0163] In the eighth embodiment, the insulating layer comprises, alone or in combination with one or more of the first to seventh embodiments, at least one of a tetragonal or cubic crystal phase.

[0164] In the ninth embodiment, alone or in combination with one or more of the first to eighth embodiments, the metal comprises aluminum and zirconium, wherein the ratio of zirconium concentration to aluminum concentration in the insulating layer is substantially uniform at different depths of the insulating layer.

[0165] In the tenth embodiment, alone or in combination with one or more of the first to ninth embodiments, the metal comprises aluminum and zirconium, wherein the concentration of zirconium in the insulating layer is greater than the concentration of aluminum in the insulating layer.

[0166] Although Figure 10 The example block diagram of process 1000 is shown. In some embodiments, compared to Figure 10 The blocks depicted in process 1000 may include additional blocks, fewer blocks, different blocks, or blocks with different configurations. Alternatively, two or more blocks of process 1000 may be executed simultaneously.

[0167] Figure 11 This is a flowchart of an example process 1100 associated with the formation of a semiconductor component. In some embodiments, Figure 11 One or more process blocks are executed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0168] like Figure 11 As shown, process 1100 may include depositing a first conductive layer within a trench formed in a dielectric layer (box 1110). For example, one or more semiconductor process tools may be used to deposit a first conductive layer (e.g., bottom electrode layer 236) within a trench (e.g., trench 232) formed in a dielectric layer (e.g., interlayer dielectric layer 214 and / or etch stop layer 216), as described herein. In some embodiments, the first conductive layer extends along the sidewalls and bottom surface of the trench.

[0169] like Figure 11 As further shown, process 1100 may include performing processing operations to transform a portion of the first conductive layer into a buffer layer (block 1120). For example, one or more semiconductor process tools may be used to perform the processing operations to transform a portion of the first conductive layer into a buffer layer (e.g., buffer layer 238), as described herein.

[0170] like Figure 11As further shown, process 1100 may include depositing an insulating layer on the buffer layer (block 1130). For example, an insulating layer (e.g., insulating layer 240) may be deposited on the buffer layer using one or more semiconductor process tools, as described herein. In some embodiments, the insulating layer is an amorphous composition comprising a mixture of a first metallic material, a second metallic material, and oxygen.

[0171] like Figure 11 As further shown, process 1100 may include depositing a second conductive layer on the insulating layer (block 1140). For example, one or more semiconductor process tools may be used to deposit the second conductive layer (e.g., top electrode layer 242) on the insulating layer, as described herein.

[0172] Process 1100 may include additional embodiments, such as any single or combined embodiments described below, and / or one or more other processes described elsewhere herein.

[0173] In the first embodiment, at least some of the first metal material and the oxygen in the first portion combine with each other to form a first high dielectric metal oxide, and at least some of the second metal material and the oxygen in the second portion combine with each other to form a second high dielectric metal oxide.

[0174] In the second embodiment, alone or in combination with the first embodiment, depositing an insulating layer includes performing multiple atomic layer deposition cycles to deposit alternating first high-dielectric metal oxide layers and second high-dielectric metal oxide layers.

[0175] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the atomic layer of the first high-dielectric metal oxide is deposited at a higher rate than the atomic layer of the second high-dielectric metal oxide.

[0176] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, the deposition of the insulating layer is such that the ratio of the first high dielectric metal oxide to the second high dielectric metal oxide is in the range of about 3:4 to about 9:2.

[0177] although Figure 11 The block diagram shows an example of process 1100, but in some embodiments, process 1100 includes... Figure 11 The blocks depicted are compared to additional blocks, fewer blocks, different blocks, or blocks with different configurations. Alternatively, two or more blocks of process 1100 may be executed in parallel.

[0178] Thus, image sensor assemblies (e.g., CMOS image sensor assemblies) include capacitor structures (e.g., MIM capacitors) with an insulating layer having an amorphous composition comprising a mixture of zirconium, aluminum, and oxygen. Compared to crystalline insulating layer stacks (such as ZrO2 / Al2O3 / ZrO2 (ZAZ) dielectric layer stacks), this amorphous composition reduces or prevents interface defects and electron trapping. In particular, the amorphous composition of the insulating layer avoids interfaces between different zirconium oxide and aluminum oxide layers, which reduces and / or prevents the formation of crystal defects (such as oxygen vacancies) in the insulating layer. Because charge trapping in the capacitor structure is reduced, minimized, and / or prevented due to reduced and / or prevented crystal defects, the resulting image sensor assembly exhibits reduced latency when generating images and / or videos. For example, in some embodiments, the image sensor assembly may exhibit a latency reduction of greater than 20% when generating images and / or videos compared to other capacitor structures including ZAZ dielectric layer stacks. Furthermore, the amorphous composition of the insulating layer may increase the capacitance of the capacitor structure compared to other capacitor structures including ZAZ dielectric layer stacks. For example, in some embodiments, the capacitance of the capacitor structure can be increased by about 30% compared to other methods.

[0179] As described in detail above, some embodiments described herein provide a method of forming a semiconductor component. The method includes forming a trench in a dielectric layer. The method includes depositing a first electrode layer of a semiconductor layer stack in the trench. The method includes depositing an insulating layer of the semiconductor layer stack on the first electrode layer in the trench. The method includes depositing a second electrode layer of the semiconductor layer stack on the insulating layer in the trench, wherein the semiconductor layer stack extends along the sidewalls and bottom surface of the trench, and wherein the insulating layer is an amorphous layer comprising a combination of metal and oxygen.

[0180] As described in detail above, some embodiments described herein provide a method of forming a semiconductor component. The method includes depositing a first conductive layer within a trench formed in a dielectric layer, wherein the first conductive layer extends along the sidewalls and bottom surface of the trench. The method includes performing processing operations to transform a portion of the first conductive layer into a buffer layer. The method includes depositing an insulating layer on the buffer layer, wherein the insulating layer is an amorphous composition comprising a mixture of a first metallic material, a second metallic material, and oxygen. The method includes depositing a second conductive layer on the insulating layer.

[0181] As described in detail above, some embodiments described herein provide a semiconductor component. The semiconductor component includes a first electrode layer extending along the sidewalls and bottom surface of a trench. The semiconductor component includes a second electrode layer within the trench. The semiconductor component includes an insulating layer between the first and second electrode layers, wherein the insulating layer extends along the sidewalls and bottom surface of the trench, and wherein the insulating layer has an amorphous structure comprising a mixture of multiple high-k dielectric oxide materials.

[0182] The terms "approximately" and "substantially" can indicate that the value of a given quantity varies within a range of 5% (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and not limiting. The terms "approximately" and "substantially" can refer to a percentage of a value as interpreted by one of ordinary skill in the art based on the teachings herein.

[0183] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for forming a semiconductor component, characterized in that, include: Trenches are formed in the dielectric layer; A first electrode layer of a semiconductor layer stack is deposited in the trench; In the trench, an insulating layer of the semiconductor layer stack is deposited on the first electrode layer; as well as In the trench, a second electrode layer of the semiconductor layer stack is deposited on the insulating layer. The semiconductor layer stack extends along the sidewalls and bottom surface of the trench, and The insulating layer therein is an amorphous layer containing a combination of metal and oxygen.

2. The method according to claim 1, characterized in that, The deposition of the insulating layer includes: Multiple atomic layer deposition cycles are performed to deposit the insulating layer. The execution of the atomic layer deposition cycle among the plurality of atomic layer deposition cycles includes: Zirconia was deposited using a first material precursor; and Alumina is deposited on the zirconium oxide using a second material precursor.

3. The method according to claim 2, characterized in that, The zirconium oxide deposition thickness is greater than the alumina deposition thickness.

4. The method according to claim 2, characterized in that, The zirconium oxide deposition thickness is less than the alumina deposition thickness.

5. The method according to claim 2, characterized in that, The deposition thickness of the zirconium oxide is approximately equal to the deposition thickness of the alumina.

6. The method according to claim 2, characterized in that, The plurality of atomic layer deposition cycles are performed to deposit alternating zirconium oxide atomic layers and aluminum oxide atomic layers.

7. The method according to claim 1, characterized in that, The metals mentioned include aluminum and zirconium, and The ratio of the zirconium concentration to the aluminum concentration in the insulating layer is substantially uniform at different depths of the insulating layer.

8. The method according to claim 1, characterized in that, The metals mentioned include aluminum and zirconium, and The concentration of zirconium in the insulating layer is greater than the concentration of aluminum in the insulating layer.

9. A method for forming a semiconductor component, characterized in that, include: A first conductive layer is deposited in a trench formed in the dielectric layer. The first conductive layer extends along the sidewalls and bottom surface of the trench; Perform a processing operation to transform a portion of the first conductive layer into a buffer layer; An insulating layer is deposited on the buffer layer. The insulating layer is an amorphous composition, comprising a mixture of a first metallic material, a second metallic material, and oxygen; and A second conductive layer is deposited on the insulating layer.

10. A semiconductor component, characterized in that, include: The first electrode layer extends along the sidewalls and bottom surface of the trench; The second electrode layer is located in the trench; as well as An insulating layer is located between the first electrode layer and the second electrode layer. The insulating layer extends along the sidewalls and bottom surface of the trench, and The insulating layer has an amorphous structure and comprises a mixture of multiple highly dielectric oxide materials.

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