Display device, method of manufacturing display device, and electronic apparatus

Abstract

A display device, a method of manufacturing the display device, and an electronic apparatus are provided. The display device includes: a first transistor disposed on a substrate and including a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer, the first semiconductor layer including a silicon semiconductor material; and a first capacitor disposed on the substrate, in which the first capacitor includes: a 1-1 electrode including a silicon semiconductor material; a 1-2 electrode overlapping the 1-1 electrode, the 1-2 electrode and the first gate electrode being disposed on the same layer and including the same material; and a 1-3 electrode overlapping the 1-2 electrode.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0110008, filed on August 16, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device and a method of manufacturing a display device, as well as an electronic device. Background Technology

[0003] Display devices visually display data. They are used as displays for small products such as mobile phones or for large products such as televisions.

[0004] Display devices include pixels that emit light by receiving electrical signals to display images to the outside. Each pixel includes a display element. For example, organic light-emitting display devices include organic light-emitting diodes (OLEDs) as display elements. Typically, in organic light-emitting display devices, thin-film transistors and OLEDs are formed on a substrate, and the OLEDs emit light themselves.

[0005] In recent years, with the diversification of applications for display devices, various designs have been developed to improve the quality of display devices. Summary of the Invention

[0006] One or more embodiments include a display device with improved reliability and quality, as well as a method and electronic device for manufacturing the display device. However, the embodiments are exemplary and do not limit the scope of this disclosure.

[0007] Additional aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practice of the embodiments.

[0008] According to one or more embodiments, a display device includes: a first transistor disposed on a substrate and including a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer, the first semiconductor layer including a silicon semiconductor material; and a first capacitor disposed on the substrate, wherein the first capacitor includes: a 1-1 electrode including a silicon semiconductor material; a 1-2 electrode overlapping the 1-1 electrode, the 1-2 electrode and the first gate electrode being disposed on the same layer and including the same material; and a 1-3 electrode overlapping the 1-2 electrode.

[0009] According to an embodiment, the 1-1 electrode of the first capacitor may be a doped layer comprising silicon semiconductor material.

[0010] According to an embodiment, the 1-1 electrode and the first semiconductor layer may be integral to each other.

[0011] According to an embodiment, electrodes 1-2 can be disposed on electrode 1-1.

[0012] According to an embodiment, electrodes 1-3 can be disposed on electrodes 1-2.

[0013] According to an embodiment, the display device may further include a second transistor disposed on a first capacitor and including a second semiconductor layer and a second gate electrode overlapping the second semiconductor layer, the second semiconductor layer comprising an oxide semiconductor material.

[0014] According to an embodiment, the display device may further include a second capacitor disposed on a substrate, wherein the second capacitor includes: an electrode 2-1; and an electrode 2-2 overlapping the electrode 2-1, and the electrode 2-1 and the first gate electrode are disposed on the same layer and comprise the same material.

[0015] According to an embodiment, electrode 2-2 can be disposed on electrode 2-1.

[0016] According to an embodiment, the second capacitor may further include an electrode 2-3 disposed below the electrode 2-1 to overlap with the electrode 2-1.

[0017] According to an embodiment, the first semiconductor layer of electrodes 2-3 and the first transistor may comprise the same material and may be disposed in the same layer.

[0018] According to an embodiment, electrodes 2-3 may comprise silicon semiconductor material.

[0019] According to an embodiment, electrodes 2-3 may be doped layers comprising silicon semiconductor material.

[0020] According to one or more embodiments, a method of manufacturing a display device includes: disposing of a first semiconductor layer forming material and a 1-1 electrode forming material of a first capacitor on a substrate, the first semiconductor layer forming material and the 1-1 electrode forming material of the first capacitor comprising a silicon semiconductor material; disposing of a barrier layer on at least a portion of the first semiconductor layer forming material; and forming a 1-1 electrode of the first capacitor by doping a 1-1 electrode forming material on which no barrier layer is disposed.

[0021] According to an embodiment, the method may further include: removing a barrier layer; forming a first gate electrode on at least a portion of the first semiconductor layer forming material; and forming a first semiconductor layer by doping at least a portion of the first semiconductor layer forming material on which the first gate electrode is not formed.

[0022] According to an embodiment, the first transistor may include a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer.

[0023] According to an embodiment, the method may further include forming a 1-2 electrode on the 1-1 electrode of the first capacitor to overlap with the 1-1 electrode.

[0024] According to an embodiment, the first gate electrode and the first capacitor's first and second electrodes can be disposed on the same layer and can comprise the same material.

[0025] According to an embodiment, the first semiconductor layer forming material and the 1-1 electrode forming material of the first capacitor can be disposed in the same layer.

[0026] According to an embodiment, the first semiconductor layer and the 1-1 electrode of the first capacitor may be integral to each other.

[0027] According to an embodiment, the method may further include forming electrodes 1-3 of the first capacitor on electrodes 1-2 of the first capacitor to overlap with electrodes 1-2.

[0028] According to one or more embodiments, an electronic device may include a display device, the display device including: a first transistor disposed on a substrate and including a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer, the first semiconductor layer including a silicon semiconductor material; and a first capacitor disposed on the substrate, wherein the first capacitor may include: a 1-1 electrode including a silicon semiconductor material; a 1-2 electrode overlapping the 1-1 electrode, the 1-2 electrode and the first gate electrode being disposed on the same layer and including the same material; and a 1-3 electrode overlapping the 1-2 electrode.

[0029] According to an embodiment, the 1-1 electrode of the first capacitor may be a doped layer comprising silicon semiconductor material.

[0030] According to an embodiment, the 1-1 electrode and the first semiconductor layer may be integral to each other.

[0031] According to an embodiment, electrodes 1-2 can be disposed on electrode 1-1.

[0032] According to an embodiment, electrodes 1-3 can be disposed on electrodes 1-2.

[0033] According to embodiments, the electronic device may be at least one of a television, monitor, billboard, Internet of Things (IoT) device, portable electronic device (including mobile phone, smartphone, tablet PC, laptop computer, mobile communication terminal, electronic notebook, e-book, portable multimedia player (PMP), navigation device, ultra-mobile personal computer (UMPC), smartwatch, watch phone, glasses display, head-mounted display (HMD)), vehicle dashboard, vehicle center console, central information display (CID) on dashboard, vehicle rearview mirror display, and display of an entertainment system on the back of the front seats in a vehicle. Attached Figure Description

[0034] The above and other aspects, features and advantages of the specific embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0035] Figure 1 This is a schematic plan view illustrating a display device according to an embodiment;

[0036] Figure 2 This is a schematic block diagram illustrating a display device according to an embodiment;

[0037] Figure 3 This is a schematic diagram illustrating, according to an embodiment, a light-emitting diode (LED) of a display element corresponding to a pixel of a display device and a pixel circuit electrically connected to the LED;

[0038] Figures 4 to 6 This is a schematic plan view showing the pixel circuitry included in the display device for each layer according to an embodiment;

[0039] Figure 7 It is along Figure 6 A schematic cross-sectional view of the display device taken along line I-I';

[0040] Figures 8 to 12 This is a schematic plan view showing the pixel circuitry included in the display device for each layer according to an embodiment;

[0041] Figure 13 This is a schematic plan view showing a barrier layer disposed on at least a portion of the semiconductor layer forming material;

[0042] Figures 14 to 17 This is a schematic cross-sectional view illustrating a method for manufacturing the sixth transistor and the first capacitor;

[0043] Figures 18 to 20 This is a schematic plan view showing the pixel circuitry included in the display device for each layer according to an embodiment;

[0044] Figure 21 It is along Figure 20 A schematic cross-sectional view of the display device taken from line III-III';

[0045] Figure 22 This is a schematic plan view showing a barrier layer disposed on at least a portion of the semiconductor layer forming material;

[0046] Figures 23 to 25 This is a schematic cross-sectional view illustrating a portion of a method for manufacturing a sixth transistor, a first capacitor, and a second capacitor; and

[0047] Figure 26 and Figure 27 This is a schematic perspective view illustrating an application example of an electronic device. Detailed Implementation

[0048] Reference will now be made in detail to embodiments illustrated in the accompanying drawings, in which the same reference numerals consistently refer to the same elements. At this point, embodiments may take different forms and should not be construed as limited to the description set forth herein. Accordingly, embodiments are described below with reference to the accompanying drawings only to explain aspects of the description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] Because this disclosure allows for various modifications and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in the detailed description. The effects and features of this disclosure, as well as methods of achieving them, will be illustrated with reference to the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below and can be embodied in various forms.

[0050] In the following description, embodiments will be described in detail with reference to the accompanying drawings, in which the same or corresponding elements are always indicated by the same reference numerals and repeated descriptions are omitted.

[0051] Although terms such as "first," "second," etc., can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0052] As used herein, the singular forms “a” and “the (said)” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0053] It will be understood that the terms “comprising,” “including,” and “having” are intended to indicate the presence of a feature or element described in the specification and are not intended to exclude the possibility that one or more other features or elements may be present or added.

[0054] It will be further understood that when a layer, area, or component is referred to as being "on" another layer, area, or component, the layer, area, or component may be directly on that other layer, area, or component, or the layer, area, or component may be indirectly on that other layer, area, or component, wherein the intermediary layer, area, or component is between the layer, area, or component and the other layer, area, or component.

[0055] For ease of explanation, the dimensions of the components in the accompanying drawings may be exaggerated or reduced. For example, because the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of explanation, the embodiments are not limited thereto.

[0056] When an embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0057] "A and / or B" is used in this document to select only A, select only B, or select both A and B. "At least one of A and B" is used to select only A, select only B, or select both A and B.

[0058] It will be understood that when a layer, area, or component is referred to as being "connected" to another layer, area, or component, that layer, area, or component may be "directly connected" to that other layer, area, or component, or that layer, area, or component may be "indirectly connected" to that other layer, area, or component, wherein the intermediary layer, area, or component is between that layer, area, or component and the other layer, area, or component. For example, when a layer, area, or component is referred to as being "electrically connected" to another layer, area, or component, that layer, area, or component may be directly electrically connected to that other layer, area, or component, or that layer, area, or component may be indirectly electrically connected to that other layer, area, or component, wherein the intermediary layer, area, or component is between that layer, area, or component and the other layer, area, or component.

[0059] The x, y, and z directions are not limited to directions corresponding to the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the x, y, and z directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0060] Figure 1 This is a schematic plan view illustrating a display device according to an embodiment.

[0061] refer to Figure 1 The display device 1 may include a display area DA for displaying an image and a non-display area NDA outside the display area DA. The display area DA may be surrounded (e.g., completely surrounded) by the non-display area NDA.

[0062] In a plan view, the display area DA can be rectangular. In another embodiment, the display area DA can be other polygonal shapes (e.g., triangular, pentagonal, or hexagonal), circular, elliptical, or irregular shapes. The display area DA can also have rounded corners.

[0063] Display device 1 can be a device for displaying moving or still images, and can be used in portable electronic devices such as laptop computers, tablet PCs, mobile phones, smartphones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, or ultra-mobile PCs (UMPCs). In another example, display device 1 can be used in electronic devices such as televisions, monitors, billboards, or Internet of Things (IoT) devices, or in wearable electronic devices such as smartwatches, smartwatch phones, glasses displays, or head-mounted displays (HMDs). For example, display device 1 according to embodiments can be used in a vehicle's dashboard, vehicle's center console, a central information display (CID) located on the vehicle's instrument panel, an interior rearview mirror display replacing the vehicle's side mirrors, or a display located on the back of the front seats for entertainment of people in the rear seats of the vehicle.

[0064] Figure 2 This is a schematic block diagram illustrating a display device according to an embodiment.

[0065] refer to Figure 1 and Figure 2 The display device 1 according to the embodiment may include a pixel unit 51, a gate driving circuit 53, a data driving circuit 55, a power supply circuit 57, and a controller 59.

[0066] Pixel unit 51 may include elements disposed in display area DA (see [reference]). Figure 1 The pixels PX in ) can be arranged in a pattern such as stripes, The image can be displayed using any of various shapes, such as a diamond arrangement or a mosaic arrangement. Each pixel PX may include a display element (e.g., a light-emitting diode), and the display element may be electrically connected to the pixel circuitry. Pixels PX can display images using light emitted from the display element corresponding to each pixel PX. Each pixel circuit may be electrically connected to a gate line GL and a data line DL, and may include multiple transistors and at least one capacitor.

[0067] In the non-display area NDA (see...) Figure 1 In the configuration file, you can set the parameters for transmitting data to be applied to the display area DA (see [reference]). Figure 1 The various conductive lines of the electrical signals, the external circuitry electrically connected to the pixel circuitry, and the pads on which printed circuit boards or driver integrated circuit (IC) chips are attached. For example, in the non-display area NDA (see... Figure 1 In this circuit, a gate drive circuit 53, a data drive circuit 55, a power supply circuit 57, and a controller 59 may be provided or configured.

[0068] The gate drive circuit 53 can be electrically connected to the gate line GL and can generate a gate signal in response to the control signal GCS from the controller 59, and can sequentially supply the gate signal to the gate line GL. The gate signal can be a gate control signal for turning on or off the transistor electrically connected to the gate line GL. The gate signal can be a square wave signal including an on-state voltage for turning on the transistor and an off-state voltage for turning off the transistor. In an embodiment, the on-state voltage can be a high-level voltage (or a first-level voltage) or a low-level voltage (or a second-level voltage).

[0069] Despite Figure 2 The pixel circuit corresponding to one pixel PX is connected to one gate line GL, but this is just an example. The pixel circuit corresponding to one pixel PX can be connected to two or more gate lines, and the gate drive circuit 53 can supply two or more gate signals with different timings for applying a turn-on voltage to the gate lines. For example, the pixel circuit can be connected to the first through fifth gate lines, and the gate drive circuit 53 can apply a first gate signal GW, a second gate signal GR, a third gate signal EM, a fourth gate signal GB, and a fifth gate signal EMB to the first, second, third, fourth, and fifth gate lines, respectively. The third gate signal EM can be an emitter control signal used to turn on or off a transistor having a gate connected to the third gate line.

[0070] The data drive circuit 55 can be connected to the data line DL and can supply the data signal DATA to the data line DL in response to the control signal DCS from the controller 59. The data signal DATA supplied to the data line DL can be supplied to the pixel circuit. The data drive circuit 55 can convert the grayscale input image data input from the controller 59 into a data signal DATA in the form of voltage or current.

[0071] Power supply circuit 57 can generate the voltage required to drive pixel PX in response to control signal PCS from controller 59. Power supply circuit 57 can generate a drive voltage ELVDD and a common voltage ELVSS, and can supply the drive voltage ELVDD and the common voltage ELVSS to pixel PX. The drive voltage ELVDD can be a high-level voltage provided to a first electrode (e.g., pixel electrode or anode) of the display element included in pixel PX. The common voltage ELVSS can be a low-level voltage provided to a second electrode (e.g., counter electrode or cathode) of the display element included in pixel PX. Power supply circuit 57 can generate a reference voltage Vref, a first initialization voltage Vaint, and a second initialization voltage Vint, and can supply the reference voltage Vref, the first initialization voltage Vaint, and the second initialization voltage Vint to pixel PX.

[0072] The driving voltage ELVDD can be higher than the common voltage ELVSS. The reference voltage Vref can be lower than the driving voltage ELVDD. The first initialization voltage Vaint can be higher than the second initialization voltage Vint. The second initialization voltage Vint can be lower than the common voltage ELVSS. The first initialization voltage Vaint can be equal to or higher than the common voltage ELVSS.

[0073] The controller 59 can generate control signals GCS, DCS, and PCS based on signals input from an external source, and can supply the control signals GCS, DCS, and PCS to the gate drive circuit 53, the data drive circuit 55, and the power supply circuit 57, respectively. The control signal GCS output to the gate drive circuit 53 may include a clock signal and a gate start signal. The control signal DCS output to the data drive circuit 55 may include a source start signal and a clock signal.

[0074] Figure 3 This is a schematic diagram illustrating, according to an embodiment, a light-emitting diode (LED) of a display element corresponding to a pixel of a display device and a pixel circuit electrically connected to the LED.

[0075] refer to Figure 3 Some of the transistors in the pixel circuit PC may be N-type transistors, and the others may be P-type transistors. The first to fourth transistors T1, T2, T3, and T4 may be N-type transistors, and the fifth transistor T5 and the sixth transistor T6 may be P-type transistors. The semiconductor layers of the first to fourth transistors T1, T2, T3, and T4 may contain materials different from those of the semiconductor layers of the fifth transistor T5 and the sixth transistor T6. In some embodiments, the semiconductor layers of the first to fourth transistors T1, T2, T3, and T4 may contain oxides, and the semiconductor layers of the fifth transistor T5 and the sixth transistor T6 may contain amorphous silicon, polycrystalline silicon, or organic semiconductors.

[0076] The pixel circuit PC can be electrically connected to the first gate line GWL for transmitting the first gate signal GW, the second gate line GRL for transmitting the second gate signal GR, the third gate line EML for transmitting the third gate signal EM, the fourth gate line GBL for transmitting the fourth gate signal GB, the fifth gate line EMBL for transmitting the fifth gate signal EMB, and the data line DL for transmitting the data signal DATA. Because the light emission of the LED is controlled by the third gate signal EM and the fifth gate signal EMB, the third gate signal EM and the fifth gate signal EMB can be emission control signals, and the third gate line EML and the fifth gate line EMBL can be emission control lines. For example, the pixel circuit PC may include the driving voltage line PL for transmitting the driving voltage ELVDD, the reference voltage line VRL for transmitting the reference voltage Vref, and the first initialization voltage line VAL for transmitting the first initialization voltage Vaint.

[0077] In an embodiment, the transistor included in the pixel circuit PC may be an N-type oxide transistor. An oxide transistor may be a transistor in which the semiconductor layer comprises an oxide layer. However, this is an example, and the transistors disclosed herein are not limited thereto. For example, the semiconductor layer included in an N-type transistor may comprise an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon) or an organic semiconductor.

[0078] The pixel circuit PC may include first to sixth transistors T1, T2, T3, T4, T5, and T6, a first capacitor C1, a second capacitor C2, and an auxiliary capacitor Ca. The first transistor T1 may be a driving transistor that outputs a driving current corresponding to the data signal DATA, and the second to sixth transistors T2, T3, T4, T5, and T6 may be switching transistors that transmit signals. Depending on the voltage at the first terminal (or first electrode) and the second terminal (or second electrode) of each of the first to sixth transistors T1, T2, T3, T4, T5, and T6, the first terminal and the second terminal may be sources (or source electrodes) or drains (or drain electrodes). For example, depending on the voltage at the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or vice versa. In the following, the node to which the 1-1 gate electrode of the first transistor T1 is connected may be defined as a first node N1, and the node to which the second terminal of the first transistor T1 is connected may be defined as a second node N2.

[0079] The first transistor T1 can be connected between the driving voltage line PL and the light-emitting diode (LED). The first transistor T1 can be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may include a first gate (or first gate electrode), a first terminal, and a second terminal connected to the second node N2. The first transistor T1 may include a 1-1 gate connected to the first node N1. The first transistor T1 may further include a 1-2 gate connected to the second terminal of the first transistor T1. The 1-1 gate and the 1-2 gate can be disposed on different layers facing each other. For example, the 1-1 gate and the 1-2 gate of the first transistor T1 can face each other, with a semiconductor layer between the 1-1 gate and the 1-2 gate. In the description, the first gate (or first gate electrode) of the first transistor T1 may refer to the 1-1 gate (or 1-1 gate electrode) involved in the conduction and cutoff of the first transistor T1.

[0080] The first gate (or 1-1 gate) of the first transistor T1 can be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the second capacitor C2. The 1-2 gate of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 can be connected to the drive voltage line PL via the fifth transistor T5, and the second terminal of the first transistor T1 can be connected to the pixel electrode of the light-emitting diode (LED) via the sixth transistor T6. The first terminal of the first transistor T1 can be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 can receive the data signal DATA according to the switching operation of the second transistor T2, and can control the amount of drive current flowing to the LED.

[0081] The second transistor T2 can be connected to the data line DL and the first gate of the first transistor T1. The second transistor T2 may include a second gate (or second gate electrode) connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 can be connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the second capacitor C2. The second transistor T2 can be turned on according to the first gate signal GW transmitted through the first gate line GWL to electrically connect the data line DL to the first node N1, and can transmit the data signal DATA received through the data line DL to the first node N1.

[0082] The third transistor T3 can be connected to the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a third gate (or third gate electrode) connected to the second gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 can be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the second capacitor C2. The third transistor T3 can be turned on according to the second gate signal GR transmitted through the second gate line GRL to transmit the reference voltage Vref received through the reference voltage line VRL to the first node N1.

[0083] A fourth transistor T4 can be connected to the second terminal of the sixth transistor T6 and the first initialization voltage line VAL. The fourth transistor T4 can be connected between the light-emitting diode (LED) and the first initialization voltage line VAL. The fourth transistor T4 may include a fourth gate (or fourth gate electrode) connected to the fourth gate line GBL, a first terminal connected to the third node N3, and a second terminal connected to the first initialization voltage line VAL. The first terminal of the fourth transistor T4 can be connected to the second terminal of the sixth transistor T6 and the pixel electrode of the LED. The fourth transistor T4 can be turned on according to the fourth gate signal GB transmitted through the fourth gate line GBL to transmit the first initialization voltage Vaint received through the first initialization voltage line VAL to the third node N3, thereby initializing the pixel electrode (e.g., the anode) of the LED.

[0084] The fifth transistor T5 can be connected to the drive voltage line PL and the first terminal of the first transistor T1. The fifth transistor T5 may include a fifth gate (or fifth gate electrode) connected to the third gate line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or off according to the third gate signal EM transmitted through the third gate line EML.

[0085] The sixth transistor T6 can be connected to the second terminal of the first transistor T1 and the pixel electrode of the light-emitting diode (LED). The sixth transistor T6 can be connected between the second node N2 and the third node N3. The sixth transistor T6 may include a sixth gate (or sixth gate electrode) connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 can be connected to the second terminal of the first transistor T1, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 can be connected to the first terminal of the fourth transistor T4 and the pixel electrode of the LED. The sixth transistor T6 can be turned on or off according to the fifth gate signal EMB transmitted through the fifth gate line EMBL.

[0086] The second capacitor C2 can be connected between the first gate of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the second capacitor C2 can be connected to the first node N1, and the second electrode of the second capacitor C2 can be connected to the second node N2. The first electrode of the second capacitor C2 can be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the second capacitor C2 can be connected to the second terminal and gate 1-2 of the first transistor T1, the second electrode of the first capacitor C1, and the first terminal of the sixth transistor T6. The second capacitor C2 can be a storage capacitor and can store a voltage corresponding to the data signal DATA and the threshold voltage of the second transistor T2.

[0087] With the third transistor T3 and the fifth transistor T5 turned on, the first transistor T1 can be turned on. When the voltage at the second terminal of the first transistor T1 drops to the difference (Vref-Vth1) between the reference voltage Vref and the threshold voltage (Vth1) of the first transistor T1, the first transistor T1 can be turned off, and the voltage corresponding to the threshold voltage (Vth1) of the first transistor T1 can be stored in the second capacitor C2, so that the threshold voltage (Vth1) of the first transistor T1 can be compensated.

[0088] The first capacitor C1 can be connected between the drive voltage line PL and the second node N2. The first electrode of the first capacitor C1 can be connected to the drive voltage line PL. The second electrode of the first capacitor C1 can be connected to the second terminal and gate 1-2 of the first transistor T1, the second electrode of the second capacitor C2, and the first terminal of the sixth transistor T6.

[0089] The capacitance of the first capacitor C1 and the second capacitor C2 can vary according to the color of the light emitted by the light-emitting diode (LED).

[0090] The auxiliary capacitor Ca can be electrically connected to the second terminal of the sixth transistor T6, the sustaining voltage line VSSL, and the pixel electrode of the light-emitting diode (LED). The auxiliary capacitor Ca can store and maintain a voltage corresponding to the voltage difference between the pixel electrode of the LED and the sustaining voltage line VSSL, thereby preventing the black brightness from increasing when the sixth transistor T6 is turned off.

[0091] A light-emitting diode (LED) can be connected to a first transistor T1 via a sixth transistor T6. The LED may include a pixel electrode (e.g., anode) connected to a third node N3 and a counter electrode (e.g., cathode) facing the pixel electrode, and the counter electrode may receive a common voltage ELVSS. In an embodiment, the counter electrode (e.g., cathode) may extend to the non-display area NDA (see [link to documentation]). Figure 1 It can be electrically connected to the sustaining voltage line VSSL that provides the common voltage ELVSS. Due to the conduction of the fifth transistor T5 and the sixth transistor T6, the drive current output by the first transistor T1 can flow through the light-emitting diode LED, and the light-emitting diode LED can emit light with a brightness corresponding to the magnitude of the drive current.

[0092] Figures 4 to 6 This is a schematic plan view showing the pixel circuitry included in the display device for each layer according to an embodiment. Figure 7 It is along Figure 6 A schematic cross-sectional view of the display device taken from line I-I'.

[0093] refer to Figure 4 The fifth semiconductor layer A5, the sixth semiconductor layer A6, and the first capacitor C1 (see...) Figure 6 Electrode C11 of 1-1 can be disposed on substrate 100 (see...) Figure 7 For example, the fifth semiconductor layer A5, the sixth semiconductor layer A6, and the 1-1 electrode C11 of the first capacitor C1 can be disposed on the same layer. The fifth semiconductor layer A5, the sixth semiconductor layer A6, and the 1-1 electrode C11 of the first capacitor C1 can include the same material. For example, the fifth semiconductor layer A5, the sixth semiconductor layer A6, and the 1-1 electrode C11 of the first capacitor C1 can include silicon semiconductor material. For example, the fifth semiconductor layer A5, the sixth semiconductor layer A6, and the 1-1 electrode C11 of the first capacitor C1 can include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In another embodiment, the fifth semiconductor layer A5, the sixth semiconductor layer A6, and the 1-1 electrode C11 of the first capacitor C1 can include polycrystalline silicon or amorphous silicon.

[0094] The sixth semiconductor layer A6 and the 1-1 electrode C11 of the first capacitor C1 can be integrally formed with each other (or may be integral with each other). For example, the sixth semiconductor layer A6 and the 1-1 electrode C11 of the first capacitor C1 can be integrally connected with each other. The fifth semiconductor layer A5 can be disposed adjacent to the sixth semiconductor layer A6 and the 1-1 electrode C11 of the first capacitor C1, but can be separated from and spaced apart from the sixth semiconductor layer A6 and the 1-1 electrode C11 of the first capacitor C1.

[0095] refer to Figure 5 The fifth gate electrode G5, the sixth gate electrode G6, the first conductive layer 111, the driving voltage line PL, the third gate line EML, the fifth gate line EMBL, the first capacitor C1's first and second electrodes C12, and the second capacitor C2 (see...). Figure 6 The 2-1 electrode C21 of the first capacitor C1 can be disposed on the fifth semiconductor layer A5, the sixth semiconductor layer A6, and the 1-1 electrode C11 of the first capacitor C1. The first conductive layer 111 can have an isolated shape. The drive voltage line PL, the third gate line EML, and the fifth gate line EMBL can extend in a first direction (e.g., the positive x direction or the negative x direction).

[0096] The fifth gate electrode G5, the sixth gate electrode G6, the first conductive layer 111, the driving voltage line PL, the third gate line EML, the fifth gate line EMBL, the 1-2 electrode C12 of the first capacitor C1, and the 2-1 electrode C21 of the second capacitor C2 may be made of the same material. For example, the fifth gate electrode G5, the sixth gate electrode G6, the first conductive layer 111, the driving voltage line PL, the third gate line EML, the fifth gate line EMBL, the 1-2 electrode C12 of the first capacitor C1, and the 2-1 electrode C21 of the second capacitor C2 may be made of molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure comprising the above materials.

[0097] The driving voltage line PL may include electrode C12 (1-2) of the first capacitor C1. Electrode C12 (1-2) of the first capacitor C1 may be part of the driving voltage line PL. For example, the driving voltage line PL and electrode C12 (1-2) of the first capacitor C1 may be integrally formed with each other (or may be integral with each other). Electrode C12 (1-2) of the first capacitor C1 may overlap with electrode C11 (1-1) of the first capacitor C1.

[0098] The first conductive layer 111 may include the 2-1 electrode C21 of the second capacitor C2. The 2-1 electrode C21 of the second capacitor C2 may be a part of the first conductive layer 111. For example, the first conductive layer 111 and the 2-1 electrode C21 of the second capacitor C2 may be integrally formed with each other (or may be integral with each other).

[0099] The third gate line EML may include a fifth gate electrode G5 that overlaps with the channel region CH5 of the fifth transistor T5. (Reference) Figure 4 The fifth semiconductor layer A5 described may include a channel region CH5 overlapping with the fifth gate electrode G5, a source region S5 disposed on one side of the channel region CH5, and a drain region D5 disposed on the other side of the channel region CH5.

[0100] The fifth gate line EMBL may include a sixth gate electrode G6 that overlaps with the channel region CH6 of the sixth transistor T6. (See reference) Figure 4 The sixth semiconductor layer A6 described may include a channel region CH6 overlapping with the sixth gate electrode G6, a source region S6 disposed on one side of the channel region CH6, and a drain region D6 disposed on the other side of the channel region CH6.

[0101] The fifth gate line EMBL can be disposed relatively far from the first conductive layer 111. In some embodiments, the drive voltage line PL and the third gate line EML can be disposed between the first conductive layer 111 and the fifth gate line EMBL.

[0102] refer to Figure 6 The reference voltage line VRL, the second conductive layer 112, the 1-3 electrode C13 of the first capacitor C1 and the 2-2 electrode C22 of the second capacitor C2 can be disposed on the fifth gate electrode G5, the sixth gate electrode G6, the first conductive layer 111, the driving voltage line PL, the third gate line EML, the fifth gate line EMBL, the 1-2 electrode C12 of the first capacitor C1 and the 2-1 electrode C21 of the second capacitor C2.

[0103] The second conductive layer 112 may have an isolated shape. The reference voltage line VRL may extend in a first direction (e.g., the positive x-direction or the negative x-direction).

[0104] The second conductive layer 112 may include the 1-3 electrodes C13 of the first capacitor C1. The 1-3 electrodes C13 of the first capacitor C1 may be part of the second conductive layer 112. For example, the second conductive layer 112 and the 1-3 electrodes C13 of the first capacitor C1 may be integrally formed with each other (or may be integral with each other). The 1-3 electrodes C13 of the first capacitor C1 may overlap with the 1-1 electrode C11 and the 1-2 electrode C12. The first capacitor C1 may include the 1-1 electrode C11, the 1-2 electrode C12, and the 1-3 electrode C13.

[0105] The second conductive layer 112 may include the 2-2 electrode C22 of the second capacitor C2. The 2-2 electrode C22 of the second capacitor C2 may be a part of the second conductive layer 112. For example, the second conductive layer 112 and the 2-2 electrode C22 of the second capacitor C2 may be integrally formed with each other (or may be integral with each other). The 2-2 electrode C22 of the second capacitor C2 may overlap with the 2-1 electrode C21. The second capacitor C2 may include the 2-1 electrode C21 and the 2-2 electrode C22.

[0106] refer to Figure 7 The sixth transistor T6 and the first capacitor C1 can be disposed on the substrate 100. The sixth transistor T6 may include a sixth gate electrode G6 and a sixth semiconductor layer A6 comprising silicon semiconductor material. The sixth semiconductor layer A6 may include a source region S6, a channel region CH6, and a drain region D6.

[0107] The first capacitor C1 may include electrode C11 (1-1), electrode C12 (1-2), and electrode C13 (1-3). Electrodes C11, C12, and C13 may overlap each other. Electrode C12 (1-2) may be disposed on top of electrode C11 (1-1) to overlap with it. Electrode C13 (1-3) may be disposed on top of electrode C12 (1-2) to overlap with it.

[0108] The 1-1 electrode C11 of the first capacitor C1 may comprise a silicon semiconductor material. For example, the 1-1 electrode C11 of the first capacitor C1 may be a doped layer comprising a silicon semiconductor material. The 1-1 electrode C11 of the first capacitor C1 and the sixth semiconductor layer A6 of the sixth transistor T6 may be integrally connected to each other. For example, the 1-1 electrode C11 of the first capacitor C1 and the sixth semiconductor layer A6 of the sixth transistor T6 may be integrally formed with each other (or may be integral with each other).

[0109] The first capacitor C1's first electrode C12 and the sixth transistor T6's sixth gate electrode G6 can be disposed on the same layer. The first capacitor C1's first electrode C12 and the sixth transistor T6's sixth gate electrode G6 can be made of the same material.

[0110] In one embodiment, a second capacitor C2 may be disposed on the substrate 100. The second capacitor C2 may include a 2-1 electrode C21 and a 2-2 electrode C22. The 2-1 electrode C21 and the 2-2 electrode C22 may overlap each other. The 2-2 electrode C22 may be disposed on top of the 2-1 electrode C21 to overlap with the 2-1 electrode C21.

[0111] The second capacitor C2's electrode C21 and the sixth transistor T6's gate electrode G6 can be disposed on the same layer. The second capacitor C2's electrode C21 and the sixth transistor T6's gate electrode G6 can be made of the same material.

[0112] In the comparative example, where the two electrodes of the first capacitor are formed by two metal layers disposed on a semiconductor layer, the size of the first capacitor is limited by increasing the number of pixels per unit area to improve the brightness of the display device.

[0113] In an embodiment, the first capacitor C1 may include a doped layer comprising a silicon semiconductor material serving as electrodes, and therefore, the first capacitor C1 may include three electrodes. Because the first capacitor C1 includes a doped layer and two metal layers disposed on the doped layer as three electrodes, the capacitance of the capacitor for the pixel circuit can be unlimited as the number of pixels per unit area of ​​the display device increases, and therefore, the brightness and reliability of the display device can be improved.

[0114] Figures 8 to 12 This is a schematic plan view showing the pixel circuitry included in the display device for each layer according to an embodiment.

[0115] refer to Figure 8 The first semiconductor layer A1, the second semiconductor layer A2, the third semiconductor layer A3, and the fourth semiconductor layer A4 can be disposed on the substrate 100 (see [reference]). Figure 7 On the same layer, for example, the first semiconductor layer A1, the second semiconductor layer A2, the third semiconductor layer A3, and the fourth semiconductor layer A4 can be disposed on the same layer. The first semiconductor layer A1, the second semiconductor layer A2, the third semiconductor layer A3, and the fourth semiconductor layer A4 can include the same material. For example, the first semiconductor layer A1, the second semiconductor layer A2, the third semiconductor layer A3, and the fourth semiconductor layer A4 can be formed of zinc (Zn) oxide materials such as zinc (Zn) oxide, indium (In)-zinc (Zn) oxide, or gallium (Ga)-indium (In)-zinc (Zn) oxide. In another example, the first semiconductor layer A1, the second semiconductor layer A2, the third semiconductor layer A3, and the fourth semiconductor layer A4 can be formed of indium gallium zinc oxide (IGZO) semiconductor that includes metals such as indium (In) and gallium (Ga) in ZnO.

[0116] The second semiconductor layer A2 and the third semiconductor layer A3 can be integrally formed with each other (or can be integral with each other). For example, the second semiconductor layer A2 and the third semiconductor layer A3 can be integrally connected with each other.

[0117] The first semiconductor layer A1 may be disposed adjacent to the second semiconductor layer A2 and the third semiconductor layer A3, but may be separated from and spaced apart from the second semiconductor layer A2 and the third semiconductor layer A3. The first semiconductor layer A1 may have an isolated shape.

[0118] The fourth semiconductor layer A4 may be disposed adjacent to the first semiconductor layer A1, but may be separated from and spaced apart from the first semiconductor layer A1. The fourth semiconductor layer A4 may have an isolated shape.

[0119] refer to Figure 9 The second gate line GRL, the fourth gate line GBL, the third conductive layer 113, and the fourth conductive layer 114 can be disposed on the first to fourth semiconductor layers A1, A2, A3, and A4. Each of the third conductive layer 113 and the fourth conductive layer 114 can have an isolated shape. The second gate line GRL and the fourth gate line GBL can extend in a first direction (e.g., the positive x-direction or the negative x-direction).

[0120] The second gate line GRL, the fourth gate line GBL, the third conductive layer 113, and the fourth conductive layer 114 may comprise the same material. For example, the second gate line GRL, the fourth gate line GBL, the third conductive layer 113, and the fourth conductive layer 114 may comprise molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure comprising the aforementioned materials.

[0121] The second gate line GRL may include a third gate electrode G3 that overlaps with the channel region CH3 of the third transistor T3. (See reference) Figure 8 The described third semiconductor layer A3 may include a channel region CH3 overlapping with the third gate electrode G3, a source region S3 disposed on one side of the channel region CH3, and a drain region D3 disposed on the other side of the channel region CH3.

[0122] The third conductive layer 113 may include a second gate electrode G2 that overlaps with the channel region CH2 of the second transistor T2. (See reference) Figure 8 The second semiconductor layer A2 described may include a channel region CH2 overlapping with the second gate electrode G2, a source region S2 disposed on one side of the channel region CH2, and a drain region D2 disposed on the other side of the channel region CH2.

[0123] The fourth conductive layer 114 may include a first gate electrode G1 that overlaps with the channel region CH1 of the first transistor T1. (See reference...) Figure 8 The first semiconductor layer A1 described may include a channel region CH1 overlapping with the first gate electrode G1, a source region S1 disposed on one side of the channel region CH1, and a drain region D1 disposed on the other side of the channel region CH1.

[0124] The fourth gate line GBL may include a fourth gate electrode G4 that overlaps with the channel region CH4 of the fourth transistor T4. (See reference...) Figure 8 The fourth semiconductor layer A4 described may include a channel region CH4 overlapping with the fourth gate electrode G4, a source region S4 disposed on one side of the channel region CH4, and a drain region D4 disposed on the other side of the channel region CH4.

[0125] The second gate line GRL and the fourth gate line GBL can be disposed relatively far from each other. In some embodiments, the third conductive layer 113 and the fourth conductive layer 114 can be disposed between the second gate line GRL and the fourth gate line GBL.

[0126] For example, a transistor comprising a semiconductor layer containing an oxide semiconductor material and a gate electrode overlapping the semiconductor layer can be disposed on the first capacitor C1. For example, a transistor comprising a semiconductor layer containing an oxide semiconductor material and a gate electrode overlapping the semiconductor layer can be disposed on the second capacitor C2.

[0127] refer to Figure 10 The first to eighth connecting electrodes 201, 202, 203, 204, 205, 206, 207 and 208, the first gate line GWL, and the first initialization voltage line VAL can be disposed on the second gate line GRL, the fourth gate line GBL, the third conductive layer 113 and the fourth conductive layer 114. The first gate line GWL and the first initialization voltage line VAL can extend in a first direction (e.g., the positive x direction or the negative x direction). Each of the first to eighth connecting electrodes 201, 202, 203, 204, 205, 206, 207 and 208 can have an isolated shape.

[0128] The first to eighth connecting electrodes 201, 202, 203, 204, 205, 206, 207 and 208, the first gate line GWL, and the first initialization voltage line VAL may comprise the same material. For example, the first to eighth connecting electrodes 201, 202, 203, 204, 205, 206, 207 and 208, the first gate line GWL, and the first initialization voltage line VAL may comprise molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure comprising the aforementioned materials.

[0129] The first connection electrode 201 can electrically connect the source region S3 of the third transistor T3 to the reference voltage line VRL. The first connection electrode 201 can be connected to the source region S3 of the third transistor T3 through a contact hole 11 passing through at least one insulating layer disposed between the first connection electrode 201 and the source region S3 of the third semiconductor layer A3 of the third transistor T3. The first connection electrode 201 can be connected to the reference voltage line VRL through a contact hole 21 passing through at least one insulating layer disposed between the first connection electrode 201 and the reference voltage line VRL.

[0130] The second connection electrode 202 can be connected to the drain region D2 of the second transistor T2 through a contact hole 12 passing through at least one insulating layer disposed between the second connection electrode 202 and the drain region D2 of the second semiconductor layer A2 of the second transistor T2.

[0131] The third connection electrode 203 can be connected to the source region S2 of the second transistor T2 through a contact hole 14 passing through at least one insulating layer between the third connection electrode 203 and the source region S2 of the second transistor T2. The third connection electrode 203 can be connected to the drain region D3 of the third transistor T3 through a contact hole 14 passing through at least one insulating layer between the third connection electrode 203 and the drain region D3 of the third transistor T3. The third connection electrode 203 can be connected to the first conductive layer 111 through a contact hole 22 passing through at least one insulating layer between the third connection electrode 203 and the first conductive layer 111. The third connection electrode 203 can be connected to the fourth conductive layer 114 through a contact hole 15 passing through at least one insulating layer between the third connection electrode 203 and the fourth conductive layer 114.

[0132] The fourth connection electrode 204 can be connected to the source region S6 of the sixth transistor T6 through a contact hole 24 passing through at least one insulating layer between the fourth connection electrode 204 and the source region S6 of the sixth transistor T6. The fourth connection electrode 204 can be connected to the source region S1 of the first transistor T1 through a contact hole 16 passing through at least one insulating layer between the fourth connection electrode 204 and the source region S1 of the first transistor T1. The fourth connection electrode 204 can be connected to the second conductive layer 112 through a contact hole 23 passing through at least one insulating layer between the fourth connection electrode 204 and the second conductive layer 112.

[0133] The fifth connection electrode 205 can be connected to the drain region D1 of the first transistor T1 through a contact hole 17 that passes through at least one insulating layer between the fifth connection electrode 205 and the drain region D1 of the first transistor T1. The fifth connection electrode 205 can be connected to the source region S5 of the fifth transistor T5 through a contact hole 25 that passes through at least one insulating layer between the fifth connection electrode 205 and the source region S5 of the fifth transistor T5.

[0134] The sixth connection electrode 206 can be connected to the drain region D6 of the sixth transistor T6 through a contact hole 26 passing through at least one insulating layer between the sixth connection electrode 206 and the drain region D6 of the sixth transistor T6. The sixth connection electrode 206 can be connected to the source region S4 of the fourth transistor T4 through a contact hole 18 passing through at least one insulating layer between the sixth connection electrode 206 and the source region S4 of the fourth transistor T4.

[0135] The seventh connecting electrode 207 can be connected to the reference voltage line VRL through a contact hole 29 that passes through at least one insulating layer disposed between the seventh connecting electrode 207 and the reference voltage line VRL.

[0136] The eighth connection electrode 208 can be connected to the drive voltage line PL through a contact hole 27 passing through at least one insulating layer disposed between the eighth connection electrode 208 and the drive voltage line PL. The eighth connection electrode 208 can be connected to the drain region D5 of the fifth transistor T5 through a contact hole 28 passing through at least one insulating layer disposed between the eighth connection electrode 208 and the drain region D5 of the fifth transistor T5.

[0137] The first gate line GWL and the third conductive layer 113 can be electrically connected to each other. The first gate line GWL can be connected to the third conductive layer 113 through a contact hole 13 that passes through at least one insulating layer disposed between the first gate line GWL and the third conductive layer 113.

[0138] The first initialization voltage line VAL can be electrically connected to the drain region D4 of the fourth transistor T4. The first initialization voltage line VAL can be connected to the drain region D4 of the fourth transistor T4 through a contact hole 19 passing through at least one insulating layer disposed between the first initialization voltage line VAL and the drain region D4 of the fourth transistor T4.

[0139] refer to Figure 11 The first data line DL1, the second data line DL2, the reference voltage line VRL, and the ninth connection electrode 209 can be disposed on the first to eighth connection electrodes 201, 202, 203, 204, 205, 206, 207, and 208, the first gate line GWL, and the first initialization voltage line VAL. The first data line DL1, the second data line DL2, and the reference voltage line VRL can extend in a second direction (e.g., the positive y-direction or the negative y-direction). The ninth connection electrode 209 can have an isolated shape.

[0140] The second data line DL2 can be connected to the second conductive layer 112 through a contact hole 31 that passes through at least one insulating layer disposed between the second data line DL2 and the second conductive layer 112.

[0141] The reference voltage line VRL can be connected to the seventh connection electrode 207 through a contact hole 32 that passes through at least one insulating layer disposed between the reference voltage line VRL and the seventh connection electrode 207.

[0142] The ninth connecting electrode 209 can be connected to the sixth connecting electrode 206 through a contact hole 33 that passes through at least one insulating layer disposed between the ninth connecting electrode 209 and the sixth connecting electrode 206.

[0143] refer to Figure 12 The first to sixth transistors T1, T2, T3, T4, T5 and T6 in the pixel circuit, the first capacitor C1 and the second capacitor C2 can be disposed on the substrate 100. Figure 12 It is a schematic plan view showing a fifth transistor T5 and a sixth transistor T6 made of silicon semiconductor material, a first to a fourth transistor T1, T2, T3 and T4 made of oxide semiconductor material, a first capacitor C1 and a second capacitor C2.

[0144] Figure 13 This is a schematic plan view showing a barrier layer disposed on at least a portion of the semiconductor layer forming material. Figures 14 to 17 This is a schematic cross-sectional view illustrating a method for manufacturing the sixth transistor and the first capacitor. For example, Figure 14 It is along Figure 13 A schematic cross-sectional view of the display device taken from line II-II'.

[0145] refer to Figure 13 and Figure 14 The first capacitor C1's 1-1 electrode forming material C11s and the sixth semiconductor layer forming material A6s, both made of silicon semiconductor material, can be disposed on the same layer on the substrate 100. The first capacitor C1's 1-1 electrode forming material C11s and the sixth semiconductor layer forming material A6s can be integrally formed with each other (or may be integral with each other). The first capacitor C1's 1-1 electrode forming material C11s and the sixth semiconductor layer forming material A6s can include oxides of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In another embodiment, the first capacitor C1's 1-1 electrode forming material C11s and the sixth semiconductor layer forming material A6s can include polycrystalline silicon or amorphous silicon.

[0146] The barrier layer BL may be disposed on at least a portion of the sixth semiconductor layer forming material A6s. The barrier layer BL may comprise the same material as the photoresist used in the general process of manufacturing a display device. However, the embodiments are not limited thereto.

[0147] refer to Figure 15 The barrier layer BL may not be disposed on the 1-1 electrode forming material C11s of the first capacitor C1. The 1-1 electrode C11 of the first capacitor C1 can be formed by doping the 1-1 electrode forming material C11s of the first capacitor C1 without the barrier layer BL disposed thereon. After the process of doping the 1-1 electrode forming material C11s of the first capacitor C1, the barrier layer BL can be removed.

[0148] refer to Figure 16 The sixth gate electrode G6 can be formed on at least a portion of the sixth semiconductor layer forming material A6s. The 1-2 electrode C12 can be formed above the 1-1 electrode C11 of the first capacitor C1 to overlap with the 1-1 electrode C11. The 1-2 electrode C12 of the first capacitor C1 and the sixth gate electrode G6 of the sixth transistor T6 can be disposed in the same layer and can comprise the same material. The 1-2 electrode C12 of the first capacitor C1 can be formed simultaneously with the sixth gate electrode G6 of the sixth transistor T6. For example, the 1-2 electrode C12 of the first capacitor C1 and the sixth gate electrode G6 of the sixth transistor T6 can comprise molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single-layer structure or a multi-layer structure comprising the aforementioned materials.

[0149] The sixth gate electrode G6 may not be disposed on at least a portion of the sixth semiconductor layer forming material A6s. The sixth semiconductor layer A6 can be formed by doping the portion of the sixth semiconductor layer forming material A6s on which the sixth gate electrode G6 is not disposed. For example, the doped portion of the sixth semiconductor layer forming material A6s may be the source region S6 and the drain region D6, and the undoped portion of the sixth semiconductor layer forming material A6s overlapping with the sixth gate electrode G6 may be the channel region CH6. The sixth semiconductor layer A6 may include the source region S6, the channel region CH6, and the drain region D6. The sixth transistor T6 may include the sixth semiconductor layer A6 and the sixth gate electrode G6 overlapping with the sixth semiconductor layer A6.

[0150] refer to Figure 17 Electrode C13 (1-3) can be formed on top of electrode C12 (1-2) of the first capacitor C1 to overlap with electrode C12 (1-2). The first capacitor C1 may include electrode C11 (1-1), electrode C12 (1-2), and electrode C13 (1-3) that overlap each other.

[0151] In the comparative example, where no doping process follows the placement of the barrier layer BL on at least a portion of the sixth semiconductor layer forming material A6s, doping occurs because of the doping on the sixth gate electrode G6 and the third gate line EML (see...). Figure 5 ) and drive voltage line PL (see Figure 5The formation is performed after the sixth semiconductor layer is formed on the forming material A6s, so the portion of the sixth semiconductor layer A6 that overlaps with the sixth gate electrode G6, the third gate line EML and the drive voltage line PL can be an undoped channel region, and therefore, any part of the layer including the sixth semiconductor layer A6 cannot be used as wiring.

[0152] In an embodiment, before the sixth gate electrode G6 is formed on at least a portion of the sixth semiconductor layer forming material A6s and doping is performed, a barrier layer BL can be formed on at least a portion of the sixth semiconductor layer forming material A6s, and then doping can be performed to form the 1-1 electrode C11 of the first capacitor C1. Because the 1-1 electrode forming material C11s is doped after the barrier layer BL is formed on at least a portion of the sixth semiconductor layer forming material A6s, the 1-1 electrode C11 of the first capacitor C1, integrally formed (or integrally formed) with the sixth semiconductor layer A6, can be formed. Because the first capacitor C1 includes three electrodes (which include a doped layer containing silicon semiconductor material and two metal layers on the doped layer), the capacitance of the capacitor for the pixel circuit can be unlimited as the number of pixels per unit area of ​​the display device increases, thereby improving the brightness and reliability of the display device.

[0153] Figures 18 to 20 This is a schematic plan view showing the pixel circuitry included in the display device for each layer according to an embodiment. Figure 21 It is along Figure 20 A schematic cross-sectional view of the display device taken from line III-III'.

[0154] refer to Figure 18 Fifth semiconductor layer A5, sixth semiconductor layer A6, first capacitor C1 (see...) Figure 20 Electrode C11 and capacitor C2 (see ) Figure 20 Electrodes C23 2-3 can be disposed on substrate 100 (see Figure 21For example, the fifth semiconductor layer A5, the sixth semiconductor layer A6, the 1-1 electrode C11 of the first capacitor C1, and the 2-3 electrode C23 of the second capacitor C2 can be disposed on the same layer. The fifth semiconductor layer A5, the sixth semiconductor layer A6, the 1-1 electrode C11 of the first capacitor C1, and the 2-3 electrode C23 of the second capacitor C2 can all be made of the same material. For example, the fifth semiconductor layer A5, the sixth semiconductor layer A6, the 1-1 electrode C11 of the first capacitor C1, and the 2-3 electrode C23 of the second capacitor C2 can all be made of silicon semiconductor material. For example, the fifth semiconductor layer A5, the sixth semiconductor layer A6, the 1-1 electrode C11 of the first capacitor C1, and the 2-3 electrode C23 of the second capacitor C2 may comprise oxides of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In another embodiment, the fifth semiconductor layer A5, the sixth semiconductor layer A6, the 1-1 electrode C11 of the first capacitor C1, and the 2-3 electrode C23 of the second capacitor C2 may comprise polycrystalline silicon or amorphous silicon.

[0155] The sixth semiconductor layer A6, the 1-1 electrode C11 of the first capacitor C1, and the 2-3 electrode C23 of the second capacitor C2 can be integrally formed with each other (or can be integral with each other). For example, the sixth semiconductor layer A6, the 1-1 electrode C11 of the first capacitor C1, and the 2-3 electrode C23 of the second capacitor C2 can be integrally connected with each other. The fifth semiconductor layer A5 can be disposed adjacent to the sixth semiconductor layer A6, the 1-1 electrode C11 of the first capacitor C1, and the 2-3 electrode C23 of the second capacitor C2, but can be separated from and spaced apart from the sixth semiconductor layer A6, the 1-1 electrode C11 of the first capacitor C1, and the 2-3 electrode C23 of the second capacitor C2.

[0156] refer to Figure 19 The fifth gate electrode G5, the sixth gate electrode G6, the third gate line EML, the fifth gate line EMBL, the driving voltage line PL, the fifth conductive layer 115, the 1-2 electrode C12 of the first capacitor C1, and the 2-1 electrode C21 of the second capacitor C2 can be disposed on the fifth semiconductor layer A5, the sixth semiconductor layer A6, the 1-1 electrode C11 of the first capacitor C1, and the 2-3 electrode C23 of the second capacitor C2. Each of the fifth conductive layer 115 and the driving voltage line PL can have an isolated shape. The third gate line EML and the fifth gate line EMBL can extend in a first direction (e.g., the positive x direction or the negative x direction).

[0157] The fifth gate electrode G5, the sixth gate electrode G6, the third gate line EML, the fifth gate line EMBL, the driving voltage line PL, the fifth conductive layer 115, the 1-2 electrode C12 of the first capacitor C1, and the 2-1 electrode C21 of the second capacitor C2 may contain the same material. For example, the fifth gate electrode G5, the sixth gate electrode G6, the third gate line EML, the fifth gate line EMBL, the driving voltage line PL, the fifth conductive layer 115, the 1-2 electrode C12 of the first capacitor C1, and the 2-1 electrode C21 of the second capacitor C2 may contain molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure containing the above materials.

[0158] The driving voltage line PL may include electrode C12 (1-2) of the first capacitor C1. Electrode C12 (1-2) of the first capacitor C1 may be part of the driving voltage line PL. For example, the driving voltage line PL and electrode C12 (1-2) of the first capacitor C1 may be integrally formed with each other (or may be integral with each other). Electrode C12 (1-2) of the first capacitor C1 may overlap with electrode C11 (1-1) of the first capacitor C1.

[0159] The fifth conductive layer 115 may include the 2-1 electrode C21 of the second capacitor C2. The 2-1 electrode C21 of the second capacitor C2 may be a part of the fifth conductive layer 115. For example, the fifth conductive layer 115 and the 2-1 electrode C21 of the second capacitor C2 may be integrally formed with each other (or may be integral with each other). The 2-1 electrode C21 of the second capacitor C2 may be disposed on top of the 2-3 electrode C23 to overlap with the 2-3 electrode C23.

[0160] The third gate line EML may include a fifth gate electrode G5 that overlaps with the channel region CH5 of the fifth transistor T5. (Reference) Figure 18 The fifth semiconductor layer A5 described may include a channel region CH5 overlapping with the fifth gate electrode G5, a source region S5 disposed on one side of the channel region CH5, and a drain region D5 disposed on the other side of the channel region CH5.

[0161] The fifth gate line EMBL may include a sixth gate electrode G6 that overlaps with the channel region CH6 of the sixth transistor T6. (See reference) Figure 18 The sixth semiconductor layer A6 described may include a channel region CH6 overlapping with the sixth gate electrode G6, a source region S6 disposed on one side of the channel region CH6, and a drain region D6 disposed on the other side of the channel region CH6.

[0162] The fifth gate line EMBL can be disposed relatively far from the fifth conductive layer 115. In some embodiments, the third gate line EML and the drive voltage line PL can be disposed between the fifth gate line EMBL and the fifth conductive layer 115.

[0163] refer to Figure 20 The reference voltage line VRL, the sixth conductive layer 116, the 1-3 electrodes C13 of the first capacitor C1, and the 2-2 electrodes C22 of the second capacitor C2 can be disposed on the fifth gate electrode G5, the sixth gate electrode G6, the third gate line EML, the fifth gate line EML, the drive voltage line PL, the fifth conductive layer 115, the 1-2 electrodes C12 of the first capacitor C1, and the 2-1 electrode C21 of the second capacitor C2. The sixth conductive layer 116 can have an isolated shape. The reference voltage line VRL can extend in a first direction (e.g., the positive x-direction or the negative x-direction).

[0164] The sixth conductive layer 116 may include the 1-3 electrode C13 of the first capacitor C1. The 1-3 electrode C13 of the first capacitor C1 may be a part of the sixth conductive layer 116. For example, the sixth conductive layer 116 and the 1-3 electrode C13 of the first capacitor C1 may be integrally formed with each other (or may be integral with each other). The 1-3 electrode C13 of the first capacitor C1 may overlap with the 1-1 electrode C11 and the 1-2 electrode C12. The first capacitor C1 may include the 1-1 electrode C11, the 1-2 electrode C12, and the 1-3 electrode C13.

[0165] The sixth conductive layer 116 may include the 2-2 electrode C22 of the second capacitor C2. The 2-2 electrode C22 of the second capacitor C2 may be part of the sixth conductive layer 116. For example, the sixth conductive layer 116 and the 2-2 electrode C22 of the second capacitor C2 may be integrally formed with each other (or may be integral with each other). The 2-2 electrode C22 of the second capacitor C2 may overlap with the 2-3 electrode C23 and the 2-1 electrode C21. The second capacitor C2 may include the 2-1 electrode C21, the 2-2 electrode C22, and the 2-3 electrode C23.

[0166] refer to Figure 21 The first capacitor C1 and the second capacitor C2 can be disposed on the substrate 100. The first capacitor C1 may include an overlapping 1-1 electrode C11, an overlapping 1-2 electrode C12, and an overlapping 1-3 electrode C13. The second capacitor C2 may include an overlapping 2-1 electrode C21, an overlapping 2-2 electrode C22, and an overlapping 2-3 electrode C23.

[0167] The 1-1 electrode C11 of the first capacitor C1 and the 2-3 electrode C23 of the second capacitor C2 can be disposed in the same layer and can comprise the same material. The 1-1 electrode C11 of the first capacitor C1 and the 2-3 electrode C23 of the second capacitor C2 can comprise silicon semiconductor material. The 1-1 electrode C11 of the first capacitor C1 and the 2-3 electrode C23 of the second capacitor C2 can be doped layers comprising silicon semiconductor material.

[0168] Electrode C12 (1-2) of the first capacitor C1 can be disposed above and overlap with electrode C11 (1-1). Electrode C21 (2-1) of the second capacitor C2 can be disposed above and overlap with electrode C23 (2-3). Electrode C23 (2-3) of the second capacitor C2 can be disposed below and overlap with electrode C21 (2-1). Electrodes C12 (1-2) of the first capacitor C1 and electrode C21 (2-1) of the second capacitor C2 can be disposed in the same layer and can comprise the same material.

[0169] The 1-3 electrode C13 of the first capacitor C1 can be disposed above and overlap with the 1-2 electrode C12. The 2-2 electrode C22 of the second capacitor C2 can be disposed above and overlap with the 2-1 electrode C21. The 1-3 electrode C13 of the first capacitor C1 and the 2-2 electrode C22 of the second capacitor C2 can be disposed in the same layer and can comprise the same material. The 1-3 electrode C13 of the first capacitor C1 and the 2-2 electrode C22 of the second capacitor C2 can be integrally formed with each other (or can be integral with each other). However, the embodiments are not limited thereto.

[0170] In this embodiment, not only can the first capacitor C1 include a doped layer containing silicon semiconductor material as an electrode, but the second capacitor C2 can also include a doped layer containing silicon semiconductor material as an electrode, and both the first capacitor C1 and the second capacitor C2 can include three electrodes. Because the first capacitor C1 and the second capacitor C2 include three electrodes containing a doped layer and two metal layers disposed on the doped layer, the capacitance of the capacitors in the pixel circuit can be unlimited as the number of pixels per unit area of ​​the display device increases, thereby improving the brightness and reliability of the display device.

[0171] Figure 22 This is a schematic plan view showing a barrier layer disposed on at least a portion of the semiconductor layer forming material. Figures 23 to 25 This is a schematic cross-sectional view illustrating a portion of a method for manufacturing a sixth transistor, a first capacitor, and a second capacitor. For example, Figure 23 It is along Figure 22 A schematic cross-sectional view of the display device taken from line IV-IV'.

[0172] refer to Figure 22 and Figure 23The sixth semiconductor layer forming material A6s, including silicon semiconductor material, the 1-1 electrode forming material C11s of the first capacitor C1, and the 2-3 electrode forming material C23s of the second capacitor C2 can be disposed on the same layer on the substrate 100. The sixth semiconductor layer forming material A6s, the 1-1 electrode forming material C11s of the first capacitor C1, and the 2-3 electrode forming material C23s of the second capacitor C2 can be integrally formed with each other (or may be integral with each other). The sixth semiconductor layer forming material A6s, the 1-1 electrode forming material C11s of the first capacitor C1, and the 2-3 electrode forming material C23s of the second capacitor C2 can include oxides of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In another embodiment, the sixth semiconductor layer forming material A6s, the 1-1 electrode forming material C11s of the first capacitor C1, and the 2-3 electrode forming material C23s of the second capacitor C2 may include polycrystalline silicon or amorphous silicon.

[0173] The barrier layer BL may be disposed on at least a portion of the sixth semiconductor layer forming material A6s. The barrier layer BL may comprise the same material as the photoresist used in the general process of manufacturing a display device. However, the embodiments are not limited thereto.

[0174] refer to Figure 24 The barrier layer BL may not be present on the 1-1 electrode forming material C11s of the first capacitor C1 and the 2-3 electrode forming material C23s of the second capacitor C2. The 1-1 electrode C11 of the first capacitor C1 and the 2-3 electrode C23s of the second capacitor C2 can be formed by doping the 1-1 electrode forming material C11s of the first capacitor C1 without the barrier layer BL and the 2-3 electrode forming material C23s of the second capacitor C2 without the barrier layer BL. After the process of doping the 1-1 electrode forming material C11s of the first capacitor C1 and the 2-3 electrode forming material C23s of the second capacitor C2, the barrier layer BL can be removed.

[0175] refer to Figure 25The sixth gate electrode G6 can be formed on at least a portion of the sixth semiconductor layer forming material A6s. Alternatively, the sixth gate electrode G6 may not be disposed on at least a portion of the sixth semiconductor layer forming material A6s. The sixth semiconductor layer A6 can be formed by doping the portion of the sixth semiconductor layer forming material A6s on which the sixth gate electrode G6 is not disposed. For example, the doped portion of the sixth semiconductor layer forming material A6s can be the source region S6 and the drain region D6, and the undoped portion of the sixth semiconductor layer forming material A6s that overlaps with the sixth gate electrode G6 can be the channel region CH6.

[0176] When the sixth semiconductor layer A6 is formed, the sixth transistor T6 can be formed. The sixth transistor T6 may include the sixth semiconductor layer A6 and a sixth gate electrode G6 overlapping the sixth semiconductor layer A6.

[0177] When the sixth gate electrode G6 is formed on at least a portion of the sixth semiconductor layer forming material A6s, the 1-2 electrode C12 can be formed on the 1-1 electrode C11 of the first capacitor C1, and the 2-1 electrode C21 can be formed on the 2-3 electrode C23 of the second capacitor C2. The 1-2 electrode C12 of the first capacitor C1, the 2-1 electrode C21 of the second capacitor C2, and the sixth gate electrode G6 of the sixth transistor T6 can all be made of the same material. The 1-2 electrode C12 of the first capacitor C1, the 2-1 electrode C21 of the second capacitor C2, and the sixth gate electrode G6 of the sixth transistor T6 can be formed simultaneously.

[0178] The first capacitor C1's 1-2 electrode C12 can be disposed above the 1-1 electrode C11 to overlap with the 1-1 electrode C11. The second capacitor C2's 2-1 electrode C21 can be disposed above the 2-3 electrode C23 to overlap with the 2-3 electrode C23.

[0179] Electrode C13 (1-3) can be disposed above electrode C12 (1-2) of the first capacitor C1 to overlap with electrode C12 (1-2) and electrode C11 (1-1). Electrode C22 (2-2) can be disposed above electrode C21 (2-1) of the second capacitor C2 to overlap with electrode C21 (2-1) and electrode C23 (2-3). Electrode C13 (1-3) of the first capacitor C1 and electrode C22 (2-2) of the second capacitor C2 can be disposed in the same layer and can comprise the same material.

[0180] The first capacitor C1 may include overlapping electrodes C11 (1-1), C12 (1-2), and C13 (1-3). The second capacitor C2 may include overlapping electrodes C21 (2-1), C22 (2-2), and C23 (2-3).

[0181] In an embodiment, the first capacitor C1 may include a doped layer comprising a silicon semiconductor material serving as electrodes, and therefore, the first capacitor C1 may include three electrodes. Because the first capacitor C1 includes three electrodes comprising a doped layer and two metal layers disposed on the doped layer, the capacitance of the capacitor for the pixel circuit can be unlimited as the number of pixels per unit area of ​​the display device increases, thereby improving the brightness and reliability of the display device.

[0182] Figure 26 and Figure 27 This is a schematic perspective view illustrating an application example of an electronic device.

[0183] refer to Figure 26 Electronic devices can be applied to a smartwatch 1000, which includes a display section 1100 and a band section 1200.

[0184] The smartwatch 1000 can be a wearable electronic device. For example, the smartwatch 1000 may have a structure in which a band portion 1200 is mounted on the user's wrist. Electronic devices may be applied to the display portion 1100, enabling the display to provide the user with image data including time information.

[0185] refer to Figure 27 Electronic devices can be applied to head-mounted display devices 2000.

[0186] The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 2000 can be a wearable device for virtual reality (VR) or mixed reality (MR). The head-mounted display device 2000 may include a head-mounting strap 2100 and a display housing 2200. The head-mounting strap 2100 can be connected to the display housing 2200. The head-mounting strap 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to the user's head. The horizontal strap may be configured to surround the sides of the user's head, and the vertical strap may be configured to surround the top of the user's head. However, the embodiments are not limited thereto. For example, within the spirit and scope of this disclosure, the head-mounting strap 2100 may be implemented in the form of an eyeglass frame or a helmet, etc.

[0187] For example, electronic devices can be at least one of the following: television, monitor, billboard, Internet of Things (IoT) device, portable electronic device (including mobile phone, smartphone, tablet PC, laptop computer, mobile communication terminal, electronic notebook, e-book, portable multimedia player (PMP), navigation device, ultra-mobile personal computer (UMPC), smartwatch, watch phone, glasses display, head-mounted display (HMD)), car dashboard, car center console, central information display (CID) on dashboard, car rearview mirror display, and display of entertainment system on the back of front seat in car.

[0188] Although this disclosure has been specifically shown and described with reference to its embodiments, the embodiments are provided for illustrative purposes, and those skilled in the art will understand that various modifications and other equivalent embodiments can be made based on this disclosure. Accordingly, the true technical scope of this disclosure is defined by the technical spirit of the claims.

[0189] According to the embodiments described above, a display device with improved reliability and quality, as well as a method for manufacturing the display device, can be provided. However, the scope of this disclosure is not limited to these effects.

[0190] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended to be limiting. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: A first transistor is disposed on a substrate and includes a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer, wherein the first semiconductor layer includes a silicon semiconductor material; as well as A first capacitor is disposed on the substrate. The first capacitor includes: 1-1 Electrode, comprising the silicon semiconductor material; Electrodes 1-2 overlap with electrode 1-1, and electrodes 1-2 and the first gate electrode are disposed in the same layer and comprise the same material; and Electrodes 1-3 overlap with electrodes 1-2.

2. The display device according to claim 1, wherein, The 1-1 electrode of the first capacitor is a doped layer comprising the silicon semiconductor material.

3. The display device according to claim 1, wherein, The 1-1 electrode and the first semiconductor layer are integral to each other.

4. The display device according to claim 1, wherein, The 1-2 electrode is disposed on the 1-1 electrode.

5. The display device according to claim 1, wherein, Electrode 1-3 is disposed above electrode 1-2.

6. The display device according to claim 1, further comprising: The second transistor is disposed on the first capacitor and includes a second semiconductor layer and a second gate electrode overlapping the second semiconductor layer. The second semiconductor layer comprises an oxide semiconductor material.

7. The display device according to claim 1, further comprising: A second capacitor is disposed on the substrate. The second capacitor includes: 2-1 electrode; and Electrode 2-2 overlaps with electrode 2-1, and The 2-1 electrode and the first gate electrode are disposed in the same layer and comprise the same material.

8. The display device according to claim 7, wherein, The 2-2 electrode is disposed above the 2-1 electrode.

9. The display device according to claim 7, wherein, The second capacitor further includes: Electrode 2-3 is disposed below electrode 2-1 so as to overlap with electrode 2-1.

10. The display device according to claim 9, wherein The 2-3 electrodes and the first semiconductor layer of the first transistor are made of the same material and are disposed in the same layer.

11. The display device according to claim 9, wherein, The 2-3 electrodes comprise the silicon semiconductor material.

12. The display device according to claim 9, wherein, The 2-3 electrodes are doped layers comprising the silicon semiconductor material.

13. A method of manufacturing a display device, the method comprising: A first semiconductor layer forming material and a 1-1 electrode forming material of a first capacitor are disposed on a substrate, wherein the first semiconductor layer forming material and the 1-1 electrode forming material of the first capacitor include silicon semiconductor materials; A barrier layer is disposed on at least a portion of the material forming the first semiconductor layer; as well as The 1-1 electrode of the first capacitor is formed by doping the 1-1 electrode forming material on which the barrier layer is not disposed.

14. The method of claim 13, further comprising: Remove the barrier layer; A first gate electrode is formed on at least a portion of the material forming the first semiconductor layer; as well as The first semiconductor layer is formed by doping the first semiconductor layer forming material with at least a portion on which the first gate electrode is not formed.

15. The method according to claim 14, wherein, The first transistor includes the first semiconductor layer and the first gate electrode overlapping the first semiconductor layer.

16. The method of claim 14, further comprising: Electrode 1-2 is formed on electrode 1-1 of the first capacitor to overlap with electrode 1-1.

17. The method according to claim 16, wherein, The first gate electrode and the first capacitor's electrodes 1-2 are disposed in the same layer and comprise the same material.

18. The method according to claim 13, wherein, The first semiconductor layer forming material and the 1-1 electrode forming material of the first capacitor are disposed in the same layer.

19. The method of claim 14, wherein, The first semiconductor layer and the 1-1 electrode of the first capacitor are integral with each other.

20. An electronic device, comprising: The display device according to any one of claims 1 to 12.

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