Method for detecting open circuit of through hole in back-end process of semiconductor device

Abstract

The invention provides a method for detecting the open circuit of a through hole in the back-end process of a semiconductor device, and the method comprises the steps: providing a semiconductor wafer which is subjected to a first chemical mechanical polishing technology, and forming an interconnection structure which comprises the through hole and an overlying groove on the semiconductor wafer; performing a second chemical mechanical polishing process on the semiconductor wafer to remove the conductive material in the trench until the top surface of the through hole is exposed; and finally, detecting the processed semiconductor wafer by adopting an electron beam, and determining whether the open circuit defect exists in the through hole or not according to the voltage contrast signal. According to the method, the chemical mechanical polishing process is added once to expose and physically separate the through holes, so that the technical problem that the single open circuit defect of the multi-through-hole redundant structure cannot be detected by the existing electron beam detection is solved, the detection efficiency and the data volume are remarkably improved, and the analysis period of the process problem is shortened.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for detecting open vias in the back-end manufacturing process of semiconductor devices. Background Technology

[0002] In semiconductor device manufacturing technology, as process nodes continue to shrink, the reliability of metal interconnect structures in the back-end process (BEOL) plays a decisive role in chip performance and yield. Among them, open-circuit defects in vias used to connect different metal layers are a common failure mode that seriously affects the electrical performance of the circuit.

[0003] Currently, electron beam inspection (E-beam) is a commonly used technique for wafer defect detection. Its principle is to use a focused electron beam to scan the wafer surface and identify defects by detecting differences in secondary electron or backscattered electron signals. Because electrical defects such as open circuits or short circuits cause changes in local surface potential, this results in a significant voltage contrast (VC) in the electron signal. For example, when an upper metal layer is connected to an lower structure through a single via, if that via becomes open-circuited, electron beam inspection can effectively identify it through the dark voltage contrast (DVC) signal (e.g., ...). Figure 1 As shown in the figure, electron beam detection technology can efficiently detect such defects and has the advantages of being non-destructive, having a fast scanning speed, and a wide coverage area.

[0004] However, existing electron beam inspection methods have significant limitations when applied to the detection of open vias in back-end processes. Specifically, in advanced processes, to improve circuit reliability and electrical performance, a redundant structure with multiple vias connected to a single metal strip is typically designed. In this structure, if only some vias become open, the remaining intact vias can still provide a conductive path to the upper metal strip, maintaining the overall potential of the metal strip. Therefore, conventional electron beam inspection methods cannot generate an effective voltage contrast signal on the surface of the upper metal strip, thus failing to detect this latent defect of partially open vias.

[0005] To address these issues, the industry standard practice currently relies on Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA). For example, after identifying a chip with performance abnormalities through electrical testing (such as WAT), it is necessary to pinpoint the specific failure location with high precision and employ destructive techniques such as transmission electron microscopy (TEM) for point-by-point slicing and physical characterization to confirm the root cause of the open via. TEM analysis can reveal the specific physical morphology leading to the open via, which may include: voids between the bottom of the via and the underlying metal layer (e.g.,...). Figure 2The “void under via” shown refers to a portion of the via structure that is completely missing during the manufacturing process (e.g., ...). Figure 3 The term "via missing" indicates a void formed when the via is filled with conductive material (e.g., ...). Figure 4 The "through-hole void" shown refers to a large void that affects both the through-hole and the upper metal layer (such as...). Figure 5 The "metal and via void" shown may be due to incomplete etching leaving residue at the bottom of the via that blocks the electrical connection (e.g., ...). Figure 6 The “through-hole bottom etching residue” shown is called Via under ET, etc.

[0006] The drawbacks of this method are quite obvious: the analysis cycle is extremely long, usually more than a week for a complete analysis of a single point; it is a destructive analysis and cannot be used for subsequent processing of the wafer; it can only analyze a single point at a time, and the amount of data obtained is very small, lacking statistical significance, making it difficult to quickly and comprehensively assess the process stability of the entire wafer or batch.

[0007] Therefore, there is an urgent need to develop a new method that can quickly, extensively, and non-destructively detect single or partial open-circuit defects in multi-hole structures in advanced process back-end manufacturing, in order to improve the efficiency of defect monitoring in the R&D and production process and accelerate the resolution of process problems. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a method that can quickly and over a large area detect single or partial open-circuit defects in multi-via structures in semiconductor back-end processes, so as to overcome the shortcomings of existing technologies that electron beam detection cannot detect such defects, while physical failure analysis is time-consuming and has a small amount of data.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A method for detecting open vias in the back-end manufacturing process of semiconductor devices includes the following steps:

[0011] Step 1: Provide a semiconductor wafer that has undergone a first chemical mechanical polishing process, wherein an interconnect structure is formed on the semiconductor wafer, the interconnect structure including vias filled with conductive material and trenches located above the vias;

[0012] Step 2: Perform a second chemical mechanical polishing process on the semiconductor wafer to remove the conductive material in the trenches until the top surface of the vias is exposed; and

[0013] Step 3: The semiconductor wafer that has undergone the second chemical mechanical polishing process is inspected using an electron beam to determine whether the via has an open circuit defect based on the voltage contrast signal.

[0014] Preferably, the interconnect structure includes a plurality of through holes connected to the same trench.

[0015] Preferably, prior to step one, the semiconductor wafer undergoes a four-quadrant process experiment or an energy matrix experiment.

[0016] Preferably, the interconnect structure is a back-end process interconnect layer other than the first metal interconnect layer.

[0017] Preferably, in step two, the polishing selectivity is controlled by adjusting the process parameters of the second chemical mechanical polishing process to prevent conductive material residue or over-polishing.

[0018] Preferably, the process parameters include adjusting the pattern loading effect.

[0019] Preferably, in step three, the electron beam detection preferentially selects regions with high aperture density for scanning.

[0020] Preferably, step three further includes: analyzing the voltage contrast signal to eliminate false defect signals generated by the suspended metal structure.

[0021] Preferably, the conductive material is copper or a copper alloy.

[0022] As described above, the method for detecting open vias in the back-end process of semiconductor devices according to the present invention has the following beneficial effects:

[0023] This invention solves the technical challenge of existing electron beam inspection methods being unable to effectively detect single open-circuit defects in redundant multi-via structures by adding a chemical mechanical polishing process to expose and physically separate individual vias. Simultaneously, this invention significantly reduces defect analysis time from approximately one week for physical analysis of a single point in existing technologies to a large-area wafer scan completed within tens of hours, greatly improving inspection efficiency and accelerating the resolution of process problems. Furthermore, this invention enables large-area, non-destructive, rapid scanning, obtaining a large amount of defect data covering multiple areas of the wafer, providing statistically significant information for process monitoring, yield analysis, and process optimization—something traditional single-point destructive analysis cannot match. Attached Figure Description

[0024] Figure 1 This diagram illustrates the electron beam detection of open-circuit defects in vias according to existing technology.

[0025] Figure 2The image shown is a transmission electron microscope image of the morphology of a void defect under a through-hole, as observed using existing technology.

[0026] Figure 3 The image shown is a morphology diagram of a through-hole defect observed using transmission electron microscopy according to existing technology.

[0027] Figure 4 The image shown is a morphological diagram of a through-hole void defect observed using a transmission electron microscope according to existing technology.

[0028] Figure 5 The image shows the morphology of metal and through-hole void defects as observed by transmission electron microscopy according to existing technology.

[0029] Figure 6 The image shown is a morphology diagram of residual defects in the bottom etching of a through-hole as observed by transmission electron microscopy according to the prior art.

[0030] Figure 7 The diagram shows a method flow diagram according to an embodiment of the present invention.

[0031] Figure 8 The diagram shown is a cross-sectional view of the interconnect structure to be tested according to an embodiment of the present invention.

[0032] Figure 9 The diagram shows a four-quadrant process experiment according to an embodiment of the present invention.

[0033] Figure 10 The diagram shown is an experimental schematic of an energy matrix according to an embodiment of the present invention.

[0034] Figure 11 The diagram shows a cross-sectional view of the interconnect structure after a second chemical mechanical polishing process, according to an embodiment of the present invention.

[0035] Figure 12 The image shown is a voltage contrast defect signal detected by electron beam detection according to an embodiment of the present invention.

[0036] Figure 13 Displayed as a layered defect diagram obtained according to an embodiment of the present invention;

[0037] Figure 14 The diagram illustrates a defect generation mechanism according to an embodiment of the present invention.

[0038] Figure 15 The image shown is a wafer distribution diagram of the total number of defects obtained according to an embodiment of the present invention;

[0039] Figure 16 The diagram shows the distribution of true voltage contrast defects detected on a wafer according to an embodiment of the present invention. Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] This invention provides a method for detecting open vias in the back-end process of semiconductor device manufacturing, the overall process of which is as follows: Figure 7 As shown. The method includes the following steps:

[0042] Step 1: Provide a semiconductor wafer that has undergone a first chemical mechanical polishing process, on which an interconnect structure is formed, the interconnect structure including vias filled with conductive material and trenches located above the vias.

[0043] Figure 8 A schematic cross-sectional view of the interconnect structure provided in this step is shown, in which the first layer via V1 connects to the lower metal layer (not shown) and supports the second metal layer M2. The second metal layer M2 is then connected to the upper third metal layer M3 through the second layer via V2. Here, M3 corresponds to the "trench" filled with conductive material as described in the claims, and V2 is the "via" to be tested.

[0044] In specific process implementation, this interconnect structure is typically formed using a double damascene process. Taking the double damascene process as an example, its formation process generally includes the following steps: First, an etch stop layer is deposited on the bottom metal interconnect layer or substrate. The etch stop layer material can be silicon nitride (SiN), silicon carbide nitride (SiCN), or silicon oxynitride (SiON) to precisely control the etching depth in subsequent etching steps. Next, one or more interlayer dielectric (ILD) materials are deposited on the etch stop layer. These interlayer dielectric materials are typically low-k or ultra-low-k materials. Subsequently, through-hole patterns and trench patterns are sequentially or simultaneously formed in the interlayer dielectric material using photolithography and etching processes. After etching, a barrier layer and / or a pad layer are deposited on the patterned dielectric layer surface and the inner walls of the through-holes and trenches using methods such as physical vapor deposition (PVD) or atomic layer deposition (ALD). The barrier layer material is typically tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), or a multilayer stacked structure thereof. Finally, conductive material is filled into the vias and trenches using methods such as electrochemical deposition (ECP) or physical vapor deposition, and a first chemical mechanical polishing process is performed for planarization.

[0045] In some embodiments, the interconnect structure includes multiple vias connected to the same trench. This redundant design of multiple vias connected to a single metal strip is very common in advanced process nodes to improve circuit reliability. However, it is precisely this design that makes it impossible for conventional electron beam inspection methods to detect open-circuit defects in a single via, because other intact vias can still provide conductive paths to the upper metal strip, thus masking the defect signal. The method of the present invention precisely solves this technical problem.

[0046] In some embodiments, prior to step one, the semiconductor wafer undergoes a four-quadrant process experiment or an energy matrix (EM) experiment. For example... Figure 9 The diagram illustrates a four-quadrant process experiment. By applying different process parameters (such as DOSE offset) to different quadrant regions of the wafer, the process window can be systematically studied and potential edge defects can be actively induced. Similarly, Figure 10 The diagram illustrates an energy matrix experiment that systematically adjusts the process energy (e.g., photolithography exposure energy or etching energy) used to form vias to deliberately alter the critical dimensions of the vias in different regions of the wafer. These process treatments can impose specific process parameter deviations on the wafer, effectively inducing or amplifying potential, weak open-circuit defects in the process, thereby improving the detection rate of such defects in subsequent inspection steps.

[0047] In some embodiments, the interconnect structure is a back-end process interconnect layer other than the first metal interconnect layer. Typically, this method is applied to global or semi-global interconnect layers at the second metal interconnect layer (M2) and above. This is because the first metal interconnect layer (M1) is usually directly connected to front-end devices such as transistors, and its structure and design rules are different from those of the upper metal layer, while redundant structures with multiple vias are more common in layers M2 and above.

[0048] In some embodiments, the conductive material is copper or a copper alloy. In other embodiments, the conductive material may also be other advanced conductive metals suitable for later-stage processes, such as cobalt (Co), ruthenium (Ru), molybdenum (Mo), or combinations thereof, to meet the resistivity and reliability requirements at smaller process nodes.

[0049] Step 2: Perform a second chemical mechanical polishing (CMP) process on the semiconductor wafer to remove the conductive material in the trenches until the top surface of the vias is exposed. By performing an additional CMP, the upper metal strip (i.e.,...) is removed. Figure 8 The M3 in the middle was completely removed, so that the multiple through holes (such as those originally connected by the metal strip) were completely removed. Figure 8 The top of V2 is exposed and physically separated from each other. The processed structural cross-section is as follows: Figure 11As shown. In this way, each via becomes an independent electrical detection node, creating the necessary conditions for subsequent accurate identification of the open circuit status of individual vias using an electron beam.

[0050] In some embodiments, in step two, the polishing selectivity is controlled by adjusting the process parameters of the second chemical mechanical polishing process to prevent conductive material residue or over-polishing. The process parameters include adjusting the pattern loading effect. To achieve precise removal of conductive material from the trenches without damaging the exposed via top surface and surrounding dielectric material, fine-tuning of the chemical mechanical polishing parameters is necessary. Precise process control ensures a smooth surface, which is beneficial for the stability and accuracy of subsequent electron beam detection signals.

[0051] Step 3: An electron beam is used to inspect the semiconductor wafer after the second chemical mechanical polishing process to determine the presence of open-circuit defects in the vias based on the voltage contrast signal. After the top surface of the via is exposed, the wafer surface is scanned using an electron beam. For vias with normal connections, an effective discharge circuit can be formed through the underlying metal structure, and their surface potential remains stable or close to the substrate potential under electron beam irradiation. However, for vias with open-circuit defects, they are electrically suspended and charge accumulates under electron beam irradiation, causing their surface potential to differ significantly from that of normal vias, thus forming a voltage contrast signal with sharp brightness in the secondary electron image. Figure 12 As shown, the bright spot marked in the GVC (Gray Voltage Contrast) image on the left is a via with an open circuit defect, while the reference (REF.) image on the right shows the signal in the normal area. Figure 13 The layered defect map obtained by the method of this invention is further illustrated. As can be seen in the figure, a significant defect signal appears on the VDEF (via defect) layer in the middle row, while there is no signal on the M2 DEF (metal layer defect) and VDEF_SC (short circuit defect) layers above and below. This clearly indicates that the defect type is a via open circuit, rather than a metal layer open circuit or via short circuit, verifying the accuracy of this method. Figure 14 This intuitively explains the physical cause of the defect: the etching residue at the bottom of the via (Via under ET) caused the electrical connection between the via V2 and the metal layer M2 to break, thus generating the DVC signal.

[0052] In some embodiments, in step three, electron beam detection preferentially scans areas with high via density. In chip layout, areas with high via density are often challenging points for process control, with a relatively higher probability of defects. Therefore, prioritizing scanning these areas can more efficiently identify potential process problems and maximize the defect detection rate within a limited detection time.

[0053] In some embodiments, step three further includes analyzing the voltage contrast signal to eliminate spurious defect signals generated by suspended metal structures. In layout design, there may be test structures or infill metal patterns that are inherently electrically suspended; these structures will also generate voltage contrast signals during electron beam detection. Therefore, it is necessary to compare the detected defect coordinates with the design layout, or use specific algorithms for intelligent filtering to eliminate spurious defect signals generated by these known suspended structures, thereby ensuring that the defects reported in the final report are all genuine open via issues.

[0054] The method proposed in this invention overcomes the bottlenecks of existing technologies, enabling rapid, large-area detection of single or partial open vias in multi-via structures. At advanced process nodes, this method can scan 61 wafer locations (dies), such as... Figure 15 The image shown is a wafer map showing the total number of defects, where colors and values ​​represent defect densities in different areas. It only takes 36 hours to cover 1.28% of the wafer area and successfully detected 6 true voltage contrast defects. Figure 16 As shown, these six real GVC defect points are clearly distributed on the wafer map. Compared with the traditional method that relies on physical failure analysis (EFA) for individual points, which takes about a week per point, the efficiency of this invention is greatly improved. This method not only significantly shortens the analysis cycle of process problems, but also provides a large amount of statistically significant data, providing technical support for the research and development, mass production, and yield monitoring of advanced semiconductor processes.

[0055] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0056] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for detecting open vias in the back-end manufacturing process of semiconductor devices, characterized in that, At least including: Step 1: Provide a semiconductor wafer that has undergone a first chemical mechanical polishing process, wherein an interconnect structure is formed on the semiconductor wafer, the interconnect structure including vias filled with conductive material and trenches located above the vias; Step 2: Perform a second chemical mechanical polishing process on the semiconductor wafer to remove the conductive material in the trench until the top surface of the via is exposed; Step 3: The semiconductor wafer that has undergone the second chemical mechanical polishing process is inspected using an electron beam to determine whether the via has an open circuit defect based on the voltage contrast signal.

2. The method for detecting open vias in the back-end process of semiconductor devices according to claim 1, characterized in that: The interconnect structure includes a plurality of vias connected to the same trench.

3. The method for detecting open vias in the back-end process of a semiconductor device according to claim 1 or 2, characterized in that: Prior to step one, the semiconductor wafer undergoes a four-quadrant process experiment or an energy matrix experiment.

4. The method for detecting open vias in the back-end process of semiconductor devices according to claim 1, characterized in that: The interconnect structure is a back-end process interconnect layer other than the first metal interconnect layer.

5. The method for detecting open vias in the back-end process of semiconductor devices according to claim 1, characterized in that: In step two, the polishing selectivity is controlled by adjusting the process parameters of the second chemical mechanical polishing process to prevent conductive material residue or over-polishing.

6. The method for detecting open vias in the back-end process of semiconductor devices according to claim 5, characterized in that: The process parameters include adjusting the pattern loading effect.

7. The method for detecting open vias in the back-end process of semiconductor devices according to claim 1, characterized in that: In step three, the electron beam detection preferentially selects regions with high aperture density for scanning.

8. The method for detecting open vias in the back-end process of semiconductor devices according to claim 1, characterized in that: Step three also includes: analyzing the voltage contrast signal to eliminate false defect signals generated by the suspended metal structure.

9. The method for detecting open vias in the back-end process of semiconductor devices according to claim 1, characterized in that: The conductive material is copper or a copper alloy.

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