Wafer processing technology and processing tool
By bonding the contact surfaces together and heat-treating them in a sealed cavity during the wafer heat treatment process, and using a supersaturated silicon atmosphere to suppress silicon atom overflow, the problem of silicon overflow during wafer heat treatment is solved, and high-quality wafer processing is achieved.
Patent Information
- Application Number
- CN202511758714.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-27
- Publication Date
- 2026-03-03
AI Technical Summary
During wafer heat treatment, silicon atoms are prone to overflow at the contact surface, leading to surface carbonization, which affects wafer quality, fails to meet the requirements of subsequent epitaxial growth processes, and results in resource waste and increased production costs.
The wafer fabrication process involves bonding the contact surfaces of two pre-treated wafers together to form a wafer assembly, and then performing heat treatment in a sealed cavity. The supersaturated silicon atmosphere is used to suppress the overflow of silicon atoms, forming a stepped contact surface. Combined with low-temperature heat treatment and annealing processes, the quality of the wafers is improved.
It effectively suppresses silicon atom overflow, forms a stepped contact surface that meets the requirements of epitaxial growth process, improves wafer processing quality and production efficiency, and reduces resource waste and costs.
Smart Images
Figure CN121604802A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor processing technology, and in particular to a wafer processing process and processing tooling. Background Technology
[0002] In the field of wafer manufacturing, the conventional process involves sequentially performing multiple steps such as cutting, grinding, chamfering, polishing, cleaning, and testing on the wafer, then placing it in a specific tooling structure for heat treatment, and finally removing it for use.
[0003] A silicon carbide wafer has two axially opposite surfaces: one is the contact surface, typically the silicon surface, which, after heat treatment, needs to form a stepped shape to meet the requirements of subsequent epitaxial growth processes; the other is the non-contact surface, mostly the carbon surface. As a hard and brittle material, SiC single crystals have high technical requirements for processing. Damage generated in each production stage can have a certain degree of heritability, passing to the next process and ultimately affecting product quality. Ideally, after chemical mechanical polishing (CMP), the surface of a silicon carbide wafer is free of scratches and subsurface damage layers, and possesses atomic steps similar to the natural cleavage planes of crystals. However, due to limitations in equipment and consumables, as well as the stability of processes and crystal quality, it is difficult for polished silicon carbide wafers to exhibit atomic step flow. This patent proposes a solution for the stable preparation of stepped-flow wafers, laying the foundation for high-quality crystals.
[0004] Furthermore, current technologies have significant problems in the wafer heat treatment process. When wafers are placed in the fixture for heat treatment, single-element silicon leakage is highly likely to occur at the contact surface. The carbon atoms that lose silicon atoms cause carbonization on the contact surface, severely affecting the wafer surface quality. The carbonized contact surface cannot meet the stringent surface quality standards required for subsequent epitaxial growth processes, making it difficult to use the heat-treated wafers in subsequent production processes. This not only wastes wafer resources but also increases production costs, hindering the improvement of production efficiency and product quality in the wafer manufacturing industry.
[0005] Therefore, there is an urgent need for a wafer processing technology and tooling to solve the aforementioned problems. Summary of the Invention
[0006] Based on the above, the purpose of this invention is to provide a wafer processing technology and processing fixture. During the heat treatment of the processing fixture and the wafer group within the processing fixture, the overflow of silicon atoms on the two contact surfaces can be effectively suppressed, and the contact surfaces form a stepped shape to obtain the target wafer, thereby meeting the requirements of the target wafer in the subsequent epitaxial growth process and improving the processing quality of the target wafer.
[0007] To achieve the above objectives, the present invention adopts the following technical solution:
[0008] On the one hand, a wafer fabrication process is provided, including the following steps:
[0009] S1. Obtain two pre-processed wafers, each pre-processed wafer including a contact surface and a non-contact surface. After bonding the contact surfaces of the two pre-processed wafers together, a wafer group is formed.
[0010] S2. Place the wafer assembly into the sealed cavity of the processing fixture;
[0011] S3. Perform heat treatment on the processing fixture and the wafer assembly within the processing fixture;
[0012] S4. Remove the wafer assembly from the sealed cavity and separate the two pre-treated wafers to obtain the target wafer.
[0013] As a preferred technical solution for wafer fabrication, in step S1, the pretreatment of the wafer includes the following steps:
[0014] S11. Obtain the initial wafer;
[0015] S12. Polish the contact surface and non-contact surface of the initial wafer to obtain a polished wafer;
[0016] S13. Detect the surface roughness of the polished wafer and determine whether the surface roughness of the polished wafer is less than a preset roughness; if not, proceed to S12; if yes, proceed to S14.
[0017] S14. Remove the polished wafer after inspection to obtain the pre-treated wafer.
[0018] As a preferred technical solution for wafer fabrication, in step S3, the heat treatment includes the following steps:
[0019] S31. Heat the processing fixture and the wafer assembly within the processing fixture;
[0020] S32. The processing fixture and the wafer assembly within the processing fixture are kept in an inert gas environment at a preset insulation pressure for a preset time.
[0021] S33. The processing fixture and the wafer assembly within the processing fixture are cooled to a preset cooling temperature at a preset annealing rate.
[0022] As a preferred technical solution for wafer fabrication, the heating of the processing fixture and the wafer assembly within the processing fixture in step S31 includes the following steps:
[0023] The processing fixture, along with the wafer assembly inside it, which is at room temperature, is subjected to a first heat treatment at a heating rate of 4°C / min to 5°C / min to 990°C to 1000°C; then, a second heat treatment is performed at a heating rate of 2°C / min to 3°C / min to 1300°C to 1500°C.
[0024] As a preferred technical solution for wafer processing, in step S32, the preset insulation pressure is 50 kPa, the preset time is 28-30 minutes, and the inert gas environment is argon.
[0025] As a preferred technical solution for wafer processing, in step S33, the preset annealing rate is 1℃ / min~2℃ / min, and the preset cooling temperature is 25℃.
[0026] As a preferred technical solution for wafer processing, the contact surface is a silicon surface and the non-contact surface is a carbon surface.
[0027] On the other hand, a processing fixture is provided for use in any of the above-described wafer processing processes, the processing fixture comprising:
[0028] A tooling holder, wherein the tooling holder is provided with a receiving groove;
[0029] A gasket is disposed within the receiving groove, the gasket being used to support the wafer assembly;
[0030] A tooling cover, which is sealed and detachably connected to the opening of the receiving groove, the tooling cover and the receiving groove forming a sealed cavity.
[0031] As a preferred technical solution for processing tooling, the opening edge of the receiving groove is stepped, and the opening edge of the receiving groove is provided with a first stepped surface; the outer periphery of the tooling cover is stepped, and the outer periphery of the tooling cover is provided with a second stepped surface, and the second stepped surface is sealed and overlapped with the first stepped surface.
[0032] As a preferred technical solution for processing tooling, there are multiple tooling trays and gaskets that correspond one-to-one. The multiple tooling trays are stacked sequentially. The bottom of the upper tooling tray is sealed and detachably connected to the opening of the receiving groove of the lower tooling tray. The adjacent tooling trays form a sealed cavity. The tooling cover is sealed and detachably connected to the opening of the receiving groove of the uppermost tooling tray.
[0033] The beneficial effects of this invention are as follows:
[0034] This invention provides a wafer processing technology and processing fixture, comprising the following steps: obtaining two pre-processed wafers, each pre-processed wafer including a contact surface and a non-contact surface; bonding the contact surfaces of the two pre-processed wafers together to form a wafer assembly; placing the wafer assembly into a sealed cavity of the processing fixture; performing heat treatment on the processing fixture and the wafer assembly within the processing fixture; removing the wafer assembly from the sealed cavity and separating the two pre-processed wafers to obtain the target wafer. By bonding the contact surfaces of two pre-processed wafers together, a near-sealed space is formed between the contact surfaces. Within this space, the silicon gas atmosphere is supersaturated, exceeding the C and N gas concentrations within the sealed cavity. Therefore, during the heat treatment of the processing fixture and the wafer assembly within it, the overflow of silicon atoms from the two contact surfaces can be effectively suppressed. As unstable bonds on the contact surfaces volatilize and a small amount of silicon carbide overflows, the contact surfaces form a stepped shape, resulting in the target wafer. This meets the requirements of the target wafer in subsequent epitaxial growth processes, improving the processing quality of the target wafer. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the content of the embodiments of the present invention and these drawings without creative effort.
[0036] Figure 1 This is a flowchart of the wafer processing technology provided in a specific embodiment of the present invention;
[0037] Figure 2 This is a flowchart of the pre-processing process for wafers provided in a specific embodiment of the present invention;
[0038] Figure 3 This is a flowchart of the heat treatment process provided in a specific embodiment of the present invention;
[0039] Figure 4 This is a schematic diagram of the structure of the wafer assembly provided in a specific embodiment of the present invention;
[0040] Figure 5 This is a schematic diagram of the processing tooling provided in a specific embodiment of the present invention;
[0041] Figure 6 This is an exploded view of the processing tooling and wafer assembly provided in a specific embodiment of the present invention;
[0042] Figure 7 This is a cross-sectional view of the processing fixture and wafer assembly provided in a specific embodiment of the present invention.
[0043] The markings in the image are as follows:
[0044] 1. Wafer assembly; 11. Pre-processed wafer; 111. Contact surface; 112. Non-contact surface;
[0045] 2. Machining fixture; 21. Fixture support; 211. Receiving groove; 22. Gasket; 23. Fixture cover; 24. Sealing cavity. Detailed Implementation
[0046] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.
[0047] In the description of this invention, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0048] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0049] In the description of this embodiment, the terms "upper," "lower," "left," and "right," etc., refer to the orientation or positional relationship shown in the accompanying drawings. They are used only for ease of description and simplification of operation, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first" and "second" are used only for distinction in description and have no special meaning.
[0050] like Figure 1 , Figure 4 and Figure 5As shown, this embodiment provides a wafer fabrication process, which includes the following steps:
[0051] S1. Obtain two pre-processed wafers 11. Each pre-processed wafer 11 includes a contact surface 111 and a non-contact surface 112. After bonding the contact surfaces 111 of the two pre-processed wafers 11 together, a wafer group 1 is formed.
[0052] S2. Place the wafer assembly 1 into the sealed cavity 24 of the processing fixture 2;
[0053] S3. Perform heat treatment on the processing fixture 2 and the wafer group 1 within the processing fixture 2;
[0054] S4. Remove wafer group 1 from the sealed cavity 24 and separate the two pre-processed wafers 11 to obtain the target wafer.
[0055] By bonding the contact surfaces 111 of two pre-processed wafers 11 together, a nearly sealed space is formed between the contact surfaces 111 of the two pre-processed wafers 11. In this space, the silicon gas atmosphere between the gaps is supersaturated, which is higher than the C and N gas concentrations in the sealed cavity 24. Therefore, during the heat treatment of the processing fixture 2 and the wafer group 1 within the processing fixture 2, the overflow of silicon atoms on the two contact surfaces 111 can be effectively suppressed. As the unstable bonds on the contact surfaces 111 volatilize and a small amount of silicon carbide overflows, the contact surfaces 111 form a stepped shape, resulting in the target wafer, which meets the requirements of the target wafer in the subsequent epitaxial growth process and improves the processing quality of the target wafer.
[0056] In this embodiment, the hardness of the contact surface 111 is lower than that of the non-contact surface 112, and the surface atoms of the contact surface 111 are more likely to volatilize during low-temperature heat treatment compared to the non-contact surface 112. It should be noted that the wafer is a third-generation semiconductor, which uses diatomic semiconductors such as aluminum nitride, silicon carbide, and gallium oxide. In this embodiment, the wafer is made of silicon carbide, with the contact surface 111 being the silicon surface and the non-contact surface 112 being the carbon surface. Both pre-treated wafers 11 are approximately columnar, and their thicknesses can differ. The contact surfaces 111 of the two pre-treated wafers 11 have the same size and shape, allowing them to completely cover and adhere to form wafer group 1. This avoids silicon overflow from the contact surfaces 111, prevents carbonization of the target wafer surface, and improves the surface quality of the target wafer.
[0057] If the initial wafer is placed directly into the processing fixture 2 after being provided, its surface roughness is not up to standard. Therefore, during heat treatment, defects such as dislocations, stacking faults, impurities, and micropipes are easily generated. To solve these problems, such as... Figure 2As shown, in step S1, the preprocessing of the wafer includes the following steps:
[0058] S11. Obtain the initial wafer;
[0059] S12. Polish the contact surface 11 and non-contact surface 112 of the initial wafer to obtain a polished wafer;
[0060] S13. Detect the surface roughness of the polished wafer and determine whether the surface roughness of the polished wafer is less than the preset roughness; if not, proceed to S12; if yes, proceed to S14.
[0061] S14. Remove the polished wafer after inspection to obtain the pre-processed wafer 11.
[0062] In this process, after the initial wafer is polished, its thickness and surface roughness are controlled within a certain range. The preset roughness is set to 10nm. In step S13, if the surface roughness of the polished wafer is greater than or equal to 10nm, the process returns to step S12 and continues the polishing operation until the surface roughness of the polished wafer is less than 10nm, so as to obtain the pre-processed wafer 11.
[0063] Furthermore, such as Figure 3 As shown, in step S3, the heat treatment includes the following steps:
[0064] S31. Heat the processing fixture 2 and the wafer assembly 1 within the processing fixture 2;
[0065] S32. The processing fixture 2 and the wafer group 1 inside the processing fixture 2 are kept in an inert gas environment with a preset insulation pressure for a preset time.
[0066] S33. The processing fixture 2 and the wafer group 1 within the processing fixture 2 are cooled to the preset cooling temperature at a preset annealing rate.
[0067] During processes S31 and S32, the unstable bonds on the contact surface 111 volatilize and a small amount of silicon carbide overflows, forming a stepped shape on the contact surface 111; during process S33, the stress on the wafer can be removed.
[0068] Furthermore, in step S31, heating the processing fixture 2 and the wafer assembly 1 within it includes the following steps: The processing fixture 2, along with the wafer assembly 1 inside it, is at room temperature and undergoes a first heating treatment to 990℃~1000℃ at a heating rate of 4℃ / min~5℃ / min; then, a second heating treatment is performed at a heating rate of 2℃ / min~3℃ / min to 1300℃~1500℃. In this embodiment, the heating rate of the first heating treatment is greater than that of the second heating treatment. The purpose of the first heating treatment is to rapidly bake the furnace and quickly increase the temperature, while the lower heating rate of the second heating treatment is to avoid excessively rapid heating and to promote temperature uniformity. The ambient temperature of the processing fixture 2 and its internal wafer assembly 1 is raised from room temperature to 1300℃~1500℃ through two heating processes. This allows the processing fixture 2 and its internal wafer assembly 1 to maintain a surface heat treatment at this temperature. It should be noted that "room temperature" in this embodiment refers to room temperature, i.e., 25℃. The above heating process is a low-temperature heat treatment, which prevents the pre-treated wafers 11 from becoming too hot, thereby avoiding adhesion between the two pre-treated wafers 11 in the wafer assembly 1.
[0069] It should be noted that the heating process in step S31 is to bring wafer group 1 to a preset heating temperature, which is in the range of 1300℃~1500℃. Optionally, the preset heating temperature range is 1300℃~1400℃, 1400℃~1450℃, or 1450℃~1500℃.
[0070] In step S32, the preset insulation pressure is 50 kPa, the preset time is 28 to 30 minutes, and the inert gas environment is argon. Under this insulation and pressure environment, the contact surface 111 can stably generate a stepped shape.
[0071] For example, after the heat treatment in step S31 is completed, the processing fixture 2, together with the wafer assembly 1 inside it, is kept at a temperature of 1400°C for 28 to 30 minutes under a 50 kPa argon atmosphere. It should be understood that this heat treatment process is the surface heat treatment process. In this embodiment, a low pressure (50 kPa) is used during the heat treatment process, which also helps to prevent atomic overflow from the surface of the pretreated wafer 11. Therefore, the combined effect of the wafer assembly 1 and the low-pressure heat treatment provided in this embodiment further enhances the suppression effect on silicon overflow at the contact surface 111.
[0072] In step S33, the preset annealing rate is 1℃ / min to 2℃ / min, and the preset cooling temperature is 25℃, i.e., cooling to room temperature. After the pre-processed wafer 11 undergoes low-temperature heat treatment, various stresses and defects exist within the wafer. This annealing process eliminates these stresses, allowing the target wafer to be used in epitaxial production, thus improving the crystal quality and stability. Furthermore, using this preset annealing rate prevents excessively rapid cooling and the generation of large stresses within the wafer. Annealing is a common heat treatment process. Its purpose is to improve the crystal lattice structure, reduce defects, eliminate stress, and improve the surface quality of the wafer by heating the wafer to a certain temperature and controlling the time, followed by gradual cooling. In this embodiment, a low-rate annealing is used. For example, the annealing temperature for the processing fixture 2 starts at 1400℃ and ends at 0℃. Specifically, the preset annealing rate is 1.17℃ / min. It should be understood that low-rate annealing cooling can prevent the two pre-processed wafers 11 in wafer group 1 from generating large internal stress due to rapid cooling.
[0073] To facilitate understanding of the effects of the wafer fabrication process provided in this disclosure, two experimental groups and one control group are provided.
[0074] Experimental Group 1: A 6-inch N-type silicon carbide polished wafer with a diameter of 150 mm and a thickness of 350 μm was selected. The surface polishing quality was at a relatively good level, but the atomic step morphology could not be polished out, and the surface of the polished wafer was deflected by 6° in the horizontal direction. Based on the wafer processing technology provided in this embodiment, two silicon carbide polished wafers were placed in the processing fixture 2 as pre-processed wafers 11. The processing fixture 2 was subjected to heat treatment, and the target wafer was obtained after heat treatment. The low-temperature heat treatment process during heat treatment was 1400℃, the heat treatment time was 30 min, and the heat treatment atmosphere was 50 kPa argon.
[0075] Experimental Group 2: A 6-inch N-type silicon carbide polished wafer with a diameter of 150 mm and a thickness of 350 μm was selected. The surface polishing quality was at a relatively good level, but the atomic step morphology could not be polished out, and the surface of the polished wafer was deflected by 4° in the horizontal direction. Based on the wafer processing technology provided in this embodiment, two silicon carbide polished wafers were placed in the processing fixture 2 as pre-processed wafers 11. The processing fixture 2 was subjected to heat treatment, and the target wafer was obtained after heat treatment. The low-temperature heat treatment process during heat treatment was 1400℃, the heat treatment time was 30 min, and the heat treatment atmosphere was 50 kPa argon.
[0076] Comparative group: A 6-inch N-type silicon carbide polished wafer with a diameter of 150 mm and a thickness of 350 μm was selected. The surface polishing quality was at a relatively good level, but the atomic step morphology could not be polished out, and the surface of the polished wafer was deflected by 6° in the horizontal direction. A silicon carbide polished wafer was placed in processing fixture 2 for heat treatment. After heat treatment, the target wafer was obtained.
[0077] The target wafers obtained from Experimental Group 1, Experimental Group 2, and the control group were examined using an atomic microscope, and the results are shown in Table 1 below:
[0078]
[0079] Table 1: Detection Results of the Target Wafer
[0080] According to the results in Table 1, the target wafer obtained in Experiment 1 has a step height of approximately 10 nm and a width of approximately 200 nm on the contact surface 111, which is approximately 5-7 silicon carbide unit cells. The target wafer obtained in Experiment 2 has a step height of approximately 2 nm and a width of approximately 50 nm on the contact surface 111, which is approximately 1-2 silicon carbide unit cells. The target wafer obtained in the control group exhibits silicon overflow at the contact surface 111. The differences in step height, step width, and silicon carbide unit cell size between Experiment 1 and Experiment 2 during the inspection of the target wafers are mainly caused by the deflection direction of the pre-treated wafer 11. The control group exhibits silicon overflow, resulting in defects. Therefore, this wafer processing technology can effectively suppress silicon atom overflow, preventing carbonization of the contact surface 111.
[0081] Furthermore, such as Figures 4-7 As shown, this embodiment also provides a processing fixture 2, applied to the above-mentioned wafer processing process. The processing fixture 2 includes a fixture tray 21, a gasket 22, and a fixture cover 23. The fixture tray 21 is provided with a receiving groove 211; the gasket 22 is disposed in the receiving groove 211 and is used to support the wafer assembly 1; the fixture cover 23 is sealed and detachably connected to the opening of the receiving groove 211, and the fixture cover 23 and the receiving groove 211 form a sealed cavity 24. In use, the fixture cover 23 is first removed, and then the wafer assembly 1 is placed on the gasket 22 in the receiving groove 211. At this time, the two ends of the wafer assembly 1 are exactly the non-contact surfaces 112 of two pre-processed wafers. The non-contact surfaces 112 at the bottom of the pre-processed wafer 11 are in contact with the gasket 22. Finally, the fixture cover 23 is sealed and detachably connected to the opening of the receiving groove 211.
[0082] In this embodiment, the material of the spacer 22 corresponds to the material of the pre-processed wafer 11. For example, when the pre-processed wafer 11 is a silicon carbide wafer, a graphite spacer 22 can be used; when the pre-processed wafer 11 is an aluminum nitride wafer, a tungsten spacer 22 can be used. Furthermore, the material of the entire processing fixture 2 and the material of the spacer 22 also correspond. For example, when the pre-processed wafer 11 to be processed is a silicon carbide wafer, a graphite processing fixture 2 can be used, with a graphite density ≥ 1.7 g / cm³. When the pre-processed wafer 11 to be processed is an aluminum nitride wafer, a tungsten processing fixture 2 can be used. In this embodiment, the function of the gasket 22 is to ensure heat conduction while preventing the pre-processed wafer 11 from directly contacting the bottom of the receiving tank 211 and contaminating the surface of the pre-processed wafer 11; secondly, compared with the tooling tray 21, the gasket 22 has better elasticity, and will not generate large stress due to the difference in thermal expansion coefficient between it and the pre-processed wafer 11 during the heating or cooling process.
[0083] Preferably, in this embodiment, the receiving groove 211 is columnar, and the projection of the gasket 22 along the axial direction of the receiving groove 211 coincides with the bottom area of the receiving groove 211. It should be understood that the gasket 22 repeatedly adheres to the bottom surface of the receiving groove 211 to prevent the gasket 22 from lifting up during the heating process.
[0084] In this embodiment, the opening edge of the receiving groove 211 is stepped, and a first stepped surface is provided on the opening edge of the receiving groove 211; the outer periphery of the tooling cover 23 is stepped, and a second stepped surface is provided on the outer periphery of the tooling cover 23. The second stepped surface seals and overlaps with the first stepped surface, thereby achieving a sealed connection of the tooling cover 23 to the opening of the receiving groove 211. Preferably, a sealing ring can be provided between the first stepped surface and the second stepped surface to improve the sealing performance.
[0085] Preferably, there are multiple tooling trays 21 and gaskets 22, each corresponding to the other. Multiple tooling trays 21 are stacked sequentially. The bottom of the upper tooling tray 21 is sealed and detachably connected to the opening of the receiving groove 211 of the lower tooling tray 21. Adjacent tooling trays 21 form a sealed cavity 24. A tooling cover 23 is sealed and detachably connected to the opening of the receiving groove 211 of the uppermost tooling tray 21. Because multiple tooling trays 21 are stacked sequentially, this processing fixture 2 can carry multiple wafer sets 1 at a time, increasing the number of wafers processed at once and improving processing efficiency. The number of tooling trays 21 can be adaptively designed according to usage requirements. In this embodiment, tooling trays 21 and tooling covers 23 can be connected by snap-fit connections.
[0086] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.
Claims
1. A wafer fabrication process, characterized in that, Includes the following steps: S1. Obtain two pre-processed wafers (11), each pre-processed wafer (11) including a contact surface (111) and a non-contact surface (112). After bonding the contact surfaces (111) of the two pre-processed wafers (11), a wafer group (1) is formed. S2. Place the wafer assembly (1) into the sealed cavity (24) of the processing fixture; S3. Perform heat treatment on the processing fixture and the wafer assembly (1) within the processing fixture; S4. Take the wafer group (1) out of the sealed cavity (24) and separate the two pre-processed wafers (11) to obtain the target wafer.
2. The wafer processing technology according to claim 1, characterized in that, In step S1, the pretreatment of the wafer includes the following steps: S11. Obtain the initial wafer; S12. Polish the contact surface (111) and non-contact surface (112) of the initial wafer to obtain a polished wafer; S13. Detect the surface roughness of the polished wafer and determine whether the surface roughness of the polished wafer is less than a preset roughness; if not, proceed to S12; if yes, proceed to S14. S14. The polished wafer after inspection is taken out to obtain the pre-treated wafer (11).
3. The wafer processing technology according to claim 1, characterized in that, In step S3, the heat treatment includes the following steps: S31. Heat the processing fixture and the wafer assembly (1) within the processing fixture; S32. The processing fixture and the wafer group (1) within the processing fixture are kept in an inert gas environment with a preset heat preservation pressure for a preset time. S33. The processing fixture and the wafer group (1) within the processing fixture are cooled to a preset cooling temperature at a preset annealing rate.
4. The wafer processing technology according to claim 3, characterized in that, In step S31, heating the processing fixture and the wafer assembly (1) within the processing fixture includes the following steps: The processing fixture, together with the wafer assembly (1) inside it, which is at room temperature, is subjected to a first heating treatment at a heating rate of 4℃ / min to 5℃ / min to 990℃ to 1000℃; then a second heating treatment is performed at a heating rate of 2℃ / min to 3℃ / min to 1300℃ to 1500℃.
5. The wafer processing technology according to claim 3, characterized in that, In step S32, the preset insulation pressure is 50 kPa, the preset time is 28-30 minutes, and the inert gas environment is argon.
6. The wafer processing technology according to claim 3, characterized in that, In step S33, the preset annealing rate is 1℃ / min to 2℃ / min, and the preset cooling temperature is 25℃.
7. The wafer processing technology according to claim 1, characterized in that, The contact surface (111) is a silicon surface, and the non-contact surface (112) is a carbon surface.
8. A machining tooling, characterized in that, The wafer fabrication process described in any one of claims 1-7, wherein the fabrication fixture comprises: Tooling tray (21), wherein the tooling tray (21) is provided with a receiving groove (211); A gasket (22) is disposed in the receiving groove (211) and the gasket (22) is used to support the wafer assembly (1). A tooling cover (23) is sealed and detachably connected to the opening of the receiving groove (211), and the tooling cover (23) and the receiving groove (211) form a sealed cavity (24).
9. The machining tooling according to claim 8, characterized in that, The opening edge of the receiving groove (211) is stepped, and the opening edge of the receiving groove (211) is provided with a first stepped surface; the outer periphery of the tooling cover (23) is stepped, and the outer periphery of the tooling cover (23) is provided with a second stepped surface, and the second stepped surface is sealed and overlapped with the first stepped surface.
10. The machining tooling according to claim 8, characterized in that, The tooling tray (21) and the gasket (22) are multiple and correspond one-to-one. The multiple tooling trays (21) are stacked in sequence. The bottom of the upper tooling tray (21) is sealed and detachably connected to the opening of the receiving groove (211) of the lower tooling tray (21). The adjacent tooling trays (21) form the sealing cavity (24). The tooling cover (23) is sealed and detachably connected to the opening of the receiving groove (211) of the uppermost tooling tray (21).