Semiconductor device with vertical interconnection structure and preparation method thereof

Abstract

The invention discloses a semiconductor device with a vertical interconnection structure and a preparation method thereof, the semiconductor device is formed on a substrate, the substrate is provided with one or more device units, isolation grooves are arranged around the device units or between adjacent device units, and the isolation grooves are communicated with the substrate. Each device unit comprises an epitaxial layer arranged on the substrate, a vertical through hole penetrating through the epitaxial layer is formed in each device unit, and the vertical through hole extends to the surface of the substrate; the preparation method comprises the following step of forming the vertical through hole while forming the isolation groove. According to the preparation method of the semiconductor device with the vertical interconnection structure, the gallium nitride semiconductor device with the vertical interconnection structure can be prepared, and the preparation method is suitable for cascading devices, optimizing the packaging form, reducing the packaging complexity and saving the manufacturing cost of the devices.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a method for fabricating a gallium nitride semiconductor device including a vertical interconnect structure, and the semiconductor device fabricated using this method. Background Technology

[0002] As a third-generation semiconductor material, GaN has significant advantages over first-generation Si and second-generation GaAs semiconductor materials. AlGaN / GaN HEMTs possess a large band gap, high peak saturation electron velocity, high concentration of two-dimensional electron gas, and high electron mobility, making them commonly used in high-frequency and high-power electronic devices. AlGaN / GaN HEMTs are widely used in RF, microwave, and power switching power supplies, among other applications.

[0003] Traditional devices in the industry typically include at least 1-3 layers of interconnect metal leads in their vertical structure for wire bonding and packaging. The primary implementation is DUP (device under pad), where the device is located below the pad, making efficient use of the layout area. To reduce parasitic parameters caused by cascaded packaging, save area, and improve overall performance, a stacked packaging (die-on-die / Si on GaN) approach exists, where a conventional Si MOSFET is mounted on the source pad of a GaN HEMT. This stacked packaging method reduces parasitic parameters generated by the metal layer between the Si MOSFET drain and the GaN HEMT source. However, this stacked packaging method imposes design rule constraints on some layouts, preventing proper arrangement of electrode pads or resulting in excessively large device areas, increasing manufacturing costs.

[0004] To reduce the cost of GaN power devices and enhance their competitive advantage, the industry has introduced a vertical interconnect via structure. In silicon-based GaN devices, since the substrate is conductive, it can be connected to electrodes through vias. By combining this with packaging solutions, vertical interconnects can be achieved.

[0005] For example, patent CN113826206A discloses a vertical via in its integrated design of a III-nitride device, where the via structure is mainly formed below the gate electrode metal. The via is etched on the buffer layer, channel layer, barrier layer, and insulating layer below the gate electrode metal. The via size should not be too large; excessively large vias require a larger device area, increasing manufacturing costs; conversely, if the via is too small, "the gate electrode is at least partially formed in the via," increasing the device resistance.

[0006] For example, patent CN116075925A discloses a III-nitride device with a through-path structure, which has a path directly connected to the substrate below the electrode. However, this path is formed by etching alone, and the above-mentioned problems still exist. Moreover, the process is still not simple enough.

[0007] The above background information is provided only to aid in understanding the inventive concept and technical solution of this invention. It does not necessarily belong to the prior art of this invention. In the absence of clear evidence that the above information was disclosed before the filing date of this invention, the above background information should not be used to evaluate the novelty and inventiveness of this invention. Summary of the Invention

[0008] In view of this, in order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a method for fabricating a semiconductor device with a vertical interconnect structure, which simplifies the fabrication process, optimizes the packaging form, reduces packaging complexity, and saves device manufacturing costs.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: A method for fabricating a semiconductor device with a vertical interconnect structure, wherein the semiconductor device is formed on a substrate, the substrate has one or more device units, isolation trenches are provided around the device units or between adjacent device units, each device unit includes an epitaxial layer disposed on the substrate, and each device unit has a vertical via extending through the epitaxial layer, the vertical via extending to the surface of the substrate, and the vertical via extending in a vertical direction; the fabrication method includes the following steps: forming the vertical via while forming the isolation trench.

[0010] According to some preferred embodiments of the present invention, the device unit includes an electrode, and the vertical through-hole is filled with a connecting metal, the connecting metal being electrically connected to the electrode.

[0011] According to some preferred embodiments of the present invention, the depth of the vertical via is greater than or equal to the distance between the top surface of the electrode and the substrate. When the vertical via and the corresponding connected electrode are projected onto the plane where the substrate is located, the vertical via and the electrode are located at different positions, that is, the vertical via and the electrode are located on different vertical planes. The vertical via extends upward to above the electrode. One end of the connecting metal extends horizontally and contacts the top surface of the electrode, and the other end contacts the substrate.

[0012] According to some preferred embodiments of the present invention, the device unit further includes a passivation layer stacked on the epitaxial layer, the vertical via penetrating the passivation layer; the connecting metal has the passivation layer outside, a portion of the passivation layer being located between the isolation trench and the vertical via, the portion of the passivation layer being used to protect the metal within the vertical via and to isolate the isolation trench and the vertical via.

[0013] According to some preferred embodiments of the present invention, the depth of the vertical via is equal to the distance between the bottom surface of the electrode and the substrate. When the vertical via and the corresponding connected electrode are projected onto the plane where the substrate is located, the vertical via and the electrode are located at the same position, that is, the vertical via and the electrode are located on the same vertical plane. One end of the connecting metal is in contact with the bottom surface of the electrode, and the other end is in contact with the substrate.

[0014] According to some preferred embodiments of the present invention, the device unit further includes a passivation layer stacked on the epitaxial layer, wherein the vertical via does not penetrate the passivation layer, that is, the vertical via and the connecting metal therein are only located in the epitaxial layer of the device, or, when the substrate is a non-conductive substrate, the vertical via and the connecting metal therein also need to penetrate the substrate to connect with the back metal.

[0015] According to some preferred embodiments of the present invention, the electrode includes a source electrode, a drain electrode, and a gate electrode, the substrate has a vertical via, and the connecting metal in the vertical via is electrically connected to one of the source electrode, the drain electrode, and the gate electrode (the substrate may be conductive or non-conductive); the substrate has multiple vertical vias, and different vertical vias and their connecting metals are connected to different electrodes (only non-conductive substrates are allowed).

[0016] According to some preferred embodiments of the present invention, the epitaxial layer includes a buffer layer, a channel layer and a barrier layer sequentially disposed on the substrate, and the electrode is located above the barrier layer.

[0017] According to some preferred embodiments of the present invention, the substrate is a conductive material, the vertical through-hole extends to the upper surface of the substrate, and the connecting metal is in contact with the substrate.

[0018] According to some preferred embodiments of the invention, the substrate is a non-conductive material, the vertical through-hole penetrates the substrate and extends to the lower surface of the substrate, and the connecting metal passes through the lower surface of the substrate and is exposed.

[0019] According to some preferred embodiments of the invention, the lower surface of the substrate has a back metal, which is connected to the electrode together with a connecting metal or a conductive substrate.

[0020] Specifically, the substrate can be either conductive or non-conductive: 1) Conductive substrate The substrate can only have one vertical via, and the connecting metal within the vertical via is electrically connected to one of the source, drain, and gate electrodes. The vertical via extends to the upper surface of the substrate, and the connecting metal contacts the upper surface of the substrate. The back side (lower surface) of the substrate has a back metal, which is electrically connected to the electrodes through the conductive substrate and the connecting metal within the vertical via.

[0021] 2) Non-conductive substrate A vertical via penetrates the substrate and extends to its lower surface, with connecting metal passing through and exposed on the lower surface. The lower surface of the substrate has a back metal, which is connected to the electrodes via the connecting metal within the vertical via. In this case, the substrate may have one or more vertical vias. When multiple vertical vias are present, different vias and their connecting metals connect different electrodes, which are separated by patterning of the back metal.

[0022] According to some preferred embodiments of the present invention, the device unit has an active region and an active region, and the vertical via is formed in the active region.

[0023] According to some preferred embodiments of the present invention, the substrate is a highly N-type doped substrate, which is exposed after the isolation trench is etched, and then polysilicon is grown on the substrate surface in the isolation trench region, and then N-type ions are implanted to make its doping concentration lower than that in the substrate to form an N-region.

[0024] According to some preferred embodiments of the present invention, the location of the isolation trench is patterned, a portion of the substrate with low doping concentration is etched away, and an electrode metal is grown so that the electrode metal simultaneously connects the N- region and the N+ type substrate; finally, the back side of the substrate is metallized to form a back metal electrode.

[0025] According to some preferred embodiments of the present invention, the substrate is a highly N-type doped substrate. After the front-side process is completed, polysilicon is grown on the lower surface of the substrate, and then N-type ion implantation is performed to make its doping concentration lower than that in the substrate, so as to form an N-region.

[0026] According to some preferred embodiments of the present invention, the location of the isolation trench is patterned, and a portion of the substrate with low doping concentration is etched away at the location corresponding to the vertical via; a back metal is fabricated thereon to form a back metal electrode, such that the back metal electrode covers the substrate and N-region corresponding to the location of the front via.

[0027] The present invention also provides a semiconductor device having a vertical interconnect structure prepared according to the above-described preparation method.

[0028] Due to the adoption of the above technical solutions, the advantages of the present invention compared with the prior art are as follows: the method for fabricating semiconductor devices with vertical interconnect structures of the present invention is simpler than the traditional fabrication method, can fabricate gallium nitride semiconductor devices containing vertical interconnect structures without sacrificing device area, is suitable for cascaded devices, optimizes packaging form, reduces packaging complexity, saves device manufacturing costs, and enhances the competitive advantage of products. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a top view of the semiconductor device in Embodiment 1 of the present invention; Figure 2 This is a three-dimensional structural diagram of the semiconductor device in Embodiment 1 of the present invention; Figure 3 This is a schematic cross-sectional view of the semiconductor device fabrication process corresponding to step S3 in Embodiment 1 of the present invention; Figure 4 This is a schematic cross-sectional view of step S4 in the semiconductor device fabrication process of Embodiment 1 of the present invention; Figure 5 This is a schematic cross-sectional view of step S5 in the semiconductor device fabrication process of Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the cross-sectional structure after the second passivation layer is deposited and the first metal via is formed in step S6 during the semiconductor device fabrication process of Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the cross-sectional structure after filling the first metal via in the second passivation layer with metal in step S6 of the semiconductor device fabrication process in Embodiment 1 of the present invention. Figure 8 This is a schematic diagram of the cross-sectional structure after the deposition of the third passivation layer and the formation of the second metal via in step S7 of the semiconductor device fabrication process in Embodiment 1 of the present invention; Figure 9 This is a schematic diagram of the cross-sectional structure after filling the second metal via of the third passivation layer with metal in step S7 of the semiconductor device fabrication process in Embodiment 1 of the present invention. Figure 10 This is a schematic diagram of the cross-sectional structure after the deposition of the fourth passivation layer in step S8 during the semiconductor device fabrication process in Embodiment 1 of the present invention; Figure 11 This is a schematic diagram of the cross-sectional structure after the formation of the third metal via on the fourth passivation layer in step S8 during the semiconductor device fabrication process in Embodiment 1 of the present invention; Figure 12 This is a schematic cross-sectional view of step S9 in the semiconductor device fabrication process of Embodiment 1 of the present invention; Figure 13 This is a schematic cross-sectional view of the corresponding step S10 in the semiconductor device fabrication process of Embodiment 1 of the present invention; Figure 14 This is a schematic cross-sectional view of the corresponding step S11 in the semiconductor device fabrication process of Embodiment 1 of the present invention; Figure 15 This is a schematic diagram of the cross-sectional structure of the semiconductor device in Embodiment 1 of the present invention; Figure 16 for Figure 1 A schematic diagram of the cross-sectional structure corresponding to the mid-section BB; Figure 17 This is a circuit diagram corresponding to the semiconductor device in Embodiment 2 of the present invention; Figure 18 This is a schematic diagram of the cross-sectional structure of the semiconductor device in Embodiment 3 of the present invention; Figure 19 This is a schematic diagram of the cross-sectional structure of the semiconductor device in Embodiment 4 of the present invention; Figure 20 This is a top view of the semiconductor device in Embodiment 5 of the present invention; Figure 21 This is a schematic diagram of the cross-sectional structure of the semiconductor device in Embodiment 5 of the present invention; Figure 22 This is a schematic diagram of the cross-sectional structure of the semiconductor device in Embodiment 6 of the present invention; Figure 23 This is a schematic diagram of the cross-sectional structure of the semiconductor device in Embodiment 7 of the present invention; Figure 24 This is a schematic diagram of the cross-sectional structure of the semiconductor device in Embodiment 8 of the present invention; In the attached figures, the reference numerals include: substrate-1, buffer layer-2, channel layer-3, barrier layer-4, source contact-51, drain contact-52, first passivation layer-6, first gate-7, second passivation layer-8, first source electrode metal-91, first drain electrode metal-92, first gate electrode metal-93, third passivation layer-10, second electrode metal-11, fourth passivation layer-12, third electrode metal-13, fifth passivation layer-14, back metal electrode-15, active region-161, non-active region-162, isolation trench-163, first metal via-17, second metal via-18, third metal via-19, vertical via-20, substrate via-21, N-region-22, resistor-23, diode-24. Detailed Implementation

[0031] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0032] Due to the distribution of high-voltage and low-voltage electrodes between device electrodes, the (horizontal) spacing between electrodes needs to be increased to prevent breakdown between them. However, existing via structures require additional area to form the vias, wasting some layout area. For traditional stacked device structures, in order to accommodate a large-area Si MOSFET, the source pad area of ​​GaN HEMT is large. This greatly limits the size and distribution of the top layer metal of the drain and gate electrodes, resulting in high series resistance in the metal interconnect structure. Consequently, the resistance per unit area of ​​the entire chip increases, increasing the manufacturing cost of the device.

[0033] When all electrodes of a device are arranged on the same side, a certain (horizontal) distance needs to be maintained between the high and low voltage electrodes to prevent electrode breakdown. Due to the requirements of device current, packaging bonding, etc., the top layer is usually set with 2 to 3 thick metal layers. Covering the insulating passivation layer on the thick metal layer becomes a problem. The isolation effect between two thick metal layers will be greatly reduced. This necessitates thickening the insulating passivation layer between the metal layers. The layered passivation layer also makes it more difficult to form vias. Lateral erosion of the passivation layer will cause the sidewalls of the formed vias to have a large slope. On the other hand, too small a via size not only makes it difficult to form vias, but also increases the resistance of the device.

[0034] To address the problems existing in the prior art, this invention provides a method for manufacturing a vertical through-hole structure for GaN power devices, mainly solving the fabrication of through-hole structures and the shortcomings of existing technologies. In this invention, the lateral erosion of the passivation layer creates a sidewall slope, enabling the isolation trench to be etched into the through-hole in one step, connecting the through-hole to the isolation trench. The inclined morphology of the through-hole improves metal connectivity.

[0035] The semiconductor device with a vertical interconnect structure of the present invention is formed on a substrate, the substrate having one or more device cells, and isolation trenches being provided around the device cells or between adjacent device cells. Each device cell includes an epitaxial layer disposed on the substrate, and a vertical via extending through the epitaxial layer is formed within each device cell, extending to the surface of the substrate. In this invention, the vertical interconnect structure is defined as follows: a vertical via perpendicular to the device (substrate) is formed on the semiconductor device, and a connecting metal is disposed within the vertical via, thereby achieving interconnection between the front-side structure and the back-side metal electrode through the vertical via and the connecting metal therein. The device cell has an active region and an active region, and the vertical via is formed in the active region.

[0036] The device unit includes electrodes, and a connecting metal within a vertical via is electrically connected to the electrodes. In this invention, the connection structure between the vertical via, the electrodes, and the substrate has the following two possibilities: 1) The vertical through-hole extends upwards to above the electrode that needs to be electrically connected: The depth of the vertical via is greater than or equal to the distance between the top surface of the electrode and the substrate. When the vertical via and the corresponding connected electrode are projected onto the plane where the substrate is located, the vertical via and the electrode are located at different positions, that is, the vertical via and the electrode are located on different vertical planes. The vertical via extends upward to the top of the electrode. One end of the connecting metal extends horizontally towards the electrode and contacts the top surface of the electrode, while the other end contacts the substrate.

[0037] 2) The vertical through-hole extends upwards to the bottom of the electrode that needs to be electrically connected: The depth of the vertical via is equal to the distance between the bottom surface of the electrode and the substrate. When the vertical via and the corresponding connected electrode are projected onto the plane where the substrate is located, the vertical via and the electrode are located in the same position, that is, the vertical via and the electrode are located in the same vertical plane. One end of the connecting metal is in contact with the bottom surface of the electrode, and the other end is in contact with the substrate.

[0038] In one configuration, the substrate is made of conductive material, and a vertical via extends to the upper surface of the substrate. A connecting metal contacts the substrate, and the substrate contacts the back metal. In another configuration, the substrate is made of non-conductive material, and a vertical via penetrates the substrate and extends to the lower surface. A connecting metal passes through the lower surface of the substrate and is exposed, allowing it to contact the back metal. Specifically, when the substrate is conductive, the connection structure between the vertical via and the electrode and substrate can be either the first or second configuration described above; when the substrate is non-conductive, the connection structure between the vertical via and the electrode and substrate can only be the second configuration described above.

[0039] The epitaxial layer includes a buffer layer, a channel layer, and a barrier layer sequentially disposed on the substrate, with the electrode located above the barrier layer. The device unit also includes a passivation layer stacked on the epitaxial layer. In the first case described above, the vertical via at least penetrates a portion of the passivation layer; in the second case described above, the vertical via does not penetrate the passivation layer, as in Example 6 below where the vertical via does not penetrate the passivation layer.

[0040] In the first scenario described above, a protective layer is provided outside the connecting metal. Part of the protective layer is located between the isolation trench and the vertical via. The protective layer is formed simultaneously with the passivation layer, dividing the etching process into the isolation trench and the vertical via. The protective layer is essentially a part of the passivation layer, which protects the metal within the vertical via and isolates the isolation trench and the vertical via.

[0041] Meanwhile, the electrodes include a source electrode, a drain electrode, and a gate electrode, and the connecting metal is electrically connected to at least one of the source electrode, drain electrode, and gate electrode, depending on whether the substrate is conductive. 1) Conductive substrate The substrate can only have one vertical via, and the connecting metal within the vertical via is electrically connected to one of the source electrode S, drain electrode D, and gate electrode G. The vertical via extends to the upper surface of the substrate, and the connecting metal contacts the upper surface of the substrate. The back side (lower surface) of the substrate has a back metal, which is electrically connected to the electrodes through the conductive substrate and the connecting metal within the vertical via.

[0042] 2) Non-conductive substrate A vertical via penetrates the substrate and extends to its lower surface, with connecting metal passing through and exposed on the lower surface. The lower surface of the substrate has a back metal, which is connected to the electrodes via the connecting metal within the vertical via. In this case, the substrate may have one or more vertical vias. When multiple vertical vias are present, different vias and their connecting metals connect different electrodes, which are separated by patterning of the back metal.

[0043] Based on the structure of the semiconductor device with the vertical interconnect structure described above, the method for fabricating the semiconductor device of the present invention includes the following steps: forming a vertical via while forming an isolation trench.

[0044] Example 1: As Figures 1 to 15 As shown, the GaN HEMT power device structure with a vertical via structure in this embodiment includes a substrate 1 and an epitaxial layer arranged sequentially from bottom to top. The substrate can be Si or one or more combinations of other conductive materials. The epitaxial layer sequentially includes a buffer layer 2, a channel layer 3, and a barrier layer 4. The buffer layer 2 can be composed of one or more combinations of materials such as gallium nitride, aluminum nitride, and aluminum gallium nitride. The channel layer 3 is made of group III nitride materials such as GaN, AlGaN, AlN, and AlGaInN. Above the channel layer 3 is the nitride barrier layer 4, thus forming a complete semiconductor epitaxial layer structure, and a high concentration of two-dimensional electron gas can be formed at the heterojunction interface between the channel layer and the barrier layer to generate a conductive channel. The active region 161 of the device can be formed on the conductive channel by etching or implantation, and the electrode metal and other structures described below are disposed on the active region 161. Figure 1 This is a top view schematic diagram of the semiconductor device in this embodiment. Figure 2 This is a three-dimensional structural diagram of the semiconductor device in this embodiment. Figure 15 It is along Figure 1 or Figure 2 The diagram shows a cross-sectional structure cut along the direction indicated by the dashed line AA.

[0045] The fabrication method of the GaN HEMT power device with a vertical through-hole structure in this embodiment specifically includes the following steps: Step S1: Prepare substrate: Prepare p-type substrate 1, which is a conductive substrate 1 in this embodiment.

[0046] Step S2: Fabrication of the epitaxial layer: GaN buffer layer 2, AlGaN channel layer 3, and barrier layer 4 are sequentially grown on the substrate using techniques such as MOCVD. A two-dimensional electron gas is formed at the interface between channel layer 3 and barrier layer 4.

[0047] Step S3, prepare source contact 51 and drain contact 52: as follows Figure 3 As shown, source and drain contact regions are formed on barrier layer 4 by dry etching. Metal is deposited in the source and drain contact regions, and ohmic contacts (source contact 51 and drain contact 52) ​​are formed by RTA annealing.

[0048] Step S4: Forming the active region of the device: such as Figure 4 As shown, the active region 161 of the device is formed by destroying part of the binary electron gas through ion implantation.

[0049] Step S5, Depositing the first passivation layer and fabricating the first gate: as follows Figure 5As shown, a first passivation layer 6 is deposited, and a gate region is formed on the first passivation layer 6 by wet etching. Metal is sputtered and etched to cover the gate region to form a first gate 7. The gate controls the conductive channel (the position between the source contact 51 and the drain contact 52) ​​by applying a voltage to form an electric field. Therefore, the gate does not need to be in direct contact with the conductive channel. The source contact 51 to the drain contact 52 must be formed first, and then the gate is formed between the source and the drain.

[0050] Step S6: Deposit the second passivation layer and form the first electrode metal: as shown in the figure. Figures 6 to 7 As shown, a second passivation layer 8 is deposited, which is located between the source / drain electrode, the gate electrode 7, and the first electrode metal.

[0051] Dry etching is performed on the second passivation layer 8, stopping above the source contact 51, drain contact 52, and first gate 7, to form three first metal vias 17 corresponding to the source, drain, and gate electrodes, respectively. First electrode metal is sputtered onto the surface and etched to fill and cover the three first metal vias 17, forming the first source electrode metal 91, the first drain electrode metal 92, and the first gate electrode metal 93, respectively.

[0052] The source contact 51 is connected to the first source electrode metal 91, the drain contact 52 is connected to the first drain electrode metal 92, and the gate is connected to the first gate electrode metal 93, wherein the first source electrode metal, the first drain electrode metal, and the first gate electrode metal are not connected to each other.

[0053] Step S7: Deposit the third passivation layer and form the second electrode metal: as shown Figures 8 to 9 As shown, a third passivation layer 10 is deposited, which is located on the second passivation layer 8 and between the first electrode metal and the second electrode metal 11.

[0054] Dry etching is performed on the third passivation layer 10, stopping above the first source electrode metal 91, the first drain electrode metal 92, and the first gate electrode metal 93, respectively forming three corresponding second metal vias 18 (the second metal via 18 corresponding to the first drain electrode metal 92 is located above the first drain electrode metal 92). Figure 8 (Not shown in the image). The second electrode metal 11 is sputtered onto the surface and etched to fill and cover the three second metal vias 18, forming the second source electrode metal, the second drain electrode metal, and the second gate electrode metal, respectively.

[0055] The first source electrode metal 91 is connected to the second source electrode metal, the first drain electrode metal 92 is connected to the second drain electrode metal, and the first gate electrode metal 93 is connected to the second gate electrode metal, wherein the second source electrode metal, the second drain electrode metal, and the second gate electrode metal are not connected to each other.

[0056] Step S8, Deposit the fourth passivation layer: as follows Figures 10 to 11As shown, a fourth passivation layer 12 is deposited, which is located on the third passivation layer 10 and between the second electrode metal 11 and the third electrode metal 13.

[0057] Dry etching is performed on the fourth passivation layer 12, stopping above the second source electrode metal, the second drain electrode metal, and the second gate electrode metal, forming three corresponding third metal vias 19 (the third metal vias 19 corresponding to the second drain electrode metal are located in...). Figure 11 (Not shown in the image).

[0058] Step S9, Etching isolation trenches and vertical vias: (e.g.) Figure 12 As shown, wet etching and dry etching respectively etch away the passivation layer and epitaxial layer at the isolation trench location, so that the etching of the isolation trench 163 stops on the surface of the Si substrate 1. At the same time as the isolation trench 163 is etched, a vertical via 20 is etched between the isolation trench 163 and the active region 161 of the device (i.e., the non-active region 162). At this time, the vertical via 20 is connected to the isolation trench 163.

[0059] Step S10: Sputtering metal and forming the third electrode metal: such as Figure 13 As shown, the third electrode metal 13 is sputtered and etched to fill and cover the third metal via 19 and vertical via 20 corresponding to the gate electrode in step S8, forming the third source electrode metal, the third drain electrode metal, and the third gate electrode metal. The second source electrode metal is connected to the third source electrode metal, the second drain electrode metal is connected to the third drain electrode metal, and the second gate electrode metal is connected to the third gate electrode metal. However, the third source electrode metal, the third drain electrode metal, and the third gate electrode metal are not connected to each other. Furthermore, the third metal via 19 corresponding to the gate electrode and the vertical via 20 are connected to the same third gate electrode metal, that is, the connecting metal in the vertical via 20 is the third gate electrode metal. In terms of shape, the connecting metal extends upward from the upper surface of the substrate 1 to above the second gate electrode metal, then extends horizontally towards the second gate electrode metal, then enters the third metal via 19 corresponding to the gate electrode and extends downward to the upper surface connected to the second gate electrode metal, thus realizing the connection between the substrate 1 and the gate electrode.

[0060] In this embodiment, after the etching of the third metal via 19 in step S8 is completed, an isolation trench 163 is etched in the non-active region 162 between devices, and a vertical via 20 is formed simultaneously with the etching of the isolation trench 163. The vertical via 20 can be one or more. The vertical via 20 and the isolation trench 163 are interconnected, and the GaN on the Si surface is etched away, stopping at the Si substrate 1 surface. Then, a third electrode metal is grown, and through etching, a third source electrode and a third drain electrode are formed. The third gate electrode fills the vertical via 20 and the corresponding third metal via 19 of the gate electrode, so that the third gate electrode is connected to the conductive Si substrate through the vertical via 20 and the metal therein.

[0061] Step S11, Deposit the fifth passivation layer: as follows Figure 14 As shown, a fifth passivation layer 14 is deposited, which is located above the third electrode metal 13.

[0062] Dry etching is performed on the fifth passivation layer 14, stopping above the third source electrode metal and the third drain electrode metal, to form the source electrode and drain electrode of the device, respectively; simultaneously, it extends into the isolation trench 163 to cover the side portion (connecting metal) of the third gate electrode metal, so as to isolate the isolation trench 163 from the vertical via 20 (third gate electrode metal). The third gate electrode metal is entirely covered by the fifth passivation layer 14 (protective layer).

[0063] That is, the fifth passivation layer 14 covers the third gate electrode and forms the front source and drain electrodes on the device to connect to the external package wires.

[0064] The second passivation layer 8, the third passivation layer 10, the fourth passivation layer 12, and the fifth passivation layer 14 can be formed by deposition processes and can be planarized by chemical mechanical polishing (CMP). All of the above passivation layers serve to insulate and isolate different electrodes, and include one or more combinations of SiN, SiO2, SiON, and Al2O3.

[0065] Step S12, Deposit backside metal: After the frontside process is completed, the backside of the Si substrate is thinned by mechanical grinding and polishing.

[0066] like Figure 15 As shown, titanium (Ti), nickel (Ni), and silver (Ag) are sequentially evaporated on a Si substrate to form a back metal electrode 15. The back metal electrode 15 is electrically connected to the third gate electrode metal through a conductive substrate and a vertical via. The back metal electrode is the final gate electrode of the device. The above structure and method can reduce packaging costs, on-resistance, switching inductance, and packaging complexity, and improve device performance and reliability.

[0067] The semiconductor device with a vertical interconnect structure in this embodiment forms the source, drain, and gate on a Si-based GaN device. The device is formed through multilayer metal interconnects. Between the metal layers, CMP (chemical mechanical polishing) is used to smooth the interlayer dielectric, which makes the device morphology smooth. On the other hand, the planarized passivation layer makes the thick metal coverage morphology better, and for the same dielectric thickness, the device has stronger voltage withstand capability after CMP.

[0068] Conventional through-hole structures require the development of new deep-hole etching processes, which are typically large in size, incompatible with device area, and pose certain risks in metal filling. This embodiment forms vertical through-holes by simultaneously etching the device and the isolation trench, reducing device manufacturing steps and making the formation of vertical through-holes simpler and more efficient.

[0069] In this embodiment, a third electrode metal fills a vertical via and connects the electrode to the Si substrate. Because the vertical via is connected to the isolation trench, the via's slanted shape improves metal connectivity. The electrode is connected to the back metal electrode 15 via the vertical via, and the back metal electrode 15 is connected to the packaging frame via conductive adhesive, reducing packaging complexity and improving device performance.

[0070] Example 2: When using a Si substrate 1 with a high N-type doping concentration, integrated devices can optionally be present in the device containing the gate vertical via structure. Specifically, based on the device of Example 1, a Si substrate 1 with a high N-type doping concentration is used. After etching the isolation trench, the Si substrate 1 is exposed. Subsequently, a layer of polysilicon (5~10µm thick) is grown on the substrate surface in the isolation trench 163 region. Then, a small amount of N-type ion implantation is performed to reduce its doping concentration to below that of the Si substrate, thereby forming the N-region 22. Figure 16 As shown, Figure 16 for Figure 1 A schematic diagram of the cross-sectional structure corresponding to the mid-section BB.

[0071] In other embodiments, a highly doped N-type Si substrate 1 can be selected first, and a thin layer of lightly doped N-epitaxial layer can be grown first. Then, the steps in Embodiment 1 can be followed until the isolation trench 163 is etched and the lightly doped N-epitaxial layer is exposed.

[0072] like Figure 16 As shown, the isolation trench positions are patterned, a portion of the lightly doped Si substrate 1 is etched away, and a third electrode metal is grown, so that the third electrode metal simultaneously connects the N- region 22 and the N+ type Si substrate 1. Finally, the back side of the substrate is metallized to form the back gate metal electrode.

[0073] like Figure 17 The diagram shows a schematic of a GaN device with a vertical via structure according to this embodiment. Due to the contact characteristics of metal and semiconductor, a potential barrier with rectification characteristics is formed on the contact surface between the third electrode metal and the N-Si above N-Si. Simultaneously, the third electrode metal forms an ohmic contact with the N-substrate. The metal electrode 15 on the back of the device forms another ohmic contact with the substrate 1, forming the cathode of the Schottky diode 24 and the other electrode of the resistor 23, respectively. The diode 24 and resistor 23 are connected in parallel. The substrate resistor 23 can be designed with different resistivity substrates based on the substrate thickness after thinning, electrode size, and other requirements.

[0074] Based on diode characteristics, when a Schottky diode is forward biased, the potential barrier is low, forming a charged state. When reverse biased, current is difficult to pass through, forming a cutoff state. Using a gate resistor can balance switching speed and switching losses, control the gate charging and discharging speed, and limit the current flowing into the device, thus protecting it from excessive current damage. Simultaneously, integrated modules reduce the manufacturing cost of external modules.

[0075] Example 3: As Figure 18 As shown, this embodiment provides another gallium nitride power device. After the vertical via 20 is formed, a third electrode metal 13 is grown, and etched to form a third source electrode, a third drain electrode, and a third gate electrode. The third source electrode fills the vertical via 20 and the third metal via 19, allowing the third source electrode to be connected to the conductive Si substrate through the vertical via 20. A fifth passivation layer 14 is grown and partially etched to cover the third gate electrode and form a front gate electrode and a drain electrode on top of the device to connect to external package leads. Then, a back metal electrode 15 is fabricated, connecting the back metal electrode 15 to the source electrode through the vertical via. The remaining steps, such as the growth of the epitaxial layer, are basically the same as in Embodiment 1.

[0076] Unlike traditional cascaded devices, this embodiment can be paired with custom Si MOSFETs, and medium and large on-resistance devices can achieve reverse stacking (GaN on Si) packaging, which greatly saves the packaging cost of the devices.

[0077] Example 4: Figure 19 As shown, this embodiment provides another gallium nitride power device. After the vertical via 20 is formed, a third electrode metal 13 is grown, and etched to form a third source electrode, a third drain electrode, and a third gate electrode. The third drain electrode fills the vertical via 20 and the corresponding metal via, allowing the third drain electrode to connect to the conductive Si substrate through the vertical via 20. A fifth passivation layer 14 is grown and partially etched to cover the third drain electrode and form a front gate electrode and a source electrode on top of the device to connect to external package leads. Then, a back metal electrode 15 is fabricated; the back metal electrode 15 is connected to the drain electrode through the vertical via. The remaining steps, such as the growth of the epitaxial layer, are basically the same as in Embodiment 1.

[0078] Example 5: Figures 20 to 21 As shown, the fabrication method of the GaN HEMT power device with a vertical through-hole structure in this embodiment specifically includes the following steps: Step S1: Prepare the substrate: Prepare a p-type substrate. The substrate can be other conductive materials such as Si or non-conductive materials such as sapphire.

[0079] Step S2: Fabrication of the epitaxial layer: GaN buffer layer 2, channel layer 3, and AlGaN barrier layer 4 are sequentially grown using techniques such as MOCVD. A two-dimensional electron gas is formed at the interface between channel layer 3 and barrier layer 4.

[0080] Step S3, Etching the isolation trench and vertical via: Dry etching is used to remove the epitaxial layer at the location of the isolation trench, exposing the substrate to form the isolation trench 163; at the same time, substrate etching is performed at the locations below the source contact 51, drain contact 52 and source contact 51 of the corresponding device to form the vertical via 20.

[0081] A conductive substrate can only have one type of via structure on a device; a non-conductive substrate can selectively have one or more types. The following process only describes the source via structure.

[0082] Step S4: Prepare source and drain contacts: The source and drain contact regions are formed on the barrier layer 4 by dry etching. The source and drain contact regions are formed by metal deposition and RTA annealing process to form source contact 51 and drain contact 52 respectively. At the same time, the metal is filled in the vertical via 20.

[0083] Step S5: Form the active region of the device; Step S6: Deposit the first passivation layer and prepare the first gate; Step S7: Deposit the second passivation layer and form the first electrode metal; Step S8: Deposit the third passivation layer and form the second electrode metal; Step S9: Deposit the fourth passivation layer, which is basically the same as in Example 1, and will not be described again here.

[0084] Step S10: Deposit back metal: Thin the back side of the Si substrate by mechanical grinding and polishing; at the same time, etch the substrate via 21 at the position corresponding to the vertical via 20 on the front side. The size of the substrate via 21 can be greater than or equal to the via 20. The etching of the substrate via 21 stops at the lower surface of the via 20.

[0085] Titanium (Ti), nickel (Ni), and silver (Ag) are evaporated on a Si substrate to form a back metal electrode 15. At the same time, the metal fills the interior of the substrate via 21, so that the back metal electrode 15 is electrically connected to the source electrode metal through the substrate via 21, the vertical via 20 and the connecting metal inside. The back metal electrode is the final source electrode of the device.

[0086] Because there are conductive channels between the S / D ohmic contacts, such as Figure 21As shown, a small portion of the device electrodes are formed outside the active region, ensuring that the two-dimensional electron gas of the epitaxial layer beneath the vertical via 20 and a small surrounding area is disrupted, allowing the via to form an electrical connection only with the electrodes. Finally, metallization is performed on the back side of the device, connecting the back metal with the metal in the vertical via 20 and the substrate via 21, forming the back electrode. Alternatively, the back metal can be patterned to form a multi-metal back electrode. Depending on the type of back electrode selected, the front metal and passivation layers can be appropriately reduced, simplifying the process.

[0087] In this embodiment, regardless of whether the substrate is conductive, the electrodes can be connected to the back electrode via vias. Simultaneously, deep hole etching on the back side connects the electrodes to the back electrode, eliminating the need for additional layers of interconnect metal to prevent breakdown between the high and low voltage electrodes. This not only significantly reduces the manufacturing cost of the device's front-side structure but also lowers the metal resistance, giving the device a stronger competitive advantage.

[0088] Example 6: As Figure 22 As shown, the difference between the GaN HEMT power device with vertical through-hole structure in this embodiment and Embodiment 5 is that the formed back metal electrode is the final drain electrode of the device, that is, the vertical through-hole and the connecting metal inside it are located below the drain electrode.

[0089] The remaining structure and preparation steps are basically the same as in Example 5.

[0090] Example 7: As Figure 23 As shown, the difference between the GaN HEMT power device with vertical through-hole structure in this embodiment and Embodiment 5 is that the formed back metal electrode is the final gate electrode of the device, that is, the vertical through-hole and the connecting metal inside it are located below the gate electrode.

[0091] After the vertical via 20 is formed, source and drain contacts are prepared, but the source and drain are not filled in the vertical via 20.

[0092] The active region of the device is formed by destroying part of the binary electron gas through ion implantation.

[0093] A first passivation layer 6 is deposited, and a gate region is formed on the first passivation layer 6 by wet etching. At the same time, the first passivation layer 6 in the vertical via 20 is etched away, so that the vertical via 20 is still exposed to the Si substrate 1. Metal is sputtered and etched so that the metal covers the gate region to form the first gate 7. At the same time, the metal fills the vertical via 20 to form the connection metal.

[0094] The remaining structure and preparation steps are basically the same as in Example 5.

[0095] Example 8: As Figure 24As shown, this embodiment uses a Si substrate 1 with a high N-type doping concentration. The device containing the gate vertical via structure may also selectively contain integrated devices, and the integrated devices and preparation steps are basically the same as those in Embodiment 2.

[0096] Based on the device of Example 1, a Si substrate 1 with a high N-type doping concentration is used (steps S2-S11 are the same as in Example 1). After the front-side process is completed, the back side of the Si substrate 1 is thinned by mechanical grinding and polishing. On the thinned side of the Si substrate, a layer of polysilicon (5-10 μm thick) is grown, and then a small amount of N-type ion implantation is performed to reduce its doping concentration to be lower than that of the Si substrate 1, thereby forming an N-region 22. The isolation trench positions are patterned, and a portion of the low-doped Si substrate 1 is etched away at the positions corresponding to the vias. A back metal electrode 15 is formed on the Si substrate 1, so that the back metal electrode 15 covers the Si substrate 1 and the N-region 22 corresponding to the positions of the front vias.

[0097] Currently known vias are all formed in back layers, with a very thick accumulated passivation layer (insulating layer). The thickness of the underlying epitaxial layer is equal to the via depth. The via depth / size is the aspect ratio; the larger the aspect ratio, the more difficult it is to implement the via. In this invention, the vias are connected to isolation trenches, resulting in a considerably large size without requiring additional area for the vias. The vertical via structure and manufacturing method of the GaN power device of this invention focus on the formation of the vertical vias and the connection method between the electrode metal and the substrate. The electrodes are connected to the substrate through deep-hole etching in the isolation trenches, simplifying the etching process. The GaN device is based on a conductive substrate, and metal patterning is performed on the back side of the device, allowing the device electrodes to connect to the back metal layer through vias to form back metal electrodes, reducing the packaging complexity of cascaded devices. Vertical vias include gate vias (TGV), source vias (TSV), and drain vias (TDV). When the substrate is conductive, only one vertical via exists; when the substrate is non-conductive, one or more vertical vias can exist through back metal patterning. Vertical vias allow for connection of the back electrode to the source, drain, and gate electrodes. Back-side patterning also enables multiple electrodes to be connected to the back side, facilitating double-sided assembly of the device. Furthermore, TGV allows for the integration of diodes and resistors on the substrate to control switching speed and protect circuitry.

[0098] The above embodiments prepared by the method of the present invention are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device with a vertical interconnect structure, characterized in that, The semiconductor device is formed on a substrate, the substrate having one or more device units, isolation trenches being formed around the device units or between adjacent device units, each device unit including an epitaxial layer disposed on the substrate, each device unit having a vertical via extending through the epitaxial layer, the vertical via extending to the surface of the substrate, the vertical via extending in a vertical direction; the device unit including an electrode, the vertical via being filled with a connecting metal, the connecting metal being electrically connected to the electrode; the fabrication method includes the following steps: forming the vertical via simultaneously with forming the isolation trench.

2. The preparation method according to claim 1, characterized in that, The depth of the vertical via is greater than or equal to the distance between the top surface of the electrode and the substrate. When the vertical via and the corresponding connected electrode are projected onto the plane of the substrate, the vertical via and the electrode are located at different positions. The vertical via extends upward above the electrode. One end of the connecting metal extends horizontally and contacts the top surface of the electrode, while the other end contacts the substrate.

3. The preparation method according to claim 2, characterized in that, The device unit further includes a passivation layer stacked on the epitaxial layer, and the vertical via penetrates the passivation layer; the connecting metal has the passivation layer on its exterior, and a portion of the passivation layer is located between the isolation trench and the vertical via.

4. The preparation method according to claim 1, characterized in that, The depth of the vertical via is equal to the distance between the bottom surface of the electrode and the substrate. When the vertical via and the corresponding connected electrode are projected onto the plane where the substrate is located, the vertical via and the electrode are located in the same position. One end of the connecting metal is in contact with the bottom surface of the electrode, and the other end is in contact with the substrate.

5. The preparation method according to claim 1, characterized in that, The substrate is made of a conductive material, the vertical through-hole extends to the upper surface of the substrate, and the connecting metal is in contact with the substrate.

6. The preparation method according to claim 5, characterized in that, The electrode includes a source electrode, a drain electrode, and a gate electrode. The substrate has a vertical via, and the connecting metal in the vertical via is electrically connected to one of the source electrode, the drain electrode, and the gate electrode.

7. The preparation method according to claim 1, characterized in that, The substrate is a non-conductive material, the vertical through-hole penetrates the substrate and extends to the lower surface of the substrate, and the connecting metal passes through the lower surface of the substrate and is exposed.

8. The preparation method according to claim 7, characterized in that, The electrode includes a source electrode, a drain electrode, and a gate electrode. The substrate has a vertical via, and the connecting metal in the vertical via is electrically connected to one of the source electrode, the drain electrode, and the gate electrode; or, the substrate has multiple vertical vias, and different vertical vias and their connecting metals are connected to different electrodes.

9. The preparation method according to claim 1, characterized in that, The lower surface of the substrate has a back metal, which is connected to the electrode via a connecting metal or a conductive substrate and the connecting metal.

10. The preparation method according to claim 1, characterized in that, The device unit has an active region and an active region, and the vertical via is formed in the active region.

11. The preparation method according to claim 1, characterized in that, The substrate is a highly N-type doped substrate. After the isolation trench is etched, the substrate is exposed. Then, polysilicon is grown on the substrate surface in the isolation trench region. N-type ions are implanted to make the doping concentration lower than that in the substrate to form an N-region. The isolation trench is patterned, a portion of the substrate with low doping concentration is etched away, and electrode metal is grown so that the electrode metal simultaneously connects the N- region and the N+ type substrate; finally, the back side of the substrate is metallized to form a back metal electrode.

12. The preparation method according to claim 1, characterized in that, The substrate is a highly N-type doped substrate. After the front-side process is completed, polycrystalline silicon is grown on the lower surface of the substrate, and then N-type ion implantation is performed to make its doping concentration lower than that in the substrate, so as to form an N-region. The isolation trench position is patterned, and a portion of the substrate with low doping concentration is etched away at the position corresponding to the vertical via. A back metal is then fabricated on it to form a back metal electrode, which covers the substrate and N-region corresponding to the position of the front via.

13. A semiconductor device having a vertical interconnect structure prepared by the preparation method according to any one of claims 1-12.

Images