Method for processing embedded multi-chip interconnection bridging groove of IC (integrated circuit) support plate
By employing laser ablation technology and substrate pretreatment processes, the problems of dielectric layer thickness fluctuation and size limitations in controlled depth milling were solved, enabling high-precision machining of embedded multi-chip interconnection bridging grooves on IC carrier boards. This ensures groove depth and position accuracy, improving machining quality and reliability.
Patent Information
- Application Number
- CN202511750987.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-03-03
AI Technical Summary
Existing controlled depth milling technology is limited by the thickness fluctuation of the dielectric layer and the processing size in the processing of bridging grooves for embedded multi-chip interconnects on IC carrier boards, resulting in insufficient processing accuracy and difficulty in meeting high precision requirements.
The groove processing is carried out by laser ablation method. Through substrate pretreatment, copper surface roughening and organic film preparation, lamination and copper blackening, combined with CO2 laser ablation technology, the depth is controlled by utilizing the optical properties of the dielectric layer, eliminating equipment errors, and achieving burr-free and high-precision processing.
The groove processing achieved a depth accuracy of ±0 μm and a position accuracy within 5 μm, significantly improving processing accuracy and yield, avoiding the risks of mechanical stress and chemical penetration, and meeting the insulation requirements of high-density interconnect structures.
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Figure CN121604831A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of substrate processing technology, specifically relating to a method for processing embedded multi-chip interconnection bridging grooves on an IC substrate. Background Technology
[0002] In the current semiconductor packaging technology field, the fabrication of embedded multi-chip interconnect bridging grooves on IC substrates plays a crucial role. The core of this fabrication method lies in achieving efficient and reliable connections between chips to support increasingly complex and high-performance integrated circuit systems. Currently, controlled depth milling technology is widely used in the groove fabrication process on IC substrates due to its high precision and flexibility. However, despite the many advantages of controlled depth milling technology, certain technical challenges remain in practical operation.
[0003] First, minute fluctuations in the thickness of the dielectric layer become one of the key factors limiting the machining accuracy of the groove. Because the dielectric layer may be affected by various factors such as material properties and process conditions during production, its thickness is difficult to maintain absolutely consistent. This fluctuation is directly reflected in the depth control of the groove machining, resulting in the groove depth specification only meeting a tolerance range of ±50µm.
[0004] Furthermore, the limitations of processing dimensions are also a problem that cannot be ignored. In the micro-nano scale processing environment, any tiny deviation can have a significant impact on the performance of the final product.
[0005] In summary, although controlled depth milling technology plays a crucial role in the fabrication of bridging grooves for embedded multi-chip interconnects on IC substrates, its machining accuracy is still affected by fluctuations in dielectric layer thickness and limitations in machining dimensions. Therefore, how to further optimize the machining process and improve machining accuracy has become an important issue that urgently needs to be addressed in the current semiconductor packaging technology field. Summary of the Invention
[0006] The technical problem to be solved by this application is to overcome the shortcomings of the prior art and provide a method for processing embedded multi-chip interconnection bridging grooves on IC carrier boards. This application uses laser ablation to process the grooves, resulting in fewer foreign objects, no burrs, and the ablation depth is controlled by the layer structure, eliminating equipment errors.
[0007] The technical solution adopted in this application to solve the problems existing in the prior art is: A method for fabricating embedded multi-chip interconnect bridging grooves on an IC substrate includes the following steps: S01, Substrate pretreatment; SO2, copper surface roughening and organic film preparation; S03, lamination; S04, copper layer blackening; S05, Groove machining.
[0008] Furthermore, in step S01, the substrate is cut to the size to be processed, and an ink spraying device is used to spray a layer of ink on the bonding layer of the substrate at the location where the chip needs to be installed.
[0009] The inkjet printing process uses a graphic target on the printed layer itself for positioning.
[0010] UV lamps are used to cure the ink, isolating the copper surface at the joint from the outside environment.
[0011] Furthermore, in step S01, the formation process of the graphic target is as follows: A photosensitive film is applied to the surface of the substrate, and the non-circuit areas are cured with a UV lamp. The photosensitive film in the circuit areas is peeled off, and copper is plated in the circuit areas to form copper circuits. During the formation of copper circuits, a ring-shaped target is formed around the area to be processed for subsequent processing positioning and identification.
[0012] Furthermore, in step S02, an organic chemical solution is used during roughening to etch the substrate surface, forming an uneven surface using the "anchor bolt" principle to increase the contact area.
[0013] Using chemical solutions, an organic film is formed on the uneven surface, which bonds with copper to further increase the bonding force with copper.
[0014] Furthermore, in step S03, after stacking PP and copper foil on the roughened copper surface, the material is placed into a hydraulic press for lamination.
[0015] Furthermore, in step S04, an oxidant and a catalyst are used to chemically react with the copper surface, causing the copper layer on the surface of the layer to be processed to blacken.
[0016] Furthermore, in step S04, sodium chlorite solution is used as an oxidant and sodium phosphate as a catalyst.
[0017] Furthermore, in step S05, the target of the layer to be processed is used for positioning, and the position to be processed is precisely laser-ablated. The laser ablation reaches the connecting layer to complete the groove processing.
[0018] Compared with the prior art, the beneficial effects of this application are as follows: (1) Laser ablation produces no burrs and far fewer foreign objects than milling cutter processing. It can also be removed by plasma cleaning, resulting in a clean and tidy product.
[0019] (2) Laser ablation eliminates the risk of tearing and the risk of chemical seepage. Laser ablation stops at the connecting layer, and the ablation depth is determined by the layer structure. This eliminates the equipment's ablation depth error, and the groove processing depth specification is ±0um. The equipment's processing position accuracy is within 5um, and the error is much smaller than that of traditional controlled depth milling. Attached Figure Description
[0020] The present application will be further described below with reference to the accompanying drawings and embodiments.
[0021] Figure 1 This is a flowchart of a method for fabricating an embedded multi-chip interconnection bridging groove on an IC carrier board according to this application. Detailed Implementation
[0022] The accompanying drawings provide a more detailed description of a method for fabricating an embedded multi-chip interconnection bridging groove on an IC carrier board, but this is not intended to limit the scope of the application.
[0023] A method for fabricating embedded multi-chip interconnect bridging grooves on an IC substrate includes the following steps: S01, Substrate pretreatment: The substrate is cut to the size to be processed, and an inkjet printing device is used to spray a layer of ink onto the bonding layer of the substrate at the location where the chip needs to be installed. The inkjet printing process uses a graphic target on the printed layer itself for positioning. The formation process of the graphic target is as follows: A photosensitive film is applied to the surface of the substrate, and the non-circuit areas are cured with a UV lamp. The photosensitive film in the circuit areas is peeled off, and copper is plated in the circuit areas to form copper circuits. During the formation of copper circuits, a ring-shaped target is formed around the area to be processed for subsequent processing positioning and identification.
[0024] UV lamps are used to cure the ink, isolating the copper surface at the joint from the outside environment.
[0025] The ink is selected from epoxy-based or polyimide-based high-performance inks, which have excellent high-temperature resistance and chemical resistance. Specific specifications are as follows: ① High temperature resistance: thermal decomposition temperature ≥250°C, can be stable for a long time in a lamination environment at 180°C; ② Chemical resistance: No swelling, peeling or chemical degradation was observed during the 500-hour test at 85°C / 85%RH; ③ Electrical insulation: Volume resistivity ≥ 10¹² Ω·cm.
[0026] This type of ink ensures effective isolation of the copper surface in subsequent processes, preventing oxidation and contamination.
[0027] The thickness of the cured ink release layer is controlled within the range of 5–20 μm, preferably 10 μm. The effects of different thicknesses are as follows: ① Thickness < 5 μm: Insufficient isolation effect; the copper surface is easily corroded during roughening or blackening, leading to a decrease in connection reliability; ② Thickness 10 μm: Optimal balance, providing sufficient isolation without affecting lamination bonding strength and laser ablation accuracy; ③ Thickness > 20 μm: May hinder the flow of PP material during lamination, leading to a decrease in interfacial bonding strength and an increase in laser ablation energy requirements.
[0028] Experimental data show that when the thickness is 10 μm, the isolation layer does not carbonize or peel off during laser ablation.
[0029] The ink layer will not peel off or carbonize and contaminate the grooves during laser ablation for the following reasons: ①After UV curing, the ink forms a highly cross-linked polymer network with high thermal stability; ②Laser ablation uses short pulses and high energy density parameters to instantly vaporize the ink instead of carbonizing it; ③ The vaporization products can be completely removed by subsequent plasma cleaning, ensuring the cleanliness of the groove. Furthermore, the chemical inertness of the isolation layer effectively prevents reaction with the substrate, avoiding the introduction of impurities. By optimizing the laser scanning path and energy density, the heat-affected zone is further reduced, ensuring precise and controllable ablation process. Actual testing shows that the groove sidewalls are smooth and residue-free, meeting the insulation requirements of high-density interconnect structures. This process has been stably applied in mass production, significantly improving the yield rate.
[0030] Experimental verification showed that under the conditions of energy density of 3 J / cm² and pulse frequency of 20 kHz, the ink layer was completely vaporized, with no residue on the groove surface and smooth sidewalls.
[0031] S02, Copper surface roughening and organic film preparation: During roughening, organic solutions are used to etch the substrate surface, creating an uneven surface using the "anchor" principle to increase the contact area. Chemical solutions are then used to form an organic film on the uneven surface, which bonds with copper to further increase the adhesion to copper.
[0032] Organic solution: sodium persulfate system, concentration 80 g / L, treatment time 40 seconds, temperature 40°C; Micro-etching treatment: sulfuric acid-hydrogen peroxide system, sulfuric acid concentration 10% (v / v), hydrogen peroxide concentration 5% (v / v), treatment time 20 seconds; Surface roughness: Ra 1.2-1.8 μm after roughening, Ra 0.8–1.2 μm after micro-etching; Adhesion test: After roughening and micro-etching combined treatment, the adhesion between the copper surface and the PP layer reached 1.2–1.5 kgf / cm².
[0033] Chemical solution: γ-aminopropyltriethoxysilane coupling agent, concentration 3% (w / w), treatment time 15 seconds; Formation mechanism: The silane coupling agent forms covalent bonds on the copper surface, enhancing the interfacial bonding force; Film thickness: 0.1–0.3 μm, uniformly covering uneven surfaces.
[0034] In this application, γ-aminopropyltriethoxysilane (with the chemical structural formula NH2-(CH2)3-Si-(OC2H5)3) is used as the precursor of the organic film. The mechanism by which it forms an organic film on the copper surface and achieves high-strength bonding is a multi-step chemical-physical process, mainly including hydrolysis, condensation, coordination bonding and covalent bonding, and finally constructs a stable "molecular bridge" between the inorganic phase on the copper surface and the organic phase of the subsequently laminated PP resin.
[0035] Its bonding mechanism can be explained in detail as follows: 1. Hydrolysis of silane molecules The ethoxy group (-OC2H5) in the γ-aminopropyltriethoxysilane molecule undergoes a hydrolysis reaction upon contact with water: This reaction converts the hydrophobic ethoxy group into a hydrophilic silanol (-Si-OH), generating the reactive γ-aminopropyltrisilol.
[0036] 2. Forms an interfacial bond with the copper substrate. The roughened and micro-etched copper surface is not perfectly smooth; microscopically, it is an activated surface rich in hydroxyl groups (-OH) and copper oxide / copper hydroxide. Silanol molecules bind to the copper surface through two main mechanisms: ① Initial adsorption is characterized by hydrogen bonding: a strong hydrogen bond network is formed between the silanol groups (-Si-OH) on the silane molecule and the hydroxyl groups (Cu-OH) on the copper surface, which enables the silane molecules to be initially and tightly adsorbed on the copper surface.
[0037] ② Coordination bonding (key enhancement): The amino group (-NH2) at the end of the silane molecule has a lone pair of electrons, which can act as an electron donor, reacting with copper ions (Cu). 2+ Alternatively, copper atoms can form coordinate bonds through empty orbitals. This coordination is much stronger than physical adsorption, significantly enhancing the anchoring strength of silane molecules on the copper surface.
[0038] 3. Condensation of silanols and film formation The silane molecules adsorbed on the copper surface undergo further condensation reactions at their silanol groups, forming a stable three-dimensional network polymer film with Si-O-Si as the main chain, which firmly covers the uneven structure of the copper surface. Meanwhile, the remaining silanol groups will also condense with the hydroxyl groups on the copper surface to form strong Cu-O-Si covalent bonds, which is one of the core chemical bonds for achieving high bonding strength.
[0039] 4. Chemical bonding with PP resin to form a "molecular bridge". During the subsequent SO3 lamination process, the epoxy groups of the polymers such as epoxy resin in PP will undergo a ring-opening reaction with the amino-NH2 at the other end of the silane molecule when heated and molten, forming a strong covalent bond.
[0040] In summary, γ-aminopropyltriethoxysilane achieves its "molecular bridge" function through its unique bifunctional structure: one silanol end tightly binds to the inorganic phase of the copper surface via hydrogen bonds, coordination bonds, and Cu-O-Si covalent bonds; the other amino end chemically reacts with the organic phase of PP resin via covalent bonds. This chemical bonding at the "inorganic-organic" interface, combined with the "anchor" physical interlocking effect generated by the roughening treatment, synergistically increases the bonding force between the copper surface and PP resin from 0.6–0.9 kgf / cm² in traditional methods to 1.2–1.5 kgf / cm² in this application, significantly improving the reliability of the encapsulation structure and its resistance to moisture and heat, as well as its resistance to thermal cycling.
[0041] ①Limitations of single coarsening treatment Existing technologies only use a sodium persulfate system for roughening, resulting in a copper surface adhesion of approximately 0.6-0.8 kgf / cm². This leads to issues such as uneven surface roughness (Ra 1.2-1.8 μm) and insufficient interfacial adhesion. Under high temperature and humidity testing (85℃ / 85%RH), delamination occurs at a rate exceeding 15% after 500 hours. While micro-etching using a sulfuric acid-hydrogen peroxide system achieves better surface uniformity (Ra 0.8-1.2 μm), the adhesion is only 0.7-0.9 kgf / cm², with limited peel strength. Under thermal cycling testing (-55℃~125℃), the risk of interfacial failure is significant after 1000 cycles.
[0042] ② The innovative advantages of this application's combined roughening and micro-etching treatment The bonding strength is increased to 1.2-1.5 kgf / cm², with an improvement rate of over 60%; the surface roughness is optimized to Ra 1.0-1.5μm, improving uniformity; no delamination was observed after 1000 TCT reliability tests; the synergistic enhancement of "anchor effect + chemical bonding" is achieved, effectively suppressing interface failure.
[0043] S03, Lamination: After PP and copper foil are stacked on the roughened copper surface, they are placed in a hydraulic press. Under high temperature and high pressure, PP reaches a critical state, which enhances its fluidity, fills the gaps between the underlying patterns, and makes the roughened copper and copper foil tightly bonded.
[0044] ①PP thickness range 50–100 μm, preferably 60~80 μm, glass transition temperature Tg≥170°C; ② Copper foil thickness: 3μm + 18μm carrier copper foil or 5μm + 18μm carrier copper foil; ③Lamination conditions: temperature 200~250°C, pressure 3 MPa, time 90 minutes.
[0045] Under high temperature and pressure, PP has enhanced fluidity, fully filling the gaps in the underlying pattern and achieving a tight bond with the roughened copper surface.
[0046] S04, Copper layer blackening: Sodium chlorite solution is used as an oxidant and sodium phosphate as a catalyst to react chemically with the copper surface, causing the copper layer on the surface of the layer to be processed to blacken, resulting in a rough and black surface.
[0047] S05, Groove machining: Using a target based on the pattern of the layer to be processed, precise laser ablation is performed on the desired location. The laser energy and pulse parameters are adjusted, and laser ablation is used to complete the groove fabrication up to the connecting layer.
[0048] Laser type: CO2 laser; Energy density: 5 – 15 J / cm², precisely calibrated based on dielectric layer material and thickness; Pulse frequency: 10 – 50 kHz, using high-frequency pulse mode to reduce the heat-affected zone; Scanning speed: 100 – 500 mm / s; Spot diameter: 30 – 60 μm, adjustable according to the required groove width; Pulse width: 10 – 50 μs, short pulse mode is beneficial for thermal control.
[0049] Sidewall roughness: Ra < 1.5 μm Depth tolerance: ±0 μm is controlled by the connecting layer; Position accuracy: ±10 μm; Heat-affected zone (HAZ) depth: <15 μm CO2 laser light can be efficiently absorbed by the organic dielectric layer in an IC substrate, but its reflectivity on metallic copper exceeds 95%. This physical characteristic constitutes the fundamental principle of depth control in this application: The laser energy is absorbed by the dielectric layer, causing it to vaporize and decompose instantaneously through a photothermal effect, thus etching the grooves. When the ablation reaches the bottom copper interconnect layer, most of the laser energy is reflected, and the ablation process automatically terminates.
[0050] Layered structure as a "physical stop": This process is determined by the optical properties of the material itself, rather than by the travel or time control of the equipment, thus completely eliminating the depth error of the equipment and achieving a depth tolerance of ±0 μm.
[0051] The wavelength of a CO2 laser matches the vibrational energy level of polymer molecular bonds, achieving efficient photothermal ablation through resonant absorption. This directly transforms the material from a solid to a gaseous state, significantly reducing molten residue. Although CO2 laser processing may produce a small amount of carbonized residue, this can be completely removed through subsequent oxygen plasma cleaning, ensuring cleanliness and good wettability of the groove sidewalls and bottom.
[0052] Therefore, CO2 laser processing is highly efficient and suitable for removing grooves containing a certain volume of dielectric layer. The purchase and maintenance costs of CO2 lasers are typically lower than those of ultraviolet lasers of the same power. Similar to non-contact laser processing, it avoids the mechanical stress and microcracks associated with milling cutters. Inheriting the core advantage of depth control through layered structures, its precision is far superior to depth-controlled milling.
[0053] It has no burrs, few foreign objects, and no risk of drug seepage.
[0054] S06. Chip embedding and packaging: Using a patterned target for positioning, the chip is embedded in the pre-machined groove. After the chip is embedded, subsequent layer stacking and packaging are performed.
[0055] After the chip is embedded, automated optical inspection (AOI) and X-ray inspection are added.
[0056] The graphic target localization method includes the following steps: While forming the copper pattern of the circuit layer, a copper pattern target is simultaneously formed around the area to be processed. The pattern target is designed as a ring, cross, square, or dot matrix shape with a clearly defined central feature, with a linewidth of 50-100 μm and an outer diameter of 200-500 μm. Because the target processing and pattern processing are performed simultaneously, the target and the circuit layer have inherent positional accuracy, eliminating accumulated errors.
[0057] During target identification, a machine vision system is employed to acquire high-contrast images of the target through coaxial illumination. Subpixel image processing algorithms are then used to precisely extract the geometric center coordinates of the target, achieving a positioning accuracy better than ±1μm. Simultaneously, the equipment features multi-coordinate system transformation and motion compensation, establishing a mapping relationship between the camera coordinate system, machine coordinate system, and substrate coordinate system. It calculates the deviation (ΔX, ΔY, Δθ) between the actual and theoretically designed target positions and drives a high-precision motion platform for real-time compensation, achieving precise alignment of the processing position. Furthermore, by setting multiple graphic targets on the substrate and performing global position calculations, translation, rotation, and scaling errors can be compensated simultaneously, ensuring consistent positioning throughout the entire processing area.
[0058] This invention combines a proprietary copper target synchronized with the circuit, sub-pixel visual recognition, and multi-coordinate system compensation to form a closed-loop high-precision positioning system. This method overcomes the shortcomings of traditional external marking or single alignment methods, such as insufficient accuracy and susceptibility to process interference, providing crucial positioning assurance for achieving micron-level processing of embedded grooves on IC substrates and chip embedding.
[0059] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.
Claims
1. A method for processing embedded multi-chip interconnection bridging grooves on an IC substrate, characterized in that, Includes the following steps: S01, Substrate pretreatment; SO2, copper surface roughening and organic film preparation; S03, lamination; S04, copper layer blackening; S05, Groove machining.
2. The method for processing embedded multi-chip interconnection bridging grooves on an IC carrier board according to claim 1, characterized in that: In step S01, the substrate is cut to the size to be processed, and an ink spraying device is used to spray a layer of ink on the bonding layer of the substrate at the location where the chip needs to be installed. The inkjet printing process uses a graphic target on the printed layer itself for positioning; UV lamps are used to cure the ink, isolating the copper surface at the joint from the outside environment.
3. The method for processing embedded multi-chip interconnection bridging grooves on an IC carrier board according to claim 2, characterized in that: In step S01, the formation process of the graphic target is as follows: A photosensitive film is applied to the surface of the substrate, and the non-circuit areas are cured with a UV lamp. The photosensitive film in the circuit areas is peeled off, and copper is plated in the circuit areas to form copper circuits. During the formation of copper circuits, a ring-shaped target is formed around the area to be processed for subsequent processing positioning and identification.
4. The method for processing embedded multi-chip interconnection bridging grooves on an IC carrier board according to claim 1, characterized in that: In step S02, an organic chemical solution is used during roughening to etch the substrate surface, forming an uneven surface using the "anchor bolt" principle to increase the contact area. Using chemical solutions, an organic film is formed on the uneven surface, which bonds with copper to further increase the bonding force with copper.
5. The method for processing embedded multi-chip interconnect bridging grooves on an IC carrier board according to claim 1, characterized in that: In step S03, after stacking PP and copper foil on the roughened copper surface, the material is placed into a hydraulic press for lamination.
6. The method for processing embedded multi-chip interconnect bridging grooves on an IC carrier board according to claim 1, characterized in that: In step S04, an oxidant and a catalyst are used to chemically react with the copper surface, causing the copper layer on the surface of the layer to be processed to blacken.
7. The method for processing embedded multi-chip interconnect bridging grooves on an IC carrier board according to claim 6, characterized in that: In step S04, sodium chlorite solution is used as an oxidant and sodium phosphate as a catalyst.
8. The method for processing embedded multi-chip interconnect bridging grooves on an IC carrier board according to claim 1, characterized in that: In step S05, the target of the layer to be processed is used for positioning, and the position to be processed is precisely laser-ablated. The laser ablation reaches the connecting layer to complete the groove processing.