Chip stacking structure, manufacturing method thereof, chip packaging structure and electronic equipment

Abstract

The invention provides a chip stacking structure, a manufacturing method thereof, a chip packaging structure and electronic equipment. The chip stacking structure comprises a first chip, at least one second chip and a supporting structure. Each second chip is located between the first chip and the supporting structure. The first chip is electrically connected with the second chips, and the supporting structure is connected with the second chips. An integrated passive device is arranged in the supporting structure, and the integrated passive device is electrically connected with at least one second chip; and / or the integrated passive device is electrically connected with the first chip. In the embodiment of the invention, the integrated passive device is integrated into the supporting structure, so that the integrated passive device, the second chip and the first chip can be stacked in the vertical direction, the interconnection distance between the second chip and / or the first chip and the integrated passive device can be greatly reduced, the integration level of the chip stacking structure is improved, the manufacturing cost is reduced, and moreover, the chip stacking structure is suitable for large-scale popularization and application. The substrate utilization rate of the supporting structure can be improved, and the internal structure of the chip stacking structure is reasonably utilized.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a chip stacking structure, its manufacturing method, chip packaging structure and electronic device. Background Technology

[0002] As Moore's Law gradually reaches its limits, chip packaging technology is increasingly moving towards three-dimensional (3D) stacking. In the post-Moore's Law era, 3D stacked chip packaging has provided the industry with a new "performance / size ratio" solution, finding widespread application in high-performance computing, high-bandwidth storage, and mobile communication miniaturization.

[0003] Currently, 3D stacking technology includes various stacking methods such as die-to-die (D2D) stacking, die-to-wafer (D2W) stacking, and wafer-to-wafer (W2W) stacking. However, in existing die-to-wafer (D2W) stacking structures, the chip and integrated passive device (IPD) are packaged independently, and interconnected through wiring in the substrate (or interposer). The chip and IPD are arranged planarly on the substrate (or interposer), resulting in relatively long interconnection distances between them. Furthermore, in chip packaging structures that include chip stacking structures and substrates (interposers), each chip and IPD occupy area of ​​the substrate (or interposer), leading to a larger chip packaging structure with lower integration density, which is detrimental to the miniaturization and lightweighting of chip packaging structures. Summary of the Invention

[0004] This application provides a chip stacking structure, its fabrication method, a chip packaging structure, and an electronic device, which can shorten the interconnection distance between the chip and integrated passive devices, reduce the area overhead of the substrate (or interposer) in the chip packaging structure, and improve the integration of the chip packaging structure.

[0005] In a first aspect, embodiments of this application provide a chip stacking structure, which may include a first chip, at least one second chip, and a support structure integrating integrated passive devices (IPDs). Each second chip is located between the first chip and the support structure. The first chip is electrically connected to each second chip; exemplarily, the first chip and the second chip can be electrically connected via hybrid bonding, or via soldering or other methods. The support structure is connected to each second chip; for example, the support structure and each second chip can be connected via hybrid bonding or fusion bonding. Fusion bonding refers to bonding two interfaces through a dielectric material, while hybrid bonding refers to bonding two interfaces through a dielectric material and a metallic material. The support structure contains integrated passive devices, which are electrically connected to at least one second chip; and / or, the integrated passive devices are electrically connected to the first chip. The integrated passive devices may include passive devices such as resistors, capacitors, and inductors, as well as interconnect structures connected to the passive devices. The passive devices can function to transmit signals, store energy, filter signals, etc. Integrated passive components can adjust the power supply and signals, and then provide the adjusted power supply and signals to the second chip and / or the first chip. Furthermore, integrated passive components can also shield against electromagnetic interference, providing better electromagnetic protection for the second or first chip and preventing external electromagnetic signals from interfering with it.

[0006] In related technologies, the support structure is a substrate without any function. For example, the support structure can be a silicon wafer without any devices or functions, resulting in low substrate utilization. In the chip stacking structure provided in this application, integrated passive devices are integrated into the support structure. On the one hand, this allows the integrated passive devices, the second chip, and the first chip to be stacked vertically (perpendicular to the surface of the first chip), significantly reducing the interconnection distance between the second chip and / or the first chip and the integrated passive devices. The second chip and / or the first chip and the integrated passive devices do not need to be interconnected through a substrate (or interposer), thereby reducing the area overhead of the substrate (or interposer). Furthermore, this reduces the volume of the chip packaging structure including the chip stacking structure and the substrate (or interposer), improving the integration of the chip packaging structure and reducing the cost of chip packaging. On the other hand, this application embodiment allows the support structure to have device functions, making reasonable use of the internal structure of the chip stacking structure. In addition, the support structure is generally a silicon wafer, and silicon material has high heat dissipation efficiency, giving the support structure a good heat dissipation effect. Therefore, the support structure can also play a role in heat equalization and enhanced heat dissipation.

[0007] In this embodiment, the second chip can be an unpackaged die, and can be a chip with various functions such as computing and storage. The chip stacking structure in this embodiment can include one or more second chips, and the number of second chips can be set according to actual needs. When the chip stacking structure includes more second chips, the specific implementation of other second chips can be referred to the description of this application. The first chip can be a wafer or a portion of a wafer cut. For example, the first chip can include semiconductor materials such as silicon and silicon carbide, and can be a chip with various functions such as computing and storage. The second chip is connected to the first chip by a hybrid bonding method, that is, the second chip and the first chip are stacked using a die-to-wafer hybrid bonding (D2W HB) method. The support structure can be a wafer or a portion of a wafer cut. For example, the support structure can include semiconductor materials such as silicon and silicon carbide. The support structure and the second chip can be connected by hybrid bonding or fused bonding.

[0008] In this embodiment, the support structure is relatively thick, which increases the overall thickness of the chip stack structure, thus enabling the support structure to function as a heat spreader. When the chip stack structure of this application is applied to an electronic device, a heat sink can be disposed on the side of the support structure opposite to the first chip, providing a heat conduction path between each second chip and the heat sink. Furthermore, the first chip may have a first surface and a second surface disposed opposite to each other. During the manufacturing process, at least one second chip is mounted on the first surface of the first chip, and the support structure is bonded to the side of each second chip opposite to the first chip. After completing the bonding of the second chips and the bonding of the support structure, in some cases, the second surface of the first chip can be thinned and further processed. The support structure can serve as a structural support for the thinning of the first chip and subsequent processes.

[0009] In one possible implementation, the support structure may include a first substrate and a first interconnect layer, the first interconnect layer being located on the side of the first substrate closer to the first chip. Exemplarily, the first substrate may include semiconductor materials such as silicon or silicon carbide. An integrated passive device is located on the first substrate near the first interconnect layer. The integrated passive device is electrically connected to at least one second chip via the first interconnect layer; and / or, the integrated passive device is electrically connected to the first chip via the first interconnect layer. In this embodiment, placing the integrated passive device in the first substrate near the first interconnect layer can shorten the vertical distance between the integrated passive device and the second chip (and / or the first chip), making it easier to interconnect the integrated passive device with the second chip (and / or the first chip), thereby simplifying the interconnect structure in the first interconnect layer.

[0010] In the embodiments of this application, the first interconnect layer and the second chip (and / or the first chip) can be interconnected in various ways. The interconnection methods between the first interconnect layer and the second chip are described in detail below.

[0011] Method 1:

[0012] In some embodiments of this application, a first interconnect layer has a first connection terminal on its surface near the first chip. The second chip may include a second substrate and a second interconnect layer, with the second interconnect layer located on the side of the second substrate near the first chip. That is, the second chip can be flip-chip mounted on the first chip. Of course, in some cases, the second chip can also be mounted upright on the first chip; the mounting method of the second chip is not limited here. The second substrate may include semiconductor materials such as silicon or silicon carbide; for example, the second substrate may be a silicon wafer. A first conductive via is provided in the second chip, extending from the surface of the second substrate near the support structure to the interior of the second interconnect layer, and the first conductive via is electrically connected to the second interconnect layer. In specific implementations, the second substrate may include silicon material, and the first conductive via may be a through-silicon via (TSV), which may include metal materials such as copper or tungsten. The first connection terminal is electrically connected to the end of the first conductive via near the support structure. By providing a first conductive via in the second chip, the first conductive via can connect the second interconnect layer to the surface of the second substrate near the support structure, thus shortening the interconnection distance between the second chip and the first interconnect layer.

[0013] In a specific configuration, a first dielectric film is disposed on the side of the first interconnect layer near the second chip, and the first connection terminal is exposed through a via in the first dielectric film. A second dielectric film is disposed on the side of the second chip near the support structure, and the end of the first conductive via is exposed through a via in the second dielectric film. The second dielectric film on the surface of the second chip is bonded to the first dielectric film on the surface of the support structure, and the first connection terminal is bonded to the end of the first conductive via, thereby achieving a hybrid bonding between the second chip and the support structure.

[0014] Method 2:

[0015] In some embodiments of this application, the first interconnect layer has a first connection terminal on its surface near the first chip. The second chip may include a second substrate and a second interconnect layer, with the second interconnect layer located on the side of the second substrate near the first chip. That is, the second chip can be flip-chip mounted on the first chip. Of course, in some cases, the second chip can also be mounted upright on the first chip; the mounting method of the second chip is not limited here.

[0016] The chip stack structure may further include a dielectric layer located between the first chip and the support structure, filling the space between the first chip and the support structure except for each of the second chips. Exemplarily, the dielectric layer may include an inorganic dielectric material such as silicon oxide. Conductive through dielectric vias (TDVs) are provided in the dielectric layer. One end of the TDV near the support structure is electrically connected to a first connection terminal, and the other end is electrically connected to a second interconnect layer and / or the first chip. In specific configurations, the TDV can directly contact and connect to the first connection terminal, or the TDV can be connected to the first connection terminal via an interconnect line. The TDV can be connected to the second interconnect layer and / or the first chip via an interconnect line. In this embodiment, by drilling holes in the dielectric layer to form conductive through dielectric vias, the first connection terminal and the second interconnect layer are electrically connected through the TDVs. Compared to the first method described above, the second method does not require drilling holes in the second chip, which simplifies the process flow of the second chip, increases the active area ratio of the second chip, and thus reduces costs.

[0017] In a specific configuration, a first dielectric film is disposed on the side of the first interconnect layer near the first chip, and the first connection terminal is exposed through a via in the first dielectric film. A second dielectric film is disposed on the side of the second chip near the support structure, and the dielectric via passes through the second dielectric film and bonds to the first connection terminal. Furthermore, the second dielectric film on the surface of the second chip is bonded to the first dielectric film on the surface of the support structure, so that the support structure is co-bonded with the underlying die and wafer stack structure (the stack structure formed by the second chip and the first chip).

[0018] Method 3:

[0019] In some other embodiments of this application, the first interconnect layer has a first connection terminal on its surface near the first chip, and the second chip may include a second substrate and a second interconnect layer, with the second interconnect layer located on the side of the second substrate near the first chip. That is, the second chip can be flip-chip mounted on the first chip. Of course, in some cases, the second chip can also be mounted upright on the first chip; the mounting method of the second chip is not limited here.

[0020] The chip stack structure may further include a bridge chip located between the first chip and the support structure. The bridge chip has a second conductive via penetrating through it. One end of the second conductive via near the support structure is electrically connected to a first connection terminal, and the other end is electrically connected to a second interconnect layer and / or the first chip. In specific implementations, the bridge chip may have one or more second conductive vias; the number of second conductive vias in the bridge chip can be set according to actual needs and is not limited here. The bridge chip and the second chip are arranged in a horizontal direction (parallel to the surface of the first chip), and the bridge chip may be disposed around the second chip, making the distance between the bridge chip and the second chip relatively close. In specific configurations, the second conductive via can be connected to the first connection terminal via interconnect lines, and the second conductive via can be connected to the second interconnect layer and / or the first chip via interconnect lines. In one possible implementation, the substrate of the bridge chip includes silicon material, and the second conductive via can be a through-silicon via (TSV). Unlike the structure of the second chip, the bridging chip may not have an interconnect layer. Instead, it is formed by drilling holes in the substrate to create at least one second conductive via. In other words, the bridging chip does not have processing functions such as computing or storage; it serves to electrically connect the second interconnect layer of the second chip to the first connection terminal. In this embodiment, the bridging chip enables electrical connection between the first connection terminal and the second interconnect layer. Compared to the first method described above, this third method does not require drilling holes in the second chip, simplifying the manufacturing process, increasing the active area ratio of the second chip, and thus reducing costs. In this embodiment, the chip stacking structure may include one or more bridging chips. The number and location of the bridging chips can be set according to actual needs and are not limited here.

[0021] In a specific configuration, a first dielectric film is disposed on the side of the first interconnect layer closest to the second chip, and the first connection terminal is exposed through a via in the first dielectric film. A second dielectric film is disposed on the side of the second chip closest to the support structure, and the second conductive via in the bridging chip is electrically connected to the first connection terminal through an interconnect in the second dielectric film. Furthermore, the second dielectric film on the surface of the second chip is bonded to the first dielectric film on the surface of the support structure, so that the support structure is co-bonded with the underlying die and wafer stack structure (the stack structure formed by the second chip and the first chip).

[0022] In one possible implementation, the chip stack structure may include at least two second chips, with adjacent second chips electrically connected to different second conductive vias in a bridging chip. The bridging chip may be located between the two adjacent second chips. This allows the bridging chip to be closer to the two adjacent second chips, shortening the interconnection distance between the second chips and the first interconnect layer.

[0023] The above describes several interconnection methods between the first interconnect layer and the second chip and / or the first chip. In specific implementations, methods one to three can also be combined. For example, method one can be combined with method two, where a first conductive via is provided in the second chip, and a dielectric via is provided in the dielectric layer. Of course, in some cases, other interconnection methods can also be used between the first interconnect layer and the second chip and / or the first chip, and can be reasonably configured according to interconnection requirements.

[0024] In one possible implementation, the first chip may include a third substrate and a third interconnect layer, with the third interconnect layer located on the side of the third substrate closer to the support structure. Exemplarily, the third substrate may include semiconductor materials such as silicon or silicon carbide. A second connection terminal is disposed on the surface of the first chip near the support structure; that is, the third interconnect layer has a second connection terminal on its surface near the second chip, and the second interconnect layer has a third connection terminal on its surface near the first chip. The second connection terminal and the third connection terminal are electrically connected to enable interconnection between the second chip and the first chip. In a specific configuration, a third dielectric film is disposed on the side of the third interconnect layer near the second chip, and the second connection terminal is exposed through vias in the third dielectric film. A fourth dielectric film is disposed on the surface of the second chip near the first chip, and the third connection terminal is exposed through vias in the fourth dielectric film. The fourth dielectric film on the surface of the second chip is bonded to the third dielectric film on the surface of the third interconnect layer. Therefore, the second chip and the first chip are hybrid-bonded. In this embodiment, disposing the third interconnect layer on the side of the third substrate closer to the support structure allows for a shorter interconnection distance between the third interconnect layer and the second chip. Of course, in some cases, the third interconnect layer in the first chip can also be located on the side of the third substrate away from the support structure, which is not limited here.

[0025] Furthermore, a fourth connection terminal may be provided on the side of the first chip away from the support structure, and the fourth connection terminal is electrically connected to the third interconnect layer. When the chip stacking structure of this embodiment is applied to an electronic device, the chip stacking structure can be electrically connected to the circuit board via the fourth connection terminal.

[0026] Secondly, embodiments of this application also provide a method for fabricating a chip stacking structure. The method for fabricating a chip stacking structure provided in embodiments of this application may include:

[0027] Step 1: Place at least one second chip on top of the first chip and electrically connect each second chip to the first chip; wherein, the second chip is a diced die, and the second chip can be a chip with various functions such as computing and storage. The first chip can be a wafer or a portion of a wafer diced; for example, the first chip can include semiconductor materials such as silicon and silicon carbide, and the first chip can be a chip with various functions such as computing and storage. After bonding the second chip to the first chip, a die-to-wafer (D2W) stacked structure can be obtained.

[0028] Step 2: Place the support structure containing integrated passive devices on the side of each second chip facing away from the first chip, and connect the support structure to each second chip; wherein the integrated passive devices are electrically connected to at least one second chip; and / or, the integrated passive devices are electrically connected to the first chip. The support structure can be a wafer or a portion of a wafer cut off. For example, the support structure can include semiconductor materials such as silicon and silicon carbide. The integrated passive devices can include passive devices such as resistors, capacitors, and inductors, as well as interconnect structures connected to the passive devices. The passive devices can function to transmit signals, store energy, and filter signals. The integrated passive devices can adjust the power supply and signals, and provide the adjusted power supply and signals to the second chips. In addition, the integrated passive devices can also shield electromagnetic interference, so as to achieve better electromagnetic protection for the second chip or the first chip and avoid electromagnetic signals interfering with the second chip and the first chip.

[0029] In the chip stacking structure fabrication method provided in this application embodiment, by integrating passive devices into the support structure, on the one hand, the passive devices, the second chip, and the first chip can be stacked vertically (perpendicular to the surface of the first chip), which can significantly reduce the interconnection distance between the second chip and / or the first chip and the passive devices. The second chip and / or the first chip and the passive devices do not need to be interconnected through a substrate (or interposer), thereby reducing the area overhead of the substrate (or interposer) and lowering the fabrication cost of the chip stacking structure. Furthermore, the volume of the chip package structure including the chip stacking structure and the substrate (or interposer) can be reduced, improving the integration density of the chip package structure. On the other hand, the substrate utilization rate of the support structure can be improved, making better use of the internal structure of the chip stacking structure. In addition, the support structure is generally a silicon wafer, and silicon material has high heat dissipation efficiency, which can give the support structure a good heat dissipation effect. Therefore, the support structure can also play a role in heat equalization and enhanced heat dissipation.

[0030] Furthermore, after step one and before step two, the fabrication method in this application embodiment may further include: filling the gaps between the second chips with dielectric material to form a dielectric layer. Exemplarily, inorganic dielectric materials such as silicon oxide can be used to fabricate the dielectric layer. In some cases, after fabricating the dielectric layer, the back side of each second chip (the side of the second chip facing away from the first chip) can be planarized and thinned.

[0031] Based on the above description of the chip stacking structure, the first interconnect layer in the support structure and the second chip and / or the first chip can have multiple interconnection methods. The following describes in detail the fabrication method of the chip stacking structure with the above-mentioned method one to method three.

[0032] In some embodiments of this application, when the chip stacking structure has the structure described in Method 1 above, the fabrication method in these embodiments may specifically include:

[0033] The first chip may include a third substrate and a third interconnect layer. Exemplarily, the third substrate may include semiconductor materials such as silicon or silicon carbide. The second chip may include a second substrate and a second interconnect layer. Step one above may specifically include: placing the second chip on top of the first chip with the surface having the third interconnect layer facing upwards, and ensuring the second interconnect layer of the second chip faces the third interconnect layer. The second chip and the first chip are then hybrid-bonded to achieve electrical connection between the second interconnect layer and the third interconnect layer. In this embodiment, the second chip may be flip-chipped onto the first chip. In some cases, the second chip may also be mounted upright on the first chip; the mounting method of the second chip is not limited here. Furthermore, the third interconnect layer in the first chip is located on the side of the third substrate closer to the second chip, which can shorten the interconnection distance between the third interconnect layer and the second chip. Of course, in some cases, the third interconnect layer in the first chip may also be located on the side of the third substrate away from the second chip; this is not limited here.

[0034] In a specific configuration, the third interconnect layer has a second connection terminal on its surface near the second chip, and the second interconnect layer has a third connection terminal on its surface near the first chip. The second connection terminal and the third connection terminal are bonded together to interconnect the second chip and the first chip. In another specific configuration, the third interconnect layer has a third dielectric film on its surface near the second chip, and the second connection terminal is exposed through vias in the third dielectric film. The second chip has a fourth dielectric film on its surface near the first chip, and the third connection terminal is exposed through vias in the fourth dielectric film. The fourth dielectric film on the surface of the second chip is bonded to the third dielectric film on the surface of the third interconnect layer. Therefore, the second chip and the first chip are hybrid-bonded.

[0035] Following step one and preceding step two, the fabrication method in this embodiment may further include: drilling a hole in the second chip and filling the hole with a conductive material, such as a metal material filled using thin-film deposition or electroplating, to form a first conductive via extending from the surface of the second substrate away from the first chip to the interior of the second interconnect layer; wherein the first conductive via is electrically connected to the second interconnect layer. To facilitate bonding with the support structure, the first conductive via may protrude from the surface of the second substrate away from the first chip.

[0036] Alternatively, the second chip may have a first conductive via already formed in it before bonding the second chip to the first chip. After step one and before step two, the fabrication method in this embodiment may further include: thinning the surface of the second substrate away from the first chip to expose the first conductive via.

[0037] Then, a second dielectric film is formed on the second chip and the dielectric layer, and the end of the first conductive via is exposed through the via in the second dielectric film.

[0038] Next, a support structure is provided, which may include a first substrate and a first interconnect layer. The first interconnect layer has a first connection terminal on its surface facing away from the first substrate. Step two may specifically include: placing the support structure on top of the second chip, with the first interconnect layer of the support structure facing the second chip. The support structure is then bonded to each of the second chips, so that the first connection terminal is electrically connected to a first conductive via. In this embodiment, by providing a first conductive via in the second chip, the first conductive via can connect the second interconnect layer to the surface of the second substrate near the support structure, thus shortening the interconnection distance between the second chip and the first interconnect layer.

[0039] Furthermore, the support structure may also include a first dielectric film and a first connection terminal. The first dielectric film is located on the side of the first interconnect layer closer to the second chip, and the first connection terminal is electrically connected to the first interconnect layer and exposed through a via in the first dielectric film. During the bonding process in step two above, the second dielectric film on the surface of the second chip is bonded to the first dielectric film on the surface of the support structure, and the first connection terminal is bonded to the end of the first conductive via, so that the second chip and the support structure are co-bonded.

[0040] Following step two above, the fabrication method in this embodiment may further include: using a support structure as structural support, thinning the surface of the first chip away from the second chip. Additionally, a hole may be drilled in the third substrate, and conductive material may be filled into the formed hole to form a conductive via penetrating the third substrate. This conductive via can be electrically connected to the third interconnect layer. Then, a fourth connection terminal is formed on the first chip, which can be electrically connected to the third interconnect layer through the conductive via. During the thinning process of the first chip, the support structure can increase the total thickness of the entire chip stack structure, serving as structural support for the thinning of the first chip and subsequent processes. Of course, in some cases, the thinning process of the first chip can be omitted. For example, if the first chip is already thin, thinning is unnecessary; or if the third interconnect layer of the first chip is located on the side of the third substrate away from the support structure, thinning of the first chip may not be necessary.

[0041] In other embodiments of this application, when the chip stacking structure has the structure of Method Two described above, the fabrication method in the embodiments of this application may specifically include:

[0042] At least one second chip is placed on top of the first chip, and each second chip is electrically connected to the first chip. The specific connection method between the second chip and the first chip can be referred to the relevant description above, and will not be repeated here.

[0043] In step two above, dielectric material is filled into the gaps between the second chips to form a dielectric layer. For example, an inorganic dielectric material such as silicon oxide can be used to fabricate the dielectric layer. In some cases, after fabricating the dielectric layer, the back side of the second chip (the side of the second chip facing away from the first chip) can be planarized and thinned.

[0044] After the dielectric layer is formed and before step two above, the fabrication method in this application embodiment may further include: drilling holes in the dielectric layer and filling the formed holes with conductive material. For example, thin film deposition, electroplating, or other processes can be used to fill the holes with metal material to form a dielectric via that penetrates the dielectric layer. The dielectric via is electrically connected to the second interconnect layer and / or the first chip.

[0045] In some cases, after forming the dielectric layer, a second dielectric film can be formed on top of the dielectric layer. After forming the second dielectric film, holes are drilled in the second dielectric film and the dielectric layer, and conductive material is filled into the holes to form a dielectric via that penetrates the second dielectric film and the dielectric layer.

[0046] Next, a support structure is provided, which may include a first substrate and a first interconnect layer. The first interconnect layer has a first connection terminal on its surface facing away from the first substrate. Step two may specifically include: placing the support structure on top of the second chip, with the first interconnect layer of the support structure facing the second chip. The support structure and the second chip are then bonded together, so that the first connection terminal is electrically connected to a dielectric via. In this embodiment, by forming a dielectric via in the dielectric layer, the first connection terminal can be electrically connected to the second interconnect layer and / or the first chip through the dielectric via. This eliminates the need for drilling and metal filling on the second chip, simplifying the manufacturing process of the second chip, increasing the active area ratio of the second chip, and thus reducing costs.

[0047] Furthermore, the support structure may also include a first dielectric film and a first connection terminal. The first dielectric film is located on the side of the first interconnect layer closer to the second chip, and the first connection terminal is electrically connected to the first interconnect layer and exposed through a via in the first dielectric film. In the bonding process in step two above, the second dielectric film on the surface of the second chip is bonded to the first dielectric film on the surface of the support structure, and the first connection terminal is bonded to the end of the dielectric via, so that the support structure is mixed-bonded with the underlying die and wafer stack structure (the stack structure formed by the second chip and the first chip).

[0048] Following step two above, the fabrication method in this embodiment may further include: using a support structure as structural support, thinning the surface of the first chip away from the second chip. Additionally, a hole may be drilled in the third substrate, and conductive material may be filled into the formed hole to form a conductive via penetrating the third substrate. This conductive via can be electrically connected to the third interconnect layer. Then, a fourth connection terminal is formed on the first chip, which can be electrically connected to the third interconnect layer through the conductive via. During the thinning process of the first chip, the support structure is relatively thick, increasing the total thickness of the entire chip stack structure and serving as structural support for thinning the first chip. Of course, in some cases, the thinning process of the first chip can be omitted. For example, if the first chip is already thin, thinning is unnecessary; or if the third interconnect layer of the first chip is located on the side of the third substrate away from the support structure, thinning of the first chip may not be necessary.

[0049] In other embodiments of this application, when the chip stacking structure has the structure described in Method 3 above, the fabrication method in the embodiments of this application may specifically include:

[0050] A bridging chip is provided, wherein a second conductive via is provided, and the second conductive via penetrates the bridging chip. In specific implementations, the bridging chip may have one or more second conductive vias, and the number of second conductive vias in the bridging chip can be set according to actual needs, which is not limited here. In step one above, each second chip and the bridging chip are placed on top of the first chip, that is, the bridging chip is placed on top of the first chip in a position other than the second chips. Each second chip is electrically connected to the first chip, and the bridging chip is electrically connected to the first chip. In specific implementations, the second chips and the bridging chip can be electrically connected to the first chip using a hybrid bonding method. The second chips can be bonded first and then the bridging chip can be bonded, or the bridging chip can be bonded first and then the second chips can be bonded. The bonding order of the second chips and the bridging chips is not limited here. The specific bonding method between the second chip and the first chip can be referred to the relevant description above, and repeated parts will not be repeated. In the embodiments of this application, the chip stack structure may include one or more bridging chips, and the number and position of the bridging chips can be set according to actual needs, which is not limited here.

[0051] In step two above, a dielectric material is filled on the area above the first chip, excluding the second chips and the bridging chips, to form a dielectric layer. In some cases, the surface of the dielectric layer may also be planarized and thinned. Then, a second dielectric film is formed on the second chips and the bridging chips, and interconnects for leading out second conductive vias are formed, with at least a portion of the interconnects exposed on the surface of the second dielectric film.

[0052] Next, a support structure is provided, which may include a first substrate and a first interconnect layer. The first interconnect layer has a first connection terminal on its surface facing away from the first substrate. Step two may specifically include: placing the support structure on each of the second chips, with the first interconnect layer of the support structure facing the second chip. The support structure is then bonded to each of the second chips, so that the first connection terminal is electrically connected to a second conductive via, thereby electrically connecting the first connection terminal to the second interconnect layer and / or the first chip through the second conductive via. In this embodiment, by mounting a bridging chip on the first chip, the first connection terminal can be electrically connected to the second interconnect layer and / or the first chip without needing to drill holes in the second chip, simplifying the process flow of the second chip, increasing the active area ratio of the second chip, and thus reducing costs.

[0053] Furthermore, the support structure may also include a first dielectric film and a first connection terminal. The first dielectric film is located on the side of the first interconnect layer closer to the second chip, and the first connection terminal is electrically connected to the first interconnect layer and exposed through a via in the first dielectric film. In the bonding process in step two above, the second dielectric film on the surface of the second chip is bonded to the first dielectric film on the surface of the support structure, and the first connection terminal is bonded to the second conductive via, so that the support structure is mixed-bonded with the underlying die and wafer stack structure (the stack structure composed of the second chip and the first chip).

[0054] Following step two above, the fabrication method in this embodiment may further include: using a support structure as structural support, thinning the surface of the first chip away from the second chip. Additionally, a hole may be drilled in the third substrate, and conductive material may be filled into the formed hole to form a conductive via penetrating the third substrate. This conductive via can be electrically connected to the third interconnect layer. Then, a fourth connection terminal is formed on the first chip, which can be electrically connected to the third interconnect layer through the conductive via. During the thinning process of the first chip, the support structure can increase the total thickness of the entire chip stack structure, serving as a structural support for the thinning of the first chip. Of course, in some cases, the thinning process of the first chip can be omitted. For example, if the first chip is already thin, thinning is unnecessary; or if the third interconnect layer of the first chip is located on the side of the third substrate away from the support structure, thinning of the first chip may not be necessary.

[0055] The above describes the fabrication methods for chip stack structures with the structures described in methods one to three. In specific implementations, when methods one to three are combined with each other, or when the first interconnect layer and the second chip use other interconnection methods, the above fabrication methods can be referred to, and repeated details will not be repeated. Furthermore, in the above description, the fabrication method of the chip stack structure is introduced using the example of a chip stack structure including a second chip. When the chip stack structure includes multiple chips, the fabrication process of the other chips can refer to the fabrication process of the second chip, and repeated details will not be repeated.

[0056] Thirdly, embodiments of this application also provide a chip packaging structure. The chip packaging structure provided in this application embodiment may include any of the chip stacking structures described in the first aspect above and a substrate, wherein the chip stacking structure can be fixed on the substrate. Furthermore, in some cases, the chip packaging structure in this application embodiment may also include an interposer. Since the chip stacking structure in the first aspect above can shorten the interconnection distance between the chip and integrated passive devices, the area overhead of the substrate (or interposer) in the chip packaging structure can be reduced, resulting in a smaller chip packaging structure with higher integration.

[0057] Fourthly, embodiments of this application also provide an electronic device, which may include the chip packaging structure and circuit board described in the third aspect above, wherein the chip packaging structure is electrically connected to the circuit board. Because the chip stacking structure described in the first aspect can shorten the interconnection distance between the chip and integrated passive devices, and can reduce the area overhead of the substrate (or interposer) in the chip packaging structure, the chip packaging structure is smaller and has a higher integration density. Therefore, the electronic device including this chip packaging structure is also smaller and has a higher integration density. Attached Figure Description

[0058] Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;

[0059] Figure 2 This is a schematic diagram of the chip stacking structure provided in the embodiments of this application;

[0060] Figure 3 This is another schematic diagram of the chip stacking structure provided in the embodiments of this application;

[0061] Figure 4 This is another schematic diagram of the chip stacking structure provided in the embodiments of this application;

[0062] Figure 5 A flowchart illustrating the fabrication method of the chip stacking structure provided in this application embodiment;

[0063] Figures 6 to 8 The diagram shows the structure of each step in the manufacturing method provided in the embodiments of this application.

[0064] Figure label:

[0065] 100 - Electronic device; 101 - Chip packaging structure; 102 - Circuit board; 11 - First chip; 111 - Third substrate; 112 - Third interconnect layer; 12 - Second chip; 121 - Second substrate; 122 - Second interconnect layer; 13 - Support structure; 131 - First substrate; 132 - First interconnect layer; 14 - Integrated passive device; 15 - Dielectric layer; 151 - Dielectric via; 161 - First dielectric film; 162 - Second dielectric film; 163 - Third dielectric film; 164 - Fourth dielectric film; 17 - Bridge chip; T1 - First conductive via; T2 - Second conductive via; Q1 - First connection terminal; Q2 - Second connection terminal; Q3 - Third connection terminal; Q4 - Fourth connection terminal. Detailed Implementation

[0066] To shorten the interconnection distance between chips and integrated passive devices, reduce the area overhead of the substrate (or interposer) in the chip package structure, and improve the integration density of the chip package structure, embodiments of this application provide a chip stacking structure, its fabrication method, a chip package structure, and an electronic device. The chip stacking structure in this application embodiment can be applied to various types of electronic devices, such as mobile phones, tablets, laptops, smart wearable devices, and other terminal devices, or to smart TVs, smart door locks, smart home appliances, and other electronic devices.

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0068] It should be noted that the accompanying drawings in this application are for illustrative purposes only and do not represent actual scale. The same reference numerals in the accompanying drawings denote the same or similar structures, and therefore, repeated descriptions of them will be omitted.

[0069] The terms describing position and direction used in this application, such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," are merely illustrative examples based on the orientation or positional relationships shown in the accompanying drawings. They are intended solely for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Changes may be made as needed, and all such changes are included within the scope of protection of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0070] Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Figure 1 The left-hand side is a top view of the electronic device. Figure 1 The right side of the image shows a top view of the electronic device, with a cross-sectional view at the dashed line AA'. (See image below.) Figure 1 As shown, the electronic device 100 provided in this application embodiment may include: a chip package structure 101 and a circuit board 102, wherein the chip package structure 101 and the circuit board 102 are electrically connected. Figure 1 The example shown is a mobile phone. When the electronic device 100 is another device, the position, shape, and size of the chip packaging structure 101 and the circuit board 102 in the electronic device 100 can be reasonably set according to actual needs.

[0071] In this embodiment, the chip packaging structure may include a chip stack structure and a substrate. The chip stack structure may be fixed on the substrate. Furthermore, in some cases, the chip packaging structure in this embodiment may also include an interposer. Because the chip stack structure in this embodiment can shorten the interconnection distance between the chip and integrated passive devices and reduce the area overhead of the substrate (or interposer), the chip packaging structure including the chip stack structure and the substrate (or interposer) is smaller in size and has a higher integration density. Therefore, the electronic device including this chip packaging structure is also smaller in size and has a higher integration density.

[0072] Figure 2 This is a schematic diagram of the chip stacking structure provided in the embodiments of this application, as shown below. Figure 2 As shown, the chip stacking structure provided in this application embodiment may include a first chip 11, at least one second chip 12, and a support structure 13. Each second chip 12 is located between the first chip 11 and the support structure 13. The first chip 11 is electrically connected to each second chip 12. Exemplarily, the first chip 11 and the second chip 12 can be electrically connected by hybrid bonding, or by soldering or other methods. The support structure 13 is connected to each second chip 12. For example, the support structure 13 and the second chip 12 can be connected by hybrid bonding or fusion bonding. Fusion bonding refers to bonding two interfaces through a dielectric material, while hybrid bonding refers to bonding two interfaces through a dielectric material and a metallic material. An integrated passive device (IPD) 14 is disposed in the support structure 13. The IPD 14 is electrically connected to at least one second chip 12; and / or, the IPD 14 is electrically connected to the first chip 11. The integrated passive device 14 may include passive components such as resistors, capacitors, and inductors, as well as interconnection structures connected to the passive components. The passive components can function to transmit signals, store energy, and filter signals. The integrated passive device 14 can adjust the power supply and signals, and provide the adjusted power supply and signals to at least one second chip 12 and / or a first chip 11. Furthermore, the integrated passive device 14 can also shield against electromagnetic interference, providing better electromagnetic protection for the second chip 12 or the first chip 11 and preventing electromagnetic signals from interfering with them.

[0073] In related technologies, the support structure 13 is a substrate without any function; for example, the support structure 13 can be a silicon wafer, resulting in low substrate utilization. In the chip stacking structure provided in this application embodiment, the integrated passive device 14 is integrated into the support structure 13. On the one hand, this allows the integrated passive device 14, the second chip 12, and the first chip 11 to be stacked vertically (perpendicular to the surface of the first chip 11), significantly reducing the interconnection distance between the second chip 12 and / or the first chip 11 and the integrated passive device 14. The second chip 12 and / or the first chip 11 and the integrated passive device 14 do not need to be interconnected through a substrate (or interposer), thereby reducing the area overhead of the substrate (or interposer) and lowering the manufacturing cost of the chip stacking structure. Furthermore, this reduces the volume of the chip package structure including the chip stacking structure and the substrate (or interposer), improving the integration density of the chip package structure. On the other hand, it improves the substrate utilization of the support structure 13, making better use of the internal structure of the chip stacking structure. In addition, the support structure 13 is generally a silicon wafer. Silicon material has high heat dissipation efficiency, which can give the support structure 13 a good heat dissipation effect. Therefore, the support structure 13 can also play the role of heat equalization and heat dissipation enhancement.

[0074] In this embodiment, the second chip 12 is an unpackaged die, and can be a chip with various functions such as computing and storage. The chip stacking structure in this embodiment may include one or more second chips. The accompanying drawings illustrate a chip stacking structure including two second chips 12 as an example. In specific configurations, the number of second chips 12 can be set according to actual needs. When the chip stacking structure includes one or more second chips 12, the implementation of other second chips 12 can refer to the description in this application. The first chip 11 can be a wafer or a portion of a wafer diced. For example, the first chip 11 may include semiconductor materials such as silicon and silicon carbide, and can be a chip with various functions such as computing and storage. The second chip 12 and the first chip 11 can be connected by hybrid bonding, that is, the second chip 12 and the first chip 11 can be stacked using die-to-wafer hybrid bonding (D2W HB). The support structure 13 can be a wafer or a portion of a wafer diced. For example, the support structure 13 may include semiconductor materials such as silicon and silicon carbide. The support structure 13 and the second chip 12 can be connected by hybrid bonding or fusion bonding.

[0075] In this embodiment, the support structure 13 is relatively thick, which increases the overall thickness of the chip stack structure, thus enabling the support structure 13 to function as a heat spreader. When the chip stack structure of this application is applied to an electronic device, a heat sink can be provided on the side of the support structure 13 facing away from the first chip 11, providing a heat conduction path between each second chip 12 and the heat sink. Furthermore, the first chip 11 may have a first surface and a second surface disposed opposite to each other. During the manufacturing process, at least one second chip 12 is mounted on the first surface of the first chip 11, and the support structure 13 is bonded to the side of each second chip 12 facing away from the first chip 11. After completing the bonding of the second chips 12 and the bonding of the support structure 13, in some cases, the surface of the first chip 11 facing away from the second chips 12 can be thinned, and the support structure 13 can serve as a structural support for this thinning process.

[0076] Continue to refer to Figure 2 In one possible implementation, the support structure 13 may include a first substrate 131 and a first interconnect layer 132, the first interconnect layer 132 being located on the side of the first substrate 131 closer to the first chip 11. Exemplarily, the first substrate 131 may include semiconductor materials such as silicon or silicon carbide. An integrated passive device 14 is located on the first substrate 131 near the first interconnect layer 132. The integrated passive device 14 is electrically connected to at least one second chip 12 via the first interconnect layer 132; and / or, the integrated passive device 14 is electrically connected to the first chip 11 via the first interconnect layer 132. In this embodiment, placing the integrated passive device 14 in the first substrate 131 near the first interconnect layer 132 can shorten the vertical distance between the integrated passive device 14 and the second chip 12 (and / or the first chip 11), making it easier to interconnect the integrated passive device 14 and the second chip 12 (and / or the first chip 11), thereby simplifying the interconnect structure in the first interconnect layer 132.

[0077] In the embodiments of this application, the first interconnect layer 132 and the second chip 12 (and / or the first chip 11) can be interconnected in various ways. The interconnection methods of the first interconnect layer and the second chip are described in detail below with reference to the accompanying drawings.

[0078] Method 1:

[0079] like Figure 2As shown, in some embodiments of this application, the first interconnect layer 132 has a first connection terminal Q1 on its surface near the first chip 11. The second chip 12 may include a second substrate 121 and a second interconnect layer 122, with the second interconnect layer 122 located on the side of the second substrate 121 near the first chip 11. That is, the second chip 12 can be flip-chip mounted on the first chip 11. Of course, in some cases, the second chip 12 can also be mounted upright on the first chip 11; the mounting method of the second chip 12 is not limited here. The second substrate 121 may include semiconductor materials such as silicon and silicon carbide; for example, the second substrate 121 may be a silicon wafer. A first conductive via T1 is provided in the second chip 12, extending from the surface of the second substrate 121 near the support structure 13 into the interior of the second interconnect layer 122, and the first conductive via T1 is electrically connected to the second interconnect layer 122. In a specific implementation, the second substrate 121 may include silicon material, and the first conductive via T1 may be a through silicon via (TSV), which may include metal materials such as copper or tungsten. The first connection terminal Q1 is electrically connected to the end of the first conductive via T1 near the support structure 13. By providing the first conductive via T1 in the second chip 12, the first conductive via T1 can connect the second interconnect layer 122 to the surface of the second substrate 121 near the support structure 13, thereby reducing the interconnection distance between the second chip 12 and the first interconnect layer 132.

[0080] In a specific configuration, a first dielectric film 161 is disposed on the side of the first interconnect layer 132 near the first chip 11, and the first connection terminal Q1 is exposed through a via in the first dielectric film 161. A second dielectric film 162 is disposed on the side of the second chip 12 near the support structure 13, and the end of the first conductive via T1 is exposed through a via in the second dielectric film 162. The second dielectric film 162 on the surface of the second chip 12 is bonded to the first dielectric film 161 on the surface of the support structure 13, and the first connection terminal Q1 is bonded to the end of the first conductive via T1, so that the second chip 12 and the support structure 13 are co-bonded.

[0081] Method 2:

[0082] Figure 3 This is another schematic diagram of the chip stacking structure provided in the embodiments of this application, as shown below. Figure 3As shown, in some other embodiments of this application, the first interconnect layer 132 has a first connection terminal Q1 on its surface near the first chip 11. The second chip 12 may include a second substrate 121 and a second interconnect layer 122, with the second interconnect layer 122 located on the side of the second substrate 121 near the first chip 11. That is, the second chip 12 can be flip-chip mounted on the first chip 11. Of course, in some cases, the second chip 12 can also be mounted upright on the first chip 11; the mounting method of the second chip 12 is not limited here.

[0083] The chip stack structure may further include a dielectric layer 15 located between the first chip 11 and the support structure 13, filling the space between the first chip 11 and the support structure 13 except for each of the second chips 12. Exemplarily, the dielectric layer 15 may include an inorganic dielectric material such as silicon oxide. Conductive through-dielectric vias 151 (TDVs) are provided in the dielectric layer 15. One end of the TDV near the support structure 13 is electrically connected to a first connection terminal Q1, and the other end is electrically connected to a second interconnect layer 122 and / or the first chip 11. In a specific configuration, the TDV 151 may directly contact and connect to the first connection terminal Q1, or the TDV 151 may be connected to the first connection terminal Q1 via an interconnect. The TDV 151 may be connected to the second interconnect layer 122 and / or the first chip 11 via an interconnect. In this embodiment, conductive vias 151 are formed in the dielectric layer 15 by drilling holes in the dielectric layer 15. The first connection terminal Q1 is electrically connected to the second interconnect layer 122 through the vias 151. Compared with the first method described above, the second method does not require drilling holes in the second chip 12, which simplifies the process flow of the second chip, increases the active area ratio of the second chip, and thus reduces costs.

[0084] In a specific configuration, a first dielectric film 161 is disposed on the side of the first interconnect layer 132 near the first chip 11, and the first connection terminal Q1 is exposed through a via in the first dielectric film 161. A second dielectric film 162 is disposed on the side of the second chip 12 near the support structure 13, and a dielectric via 151 passes through the second dielectric film 162 and is bonded to the first connection terminal Q1. Furthermore, the second dielectric film 162 on the surface of the second chip 12 is bonded to the first dielectric film 161 on the surface of the support structure 13, so that the support structure 13 is mixed-bonded with the underlying die and wafer stack structure (the stack structure formed by the second chip 12 and the first chip 11).

[0085] Method 3:

[0086] Figure 4 This is another schematic diagram of the chip stacking structure provided in the embodiments of this application, as shown below. Figure 4As shown, in some other embodiments of this application, the first interconnect layer 132 has a first connection terminal Q1 on its surface near the first chip 11, and the second chip 12 may include a second substrate 121 and a second interconnect layer 122, with the second interconnect layer 122 located on the side of the second substrate 121 near the first chip 11. That is, the second chip 12 can be flip-chip mounted on the first chip 11. Of course, in some cases, the second chip 12 can also be mounted upright on the first chip 11; the mounting method of the second chip 12 is not limited here.

[0087] The chip stack structure may further include a bridge chip 17 located between the first chip 11 and the support structure 13. The bridge chip 17 has a second conductive via T2, which penetrates the bridge chip 17. One end of the second conductive via T2 near the support structure 13 is electrically connected to the first connection terminal Q1, and the other end is electrically connected to the second interconnect layer 122 and / or the first chip 11. In specific implementations, the bridge chip 17 may have one or more second conductive vias T2. The number of second conductive vias T2 in the bridge chip 17 can be set according to actual needs, and is not limited here. The bridge chip 17 and the second chip 12 are arranged in a horizontal direction (parallel to the surface of the first chip 11). The bridge chip 17 may be disposed around the second chip 12, making the distance between the bridge chip 17 and the second chip 12 relatively close. In specific configurations, the second conductive via T2 can be connected to the first connection terminal Q1 via an interconnect line, and the second conductive via T2 can be connected to the second interconnect layer 122 and / or the first chip 11 via an interconnect line. In one possible implementation, the substrate of the bridging chip 17 includes silicon material, and the second conductive via T2 can be a through-silicon via (TSV). Unlike the structure of the second chip 12, the bridging chip 17 may not have an interconnect layer. Instead, at least one second conductive via T2 is formed in the substrate by drilling holes to obtain the bridging chip 17. That is, the bridging chip 17 does not have computing, storage, or other processing functions; it is used to electrically connect the second interconnect layer 122 of the second chip 12 to the first connection terminal Q1. In this embodiment, by using the bridging chip 17 to electrically connect the first connection terminal Q1 to the second interconnect layer 122, compared to the first method described above, this third method does not require drilling holes in the second chip 12, simplifying the manufacturing process of the second chip, increasing the active area ratio of the second chip 12, and thus reducing costs. In this embodiment, the chip stack structure may include one or more bridging chips 17. The number and position of the bridging chips 17 can be set according to actual needs and are not limited here.

[0088] In a specific configuration, a first dielectric film 161 is disposed on the side of the first interconnect layer 132 near the second chip 12, and the first connection terminal Q1 is exposed through a via in the first dielectric film 161. A second dielectric film 162 is disposed on the side of the second chip 12 near the support structure 13, and the second conductive via T2 in the bridging chip 17 is electrically connected to the first connection terminal Q1 through an interconnect in the second dielectric film 162. Furthermore, the second dielectric film 162 on the surface of the second chip 12 is bonded to the first dielectric film 161 on the surface of the support structure 13, so that the support structure 13 is mixed-bonded with the underlying die and wafer stack structure (the stack structure composed of the second chip 12 and the first chip 11).

[0089] Continue to refer to Figure 4 In one possible implementation, the chip stack structure may include at least two second chips 12, with adjacent second chips 12 electrically connected to different second conductive vias T2 in the bridging chip 17. The bridging chip 17 may be located between the two adjacent second chips 12. This allows the bridging chip 17 to be closer to the two adjacent second chips 12, shortening the interconnection distance between the second chips 12 and the first interconnect layer 132.

[0090] The above describes several interconnection methods between the first interconnect layer and the second chip and / or the first chip. In specific implementations, methods one to three can also be combined. For example, method one can be combined with method two, where a first conductive via is provided in the second chip, and a dielectric via is provided in the dielectric layer. Of course, in some cases, other interconnection methods can also be used between the first interconnect layer and the second chip and / or the first chip, and can be reasonably configured according to interconnection requirements.

[0091] In one possible implementation, such as Figure 2As shown, the first chip 11 may include a third substrate 111 and a third interconnect layer 112, with the third interconnect layer 112 located on the side of the third substrate 111 near the support structure 13. Exemplarily, the third substrate 111 may include semiconductor materials such as silicon or silicon carbide. A second connection terminal Q2 is provided on the surface of the first chip 11 near the support structure 13; that is, the third interconnect layer 112 has a second connection terminal Q2 on its surface near the second chip 12, and the second interconnect layer 122 has a third connection terminal Q3 on its surface near the first chip 11. The second connection terminal Q2 and the third connection terminal Q3 are electrically connected to interconnect the second chip 12 with the first chip 11. In a specific configuration, a third dielectric film 163 is provided on the side of the third interconnect layer 112 near the second chip 12, and the second connection terminal Q2 is exposed through a via in the third dielectric film 163. A fourth dielectric film 164 is provided on the surface of the second chip 12 near the first chip 11, and the third connection terminal Q3 is exposed through a via in the fourth dielectric film 164. The fourth dielectric film 164 on the surface of the second chip 12 is bonded to the third dielectric film 163 on the surface of the third interconnect layer 112. Therefore, the second chip 12 and the first chip 11 are co-bonded. In this embodiment, the third interconnect layer 112 is disposed on the side of the third substrate 111 closer to the support structure 13, which allows for a shorter interconnect distance between the third interconnect layer 112 and the second chip 12. Of course, in some cases, the third interconnect layer 112 in the first chip 11 can also be located on the side of the third substrate 111 away from the support structure 13; this is not a limitation.

[0092] In addition, continue to refer to Figure 2 The first chip 11 may also have a fourth connection terminal Q4 on the side opposite to the support structure 13, and the fourth connection terminal Q4 is electrically connected to the third interconnect layer 112. When the chip stacking structure of this embodiment is applied to an electronic device, the chip stacking structure can be electrically connected to the circuit board through the fourth connection terminal Q4.

[0093] Based on the same technical concept, this application also provides a method for fabricating a chip stacking structure. Figure 5 This is a flowchart illustrating the method for fabricating a chip stacking structure provided in an embodiment of this application. Figures 6 to 8 The diagram shows the structural schematics corresponding to each step in the manufacturing method provided in the embodiments of this application. For example... Figure 5 As shown, the method for fabricating a chip stacking structure provided in this application embodiment may include:

[0094] S201. At least one second chip is placed on top of the first chip, and each second chip is electrically connected to the first chip; wherein, the second chip can be a diced die, or a chip with various functions such as computing and storage. The first chip can be a wafer or a portion thereof diced from a wafer; for example, the first chip can include semiconductor materials such as silicon or silicon carbide, and can be a chip with various functions such as computing and storage. After bonding the second chip to the first chip, a die-to-wafer (D2W) stacked structure can be obtained.

[0095] S202. A support structure with integrated passive devices is placed on the side of each second chip facing away from the first chip, and the support structure is connected to each second chip; wherein the integrated passive devices are electrically connected to at least one second chip; and / or, the integrated passive devices are electrically connected to the first chip. The support structure can be a wafer or a portion thereof cut from a wafer. For example, the support structure can include semiconductor materials such as silicon and silicon carbide. The integrated passive devices can include passive devices such as resistors, capacitors, and inductors, as well as interconnection structures connected to the passive devices. The passive devices can function to transmit signals, store energy, and filter signals. The integrated passive devices can adjust the power supply and signals, and provide the adjusted power supply and signals to the second chips. In addition, the integrated passive devices can also shield electromagnetic interference, so as to achieve better electromagnetic protection for the second chip or the first chip and avoid electromagnetic signals from interfering with the second chip and the first chip.

[0096] In the chip stacking structure fabrication method provided in this application embodiment, by integrating passive devices into the support structure, on the one hand, the passive devices, the second chip, and the first chip can be stacked vertically (perpendicular to the surface of the first chip), which can significantly reduce the interconnection distance between the second chip and / or the first chip and the passive devices. The second chip and / or the first chip and the passive devices do not need to be interconnected through a substrate (or interposer), thereby reducing the area overhead of the substrate (or interposer) and lowering the fabrication cost of the chip stacking structure. Furthermore, the volume of the chip package structure including the chip stacking structure and the substrate (or interposer) can be reduced, improving the integration density of the chip package structure. On the other hand, the substrate utilization rate of the support structure can be improved, making better use of the internal structure of the chip stacking structure. In addition, the support structure is generally a silicon wafer, and silicon material has high heat dissipation efficiency, which can give the support structure a good heat dissipation effect. Therefore, the support structure can also play a role in heat equalization and enhanced heat dissipation.

[0097] Furthermore, after step S201 and before step S202, the fabrication method in this embodiment may further include: filling the gaps between the second chips with dielectric material to form a dielectric layer. Exemplarily, inorganic dielectric materials such as silicon oxide can be used to fabricate the dielectric layer. In some cases, after fabricating the dielectric layer, the back side of each second chip (the side of the second chip facing away from the first chip) can be planarized and thinned.

[0098] Based on the above description of the chip stacking structure, the first interconnect layer in the support structure and the second chip and / or the first chip can have multiple interconnection methods. The following, in conjunction with the accompanying drawings, describes in detail the fabrication method of the chip stacking structure having the above-mentioned method one to method three.

[0099] In some embodiments of this application, when the chip stacking structure has the structure described in Method 1 above, the fabrication method in these embodiments may specifically include:

[0100] Reference Figure 6 In step (1), the first chip 11 may include a third substrate 111 and a third interconnect layer 112. For example, the third substrate 111 may include semiconductor materials such as silicon or silicon carbide. The second chip 12 may include a second substrate 121 and a second interconnect layer 122. Step S201 may specifically include: placing the second chip 12 on top of the first chip 11 with the surface of the first chip 11 having the third interconnect layer 112 facing upwards, and ensuring that the second interconnect layer 122 of the second chip 12 faces the third interconnect layer 112. The second chip 12 and the first chip 11 are then hybrid-bonded to achieve electrical connection between the second interconnect layer 122 and the third interconnect layer 112. In this embodiment, the second chip 12 may be flip-chipped onto the first chip 11. In some cases, the second chip 12 may also be mounted upright onto the first chip 11. The mounting method of the second chip 12 is not limited here. Furthermore, the third interconnect layer 112 in the first chip 11 is located on the side of the third substrate 111 closer to the second chip 12, which can make the interconnection distance between the third interconnect layer 112 and the second chip 12 shorter. Of course, in some cases, the third interconnect layer 112 in the first chip 11 can also be located on the side of the third substrate 111 away from the second chip 12, which is not limited here.

[0101] In a specific configuration, the third interconnect layer 112 has a second connection terminal Q2 on its surface near the second chip 12, and the second interconnect layer 122 has a third connection terminal Q3 on its surface near the first chip 11. The second connection terminal Q2 and the third connection terminal Q3 are bonded together to interconnect the second chip 12 and the first chip 11. In another specific configuration, the third interconnect layer 112 has a third dielectric film 163 on its surface near the second chip 12, and the second connection terminal Q2 is exposed through a via in the third dielectric film 163. The second chip 12 has a fourth dielectric film 164 on its surface near the first chip 11, and the third connection terminal Q3 is exposed through a via in the fourth dielectric film 164. The fourth dielectric film 164 on the surface of the second chip 12 is bonded to the third dielectric film 163 on the surface of the third interconnect layer 112. Therefore, the second chip 12 and the first chip 11 are hybrid-bonded.

[0102] Reference Figure 6 In step (2), dielectric material is filled into the gaps between the second chips 12 to form a dielectric layer 15. Exemplarily, an inorganic dielectric material such as silicon oxide can be used to fabricate the dielectric layer 15. In some cases, after fabricating the dielectric layer 15, the back side of the second chip 12 (the side of the second chip 12 facing away from the first chip 11) can be planarized and thinned.

[0103] Reference Figure 6 In step (3), after step S201 and before step S202, the fabrication method in this embodiment may further include: drilling holes in the second chip 12 and filling the formed holes with conductive material, for example, using thin film deposition, electroplating, or other processes to fill with metal material, to form a first conductive via T1 extending from the surface of the second substrate 121 away from the first chip 11 to the interior of the second interconnect layer; wherein the first conductive via T1 is electrically connected to the second interconnect layer 122. To facilitate bonding with the support structure, the first conductive via T1 may protrude from the surface of the second substrate 121 away from the first chip 11.

[0104] Alternatively, before bonding the second chip 12 to the first chip 11, the second chip 12 may already have a first conductive via T1. After step S201 and before step S202, the fabrication method in this embodiment may further include: thinning the surface of the second substrate 121 facing away from the first chip 11 to expose the first conductive via T1, thus obtaining... Figure 6 The structure shown in (3) is as follows.

[0105] Then, a second dielectric film 162 is formed on the second chip 12 and the dielectric layer 15, and the end of the first conductive via T1 is exposed through the via in the second dielectric film 162.

[0106] Reference Figure 6 In step (4), a support structure 13 is provided. The support structure 13 may include a first substrate 131 and a first interconnect layer 132. The first interconnect layer 132 has a first connection terminal Q1 on the surface facing away from the first substrate 131. Step S202 may specifically include: placing the support structure 13 on the second chip 12, with the first interconnect layer 132 of the support structure 13 facing the second chip 12. The support structure 13 is bonded to each of the second chips 12, so that the first connection terminal Q1 is electrically connected to the first conductive via T1. In this embodiment, by providing the first conductive via T1 in the second chip 12, the first conductive via T1 can connect the second interconnect layer 122 to the surface of the second substrate 121 near the support structure 13, which can make the interconnection distance between the second chip 12 and the first interconnect layer 132 shorter.

[0107] Continue to refer to Figure 6 In step (4), the support structure 13 may further include a first dielectric film 161 and a first connection terminal Q1. The first dielectric film 161 is located on the side of the first interconnect layer 132 near the second chip 12. The first connection terminal Q1 is electrically connected to the first interconnect layer 132 and is exposed through a via in the first dielectric film 161. During the bonding process in step S202 above, the second dielectric film 162 on the surface of the second chip 12 is bonded to the first dielectric film 161 on the surface of the support structure 13, and the first connection terminal Q1 is bonded to the end of the first conductive via T1, so that the second chip 12 and the support structure 13 are mixed-bonded.

[0108] Following step S202 above, the fabrication method in this embodiment may further include: using the support structure 13 as a structural support, thinning the surface of the first chip 11 on the side opposite to the second chip 12. Furthermore, a hole may be drilled in the third substrate 111, and conductive material may be filled into the formed hole to form a conductive via penetrating the third substrate 111. This conductive via can be electrically connected to the third interconnect layer 112. Then, a fourth connection terminal Q4 is formed on the first chip 11. The fourth connection terminal Q4 can be electrically connected to the third interconnect layer 112 through the conductive via, thereby obtaining… Figure 2 The structure shown is as follows. During the thinning process of the first chip 11, the support structure 13 can increase the total thickness of the entire chip stack structure and can serve as a structural support for the thinning of the first chip 11. Of course, in some cases, the thinning process of the first chip 11 can be omitted. For example, if the thickness of the first chip 11 is already thin, there is no need to thin it. Or, if the third interconnect layer 112 of the first chip 11 is located on the side of the third substrate 111 away from the support structure 13, the first chip 11 may not need to be thinned.

[0109] In other embodiments of this application, when the chip stacking structure has the structure of Method Two described above, the fabrication method in the embodiments of this application may specifically include:

[0110] Reference Figure 7 In step (1), at least one second chip 12 is placed on top of the first chip 11, and each second chip 12 is electrically connected to the first chip 11. The specific connection method between the second chip 12 and the first chip 11 can be referred to the above description. Figure 6 The relevant descriptions in (1) are repeated here, and will not be repeated here.

[0111] Reference Figure 7 In step (2) above, in step S202, dielectric material is filled into the gaps between each of the second chips 12 to form a dielectric layer 15. Exemplarily, an inorganic dielectric material such as silicon oxide can be used to fabricate the dielectric layer 15. In some cases, after fabricating the dielectric layer 15, the back side of the second chip 12 (the side of the second chip 12 facing away from the first chip 11) can be planarized and thinned.

[0112] Reference Figure 7 In step (3), after the dielectric layer 15 is formed and before step S202 above, the fabrication method in this application embodiment may further include: drilling holes in the dielectric layer 15 and filling the formed holes with conductive materials. For example, metal materials may be filled using thin film deposition, electroplating, or other processes to form a dielectric via 151 that penetrates the dielectric layer 15. The dielectric via 151 is electrically connected to the second interconnect layer 122 and / or the first chip 11.

[0113] In some cases, after forming the dielectric layer 15, a second dielectric film 162 may be formed on the dielectric layer 15. After forming the second dielectric film 162, holes are punched in the second dielectric film 162 and the dielectric layer 15, and conductive material is filled into the formed holes to form a dielectric via 151 that penetrates the second dielectric film 162 and the dielectric layer 15.

[0114] Reference Figure 7In step (4), a support structure 13 is provided. The support structure 13 may include a first substrate 131 and a first interconnect layer 132. The first interconnect layer 132 has a first connection terminal Q1 on its surface facing away from the first substrate 131. Step S202 may specifically include: placing the support structure 13 on the second chip 12, with the first interconnect layer 132 of the support structure 13 facing the second chip 12. The support structure 13 and the second chip 12 are bonded together so that the first connection terminal Q1 is electrically connected to the dielectric via 151. In this embodiment, by forming a dielectric via 151 in the dielectric layer 15, the first connection terminal Q1 can be electrically connected to the second interconnect layer 122 and / or the first chip 11 through the dielectric via 151. This eliminates the need for drilling and metal filling of the second chip 12, simplifies the process flow of the second chip, increases the active area ratio of the second chip, and thus reduces costs.

[0115] Continue to refer to Figure 7 In step (4), the support structure 13 may further include a first dielectric film 161 and a first connection terminal Q1. The first dielectric film 161 is located on the side of the first interconnect layer 132 near the second chip 12. The first connection terminal Q1 is electrically connected to the first interconnect layer 132 and is exposed through a via in the first dielectric film 161. During the bonding process in step S202 above, the second dielectric film 162 on the surface of the second chip 12 is bonded to the first dielectric film 161 on the surface of the support structure 13, and the first connection terminal Q1 is bonded to the end of the dielectric via 151, so that the support structure 13 is mixed-bonded with the underlying die and wafer stack structure (the stack structure formed by the second chip 12 and the first chip 11).

[0116] Following step S202 above, the fabrication method in this embodiment may further include: using the support structure 13 as a structural support, thinning the surface of the first chip 11 on the side opposite to the second chip 12. Furthermore, a hole may be drilled in the third substrate 111, and conductive material may be filled into the formed hole to form a conductive via penetrating the third substrate 111. This conductive via can be electrically connected to the third interconnect layer 112. Then, a fourth connection terminal Q4 is formed on the first chip 11. The fourth connection terminal Q4 can be electrically connected to the third interconnect layer 112 through the conductive via, thereby obtaining… Figure 3 The structure shown is as follows. During the thinning process of the first chip 11, the support structure 13 can increase the total thickness of the entire chip stack structure and can serve as a structural support for the thinning of the first chip 11. Of course, in some cases, the thinning process of the first chip 11 can be omitted. For example, if the thickness of the first chip 11 is already thin, there is no need to thin it. Or, if the third interconnect layer 112 of the first chip 11 is located on the side of the third substrate 111 away from the support structure 13, the first chip 11 may not need to be thinned.

[0117] In other embodiments of this application, when the chip stacking structure has the structure described in Method 3 above, the fabrication method in the embodiments of this application may specifically include:

[0118] Reference Figure 8 In step (1), a bridging chip 17 is provided, and the bridging chip 17 has a second conductive via T2 that penetrates through the bridging chip 17. In specific implementation, the bridging chip 17 may have one or more second conductive vias T2. The number of second conductive vias T2 in the bridging chip 17 can be set according to actual needs, and is not limited here. In the above step S201, the second chip 12 and the bridging chip 17 are placed on top of the first chip 11, that is, the bridging chip 17 is placed on top of the first chip 11 in a position other than each of the second chips 12. Each of the second chips 12 is electrically connected to the first chip 11, and the bridging chip 17 is electrically connected to the first chip 11. In practical implementation, the second chip 12 and the bridging chip 17 can be electrically connected to the first chip 11 using a hybrid bonding method. The second chip 12 can be bonded first, followed by the bridging chip 17, or vice versa. The bonding order of the second chip 12 and the bridging chip 17 is not limited here. The specific bonding method between the second chip 12 and the first chip 11 can be referred to the above description. Figure 6 The relevant description in (1) will not be repeated here. In the embodiments of this application, the chip stacking structure may include one or more bridge chips 17. The number and position of the bridge chips 17 can be set according to actual needs, and are not limited here.

[0119] Reference Figure 8 In step (2) above, in step S202, dielectric material is filled on the area above the first chip 11 excluding each of the second chips 12 and the bridging chip 17 to form a dielectric layer 15. In some cases, the surface of the dielectric layer 15 may also be planarized and thinned. Afterwards, a second dielectric film 162 is formed on each of the second chips 12 and the bridging chip 17, and an interconnect line for leading out the second conductive via T2 is formed, and at least a portion of the interconnect line may be exposed on the surface of the second dielectric film 162.

[0120] Reference Figure 8In step (3), a support structure 13 is provided. The support structure 13 may include a first substrate 131 and a first interconnect layer 132. The first interconnect layer 132 has a first connection terminal Q1 on its surface facing away from the first substrate 131. Step S202 may specifically include: placing the support structure 13 on each of the second chips 12, with the first interconnect layer 132 of the support structure 13 facing the second chip 12. The support structure 13 is bonded to each of the second chips 12, so that the first connection terminal Q1 is electrically connected to the second conductive via T2, so that the first connection terminal Q1 is electrically connected to the second interconnect layer 122 and / or the first chip 11 through the second conductive via T2. In this embodiment, by installing a bridging chip 17 on the first chip 11, the first connection terminal Q1 can be electrically connected to the second interconnect layer 122 and / or the first chip 11 without drilling holes in the second chip 12, simplifying the process flow of the second chip, increasing the active area ratio of the second chip, and thus reducing costs.

[0121] Continue to refer to Figure 8 In step (3), the support structure 13 may further include a first dielectric film 161 and a first connection terminal Q1. The first dielectric film 161 is located on the side of the first interconnect layer 132 near the second chip 12. The first connection terminal Q1 is electrically connected to the first interconnect layer 132 and is exposed through a via in the first dielectric film 161. During the bonding process in step S202 above, the second dielectric film 162 on the surface of the second chip 12 is bonded to the first dielectric film 161 on the surface of the support structure 13, and the first connection terminal Q1 is bonded to the second conductive via T2, so that the support structure 13 is mixed-bonded with the underlying die and wafer stack structure (the stack structure composed of the second chip 12 and the first chip 11).

[0122] Following step S202 above, the fabrication method in this embodiment may further include: using the support structure 13 as a structural support, thinning the surface of the first chip 11 on the side opposite to the second chip 12. Furthermore, a hole may be drilled in the third substrate 111, and conductive material may be filled into the formed hole to form a conductive via penetrating the third substrate 111. This conductive via can be electrically connected to the third interconnect layer 112. Then, a fourth connection terminal Q4 is formed on the first chip 11. The fourth connection terminal Q4 can be electrically connected to the third interconnect layer 112 through the conductive via, thereby obtaining… Figure 4The structure shown is as follows. During the thinning process of the first chip 11, the support structure 13 can increase the total thickness of the entire chip stack structure and can serve as a structural support for the thinning of the first chip 11. Of course, in some cases, the thinning process of the first chip 11 can be omitted. For example, if the thickness of the first chip 11 is already thin, there is no need to thin it. Or, if the third interconnect layer 112 of the first chip 11 is located on the side of the third substrate 111 away from the support structure 13, the first chip 11 may not need to be thinned.

[0123] The above describes the fabrication methods for chip stack structures with the structures described in methods one to three. In specific implementations, when methods one to three are combined with each other, or when the first interconnect layer and the second chip use other interconnection methods, the above fabrication methods can be referred to, and repeated details will not be repeated. Furthermore, in the above description, the fabrication method of the chip stack structure is introduced using the example of a chip stack structure including a second chip. When the chip stack structure includes multiple chips, the fabrication process of the other chips can refer to the fabrication process of the second chip, and repeated details will not be repeated.

[0124] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0125] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A chip stacking structure, characterized in that, include: First chip; A support structure, wherein integrated passive components are provided in the support structure; At least one second chip, the at least one second chip being located between the first chip and the support structure; The first chip is electrically connected to the at least one second chip, and the support structure is connected to the at least one second chip; The integrated passive device is electrically connected to at least one of the second chips; and / or, the integrated passive device is electrically connected to the first chip.

2. The chip stacking structure as described in claim 1, characterized in that, The support structure includes: a first substrate and a first interconnect layer; The first interconnect layer is located on the side of the first substrate closer to the first chip, and the integrated passive device is located on the first substrate closer to the first interconnect layer; The integrated passive device is electrically connected to at least one of the second chips through the first interconnect layer; and / or, the integrated passive device is electrically connected to the first chip through the first interconnect layer.

3. The chip stacking structure as described in claim 2, characterized in that, The first interconnect layer has a first connection terminal on the surface near the first chip; The second chip includes: a second substrate and a second interconnect layer, wherein the second interconnect layer is located on the side of the second substrate closer to the first chip; The second chip has a first conductive via, which extends from the surface of the second substrate near the support structure to the interior of the second interconnect layer, and is electrically connected to the second interconnect layer. The first connection end is electrically connected to the end of the first conductive through hole near the support structure.

4. The chip stacking structure as described in claim 2, characterized in that, The first interconnect layer has a first connection terminal on its surface near the first chip; The second chip includes: a second substrate and a second interconnect layer, wherein the second interconnect layer is located on the side of the second substrate closer to the first chip; The chip stacking structure further includes: a dielectric layer located between the first chip and the support structure; the dielectric layer is provided with conductive dielectric vias; One end of the dielectric via near the support structure is electrically connected to the first connection end, and the other end is electrically connected to the second interconnect layer and / or the first chip.

5. The chip stacking structure as described in claim 2, characterized in that, The first interconnect layer has a first connection terminal on its surface near the first chip; The second chip includes: a second substrate and a second interconnect layer, wherein the second interconnect layer is located on the side of the second substrate closer to the first chip; The chip stacking structure further includes a bridging chip located between the first chip and the support structure; The bridging chip has a second conductive via, which penetrates the bridging chip. One end of the second conductive via near the support structure is electrically connected to the first connection end, and the other end is electrically connected to the second interconnect layer and / or the first chip.

6. The chip stacking structure as described in claim 5, characterized in that, The chip stack structure includes at least two second chips, and the bridging chip is located between two adjacent second chips.

7. The chip stacking structure according to any one of claims 3 to 6, characterized in that, The first chip includes: a third substrate and a third interconnect layer, wherein the third interconnect layer is located on the side of the third substrate closer to the support structure; The third interconnect layer has a second connection terminal on the surface near the second chip, and the second interconnect layer has a third connection terminal on the surface near the first chip. The second connection terminal is electrically connected to the third connection terminal.

8. A chip packaging structure, characterized in that, include: The chip stacking structure and substrate as described in any one of claims 1 to 7, wherein the chip stacking structure is fixed on the substrate.

9. An electronic device, characterized in that, include: The chip packaging structure and circuit board as described in claim 8, wherein the chip packaging structure is electrically connected to the circuit board.

10. A method for fabricating a chip stacking structure, characterized in that, include: At least one second chip is placed on top of the first chip, and the at least one second chip is electrically connected to the first chip; A support structure with an integrated passive device is placed on the side of the at least one second chip away from the first chip, and the support structure is connected to the at least one second chip; wherein the integrated passive device is electrically connected to the at least one second chip; and / or, the integrated passive device is electrically connected to the first chip.

11. The manufacturing method as described in claim 10, characterized in that, The first chip includes a third substrate and a third interconnect layer, and the second chip includes a second substrate and a second interconnect layer; The step of placing at least one second chip on top of the first chip and electrically connecting the at least one second chip to the first chip specifically includes: With the surface of the first chip having the third interconnect layer facing upwards, place the second chip on top of the first chip, and position the second interconnect layer of the second chip facing the third interconnect layer. The second chip and the first chip are hybrid bonded to achieve electrical connection between the second interconnect layer and the third interconnect layer.

12. The manufacturing method as described in claim 10 or 11, characterized in that, The second chip includes: a second substrate and a second interconnect layer, wherein the second interconnect layer is located on the side of the second substrate closer to the first chip; After electrically connecting the at least one second chip to the first chip, and before placing the support structure with integrated passive devices on the side of the second chip facing away from the first chip, the method further includes: The second chip is punched, and the formed hole is filled with conductive material to form a first conductive via that extends from the surface of the second substrate away from the first chip to the interior of the second interconnect layer; wherein the first conductive via is electrically connected to the second interconnect layer; Alternatively, before electrically connecting the at least one second chip to the first chip, the second chip has a first conductive via; after electrically connecting the at least one second chip to the first chip and before placing the support structure with integrated passive devices on the side of the second chip facing away from the first chip, the method further includes: The surface of the second substrate facing away from the first chip is thinned to expose the first conductive via. The support structure includes: a first substrate and a first interconnect layer, wherein the first interconnect layer has a first connection terminal on its surface facing away from the first substrate; the step of placing the support structure with integrated passive devices on the side of the second chip facing away from the first chip and connecting the support structure to the at least one second chip specifically includes: The support structure is placed on top of the second chip, with the first interconnect layer of the support structure facing the second chip; The support structure is bonded to the at least one second chip, so that the first connection end is electrically connected to the first conductive via.

13. The manufacturing method as described in claim 10 or 11, characterized in that, The second chip includes: a second substrate and a second interconnect layer, the second interconnect layer being located on the side of the second substrate closer to the first chip; after electrically connecting the at least one second chip to the first chip, and before placing the support structure with integrated passive devices on the side of the second chip facing away from the first chip, the method further includes: A dielectric material is filled into the gaps between each of the second chips to form a dielectric layer; A hole is drilled in the dielectric layer, and a conductive material is filled into the hole to form a dielectric via that penetrates the dielectric layer; the dielectric via is electrically connected to the second interconnect layer and / or the first chip. The support structure includes: a first substrate and a first interconnect layer, wherein the first interconnect layer has a first connection terminal on its surface facing away from the first substrate; the step of placing the support structure with integrated passive devices on the side of the second chip facing away from the first chip and connecting the support structure to the at least one second chip specifically includes: The support structure is placed on top of the second chip, with the first interconnect layer of the support structure facing the second chip; The support structure is bonded to the second chip, so that the first connection end is electrically connected to the dielectric via.

14. The manufacturing method as described in claim 10 or 11, characterized in that, The second chip includes: a second substrate and a second interconnect layer, the second interconnect layer being located on the side of the second substrate closer to the first chip; and before electrically connecting the at least one second chip to the first chip, it further includes: A bridging chip is placed on top of the first chip, except for the at least one second chip, and the bridging chip is electrically connected to the first chip; wherein, the bridging chip is provided with a second conductive via, the second conductive via penetrating the bridging chip; A dielectric material is filled in the area above the first chip, excluding each of the second chips and the bridging chip, to form a dielectric layer; The support structure includes: a first substrate and a first interconnect layer, wherein the first interconnect layer has a first connection terminal on its surface facing away from the first substrate; placing the support structure with integrated passive devices on the side of the second chip facing away from the first chip and connecting the support structure to the second chip specifically includes: The support structure is placed on top of the at least one second chip, with the first interconnect layer of the support structure facing the second chip; The support structure is bonded to the at least one second chip, so that the first connection end is electrically connected to the second conductive via, and the first connection end is electrically connected to the second interconnect layer through the second conductive via.

15. The manufacturing method according to any one of claims 10 to 14, characterized in that, After connecting the support structure to the at least one second chip, the method further includes: Using the aforementioned support structure as structural support, the surface of the first chip facing away from the second chip is thinned.

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