Three-dimensional vertical power supply structure integrated with micro-channels, and manufacturing method therefor

Abstract

The present invention relates to a three-dimensional vertical power supply structure integrated with micro-channels, and a manufacturing method therefor. The structure comprises: a first silicon wafer; a gate driving layer; a first redistribution layer; a first bonding protection layer; a second silicon wafer; a power transistor layer; a second redistribution layer; a second bonding protection layer; a first micro-channel; a second micro-channel, wherein the first micro-channel and the second micro-channel are interconnected, and inflow and outflow of a coolant are achieved by means of a micro-channel inlet and a micro-channel outlet; a first through-silicon via; and a second through-silicon via, wherein the gate driving layer and the power transistor layer are electrically connected by means of the first through-silicon via and the second through-silicon via. In the three-dimensional vertical power supply structure integrated with micro-channels provided by the present invention, using through-silicon vias for vertical interconnection and power delivery between the gate driving layer and the power transistor layer can significantly improve the power efficiency, and integrating the micro-channels into the power supply structure allows for rapid heat dissipation of the power supply structure.

Description

Three-dimensional vertical power supply structure integrated with microfluidic channel and manufacturing method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a three-dimensional vertical power supply structure integrated with microfluidic channel and manufacturing method thereof. BACKGROUND

[0002] With the continuous evolution of advanced process nodes, and the rapid growth of demand for greater computing power in artificial intelligence, data centers and high-performance computing applications, the power of high-performance processors (such as graphics processing units GPU, central processing units CPU, application-specific integrated circuits ASIC, etc.) is rising, and the core voltage is falling. These developments bring great challenges to power supply, such as strong demand for power integrity in the package, including the need to manage the voltage gradient between the power pins of a large-current low-voltage processor caused by the rising impedance of the power distribution network (PDN), transient performance specifications, and power consumption.

[0003] The prior art usually arranges a voltage regulator module (VRM) on a printed circuit board (PCB) and supplies power to the chip through a multi-stage PDN, but the current flowing out of the VRM needs to pass through a long interconnection path to reach the chip, and the PDN impedance is high and the loss is large. When the high-performance processor has a large load current demand, the PDN impedance will cause a sharp drop in voltage and unacceptable conduction loss, thereby severely limiting the performance of the processor and reducing the energy efficiency of the system. In addition, the resulting low power efficiency requires a larger size of thermal management solution, thereby generating a larger heat dissipation problem, which will have a bad impact on the normal operation of the high-performance processor.

[0004] Therefore, with the sharp rise in power and thermal power consumption of high-performance processors, the demand for power supply and heat dissipation has increased sharply, and the existing arrangement of VRM on the PCB plus multi-stage PDN gradually cannot meet the demand. SUMMARY

[0005] In view of some or all of the problems in the prior art, the present application provides a three-dimensional vertical power supply structure integrated with microfluidic channel, which comprises:

[0006] a first silicon wafer;

[0007] a gate drive layer arranged on a first surface of the first silicon wafer;

[0008] a first rewiring layer arranged on a first surface of the gate drive layer;

[0009] a first bonding protection layer arranged on a second surface of the first silicon wafer;

[0010] a second silicon wafer;

[0011] a power transistor layer arranged on a first surface of the second silicon wafer;

[0012] a second redistribution layer arranged on a first surface of the power transistor layer;

[0013] a second bonding protection layer arranged on a second surface of the second silicon wafer;

[0014] a first microfluidic channel arranged in the first silicon wafer;

[0015] a second microfluidic channel arranged in the second silicon wafer;

[0016] the first microfluidic channel and the second microfluidic channel are interconnected, and the inflow and outflow of the cooling liquid are realized through a microfluidic inlet and a microfluidic outlet;

[0017] a first through-silicon via penetrating through the first silicon wafer and the first bonding protection layer;

[0018] a second through-silicon via penetrating through the second silicon wafer and the second bonding protection layer;

[0019] the gate drive layer and the power transistor layer are electrically connected through the first through-silicon via and the second through-silicon via.

[0020] Further, the first redistribution layer comprises a first interconnection pad electrically connected with the gate drive layer; and / or

[0021] the second redistribution layer comprises a second interconnection pad electrically connected with the power transistor layer.

[0022] Further, the power supply path of the integrated microfluidic three-dimensional vertical power supply structure is as follows:

[0023] the gate drive layer drives the power transistor layer, and the power transistor layer supplies power to the chip power supply.

[0024] The application also provides a manufacturing method of the integrated microfluidic three-dimensional vertical power supply structure, which comprises the following steps:

[0025] a gate drive layer is made on a first surface of a first silicon wafer;

[0026] A first redistribution layer is fabricated on a first surface of the gate drive layer;

[0027] A first temporary bonding layer is fabricated on a first surface of the first redistribution layer, and a first wafer sheet is bonded on a first surface of the first temporary bonding layer to form a first wafer sheet structure;

[0028] The first wafer sheet structure is flipped, and a second surface of the first silicon wafer is thinned;

[0029] A first bonding protection layer is fabricated on the second surface of the first silicon wafer, and the first bonding protection layer and the first silicon wafer are etched to form a first through-silicon via recess;

[0030] A first through-silicon via filler is deposited in the first through-silicon via recess to form a first through-silicon via;

[0031] The first bonding protection layer and the first silicon wafer are etched to form a first microfluidic channel, and a wafer structure comprising a gate drive layer is formed;

[0032] A wafer structure comprising a power transistor layer is formed, and the wafer structure comprising a power transistor layer includes a second silicon wafer, a power transistor layer, a second redistribution layer, a second temporary bonding layer, a second wafer sheet, a second bonding protection layer, a second through-silicon via, and a second microfluidic channel;

[0033] The wafer structure comprising a gate drive layer is bonded face-to-face with the wafer structure comprising a power transistor layer;

[0034] The first wafer sheet is removed, and a microfluidic channel inlet and a microfluidic channel outlet are punched at positions corresponding to inlets and outlets of the first microfluidic channel;

[0035] The second wafer sheet is removed, and an integrated microfluidic channel three-dimensional vertical power supply structure is cut.

[0036] Further, the first redistribution layer is fabricated using a damascene process, and the first redistribution layer includes a first interconnection pad; and / or

[0037] The second redistribution layer is fabricated using a damascene process, and the second redistribution layer includes a second interconnection pad.

[0038] Further, the first temporary bonding layer is silicon oxide, silicon nitride, silicon oxynitride, or organic bonding glue; and / or

[0039] The second temporary bonding layer is silicon oxide, silicon nitride, silicon oxynitride, or organic bonding glue.

[0040] Further, the first bonding protection layer is silicon oxide, silicon nitride, or silicon oxynitride; and / or

[0041] The second bonding protection layer is silicon oxide or silicon nitride or silicon oxynitride.

[0042] Further, the first through-silica via includes a first bonding pad; and / or

[0043] The second through-silica via includes a second bonding pad.

[0044] Further, the face-to-face bonding is a hybrid bonding, the first bonding pad is bonded with the second bonding pad, and the first bonding protection layer is bonded with the second bonding protection layer.

[0045] Further, the first carrier wafer is removed using mechanical separation or thermal slip or laser separation; and / or

[0046] The second carrier wafer is removed using mechanical separation or thermal slip or laser separation.

[0047] The technical solution provided by the present application has the following beneficial effects:

[0048] 1. The three-dimensional vertical power supply structure integrated with micro flow channels provided by the present application, which respectively manufactures a wafer structure containing a gate drive layer and a wafer structure containing a power transistor layer, significantly reduces the interconnection resistance and parasitic parameters, and improves the power supply efficiency.

[0049] 2. The three-dimensional vertical power supply structure integrated with micro flow channels provided by the present application, which vertically interconnects and supplies power to the gate drive layer and the power transistor layer through the through-silica via, can significantly improve the power supply transient response and reduce the loss of the power distribution network.

[0050] 3. The three-dimensional vertical power supply structure integrated with micro flow channels provided by the present application, which integrates micro flow channels in the power supply structure, can quickly cool the power supply structure and high-performance processors, and has excellent heat dissipation performance. BRIEF DESCRIPTION OF DRAWINGS

[0051] To further illustrate the above and other advantages and features of the embodiments of the present application, more detailed description of the embodiments of the present application will be presented with reference to the accompanying drawings. It can be understood that these drawings only depict typical embodiments of the present application, and therefore should not be considered as limiting the scope thereof. In the drawings, for the sake of clarity and conciseness, the same or corresponding components will be denoted by the same or similar reference numerals.

[0052] FIG. 1 shows a schematic diagram of a three-dimensional vertical power supply structure integrated with micro flow channels according to an embodiment of the present application;

[0053] FIG. 2 shows a schematic diagram of a power supply path of a three-dimensional vertical power supply structure integrated with micro flow channels according to an embodiment of the present application;

[0054] FIG. 3 shows a flow diagram of a method for fabricating a three-dimensional vertical power supply structure of an integrated microfluidic channel according to an embodiment of the present application; and

[0055] FIGS. 4a-4k show cross-sectional views of a process for forming a three-dimensional vertical power supply structure of an integrated microfluidic channel according to an embodiment of the present application. DETAILED DESCRIPTION

[0056] In the following description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration various embodiments for practicing the present application. It is to be understood that other embodiments can be utilized and structural or

[0057] In this specification, reference can be made to "one embodiment", or "the embodiment", meaning that a particular feature, structure, or characteristic described in connection with this embodiment is included in at least one embodiment of the present application. The appearance of the phrases "in one embodiment" or "in at least one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0058] In this specification, unless specifically stated otherwise, "disposed on", "disposed above", and "disposed over" do not exclude the presence of an intermediate element between the elements being described. Further, "disposed on or above" merely indicates a relative position of two components, and can be converted to "disposed below or under" in certain cases, such as when the product is inverted, and vice versa.

[0059] In this specification, unless specifically stated otherwise, "first surface", "second surface" are used to describe surfaces of the same component. Further, "first", "second", "third" are used to distinguish descriptions, and do not imply a difference in size.

[0060] In this specification, unless specifically stated otherwise, the indefinite article "a" or "an" does not exclude a plurality of elements, and the indefinite article "a" or "an" means one or more.

[0061] It has to be noted that, as used in the present application, the term "comprising" is not used in the sense of "only comprising", but in the sense of "including", i.e. "comprising" can mean "consisting only of, but it also means "consisting of, and "consisting essentially of, to the extent that the Dictionaries of National Languages and the Oxford English Dictionary allow for such

[0062] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application.

[0063] With the sharp rise of power and thermal dissipation of high-performance chips, the demand for power supply and heat dissipation increases sharply, and the existing way of arranging VRM on the PCB and adding a multi-stage PDN gradually cannot meet the demand of high-performance chips for power supply and heat dissipation. The present application provides a three-dimensional vertical power supply structure integrated with micro flow channels, a wafer structure containing a gate drive layer and a wafer structure containing a power transistor layer are respectively manufactured, the gate drive layer and the power transistor layer are vertically interconnected and powered through a through silicon via, which can significantly improve power efficiency, improve power supply transient response, and reduce PDN loss. The three-dimensional vertical power supply structure integrated with micro flow channels provided by the present application integrates micro flow channels in the power supply structure, which can quickly dissipate heat for the power supply structure and high-performance processors, and has excellent heat dissipation performance.

[0064] Figure 1 shows a schematic diagram of a three-dimensional vertical power supply structure integrated with micro flow channels according to an embodiment of the present application. The three-dimensional vertical power supply structure integrated with micro flow channels includes two parts, a wafer structure containing a gate drive layer and a wafer structure containing a power transistor layer. As shown in Figure 1, the wafer structure containing the gate drive layer includes a first silicon wafer 101, a gate drive layer 102, a first rewiring layer 103, a first bonding protection layer 106, a first through silicon via 108, a first micro flow channel 109, a micro flow channel inlet 111, and a micro flow channel outlet 112. The wafer structure containing the power transistor layer includes a second silicon wafer 201, a power transistor layer 202, a second rewiring layer 203, a second bonding protection layer 206, a second through silicon via 208, and a second micro flow channel 209.

[0065] The gate driver layer 102 is arranged on the first surface of the first silicon wafer 101, and is mainly used for driving transistors. The first redistribution layer 103 is arranged on the first surface of the gate driver layer 102. In an embodiment of the present application, the first redistribution layer 103 can be manufactured by a back-end of line (BEOL), and the first redistribution layer 103 can include multiple dielectric layers and metal layers. In an embodiment of the present application, the first redistribution layer 103 includes a first interconnection pad, the first interconnection pad is electrically connected to the gate driver layer 102, the first interconnection pad is manufactured by a metal layer, and the first interconnection pad can be manufactured by Au, Cu, Al or an alloy thereof. The first bonding protection layer 106 is arranged on the second surface of the first silicon wafer 101, and the first bonding protection layer 106 is an inorganic film layer, and is preferably silicon oxide or silicon nitride or silicon oxynitride. The first through silicon via 108 penetrates the first silicon wafer 101 and the first bonding protection layer 106, and the first through silicon via 108 is filled with a first through silicon via filler. In an embodiment of the present application, the first through silicon via filler can be Au, Cu, Sn, In or an alloy thereof. The first microfluidic channel 109 is arranged in the first silicon wafer 101.

[0066] The power transistor layer 202 is arranged on the first surface of the second silicon wafer 201, and is mainly used for driving transistors. The second redistribution layer 203 is arranged on the first surface of the power transistor layer 202. In an embodiment of the present application, the second redistribution layer 203 can be manufactured by a back-end of line (BEOL), and the second redistribution layer 203 can include multiple dielectric layers and metal layers. In an embodiment of the present application, the second redistribution layer 203 includes a second interconnection pad, the second interconnection pad is electrically connected to the power transistor layer 202, the second interconnection pad is manufactured by a metal layer, and the second interconnection pad can be manufactured by Au, Cu, Al or an alloy thereof. The second bonding protection layer 206 is arranged on the second surface of the second silicon wafer 201, and the second bonding protection layer 206 is an inorganic film layer, and is preferably silicon oxide or silicon nitride or silicon oxynitride. The second through silicon via 208 penetrates the second silicon wafer 201 and the second bonding protection layer 206, and the second through silicon via 208 is filled with a second through silicon via filler. In an embodiment of the present application, the second through silicon via filler can be Au, Cu, Sn, In or an alloy thereof. The second microfluidic channel 209 is arranged in the second silicon wafer 201.

[0067] The first microfluidic channel 109 and the second microfluidic channel 209 are interconnected, the inflow and outflow of the cooling liquid are realized through the microfluidic channel inlet 111 and the microfluidic channel outlet 112, and the power supply structure is quickly cooled through the flow of the cooling liquid in the first microfluidic channel 109 and the second microfluidic channel 209. The microfluidic channel inlet 111 and the microfluidic channel outlet 112 are made at the positions corresponding to the inlets and outlets of the first microfluidic channel 109. According to needs, the microfluidic channel inlet 111 and the microfluidic channel outlet 112 can also be made at the positions corresponding to the inlets and outlets of the second microfluidic channel 209.

[0068] In an embodiment of the present application, the first through-silica via 108 includes a first bonding pad, and the second through-silica via 208 includes a second bonding pad. The gate drive layer 102 and the power transistor layer 202 are electrically connected through the first through-silica via 108 and the second through-silica via 208.

[0069] FIG. 2 shows a schematic diagram of a power supply path of a three-dimensional vertical power supply structure integrated with a microfluidic channel according to an embodiment of the present application. As shown in FIG. 2, the SoC (System on Chips) includes a Driver Logic and Delay structure, wherein the Driver Logic structure is used to generate a PWM / PFM driving waveform, and the Delay structure is used to realize delay compensation to reduce output duty cycle distortion. The gate drive Gate Drivers are composed of a HS Driver and a LS Driver, wherein the HS Driver represents a High Side Driver, and the LS Driver represents a Low Side Driver. The HS Driver and the LS Driver are used to amplify the control signals generated by the Driver Logic and Delay structure in the SoC to drive the opening and closing of the HS MOSFET and the LS MOSFET, and adjust the output. The Power Transistors include a plurality of power transistors, and the HS MOSFET and the LS MOSFET represent power transistors on the high side (High Side) and the low side (Low Side), respectively. In most application scenarios, both of them are N-channel MOS tubes, and can also be GaN, P-channel MOS tubes, etc. In use, the HS MOSFET needs a voltage lifting circuit due to the floating of the driving signal, the source is connected to the VIN, and the VIN represents the power supply input from the PCB into the package; the driving signal of the LS MOSFET is a ground signal, and no voltage lifting circuit is needed in the driving circuit, so the drain of the MOSFET is connected to the ground, L represents an inductor, C represents a capacitor, and Vout represents the power output of the three-dimensional vertical power supply structure.

[0070] The power supply required by the SoC is divided into two parts, the first part is the power supply required by the Driver Logic and Delay structure in the SoC, and the second part is the power supply required by the working condition of the SoC. The power supply path of the three-dimensional vertical power supply structure integrated with the microfluid channel is as follows: an external power supply such as a PCB power supply directly supplies power to the Driver Logic and Delay structure in the SoC to drive the Driver Logic and Delay structure; the Driver Logic and Delay structure drives the gate driving layer; the gate driving layer drives the power transistor layer; the power transistor layer outputs Vout, and Vout directly supplies the power required by the working condition of the SoC through the through-silicon via near the inductor.

[0071] It should be noted that the structure shown in FIG. 2 is in a simplified form, and in actual application, related bootstrap capacitors, feedback resistors and the like can be added according to actual needs, and these devices can be integrated into the structure described in the application or provided through external connection or other means.

[0072] FIG. 3 shows a flowchart of a manufacturing method of the three-dimensional vertical power supply structure integrated with the microfluid channel according to an embodiment of the application. FIGS. 4a-4k show cross-sectional views of the process of forming the three-dimensional vertical power supply structure integrated with the microfluid channel according to an embodiment of the application.

[0073] The manufacturing method of the three-dimensional vertical power supply structure integrated with the microfluid channel according to an embodiment of the application will be described below in combination with FIG. 3 and FIGS. 4a-4k.

[0074] First, the gate driving layer 102 is made on the first surface of the first silicon wafer 101, as shown in FIG. 4a. In an embodiment of the application, the gate driving layer 102 is made by a front end of line (FEOL) process, which includes wafer cleaning, oxidation, doping, deposition, exposure, etching and the like.

[0075] Next, the first heavy wiring layer 103 is made on the first surface of the gate driving layer 102, as shown in FIG. 4b. The first heavy wiring layer 103 is made by a damascene process, and the first heavy wiring layer 103 includes a first interconnection pad. The first heavy wiring layer 103 can include multiple dielectric layers and metal layers. In an embodiment of the application, the first heavy wiring layer 103 includes a first interconnection pad, the first interconnection pad is electrically connected to the gate driving layer 102, the first interconnection pad is made of a metal layer, and the first interconnection pad can be made of pure metals such as Au, Cu, Al or alloys thereof.

[0076] Next, a first temporary bonding layer 104 is made on the first surface of the first redistribution layer 103, and a first carrier 105 is bonded on the first surface of the first temporary bonding layer 104 to form a first carrier structure, as shown in FIG. 4c. In an embodiment of the present application, the first temporary bonding layer 104 can be silicon oxide or silicon nitride or silicon oxynitride or an organic bonding glue, which can be TMAT, BSI, 3M, and DuPont bonding glue. In an embodiment of the present application, the first carrier 105 can be a glass or a silicon wafer or a metal plate.

[0077] Next, the first carrier structure is flipped, and the second surface of the first silicon wafer 101 is thinned, as shown in FIG. 4d. In an embodiment of the present application, the thinning includes mechanical thinning and etching.

[0078] Next, a first bonding protection layer 106 is made on the second surface of the first silicon wafer 101, and the first bonding protection layer 106 and the first silicon wafer 101 are etched to form a first through-silica via recess 107, as shown in FIG. 4e. In an embodiment of the present application, the first bonding protection layer 106 can be an inorganic film layer, preferably silicon oxide or silicon nitride or silicon oxynitride.

[0079] Next, a first through-silica via filler is deposited in the first through-silica via recess 107 to form a first through-silica via 108, as shown in FIG. 4f. In an embodiment of the present application, the first through-silica via filler can be a pure metal such as Au, Cu, Sn, In, or an alloy such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu. In an embodiment of the present application, the first through-silica via 108 includes a first bonding pad.

[0080] Next, the first bonding protection layer 106 and the first silicon wafer 101 are etched to form a first microfluidic channel 109 to form a wafer structure including a gate drive layer, as shown in FIG. 4g.

[0081] Next, a wafer structure including a power transistor layer is formed, as shown in FIG. 4h. The wafer structure including the power transistor layer includes a second silicon wafer 201 and a power transistor layer 202 and a second redistribution layer 203 and a second temporary bonding layer 204 and a second carrier 205 and a second bonding protection layer 206 and a second through-silicon via 208 and a second microfluidic channel 209. The second redistribution layer 203 can include a plurality of dielectric layers and metal layers. In an embodiment of the present application, the second redistribution layer 203 includes a second interconnection pad, the second interconnection pad is electrically connected with the power transistor layer, the second interconnection pad is made of a metal layer, and the second interconnection pad can be made of a pure metal such as Au, Cu, Al, or an alloy thereof. In an embodiment of the present application, the second temporary bonding layer 204 can be silicon oxide or silicon nitride or silicon oxynitride or an organic bonding glue, and the organic bonding glue can be TMAT, BSI, 3M, and DuPont bonding glue. In an embodiment of the present application, the second carrier 205 can be a glass or a silicon wafer or a metal plate. In an embodiment of the present application, the second bonding protection layer 206 can be an inorganic film layer, and preferably silicon oxide or silicon nitride or silicon oxynitride. In an embodiment of the present application, a second through-silicon via filler is deposited in the second through-silicon via 208, and the second through-silicon via filler can be a pure metal such as Au, Cu, Sn, In, or an alloy such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu. In an embodiment of the present application, the second through-silicon via 208 includes a second bonding pad.

[0082] Next, the wafer structure including the gate drive layer is face-to-face bonded with the wafer structure including the power transistor layer, as shown in FIG. 4i. The face-to-face bonding can be hybrid bonding, the first bonding pad is bonded with the second bonding pad, and the first bonding protection layer is bonded with the second bonding protection layer. The first bonding pad and the second bonding pad are bonded to form an electrical connection, so that the first through-silicon via is electrically connected with the second through-silicon via.

[0083] Next, the first carrier is removed, and a microfluidic channel inlet 111 and a microfluidic channel outlet 112 are punched at positions corresponding to the inlet and outlet of the first microfluidic channel, as shown in FIG. 4j. In an embodiment of the present application, the first carrier is removed by mechanical separation or thermal slip or laser separation.

[0084] Finally, the second carrier is removed, and a three-dimensional vertical power supply structure integrated with a microfluidic channel is cut, as shown in FIG. 4k. In an embodiment of the present application, the second carrier is removed by mechanical separation or thermal slip or laser separation.

[0085] The three-dimensional vertical power supply structure integrated with micro flow channels comprises a wafer structure containing a gate drive layer and a wafer structure containing a power transistor layer, and the gate drive layer and the power transistor layer are vertically interconnected and powered through a through silicon via, so that the power supply efficiency can be significantly improved, the power supply transient response is improved, the loss of the power distribution network is reduced, the micro flow channels are integrated in the power supply structure, the power supply structure and the high-performance processor can be quickly cooled, and the heat dissipation performance is excellent.

[0086] While the foregoing describes embodiments of the application, such description should be considered as exemplary and not restrictive in character. Various modifications and variations can be made to the disclosed embodiments without departing from the spirit or scope of the application. Therefore, it should be understood that the application is not to be limited by what is disclosed herein, but only by the scope of the appended claims and their equivalents.

Claims

1. A three-dimensional vertical power supply structure for integrated microfluidics, characterized by, Comprise: a first silicon wafer; a gate drive layer arranged on a first surface of the first silicon wafer; a first redistribution layer arranged on a first surface of the gate drive layer; a first bonding protection layer arranged on a second surface of the first silicon wafer; a second silicon wafer; a power transistor layer arranged on a first surface of the second silicon wafer; a second redistribution layer arranged on a first surface of the power transistor layer; a second bonding protection layer arranged on a second surface of the second silicon wafer; a first microfluidic channel arranged in the first silicon wafer; a second microfluidic channel arranged in the second silicon wafer; the first microfluidic channel and the second microfluidic channel are interconnected, and the inflow and outflow of the cooling liquid are realized through a microfluidic inlet and a microfluidic outlet; a first through-silicon via penetrating through the first silicon wafer and the first bonding protection layer; a second through-silicon via penetrating through the second silicon wafer and the second bonding protection layer; the gate drive layer and the power transistor layer are electrically connected through the first through-silicon via and the second through-silicon via.

2. The integrated microfluidic three-dimensional vertical power supply structure according to claim 1, wherein: the first redistribution layer comprises a first interconnection pad electrically connected with the gate drive layer; and / or the second redistribution layer comprises a second interconnection pad electrically connected with the power transistor layer.

3. The integrated microfluidic three-dimensional vertical power supply structure of claim 1, wherein, The power supply path of the integrated microfluidic three-dimensional vertical power supply structure is: the gate drive layer drives the power transistor layer, and the power transistor layer supplies power to the chip power supply.

4. A method of manufacturing a three-dimensional vertical power supply structure for integrated microfluidics, characterized by, Comprise the following steps: on a first surface of a first silicon wafer, a gate drive layer is made; on a first surface of the gate drive layer, a first redistribution layer is made; on a first surface of the first redistribution layer, a first temporary bonding layer is made, and a first carrier sheet is bonded on a first surface of the first temporary bonding layer to form a first carrier sheet structure; the first carrier sheet structure is turned over, and a second surface of the first silicon wafer is thinned; a first bonding protection layer is made on a second surface of the first silicon wafer, and the first bonding protection layer and the first silicon wafer are etched to form a first through-silicon via groove; a first through-silicon via filler is deposited in the first through-silicon via groove to form a first through-silicon via; the first bonding protection layer and the first silicon wafer are etched to form a first microfluidic channel, and a wafer structure comprising a gate drive layer is formed; a wafer structure comprising a power transistor layer is formed, which comprises a second silicon wafer, a power transistor layer, a second redistribution layer, a second temporary bonding layer, a second carrier sheet, a second bonding protection layer, a second through-silicon via, and a second microfluidic channel; the wafer structure comprising a gate drive layer is bonded face to face with the wafer structure comprising a power transistor layer; removing the first carrier wafer and punching the first carrier wafer to form a microfluidic inlet and a microfluidic outlet at the corresponding positions of the microfluidic inlet and the microfluidic outlet of the first microfluidic channel; removing the second carrier wafer and cutting to form a three-dimensional vertical power supply structure integrated with the microfluidic channel. 5.The method of claim 4, wherein the first redistribution layer is fabricated using a damascene process, and the first redistribution layer includes first interconnection pads; and / or the second redistribution layer is fabricated using a damascene process, and the second redistribution layer includes second interconnection pads. 6.The method of claim 4, wherein the first temporary bonding layer is silicon oxide, silicon nitride, silicon oxynitride, or an organic bonding glue; and / or the second temporary bonding layer is silicon oxide, silicon nitride, silicon oxynitride, or an organic bonding glue. 7.The method of claim 4, wherein the first bonding protection layer is silicon oxide, silicon nitride, or silicon oxynitride; and / or the second bonding protection layer is silicon oxide, silicon nitride, or silicon oxynitride. 8.The method of claim 4, wherein the first through-silicon via includes a first bonding pad; and / or the second through-silicon via includes a second bonding pad. 9.The method of claim 4 or 8, wherein the face-to-face bonding is a hybrid bonding, the first bonding pad is bonded to the second bonding pad, and the first bonding protection layer is bonded to the second bonding protection layer. 10.The method of claim 4, wherein the first carrier wafer is removed using mechanical separation, thermal slip, or laser separation; and / or the second carrier wafer is removed using mechanical separation, thermal slip, or laser separation. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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