Three-dimensional core particle stacked system-on-chip and manufacturing method thereof
By using a vertical interconnect structure for a three-dimensional stacked system-on-a-chip, the problem of low system-on-a-chip integration is solved, achieving high integration, low power consumption, and high speed chip packaging.
Patent Information
- Application Number
- CN202511696813.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-03-03
AI Technical Summary
Existing system-in-package (SiP) technology has low integration density and cannot effectively integrate chips with different process technologies, resulting in increased size during the packaging process.
The system-on-a-chip (SoC) structure employs a three-dimensional stacked chip structure, achieving vertical conductive interconnection through a vertical interconnection adapter between the main chip and the sub-chip. This adapter includes a combination of first and second bottom metal microbumps and a top metal microbump, filled with an insulating medium to form a dielectric plug for the vertical interconnection adapter.
It improves chip integration, reduces package size, lowers power consumption, and increases speed.
Smart Images
Figure CN121604875A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor chip manufacturing, and in particular to a three-dimensional stacked system-on-a-chip and its manufacturing method. Background Technology
[0002] System-in-Package (SiP) combines multiple active components with different functions, as well as passive components, microelectromechanical systems (MEMS), optical components, and other components, into a single unit to form a system or subsystem that can provide multiple functions, allowing for the integration of heterogeneous ICs. It effectively solves the problem that System-on-Chip (SoC) cannot integrate analog, radio frequency, and digital functions. SiP integration is relatively simple, with shorter design and time-to-market cycles, lower costs, and the ability to implement more complex systems.
[0003] In existing technologies, during chip packaging, the chip is first bonded to one side of a wafer without being electrically connected to the wafer. Then, a molding process is performed to seal and fix the chip. Finally, a via (with a conductive structure within it) is formed on the other side of the wafer to allow the chip's electrical signals to be led out. However, existing technologies suffer from low system-level packaging integration. Summary of the Invention
[0004] To address the aforementioned problems, the present invention aims to provide a three-dimensional stacked chip system-on-a-chip comprising: Main chip, including the main chip I / O pads disposed on the surface; The sub-core includes a first sub-core I / O pad and a second sub-core I / O pad disposed on the front side. The front side is bonded to the surface of the main core by a bonding body, and the corresponding first sub-core I / O pad is perpendicular to the main core I / O pad, and the corresponding second sub-core I / O pad is perpendicular to the main core I / O pad. A vertical interconnect adapter includes a first bottom metal microbump and a first top metal microbump disposed on the surface of the first bottom metal microbump portion. The first sub-core I / O pad and the main core I / O pad are vertically electrically interconnected through the first bottom metal microbump and the first top metal microbump. The surface of the first bottom metal microbump is also filled with a vertical interconnect adapter dielectric plug penetrating the sub-core. The vertical interconnect adapter also includes a second bottom metal microbump and a second top metal microbump disposed on the surface of the second bottom metal microbump. The second sub-core I / O pad and the main core I / O pad are vertically conductively interconnected through the second bottom metal microbump and the second top metal microbump. A vertical conductive plug is disposed on the surface of the second sub-core I / O pad, and a vertical interconnect adapter pad is disposed on the top of the vertical conductive plug.
[0005] In addition, the present invention also provides a method for manufacturing a three-dimensional stacked system-on-a-chip, comprising the following steps: S10: Provide a wafer comprising at least two identical master dies arranged in an array, the master dies comprising master die I / O metal pads disposed on a surface; Several sub-cores are provided, including a first sub-core I / O pad and a second sub-core I / O pad disposed on the front side. The first sub-core I / O pad has a through hole that passes through the sub-core on its periphery, and the bottom of the second sub-core I / O pad is interconnected with vertical conductive plugs that pass through the sub-core. Bonds are formed on the wafer, exposing the main die I / O metal pads; S20: The sub-core is bonded to the main core with the front side of the bonding body facing the main core. The I / O pads of the sub-core are perpendicular to the I / O metal pads of the main core and have a first cavity that communicates with the through-hole of the sub-core. The first sub-core I / O pads are perpendicular to the I / O metal pads of the main core and have a second cavity. The second sub-core I / O pads are perpendicular to the I / O metal pads of the main core and have a cavity. S30: A first top metal microbump is formed on the surface of the first sub-core I / O pad through the through-hole of the sub-core, and a first bottom metal microbump is formed on the surface of the main core I / O metal pad. The first top metal microbump covers part of the surface of the first bottom metal microbump and is electrically interconnected. A second top metal microbump is formed on the surface of the second sub-core I / O pad through the through-hole of the sub-core or the outer edge of the sub-core, and a second bottom metal microbump is formed on the surface of the main core I / O metal pad. The second top metal microbump covers the surface of the second bottom metal microbump and is electrically interconnected. S40: Fill the through-hole of the core particle with an insulating medium to form a vertical dielectric plug; S50: Vertical interconnect adapter pads formed on the surface of the back side of the sub-core and interconnected with vertical conductive plugs.
[0006] This invention solves the problem that chips with different process technologies cannot be produced on the same production line by three-dimensional chip stacking, as well as the problem of increased size caused by packaging chips with different process technologies. This results in larger computing chips with higher integration, lower power consumption, and faster speed. Attached Figure Description
[0007] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0008] Figure 1 This is a cross-sectional schematic diagram of a three-dimensional stacked system-on-a-chip according to an embodiment of the present invention; Figure 2 This is a schematic flowchart of a method for manufacturing a three-dimensional stacked system-on-a-chip according to an embodiment of the present invention; Figure 3 This is a schematic diagram of an intermediate process in the manufacturing method of a three-dimensional stacked system-on-a-chip according to an embodiment of the present invention.
[0009] For ease of understanding and explanation, the labels in the diagram are as follows: Main chip - 900; Main chip I / O pads - 911; Sub-chip - 100 First sub-core I / O pad - 111; Second sub-core I / O pad - 112; Bonding assembly - 101 Vertical interconnect adapter-180; Vertical conductive plug-181 First bottom metal microbump - 151B; First top metal microbump - 151T Second bottom metal microbump - 161B; Second top metal microbump - 161T Vertical interconnect adapter pad-191; Vertical interconnect adapter dielectric plug-192 Vertical interconnect dielectric sidewall-161; third sub-core-300 Second core particle - 200; Through hole - 210; First cavity - 220 Second cavity -230 Detailed Implementation
[0010] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.
[0011] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of the device in its normal operating state, while "inner" and "outer" refer to the parts relative to the outline of the device. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. This invention pertains to electrical devices; therefore, connection and interconnection both refer to conductive interconnections. Since the accompanying drawings describe the same device, the same reference numerals denote the same components. The term "chip front" as used herein refers to the side of the wafer used to form the device during chip manufacturing, and "back" refers to the substrate side of the wafer.
[0012] like Figure 1 As shown, one embodiment of the present invention provides a three-dimensional stacked system-on-a-chip, comprising: The main chip 900 includes main chip I / O pads 911 disposed on the surface; Sub-core 100 includes a first sub-core I / O pad 111 and a second sub-core I / O pad 112 disposed on the front side. The front side is bonded to the surface of the main core 900 by a bonding body 101. The corresponding first sub-core I / O pad 111 is perpendicular to the main core I / O pad 911, and the corresponding second sub-core I / O pad 112 is perpendicular to the main core I / O pad 911. The vertical interconnect adapter 180 includes a first bottom metal microbump 151B and a first top metal microbump 151T disposed on a portion of the surface of the first bottom metal microbump 151B. The first sub-core I / O pad 111 and the main core I / O pad 911 are vertically electrically interconnected through the first bottom metal microbump 151B and the first top metal microbump 151T. The surface of the first bottom metal microbump 151B is also filled with a vertical interconnect adapter dielectric plug 192 penetrating the sub-core 100. The vertical interconnect adapter 180 also includes a second bottom metal microbump 161B and a second top metal microbump 161T disposed on the surface of the second bottom metal microbump 161B. The second sub-chip I / O pad 112 and the main chip I / O pad 911 are vertically conductively interconnected through the second bottom metal microbump 161B and the second top metal microbump 161T. A vertical conductive plug 181 is disposed on the surface of the second sub-chip I / O pad 112. In this embodiment, a through silicon via (TSV) is interconnected on the second sub-chip I / O pad 112. A vertical interconnect adapter pad 191 is disposed on the top of the vertical conductive plug 181.
[0013] In one embodiment, the first bottom metal microbump 151B and the second bottom metal microbump 161B are integral. That is, the first top metal microbump 151B and the second top metal microbump 161B are interconnected with the same bottom metal microbump.
[0014] In one embodiment, the outer side of the sub-core 100 and the outer side of the second bottom metal microbump 161B and the second top metal microbump 161T are filled with an insulating dielectric material of the same material as the vertical interconnect dielectric plug 192 to form a vertical interconnect dielectric sidewall 161. That is, the first bottom metal microbump 151B and the second bottom metal microbump 161B are independent structures, and the second bottom metal microbump 161B and the second top metal microbump 161T are located in the edge region of the sub-core.
[0015] In one embodiment, the main chip 900 is the main control logic chip, and the sub-chips 100 are storage unit chips, which are stacked in an array on the main chip 900. Each main control logic chip is connected to the array of storage unit chips. This constitutes a chip system that can meet a large computing power requirement.
[0016] In one embodiment, several sub-core layers are further bonded to the back side of the sub-core 100, such as a second sub-core layer 200, a third sub-core layer 300, etc. The specific number of layers can be set as needed, and the function and type of each sub-core layer can be set as needed without limitation. Sub-cores in the same layer can also be sub-cores with different functions and types. The interconnection method between sub-core layers is the same as the interconnection method between sub-core layers and main core layers. In other words, the second sub-core layer 200 can adopt the same structure as the sub-core layer, that is, it can include a first sub-core I / O pad 111 and a second sub-core I / O pad disposed on the front side, which are connected through... The bonding body 101 is bonded to the surface of the main chip 900, and the corresponding first sub-chip I / O pad is perpendicular to the main chip I / O pad 911, and the corresponding second sub-chip I / O pad is perpendicular to the main chip I / O pad 911. The same vertical interconnect adapter 180 is used to achieve interconnection between the second sub-chip layer and the sub-chip layer. Similarly, the third sub-chip layer 300 can adopt the same structure as the second sub-chip layer 200. The second sub-chip layer 200 is also interconnected with the third sub-chip layer 300 using the same vertical interconnect adapter 180, and so on, forming a multi-layer stacked chip system, all of which are within the scope of protection of this invention. It should be particularly noted that further bonding of several sub-chip layers, such as the second sub-chip layer 200, the third sub-chip layer 300, etc., is also possible.
[0017] In one embodiment, the insulating medium is composed of one or a mixture of silicon-containing dielectric compounds, carbon compounds, and nitrogen compounds. This forms vertical interconnect dielectric sidewalls 161 and vertical interconnect adapter dielectric plugs 192 made of the same material.
[0018] In one embodiment, the vertical conductive plug 181 is made of, for example, silicon or one of copper, aluminum, nickel, tantalum, titanium or an alloy thereof.
[0019] In one embodiment, the first top metal microbump 151T and the first bottom metal microbump 151B, along with the second top metal microbump 161T and the second bottom metal microbump 161B, are made of one or an alloy of copper, aluminum, tungsten, molybdenum, nickel, tin, cobalt, tantalum, silver, and gold, or of polycrystalline silicon or SeGe.
[0020] In one embodiment, the I / O pads 911 of the main chip, the I / O pads of the sub-chips, including the I / O pads 111 of the first sub-chip and the I / O pads 112 of the second sub-chip, and the vertical interconnect adapter pads 191 are made of one of aluminum, copper, nickel, titanium, tungsten, cobalt, tantalum, silver, gold, or an alloy thereof.
[0021] In one embodiment, the sub-chip array is one or a combination of DRAM based on charge storage cells, NOR and NAND based on floating gate charge type memory, RRAM based on resistive cells, and MRAM based on magnetoresistive cells.
[0022] The embodiments will now be described in detail with reference to the accompanying drawings. Figure 2 A flowchart illustrating a three-dimensional stacked system-on-a-chip according to an embodiment of the present invention is provided below. Figures 1 to 3 The manufacturing method of the three-dimensional stacked system-on-a-chip includes the following steps: S10: A wafer is provided, the wafer comprising at least two identical master dies arranged in an array, each master die including master die I / O metal pads disposed on its surface. A plurality of sub-dies are provided, each including a first sub-die I / O pad and a second sub-die I / O pad disposed on its front side. The first sub-die I / O pad has a through-hole extending through the sub-die, and the bottom of the second sub-die I / O pad is interconnected with vertical conductive plugs extending through the sub-die. A bonding assembly is formed on the wafer, the bonding assembly exposing the master die I / O metal pads.
[0023] Specifically, in this embodiment, such as Figure 3 As shown, wafer 10 includes a semiconductor substrate 100, which is silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. In this embodiment, a silicon substrate is used. An epitaxial layer is formed on the silicon substrate, and multiple bare chips, i.e., main chips 900, consisting of an array of semiconductor devices, are formed in the epitaxial layer and the silicon substrate. An insulating layer is also formed on the epitaxial layer. The insulating layer is made of materials such as silicon dioxide and silicon nitride. The insulating layer covers the semiconductor devices and has main chip I / O metal pads 911 on the insulating layer that are interconnected with the semiconductor devices.
[0024] In this embodiment, the sub-chip 100 is a memory cell chip, specifically a bare chip. It has I / O pads on its front side. The first sub-chip I / O pad 111 has a through-hole around its periphery, and the second sub-chip I / O pad 112 has vertical conductive plugs 181 through the sub-chip interconnected at its bottom. Besides memory cells, the sub-chip can also be a logic circuit composed of MOS transistors, or a semiconductor device such as MEMS or a sensor. Furthermore, different sub-chips can be of different types, containing different semiconductor devices. The sub-chip can be the same bare chip located on the same wafer, or it can be a device formed using a different semiconductor process than the main chip. Therefore, this invention solves the problem that chips with different process technologies cannot be formed on the same production line, and the problem of increased size caused by packaging chips with different processes.
[0025] The bonded material can be a bonding dielectric sheet, such as dielectric silicon dioxide or silicon nitride. It will become molten upon heating.
[0026] S20: The sub-core 100 is bonded to the main core 900 with the front side facing the main core 900 via the bonding body 101. The I / O pads of the sub-core and the I / O metal pads of the main core are perpendicular to each other and have cavities 220 that communicate with the through holes 210 of the sub-core. The first sub-core I / O pad 111 and the main core I / O metal pad 911 are perpendicular to each other and have a first cavity 220. The second sub-core I / O pad 112 and the main core I / O metal pad 911 are perpendicular to each other and have a second cavity 230.
[0027] Specifically, the main chip is the main control logic chip, and the sub-chips are memory cell chips. The sub-chips are stacked in an array on the main chip, with one main control logic chip corresponding to the array of memory cell chips. In one embodiment, the sub-chips can be an array of sub-chips located on the same wafer. The sub-chip array is one or a combination of DRAM based on charge storage cells, NOR and NAND based on floating gate charge type memory, RRAM based on resistive cells, and MRAM based on magnetoresistive cells.
[0028] S30: A first top metal microbump 151T is formed on the surface of the first sub-core I / O pad 111 through the through-hole 210 of the sub-core, and a first bottom metal microbump 151B is formed on the surface of the main core I / O metal pad 911. The first top metal microbump 151T covers part of the surface of the first bottom metal microbump 151B and is electrically interconnected. A second top metal microbump 161T is formed on the surface of the second sub-core I / O pad 112 through the through-hole 210 of the sub-core or the outer edge of the sub-core, and a second bottom metal microbump 161B is formed on the surface of the main core I / O metal pad 911. The second top metal microbump 161T covers the surface of the second bottom metal microbump 161B and is electrically interconnected. In this embodiment, electroplating or chemical plating can be used to grow metal from the surface of the metal pad until the metal contacts together. A first top metal microbump 151T and a first bottom metal microbump 151B, a second top metal microbump 161T and a second bottom metal microbump 161B are formed. In this embodiment, the metal microbumps are made of one or an alloy of copper, aluminum, tungsten, molybdenum, nickel, tin, cobalt, tantalum, silver, and gold, or of polycrystalline silicon or SeGe.
[0029] S40: Fill the through-hole of the core particle with an insulating medium to form a vertical dielectric plug.
[0030] The insulating medium is composed of one or a mixture of silicon-containing dielectric compounds, carbon compounds, and nitrogen compounds.
[0031] S50: Vertical interconnect adapter pads formed on the surface of the back side of the sub-core and interconnected with vertical conductive plugs.
[0032] The vertical interconnect adapter pads are made of one of the following metals: aluminum, copper, nickel, titanium, tungsten, cobalt, tantalum, silver, gold, or an alloy thereof.
[0033] Formed by physical vapor deposition (PVD) methods such as magnetron sputtering or evaporation, or by chemical vapor deposition. It is composed of silicon or one of copper, aluminum, nickel, tantalum, titanium, or their alloys.
[0034] In one embodiment, the cavity between the second sub-core I / O pad and the main core I / O metal pad is connected to the through-hole of the sub-core. A second top metal micro-bump is formed on the surface of the second sub-core I / O pad through the through-hole of the sub-core, and a second bottom metal micro-bump is formed on the surface of the main core I / O metal pad. The second top metal micro-bump covers the surface of the second bottom metal micro-bump and is electrically interconnected. The first bottom metal micro-bump and the second bottom metal micro-bump are a single unit.
[0035] In one embodiment, the cavity between the second sub-core I / O pad and the main core I / O metal pad is connected to the outside of the sub-core. A second top metal microbump is formed on the surface of the second sub-core I / O pad through the outside of the sub-core, and a second bottom metal microbump is formed on the surface of the main core I / O metal pad. The second top metal microbump covers the surface of the second bottom metal microbump and is electrically interconnected. A bond is formed between the first bottom metal microbump and the second bottom metal microbump.
[0036] In one embodiment, the method further includes forming a bonding body on the back side of the sub-core, and then using steps S20 to S50 to continue bonding several layers of sub-core layers. The functional devices of each sub-core layer can be the same or different, thereby forming a multi-layer stacked structure. The specific number of stacked layers is determined as needed.
[0037] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A three-dimensional stacked chip system-on-a-chip, characterized in that, include: Main chip, including the main chip I / O pads disposed on the surface; The sub-core includes a first sub-core I / O pad and a second sub-core I / O pad disposed on the front side; the front side is bonded to the surface of the main core by a bonding agent, and the corresponding first sub-core I / O pad is perpendicular to the main core I / O pad, and the corresponding second sub-core I / O pad is perpendicular to the main core I / O pad. A vertical interconnect adapter includes a first bottom metal microbump and a first top metal microbump disposed on the surface of the first bottom metal microbump portion; the first sub-core I / O pad and the main core I / O pad are vertically electrically interconnected through the first bottom metal microbump and the first top metal microbump, and the surface of the first bottom metal microbump is also filled with a vertical interconnect adapter dielectric plug penetrating the sub-core; The vertical interconnect adapter also includes a second bottom metal microbump and a second top metal microbump disposed on the surface of the second bottom metal microbump. The second sub-core I / O pad and the main core I / O pad 911 are vertically electrically interconnected through the second bottom metal microbump and the second top metal microbump. A vertical conductive plug is disposed on the surface of the second sub-core I / O pad, and a vertical interconnect adapter pad is disposed on the top of the vertical conductive plug.
2. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The first and second bottom metal micro-bumps are a single unit.
3. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The outer side of the core chip, as well as the outer side of the second bottom metal microbump and the second top metal microbump, are filled with an insulating medium of the same material as the dielectric plug of the vertical interconnect adapter to form the vertical interconnect dielectric sidewall.
4. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The main chip is the main control logic chip, and the sub-chips are storage unit chips, which are stacked in an array on the main chip. One main control logic chip is connected to the array of storage unit chips.
5. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, Several sub-core layers are also bonded to the back side of the sub-core, and the interconnection between the sub-core layers is the same as the interconnection between the sub-core layers and the main core layer.
6. The three-dimensional stacked system-on-a-chip as described in claim 3, characterized in that, The insulating medium is composed of one or a mixture of silicon-containing dielectric compounds, carbon compounds, and nitrogen compounds.
7. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The vertical conductive plug is made of silicon or one of copper, aluminum, nickel, tantalum, titanium or an alloy thereof.
8. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The first top metal microbump and the first bottom metal microbump, as well as the second top metal microbump and the second bottom metal microbump, are made of one or an alloy of copper, aluminum, tungsten, molybdenum, nickel, tin, cobalt, tantalum, silver, and gold, or of polycrystalline silicon or SeGe.
9. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The I / O pads of the main chip, the I / O pads of the sub-chip, and the vertical interconnect adapter pads are made of one of the following metals: aluminum, copper, nickel, titanium, tungsten, cobalt, tantalum, silver, gold, or an alloy thereof.
10. The three-dimensional stacked system-on-a-chip as described in claim 4, characterized in that, The sub-core array is one or a combination of DRAM based on charge storage cells, NOR and NAND based on floating gate charge memory, RRAM based on resistive cells, and MRAM based on magnetoresistive cells.
11. A method for manufacturing a three-dimensional stacked system-on-a-chip according to claims 1 to 10, characterized in that, Including the following steps: S10: Provide a wafer comprising at least two identical master dies arranged in an array, the master dies comprising master die I / O metal pads disposed on a surface; Several sub-cores are provided, including a first sub-core I / O pad and a second sub-core I / O pad disposed on the front side. The first sub-core I / O pad has a through hole that passes through the sub-core on its periphery, and the bottom of the second sub-core I / O pad is interconnected with vertical conductive plugs that pass through the sub-core. Bonds are formed on the wafer, exposing the main die I / O metal pads; S20: The sub-core is bonded to the main core with the front side of the bonding body facing the main core. The I / O pads of the sub-core are perpendicular to the I / O metal pads of the main core and have a first cavity that communicates with the through-hole of the sub-core. The first sub-core I / O pads are perpendicular to the I / O metal pads of the main core and have a second cavity. The second sub-core I / O pads are perpendicular to the I / O metal pads of the main core and have a cavity. S30: A first top metal microbump is formed on the surface of the first sub-core I / O pad through the through-hole of the sub-core, and a first bottom metal microbump is formed on the surface of the main core I / O metal pad. The first top metal microbump covers part of the surface of the first bottom metal microbump and is electrically interconnected. A second top metal microbump is formed on the surface of the second sub-core I / O pad through the through-hole of the sub-core or the outer edge of the sub-core, and a second bottom metal microbump is formed on the surface of the main core I / O metal pad. The second top metal microbump covers the surface of the second bottom metal microbump and is electrically interconnected. S40: Fill the through-hole of the core particle with an insulating medium to form a vertical dielectric plug; S50: Vertical interconnect adapter pads formed on the surface of the back side of the sub-core and interconnected with vertical conductive plugs.
12. The manufacturing method as described in claim 12, characterized in that, The cavity between the second sub-core I / O pad and the main core I / O metal pad is connected to the through-hole of the sub-core. A second top metal micro-bump is formed on the surface of the second sub-core I / O pad through the through-hole of the sub-core, and a second bottom metal micro-bump is formed on the surface of the main core I / O metal pad. The second top metal micro-bump covers the surface of the second bottom metal micro-bump and is electrically interconnected. The first bottom metal micro-bump and the second bottom metal micro-bump are a whole.
13. The manufacturing method as described in claim 12, characterized in that, The cavity between the second sub-core I / O pad and the main core I / O metal pad is connected to the outside of the sub-core. A second top metal microbump is formed on the surface of the second sub-core I / O pad through the outside of the sub-core, and a second bottom metal microbump is formed on the surface of the main core I / O metal pad. The second top metal microbump covers the surface of the second bottom metal microbump and is electrically interconnected. There is a bond between the first bottom metal microbump and the second bottom metal microbump.
14. The manufacturing method as described in claim 12, characterized in that, It also includes continuing to form a bond on the back side of the sub-core, and continuing to bond several sub-core layers using steps S20 to S50.
15. The manufacturing method as described in claim 12, characterized in that, The method for forming the metal microbumps is electroplating or chemical plating.