Circuitry with dead time adjustment
By introducing probe and logic units into the circuit system and dynamically adjusting the dead time, the problems of low efficiency and high thermal load in high-frequency circuits are solved, achieving more efficient circuit operation and robustness optimization.
Patent Information
- Application Number
- CN202480028418.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-04-27
- Filing Date
- 2024-04-10
- Publication Date
- 2026-03-03
AI Technical Summary
Existing circuit systems are inefficient at high clock frequencies and steep control edges, have high thermal design loads, and are difficult to match different operating points economically and efficiently.
By introducing detection units and logic units into the circuit system, the dead time of the switching unit is dynamically adjusted. The dead time is adjusted according to the measurement results of the detection unit to optimize the switching process and achieve adaptive or predictive dead time variation.
It improves the efficiency of the circuit system, reduces the thermal load, and enhances robustness at different operating points and in environments susceptible to interference.
Smart Images
Figure CN121605573A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a circuit system and a method for controlling the circuit system. Background Technology
[0002] Currently, there are various solutions for switching and controlling circuit systems. The increasing demand for higher clock frequencies and steeper control edges is leading to greater challenges for control electronics.
[0003] High efficiency has always been a key objective for power electronic devices. As power increases, losses become larger in absolute terms and incur significant overhead in areas such as thermal design, thus necessitating more economical and efficient circuit systems. Summary of the Invention
[0004] The circuit system according to claim 1 has the following advantages over the prior art: the dead time of the circuit system can be continuously matched to different operating points, thus avoiding the use of statically set, inefficient dead times. Another advantage is the reduction of thermal load.
[0005] This is achieved according to the invention by the following method: the circuit system has a detection unit, a switching unit, and a logic unit. Furthermore, the logic unit is configured to create and / or receive a value for the dead time of the switching unit, wherein the detection unit is configured to determine and / or measure the dead time of the switching unit. And wherein the logic unit is configured to determine and / or calculate the dead time change based on the value of the dead time and / or the dead time determined by the detection unit.
[0006] In other words, the circuit system can therefore determine the dead time variation based on a fixed value of dead time, thereby increasing or decreasing the dead time from that fixed value. Furthermore, the circuit system has the possibility of continuously changing the dead time by means of a stable system, particularly shortening and / or lengthening the dead time, thus performing dead time variation. This has the advantage of uninterrupted oscillation around an optimal value of dead time, so that the dead time can be optimally set independently of the operating point. In particular, here, the adjustment of the dead time can be adaptive or predictive.
[0007] For example, in the circuit system, the detection unit is connected to the switching unit, thereby enabling the detection unit to measure the dead time of the switching unit. The logic unit receives a signal from the detection unit regarding whether the dead time is set too small and / or too large, and can determine or calculate the dead time change based on this signal. Here, the dead time change is preferably a lengthening and / or shortening of the dead time.
[0008] The dependent claims illustrate preferred extensions of the invention.
[0009] Preferably, the logic unit is configured to match the switching process of the switching unit based on the determined dead time variation.
[0010] The advantage of this implementation is that the dead time at the switching unit can be adjusted in a targeted manner by changing the dead time, which can result in a lower thermal load on the circuit system.
[0011] More preferably, the logic unit is configured to determine the dead time change based on a measurement point, specifically a time step (Zeitschritt) of the detection unit.
[0012] The advantage of this implementation is that the circuit system can rapidly change the dead time, thereby avoiding, for example, drift or entering an unacceptable operating point. Furthermore, the measurement point of the detection unit can specifically be the time step of the switching unit.
[0013] More preferably, the logic unit is configured to determine the dead time change based on multiple measurement points of the detection unit, particularly multiple time steps.
[0014] The advantage of this implementation is that it allows for more precise determination of dead-time variations, leading to a further reduction in the thermal load on the circuit system. Here, the multiple measurement points can also be multiple time steps of the switching unit. Another advantage is that it further improves the robustness of the circuit system in environments susceptible to interference.
[0015] Preferably, the detection unit is configured to detect at least one characteristic parameter of the switching unit, wherein the detection unit is configured to detect at least one artifact during the time variation of the characteristic parameter, and wherein the logic unit is configured to increase and / or decrease the dead time variation based on the detected artifact.
[0016] The advantage of this implementation is that the dead time oscillates around an optimal value, allowing dead time adjustment to be performed independently of possible environmental parameters or operating points. For example, the artifact can be a voltage ripple or the like. Furthermore, the detection unit can be configured to further detect the height or presence of the voltage ripple. This further improves the robustness of the circuit system.
[0017] More preferably, the logic unit is configured to match the step size of the dead-time change based on the detected artifacts.
[0018] The advantage of this implementation is that it can improve the robustness of the system, for example, when one or more artifacts are detected consecutively and the dead time is changed only based on multiple detections.
[0019] More preferably, the logic unit is configured to increase and / or decrease the dead zone time change when the detection unit does not detect artifacts during the time change of the feature parameter.
[0020] The advantage of this implementation is that the dead time thus shifts toward and oscillates around its optimal value, thereby further improving the robustness of the circuit system. For example, the detection unit can detect voltage changes in which voltage ripple occurs. Subsequently, after a dead time change occurs, or even if no dead time change occurs, the voltage ripple may no longer appear. In this case, the logic unit is configured to induce a dead time change to induce voltage ripple or the like again, so that the regulation still oscillates around the optimal value.
[0021] Preferably, the detection unit is configured to detect another artifact, wherein the logic unit is configured to increase and / or decrease the dead time change based on the other artifact.
[0022] The advantage of this implementation is that, for example, if the voltage ripple is detected multiple times consecutively, a dead-time variation can be applied to each of these detections. More preferably, the detection unit is configured to detect multiple artifacts during the variation of the characteristic parameter, wherein the logic unit is configured to increase and / or decrease the dead-time variation based on the multiple artifacts.
[0023] The advantage of this implementation is that, for example, voltage ripple can be detected ten times consecutively, so that dead time changes can be calculated and / or increased or decreased based on the plurality of artifacts.
[0024] Preferably, the detection unit has at least one bipolar transistor.
[0025] The advantage of this implementation is that it provides a simple and readily available means of detecting dead time and / or calculating dead time changes using bipolar transistors.
[0026] More preferably, the detection unit is configured to convert the signal of the bipolar transistor and digitally forward it to the logic unit.
[0027] The advantage of this implementation is that switching time can be significantly reduced by using digital processing.
[0028] Another aspect of the present invention relates to a method for controlling a circuit system as described above and below, the method comprising the following steps: - Create and / or receive values for the dead time of the switching units in the circuit system. - The dead time of the switching unit is determined and / or measured using the detection unit of the circuit system, and - Determine and / or calculate the dead time change based on the value of the dead time and / or the dead time determined by the detection unit.
[0029] The advantage of this implementation is that it can reduce the thermal load on the circuit system and / or can calculate the dead time more accurately. Attached Figure Description
[0030] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the drawings: Figure 1 According to one embodiment of the circuit system, Figure 2 A schematic diagram illustrating the functional mode of a circuit system according to one embodiment. Figure 3 According to one embodiment of the circuit system, Figure 4 A schematic diagram illustrating the functional mode of a circuit system according to one embodiment, and Figure 5 A flowchart illustrating the steps of a method according to one embodiment. Detailed Implementation
[0031] Preferably, all identical components, elements, and / or units are given the same reference numerals in all figures.
[0032] Figure 1 A circuit system 10 according to one embodiment is shown.
[0033] The circuit system 10 here includes a detection unit 12. The detection unit 12 is configured to determine and / or measure the dead time of the switching unit 14. The switching unit 14 may be part of the circuit system 10. Furthermore, a logic unit 16 (which may also be part of the circuit system 10) is configured to determine and / or calculate the dead time change based on the value of the dead time and / or the dead time determined by the detection unit 12.
[0034] More preferably, the detection unit 12 has a bipolar transistor 26.
[0035] Figure 2A schematic diagram is shown to illustrate the functional mode of a circuit system 10 according to one embodiment.
[0036] For example, the switching unit 14 has a first switch and a second switch, wherein the first switch has a first current change process 28 and the second switch has a second current change process 32. The detection unit 12 is configured to determine the dead time 33.
[0037] Figure 3 A circuit system 10 is shown having a detection unit 12 with a bipolar transistor 26. Furthermore, the circuit system 10 includes a switching unit 14, wherein the detection unit 12 is configured to monitor the switching unit 14. Additionally, the circuit system 10 includes a logic unit 16, which is specifically connected to the detection unit 12 via digital signals.
[0038] Figure 4 A schematic diagram illustrating the functional configuration of the circuit system 10 is shown. The detection unit 12 is configured to detect the characteristic parameter 18 of the switching unit 14. Furthermore, the detection unit 12 is configured to detect artifacts 20, such as voltage ripple, during the time-varying process 22 of the characteristic parameter 18. More preferably, the detection unit 12 is configured to detect another artifact 24, wherein the logic unit 16 is configured to increase and / or decrease the dead-time change based on the other artifact 24. Additionally, the detection unit 12 may be configured to detect multiple artifacts during the changing process 22 of the characteristic parameter 20, wherein the logic unit 16 is configured to increase or decrease the dead-time change based on the multiple artifacts.
[0039] Figure 5 A flowchart illustrating the steps of method 100 is shown. Method 100 includes step S1: creating and / or receiving a value for the dead time of the switching unit 14 of the circuit system 10. Furthermore, method 100 includes step S2: determining and / or measuring the dead time of the switching unit 14 using a detection unit 12 of the circuit system 10. Preferably, method 100 includes step S3: determining and / or calculating the dead time change based on the value of the dead time and / or the dead time determined by the detection unit.
Claims
1. A circuit system (10) having: - Detection unit (12) - Switching unit (14), and - Logic unit (16) in, The logic unit (16) is configured to create and / or receive a value for the dead time of the switching unit (14), wherein the detection unit (12) is configured to determine and / or measure the dead time of the switching unit (14). The logic unit (16) is configured to determine and / or calculate the dead time change based on the value of the dead time and / or the dead time determined by the detection unit (12).
2. The circuit system (10) according to claim 1, wherein, The logic unit (16) is configured to match the switching process of the switching unit (14) based on the determined dead time variation.
3. The circuit system (10) according to any one of the preceding claims, wherein, The logic unit (16) is configured to determine the dead time change based on a measurement point of the detection unit (12), specifically a time step.
4. The circuit system (10) according to any one of the preceding claims, wherein, The logic unit (16) is configured to determine the dead time change based on multiple measurement points, particularly multiple time steps, of the detection unit (12).
5. The circuit system (10) according to any one of the preceding claims, wherein, The detection unit (12) is configured to detect at least one feature parameter (18) of the switching unit (14), wherein the detection unit (12) is configured to detect at least one artifact (20) in the time change process (22) of the feature parameter (18), wherein the logic unit (16) is configured to increase and / or decrease the dead time change based on the detected artifact (20).
6. The circuit system (10) according to claim 6, wherein, The logic unit (16) is configured to match the step size of the dead time change based on the detected artifacts (20).
7. The circuit system (10) according to any one of claims 6 to 7, wherein, The logic unit (16) is configured to increase and / or decrease the dead zone time change when the detection unit (12) does not detect an artifact during the time change process (22) of the feature parameter (18).
8. The circuit system (10) according to any one of claims 6 to 8, wherein, The detection unit (12) is configured to detect another artifact (24), wherein the logic unit (16) is configured to increase and / or decrease the dead time change based on the other artifact (24).
9. The circuit system (10) according to any one of claims 6 to 9, wherein, The detection unit (12) is configured to detect multiple artifacts during the change process (22) of the feature parameter (20), wherein the logic unit (16) is configured to increase and / or decrease the dead time change based on the multiple artifacts.
10. The circuit system (10) according to any one of the preceding claims, wherein, The detection unit (12) includes at least one bipolar transistor (26).
11. The circuit system (10) according to claim 11, wherein, The detection unit (12) is configured to convert the measurement signal of the bipolar transistor (26) and digitally forward the measurement signal to the logic unit (16).
12. A method (100) for controlling a circuit system (10), particularly the circuit system according to claim 1, the method comprising the following steps: - Create and / or receive (S1) the value of the dead time for the switching unit (14) of the circuit system (10), - The dead time of the switching unit (14) is determined and / or measured (S2) by means of the detection unit (12) of the circuit system (10), and - Determine and / or obtain (S3) the dead time change based on the value of the dead time and / or the dead time determined by the detection unit (12).