Device and method for adaptive control of dead time in a half-bridge circuit

Abstract

The invention relates to a device and a method for adaptive control of the dead time in a half-bridge circuit.

Description

[0001] The invention relates to a device and a method for adaptive control of the dead time in a half-bridge circuit. State of the art

[0002] In standard half-bridge circuits, typically used in inverters and converters, introducing a dead time is crucial to prevent cross-conduction or simultaneous, even partial, conduction of high-side and low-side MOSFETs. Without this delay, there is a risk of a short circuit or overload, which could damage the components. However, the dead time is a sensitive issue: if it is too long, additional energy losses occur due to effects such as diode conduction, reverse recovery, or the switching of non-zero voltages. Therefore, it is important to optimally adjust the dead time to find the right balance between safety and efficiency.

[0003] In the literature and in practice, various approaches exist for optimizing dead time. Traditionally, many of these methods are based on direct detection of the switching node. For example, Maderbacher et al. investigated a method in which body diode conduction is detected by sensing a negative voltage spike at the switching node. Similarly, Niwa et al. proposed integrating a SenseFET within the power module to detect diode commutation [1, 2]. However, both approaches require additional components and are limited by propagation delays, which can impair their effectiveness.

[0004] Other approaches, such as that of Vahid and Dragan, have presented a sensorless approach that uses load voltage feedback to determine the optimal dead time based on the smallest duty cycle [3]. While this approach is efficient for voltage converters, it requires fast computational power and is not suitable for all applications.

[0005] Texas Instruments has developed a predictive control method based on sensing the gate-source voltage (Vgs) and drain-source voltage (Vds) of the low-side MOSFET, as described in the application report for the UCC27221 / UCC27222 [4]. However, this approach has limitations, as it requires access to high-voltage-tolerant components, which increases design complexity and cost, especially in automotive applications.

[0006] However, since all these methods require access to the switching node or the drain-source side, they face significant challenges in terms of design complexity, cost, and on-chip integration due to the need for high-voltage components in automotive applications.

[0007] Therefore, a predictive dead-time control approach based on low-voltage (LV) information regarding the gate driver (control and diagnostics) is presented here. By utilizing the Vgs of the low-side MOSFET and the high-side MOSFET, as well as the associated parasitic elements in the circuit, the dead time can be precisely adjusted without direct access to high-voltage areas. This reduces design complexity and enables simpler integration into systems that rely on cost-effective, highly integrated solutions, as is often required in the automotive industry.

[0008] [1] Niwa, A., et al. (2018). A Dead-Time-Controlled Gate Driver Using Current-Sense FET Integrated in SiC MOSFET. IEEE Transactions on Power Electronics, 33(4), 3258-3267.

[0009] [2] Maderbacher, G., Jackum, T., Pribyl, W., Wassermann, M., Petschar, A., & Sandner, C. (2011). Automatic dead-time optimization in a high-frequency DC-DC step-down converter in 65 nm CMOS. In 2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, Finland, pp. 487-490.

[0010] [3] Yousefzadeh, V., & Maksimovic, D. (2006). Sensorless optimization of dead times in DC-DC converters with synchronous rectifiers. IEEE Transactions on Power Electronics, 21(4), 994-1002.

[0011] [4] S. Mappus, “Predictive Gate Drive™ Boosts Synchronous DC / DC Power Converter Efficiency,” Texas Instruments Application Report, SLUA281, April 2003.

[0012] DE 11 2017 006 120 B4 relates to an electrical circuit arranged in a half-bridge topology, comprising: a high-side transistor and a low-side transistor, each having a source, a drain, and a gate, wherein the source of the high-side transistor is electrically connected to the drain of the low-side transistor at a first node; a gate driver electrically connected to the gate of the high-side transistor; a bootstrap capacitor electrically connected in parallel to the gate driver; a shunt diode having a cathode and an anode, wherein the cathode of the shunt diode is connected to the capacitor at a second node and the anode of the shunt diode is connected to ground, the shunt diode providing a low-voltage-drop charging path for charging the bootstrap capacitor;and a shunt resistor electrically connected between the first node and the second node, so that the shunt diode is decoupled from the first node and the current through the shunt diode is regulated and limited.

[0013] DE 10 2020 000 348 A1 relates to a control system for a DCX power converter comprising an SR control that controls the conduction times of the first and second SR transistors in response to the respective conduction conditions, and a primary-side control that provides first and second primary phase signals that control the first and second transistors, measures a first sensing signal as a time interval between a gate voltage of the first SR transistor falling below a first threshold and an activation of the second primary phase signal, an adaptive dead time proportional to an average of the current conducted in the SR transistors during their respective active times, a first reference signal as a predetermined delay time plus the adaptive dead time, and a first error signal as an average difference between the first sensing signal and the first reference signal.and controls a switching speed of the first and second primary phase signals to reduce the first error signal.

[0014] DE 10 2020 202 047 A1 relates to a semiconductor device comprising: a half-bridge circuit with a first semiconductor switching element and a second semiconductor switching element coupled to a common node which is coupled to an output terminal of the semiconductor device; a detection device configured to detect an electrical voltage at the output terminal; and a logic circuit configured to switch the second semiconductor switching element to electrical conductivity with a delay time dependent on the detected electrical voltage relative to the time at which the first semiconductor switching element is switched to electrical non-conductivity.

[0015] German patent DE 10 2021 131 880 A1 relates to techniques for controlling a power converter with a control signal and a circuit arrangement designed to convert the control signal into one or more pulse-modulated drive signals for operating the power converter. The conversion circuit arrangement can receive the control signal, extract frequency information, duty cycle, dead time, and other information from the control signal, and output at least one pulse-modulated drive signal based on the extracted information to a drive stage that can operate the power converter. The control signal can be a digital signal containing rising and falling edges. The rising edges can define the frequency information. The falling edges can define other information extracted from the conversion circuit arrangement, such as duty cycle, dead time, and so on.In some examples, the power converter can be a resonant power converter. Disclosure of the invention

[0016] In high-voltage applications, especially when silicon carbide (SiC) or gallium nitride (GaN) MOSFETs are used in a half-bridge configuration (H- or B6-bridge), precise and efficient dead-time control is crucial. Achieving optimal dead-time under varying operating conditions and scenarios, as well as component, assembly, and interconnection variations, presents a challenge, particularly when it incurs significant costs or high complexity, such as the need for complex lookup tables for numerous necessary parameters like temperature, load current, and device variations. Current solutions often require high-voltage components and external circuitry, increasing costs and complexity and hindering further integration.

[0017] This invention proposes an innovative control scheme for adjusting the dead time of SiC devices in a half-bridge configuration. Using a buck DC-DC converter as an example, this approach utilizes only the low-side gate-source voltage (Vgs) and the di / dt signal from the common source inductance of the SiC MOSFETs to predictively adjust the dead time in each switching cycle until the optimal point is reached. This significantly reduces the number of parameters required to determine the optimal dead time. The concept also applies to step-up DC-DC converters by acquiring information from the high side and can be easily implemented in inverter or rectifier applications for both high-side and low-side switches.

[0018] The core of the invention consists of the following technical features, which enable the aforementioned advantages: Acquisition and evaluation of the low-side gate-source voltage (Vgs): An electrical circuit specifically designed to accurately acquire and evaluate the low-side gate-source voltage (Vgs) and the voltage (VLS) across the common source inductor or common source transformer. The evaluation procedure is implemented accordingly on the high side.

[0019] These voltages are used to evaluate the actual dead time in real time and make adjustments, or preferably for a predictive method where the evaluation takes place in real time and the adjustments are implemented for the subsequent clock cycles.

[0020] This acquisition method is particularly efficient because it does not require any additional high-voltage components and can be integrated directly into the circuit system.

[0021] Measurement of the voltage across the common source inductance (VLS): In addition to the Vgs voltage, the voltage across the common source inductance (VLS) is measured. This inductance generates a di / dt signal, which allows conclusions to be drawn about the load current and provides important information for precisely adjusting the dead time. This dual measurement minimizes switching losses and increases efficiency.

[0022] Predictive algorithm for dead time adjustment: A predictive algorithm analyzes the acquired signals (Vgs and VLS) in real time and dynamically decides whether the dead time needs to be increased or decreased by one step to approach the optimal point. This continuous adjustment ensures that the best possible dead time is achieved under all operating conditions, without manual intervention or complex tables.

[0023] Robustness and stability: The predictive algorithm is designed to ensure system stability even under fluctuating operating conditions. It minimizes disturbances and voltage overshoots and undershoots through precise dead time control and automatically adapts to changes in load current, temperature, voltage, component degradation, packaging and interconnection technology, and other parameters. This contributes to the long-term operational reliability and efficiency of the system.

[0024] The main advantage of this solution is that it requires no additional high-voltage components and can be fully integrated into the gate drivers for the power semiconductors. It can optimize the dead time independently of the transition before the active switch turns on and after the switch turns off. Furthermore, predictive control offers greater adaptability, robustness, and stability under varying operating conditions.

[0025] The advantages can be summarized as follows: Reduced complexity and cost: The proposed approach does not require any additional high-voltage components or external circuits, which reduces the overall cost and complexity of the system.

[0026] Increased integration: The solution can be fully integrated into the gate drivers, simplifying on-chip integration and reducing design complexity. Robustness and reliability are enhanced.

[0027] Optimized dead-time control: By utilizing the low-side gate-source voltage (Vgs) and the di / dt signal from the common source inductance, the dead time can be precisely and efficiently adjusted in each switching cycle. The same applies to the high side.

[0028] Adaptability and robustness: Predictive control offers greater adaptability and robustness under varying operating conditions, thus increasing system stability. A false detection can simply be ignored and, with a sufficiently small dead time adjustment step, would only result in a negligible reduction in efficiency.

[0029] Broad applicability: The concept is not limited to buck DC-DC converters but can also be used in step-up DC-DC converters and DC / AC / DC converter applications. Even in simple switching applications (e.g., electronic fuses) where a high-side and low-side switch are used together and the current needs to be recommutated during the switching process, this method is advantageous. Over- and undervoltages are avoided during switching. A more efficient voltage class can be used for the power switches. This enables reduced chip area for power semiconductors and additional drivers, resulting in compact and cost-effective systems.

[0030] Further advantages of the invention can be seen in the figures and the figure description. Drawings

[0031] They show: Fig. 1: a device according to the invention in schematic representation, Fig. 2: Switching cycles. Description

[0032] Fig. Figure 1 shows a device for adjusting the dead time in a half-bridge circuit with SiC MOSFETs, comprising: • an electrical circuit for detecting the low-side gate-source voltage (Vgs) of the low-side MOSFET (LS), • an electrical circuit for detecting the di / dt signal of the common source inductance of the SiC MOSFETs, • an evaluation unit for determining the current dead time based on the detected voltages and signals, • a control unit to adjust the dead time in each switching cycle based on the evaluation, in order to proactively fine-tune the dead time and optimize performance. • the circuit includes a detection unit that detects the gate-source voltage (Vgs) of the low-side MOSFET and the di / dt signal from the parasitic source inductance; • a logic unit is provided which dynamically adjusts the dead times Td1 and Td2 based on the detected signals.

[0033] In this configuration, the high-side MOSFET (HS) acts as an active switch, while the low-side MOSFET (LS) operates as a synchronous switch, replacing the diode and providing a freewheeling path. The goal of the control is to avoid diode commutation losses by turning on the low-side MOSFET immediately after the high-side MOSFET turns off.

[0034] The gate-source voltage of the low-side MOSFET is continuously measured to determine the exact moment when the LS MOSFET is switched off.

[0035] The di / dt signal (change in current over time) is measured across the source inductance and provides additional information about the load current, enabling precise synchronization between switching off the HS MOSFET and switching on the LS MOSFET.

[0036] The method dynamically optimizes the dead time in each switching cycle to synchronize the switching operations of the high-voltage (HS) and low-voltage (LS) MOSFETs as precisely as possible. The current-off event of the HS MOSFET is synchronized with the current-in event of the LS MOSFET, and vice versa, to prevent any overlap of the switching operations.

[0037] Although the method is described using a buck DC-DC converter, it can also be applied to boost converters, DC-DC converters, and inverter applications, as well as applications where currents are recommutated between a high-side and low-side switch. In boost converters, the switching point of the high-side MOSFET can be similarly determined, while in inverters, precise control of the dead time is crucial for efficiency and minimizing losses. In switching applications with current recommutation between the high-side and low-side, such as an electronic fuse, the primary focus is not on efficiency gains, but rather on avoiding overshoots and undershoots that stress the semiconductors and cause interference.

[0038] During switching, the currents through the high-side (HS) and low-side (LS) MOSFET change according to Kirchhoff's current law: iDHS+iDLS=iL

[0039] The rate of change of the currents is described by the equation: diDHSdt+diDLSdt−diLdt≈Constant

[0040] Since the load inductance is large and the load current changes only slowly, the change in load current (di_L / dt) during the short switching process can be considered nearly constant and linear. Therefore, the change in current through the LS-MOSFET is given by: diDLSdt=diDHSdt|Constant.

[0041] This relationship shows that the current change in the LS switch allows conclusions to be drawn about the current change in the HS switch. By measuring the parasitic voltage difference caused by the current in the LS MOSFET, the current change in the HS MOSFET can be indirectly determined.

[0042] The switching on and off of the current in the high-voltage MOSFET is detected via the parasitic source inductance (L_s) of the low-voltage MOSFET. The voltage across the common source inductance (V_LS) is calculated as follows: VLS=LsdiDLSdt=−LsdiDHSdt+Constant

[0043] This voltage VLSV_{LS}VLS only occurs during switching operations, i.e., when the high-voltage switching current is turned on or off. When the high-voltage MOSFET is turned on, the current change rate is positive, so the voltage VLSV_{LS}VLS generates a negative pulse. When it is turned off, the current change rate is negative, resulting in a positive pulse.

[0044] To capture these impulses, two comparators are used: • Comp_didt_pos: Detects the positive di / dt pulse when the HS MOSFET is switched off. • Comp_didt_neg: Detects the negative di / dt pulse when the HS MOSFET is switched on.

[0045] Additionally, the gate-source voltage (Vgs) of the low-side MOSFET is measured to determine its state: • Vgs ≥ Vth: The LS-MOSFET is switched on. • Vgs < Vth: The LS MOSFET is switched off.

[0046] This direct measurement of Vgs indicates the current status of the LS-MOSFET and serves to synchronize the switching processes.

[0047] The working principle of the proposed control for optimizing the dead time in a half-bridge circuit is based on continuous monitoring and adjustment of the switching delays (dead times) in the switching cycles. Fig. Figure 2 shows how the dead times Td1 and Td2 between the high-side MOSFET (HS) and the low-side MOSFET (LS) are iteratively adjusted to find the optimal operating point. This minimizes switching losses and avoids discharge currents. Dead time Td1(HS off,LS on)

[0048] Td1 is the delay between the switching off of the HS MOSFET (HS pwm off) and the switching on of the LS MOSFET (LS pwm on).

[0049] The falling edge of the HS pwm signal triggers the comparator Comp_didt_pos, which monitors the current change (di / dt) in the HS MOSFET.

[0050] When the high-voltage MOSFET switches off, the current through the switch decreases, generating a voltage across the parasitic source inductance, which is detected by the comparator. The comparator outputs a signal Vdidt_pos_comp = 1 until the high-voltage MOSFET is completely switched off.

[0051] Simultaneously, the gate-source voltage (Vgs) of the LS MOSFET is monitored. As soon as the LS MOSFET begins to conduct, the comparator outputs Vgs_comp = 1.

[0052] Optimization of Td1: If the NAND gate of Vdidt_pos_comp and Vgs_comp outputs a '1', this means that the dead time Td1 is too long because the LS MOSFET is switched on too late. In this case, Td1 is decreased by one step (DOWN) for the next switching cycle.

[0053] If the AND operation of Vdidt_pos_comp and Vgs_comp returns '1', the dead time Td1 is too short, which could lead to an overlap of switching operations. In this case, Td1 is incremented by one step (UP).

[0054] After the NAND or AND signal has been output, the comparator Comp_didt_pos is deactivated, and the process is restarted in the next switching cycle until the optimal point is found. Dead time Td2(Ls off,HS on)

[0055] Td2 is the delay between the LS MOSFET being switched off (LS pwm off) and the HS MOSFET being switched on (HS pwm on).

[0056] The falling edge of the LS pwm signal activates the comparator Comp_didt_neg, which monitors the current change when the HS MOSFET is switched on.

[0057] Vdidt_neg_comp outputs a signal '1' when the HS MOSFET starts to turn on. Optimization of Td2

[0058] If the NAND gate of Vdidt_neg_comp and Vgs_comp outputs a '1', this means that the dead time Td2 is too long, and Td2 is reduced by one step (DOWN) for the next switching cycle.

[0059] If the AND operation of Vdidt_neg_comp and Vgs_comp outputs '1', this means that Td2 is too short, and Td2 is increased by one step (UP).

[0060] After the NAND or AND signal has been output, the comparator Comp_didt_neg is deactivated, and the process is triggered again in the next switching cycle. Iterative adjustment of dead time

[0061] The control logic analyzes the detected signals during each switching operation and adjusts the dead times Td1 and Td2 in small increments. This iterative process ensures that the dead time is continuously brought closer to the optimal point.

[0062] The goal is to achieve a dead time that is just long enough to avoid bursts, but short enough to prevent unnecessary losses due to diode conduction, reverse recovery, and overlapping switching operations.

[0063] This predictive algorithm results in robust and stable dead-time adjustment, which reduces energy consumption and ensures system reliability, especially in SiC-based high-frequency applications. Overshoot, undershoot, and oscillations are reduced or eliminated.

[0064] Alternatively, the circuit for sensing the low-side gate-source voltage (Vgs) and the di / dt signal of the common source inductance can be built directly on the printed circuit board (PCB) of the DC-DC converter using a few comparators. This implementation requires very little space and can therefore be easily integrated into existing designs. The comparators serve to accurately acquire and transmit the relevant voltages and signals.

[0065] The existing or an additional microcontroller can implement the control scheme together with the ASIC / ASSP gate driver. Alternatively, a separate ASIC (Application-Specific Integrated Circuit) or ASSP (Application-Specific Standard Product) can be used to implement the control logic. This flexibility allows the solution to be adapted to various requirements and existing systems.

[0066] A key advantage of this method is its complete integration into an ASIC, as it involves only low-voltage components. This is particularly beneficial for applications in half-bridge gate driver ICs for power semiconductors. Integration into an ASIC allows for further optimization in terms of system complexity and performance by minimizing additional external components and connections.

[0067] To verify the logic and algorithm, an FPGA (Field-Programmable Gate Array) can be used. Implementing it in an FPGA allows the system's functionality and performance to be tested in a real-world environment before a final ASIC implementation. This provides a flexible and cost-effective way to validate the design and ensure it meets requirements.

[0068] In summary, this solution offers a compact, flexible, and efficient method for precisely controlling dead time in DC-DC converters and other applications. The ability to integrate it into an ASIC and verify it using an FPGA helps reduce system complexity and optimize performance. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] DE 11 2017 006 120 B4

[0012] DE 10 2020 000 348 A1

[0013] DE 10 2020 202 047 A1

[0014] DE 10 2021 131 880 A1

[0015] Cited non-patent literature

[0000] Niwa, A., et al. (2018). A Dead-Time-Controlled Gate Driver Using Current-Sense FET Integrated in SiC MOSFET. IEEE Transactions on Power Electronics, 33(4), 3258-3267

[0008] Maderbacher, G., Jackum, T., Pribyl, W., Wassermann, M., Petschar, A., & Sandner, C. (2011). Automatic dead-time optimization in a high-frequency DC-DC step-down converter in 65 nm CMOS. In 2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, Finland, pp. 487-490

[0009] Yousefzadeh, V., & Maksimovic, D. (2006). Sensorless optimization of dead times in DC-DC converters with synchronous rectifiers. IEEE Transactions on Power Electronics, 21(4), 994-1002

[0010] S. Mappus, “Predictive Gate Drive™ Boosts Synchronous DC / DC Power Converter Efficiency,” Texas Instruments Application Report, SLUA281, April 2003

[0011]

Claims

[1] Method for adaptive control of the dead time in a half-bridge circuit consisting of a high-side MOSFET (HS) and a low-side MOSFET (LS), characterized by , that: • the gate-source voltage (Vgs) of the low-side MOSFET (LS) or the high-side MOSFET and the current change (di / dt) through the parasitic source inductance of the MOSFETs are detected to detect the turn-on and turn-off processes of the HS and LS MOSFETs; • Based on these acquired signals, a predictive algorithm is used to dynamically adjust the dead time (Td1, Td2) in each switching cycle, iteratively adjusting the dead time to reach the optimal point that prevents overlap of switching operations and minimizes switching losses. [2] Method according to claim 1, characterized by , that: • the delay between the switching off of the high-side MOSFET and the switching on of the low-side MOSFET is called dead time Td1 and is adjusted by a predictive algorithm based on the detected current change (di / dt) and the gate-source voltage (Vgs); • If the dead time is too long, the dead time interval for the next switching cycle is reduced by one step, and if the dead time is too short, the dead time interval is increased by one step. [3] Method according to claim 2, characterized by , that: • the delay between the switching off of the low-side MOSFET and the switching on of the high-side MOSFET is called dead time Td2 and is also adjusted by a predictive algorithm in each switching cycle. [4] Method according to any one of claims 1 to 3, characterized by , that: • Two comparators, a positive di / dt comparator (Comp_didt_pos) and a negative di / dt comparator (Comp_didt_neg), are used to monitor the current change rate during switching operations and to adjust the dead times Td1 and Td2. [5] Method according to any one of claims 1 to 4, characterized by , that: • dead time control is used in applications with silicon carbide (SiC) or gallium nitride (GaN) MOSFETs to minimize switching losses or to reduce or avoid overshoot, undershoot, and oscillations. [6] Method according to any one of claims 1 to 5, characterized by , that: • the method is used in step-up or step-down direct current converters (DC-DC converters) or inverters or current recommutating high- and low-side switches, applying the same principle to control the dead time to both switches. [7] Method according to any one of claims 1 to 6, characterized by , that: • The dead time control, taking into account various operating conditions such as load current, temperature and device variations, is carried out without the need for additional high-voltage components. [8] Circuit for carrying out the method according to any one of claims 1 to 7. [9] Use of the method according to any one of claims 1 to 7 in a DC-DC converter or an inverter for minimizing switching losses and optimizing dead time in SiC- or GaN-based power semiconductors. [10] Use of the method according to any one of claims 1 to 7 in an energy converter or current recommutating high- and low-side switches for reducing or avoiding overshoots and undershoots and disturbances.

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