Multiplexing digital-to-analog converter

Abstract

A multiplexed digital-to-analog converter (100) includes an input interface, a phase generator (104), N bit multiplexers (102), N bit-to-analog converters (106), and a summing circuit (108). An input interface receives M digital data words for conversion into a sequence of M analog values, each of the M data words comprising N bits. A phase generator receives a clock signal having a clock cycle length and generates M phase signals of the clock signal with active time portions of adjacent phase signals overlapping. Each bit multiplexer multiplexes M bits, taken from one of the M digital data words, with given localization, in response to an overlap between adjacent pairs of phase signals, thereby producing a corresponding sequence of bits. The N bit-to-analog converters convert a sequence of bits into a corresponding sequence of bit-level analog values. Summing circuitry sums the respective bit-level analog values, thereby producing a sequence of M analog values representing the M digital data words.

Description

[0001] Cross-references to related applications This application claims the benefit of U.S. Provisional Patent Application 63 / 518,327, filed August 9, 2023, the disclosure of which is incorporated herein by reference.

[0002] Invention Field This invention generally relates to digital-to-analog converters (DACs), and more specifically to multiplexing, also known as mixer-based DACs. Background of the Invention High-speed digital-to-analog converters (DACs) sometimes use multiplexing schemes, in which digital inputs are provided in multiple concurrent inputs, which are sequentially multiplexed to produce a single high-speed analog output.

[0004] U.S. Patent 10,778,263 discloses various embodiments of systems, apparatuses, and methods for providing multiphase, time-interleaved radio frequency (RF) digital-to-analog converters (DACs) suitable for radar, radio, mobile, and other RF systems.

[0005] In Olieman and Nauta's "An Interleaved Full Nyquist High-Speed ​​DAC Technique" (University of Twente, CTIT Institute, IC Design group, Enschede, The Netherlands, IEEE Journal of Solid-State Circuits Volume 50, Issue 3, March 2015), the authors proposed a 9-bit 11GS / s DAC that achieves an SFDR greater than 50 dB in the Nyquist range and an IM3 below -50 dBc in the Nyquist range. The DAC uses a double-interleaved architecture to suppress spurious signals that typically limit DAC performance.

[0006] In Dickson et al.'s paper, "A 72-GS / s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb / s Serial Links" (IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL.58, NO.4, APRIL 2023), the design and measurement of a source-side series-terminated (SST) transmitter based on a digital-to-analog converter (DAC) for wired applications employing 4-nm FinFET CMOS technology are detailed. The DAC achieves 8-bit resolution and high analog output bandwidth through the use of a segmented architecture and a single-ended LSB.

[0007] Finally, in Bechthum et al.'s paper, "A Wideband RF Mixing-DAC Achieving IMD < -82dBc Up to 1.9 GHz" (IEEE Journal of Solid-State Circuits, Volume 51, Issue 6, June 2016), the authors proposed a highly linear wideband mixing DAC architecture. The current-steering DAC core and mixer are integrated together at the unit current unit level. A 1-bit DAC output stage is cascaded with a 1-bit mixer to form the mixing DAC current unit. Invention Overview The embodiments of the present invention described herein provide a multiplexed digital-to-analog converter (M-DAC) circuit, including an input interface, a phase generator, a set of N bit-multiplexers, a set of N bit-to-analog converters, and a summing circuit. The input interface is configured to receive M digital data words for conversion into a sequence of M corresponding analog values, each of the M data words comprising N bits. The phase generator is configured to receive a clock signal having a clock cycle length and generate M phase signals of the clock signal, wherein the active times of adjacent phase signals partially overlap. In the set of N bit-multiplexers, each bit-multiplexer is configured to multiplex M bits, each with bit-significance, taken from one of the M digital data words in response to the overlap between adjacent pairs of phase signals from the M phase signals, thereby generating a corresponding bit sequence. The N bit-to-analog converters are configured to convert the bit sequence generated by the N bit-multiplexers into a corresponding bit-level analog value sequence. The summing circuit is configured to sum the corresponding bit-level analog values ​​from the bit-level analog value sequence, thereby producing a sequence of M analog values ​​representing M digital data words.

[0009] In some embodiments, the active time of the phase signal of the clock signal is longer than the clock period length divided by M. In embodiments, a bit-to-analog converter associated with a bit-to-bit weight is configured to scale the bit-level analog value according to the bit-to-bit weight. In the disclosed embodiments, a phase generator is configured to adjust the overlap period between the active times of at least two phase signals in the phase signal. In some embodiments, the summing circuit includes an electrical connection of a sequence of bit-level analog values ​​generated by at least some bit-to-analog converters.

[0010] According to an embodiment of the present invention, a method for digital-to-analog conversion is further provided. The method includes receiving M digital data words for conversion into a sequence of M corresponding analog values, each of the M data words comprising N bits. A clock signal having a clock cycle length is received, and M phase signals of the clock signal are generated, wherein the activity times of adjacent phase signals partially overlap. In response to the overlap between adjacent pairs of phase signals from the M phase signals, M bits with assigned position weights, taken from a corresponding one of the M digital data words, are multiplexed to generate a corresponding bit sequence. The bit sequence is converted into a corresponding bit-level analog value sequence. The corresponding bit-level analog values ​​from the bit-level analog value sequence are summed to generate a sequence of M analog values ​​representing the M digital data words.

[0011] The invention will be more fully understood from the following detailed description of embodiments thereof, taken in conjunction with the accompanying drawings, in which: Brief description of the attached diagram Figure 1 This is a block diagram schematically illustrating a multiplexed digital-to-analog converter (M-DAC) according to an embodiment of the present invention; Figure 2 This is a schematic block diagram illustrating a P-channel metal-oxide-silicon (PMOS) 4-bit multiplexer according to an embodiment of the present invention; Figure 3 This is a timing diagram schematically showing the waveform of a 4-input bit multiplexer according to an embodiment of the present invention; Figure 4 This is a schematic block diagram illustrating an N-channel metal-oxide-semiconductor (NMOS) 4-bit multiplexer according to an embodiment of the present invention; Figure 5 This is a block diagram schematically illustrating a complementary metal-oxide-semiconductor (CMOS) bit multiplexer according to an embodiment of the present invention; Figure 6 This is a timing diagram schematically illustrating the waveform of indirect contention in a PMOS-based bit multiplexer according to an embodiment of the present invention; and Figure 7 This is a flowchart schematically illustrating a method for multiplexing digital-to-analog conversion according to an embodiment of the present invention. Detailed Implementation

[0012] Overview Multiplexed digital-to-analog converters (M-DACs) are typically used in high-speed applications. An M-DAC receives multiple digital words in parallel at a reduced rate, sequentially multiplexes the input words, and generates a high-speed analog signal at a rate equal to the input rate multiplied by the number of parallel words. (Multiplexed DACs are sometimes referred to as mixer-based DACs. We will use these two terms interchangeably below.)

[0013] Because the multiplexing selection time for each input word is short (equal to the input time of each group of parallel words divided by the number of parallel words, hereinafter referred to as Tm), the selection signal may be short and therefore noisy.

[0014] The embodiments of the invention disclosed herein provide an M-DAC and associated methods, wherein a phase generator generates a phase signal wider than Tm, and multiplexing is performed in response to the overlap between multiple phase signals. In an embodiment, the M-DAC receives M N-bit parallel words, which are input to N bit multiplexers, each having M inputs; the outputs of the bit multiplexers are input to N bit-to-analog converters, which convert the outputs of the bit multiplexers into N corresponding analog signals, wherein the high level of the analog signal is related to 2... bs The values ​​are proportional (bs is the bit weight, e.g., the least significant bit is 0, the next bit is 1, etc.). Then, the summing circuit sums the N analog signals to produce a sequence of M analog values ​​representing M digital data words.

[0015] Other embodiments described below assume M=4 and produce complementary analog outputs (any other suitable value of M may be used in other embodiments with unipolar and / or complementary outputs).

[0016] In the embodiments disclosed below, bit multiplexers based on P-channel metal-oxide-semiconductor (PMOS) transistors are used. Each bit multiplexer selects one bit from M input bits with assigned positioning weights. The bit multiplexer includes a current source, a first group of four PMOS transistors that forward current to a first resistor, and a second group of four PMOS transistors that forward current to a second resistor. Gating circuitry is configured to enable each of the first group of PMOS transistors in response to an overlap and set bit input between two adjacent phase signals, and to enable each of the second group of PMOS transistors in response to an overlap and clear bit input between two adjacent phase signals (for PMOS transistors, "enable" is a low voltage at the gate). The bit multiplexer outputs complementary signals—Out+ and Out- signals—with Out+ connected to the first resistor and having a logic value corresponding to the logic level of the selected bit input, and Out- connected to the second resistor and having an inverted logic value corresponding to the logic level of the selected bit input.

[0017] In a similar embodiment disclosed below, the bit multiplexer is based on an N-channel metal-oxide-semiconductor (NMOS) transistor. A current source draws current from the positive power rail through two resistors and two sets of NMOS transistors. A gating circuit, similar to those in PMOS-based bit multiplexers, enables either the first or second set of transistors in response to the overlap of phase signals and the level of the bit input (for NMOS transistors, "enable" is a high gate voltage).

[0018] In another embodiment, the bit multiplexer is based on complementary metal-oxide-semiconductor (CMOS). Four pairs of NMOS-PMOS transistors (one for each bit input) drive a common output node; when a pair of adjacent phase signals overlap, one of the NMOS-PMOS transistor pairs drives the node high or low according to the logic level of the selected bit input.

[0019] System Description High-speed DAC design presents several limitations and challenges. A major issue is maintaining the desired accuracy and linearity of the analog output at increased speeds. Innovative architectures are needed to overcome these limitations: the complexity of the conversion process, coupled with constraints on power consumption, area utilization, and signal integrity.

[0020] Embodiments of the present invention introduce a high-speed DAC characterized by a mixer-based N-to-1 architecture, which effectively addresses those limitations and provides enhanced performance in terms of speed, accuracy, power efficiency and signal integrity.

[0021] The mixer-based architecture utilizes M switched current sources at the DAC output, each responsible for combining the weighted portion of the analog signal to generate the final output. This method ensures efficient conversion of the digital input by leveraging parallel processing techniques while minimizing the effects of non-ideals such as nonlinearity and distortion.

[0022] In the following description, we use the term multiplexing (M-DAC). This type of DAC is also known in the industry as a mixer-based DAC, which uses the same acronym M-DAC.

[0023] Figure 1 This is a schematic block diagram illustrating a multiplexed digital-to-analog converter (M-DAC) 100 according to an embodiment of the present invention. The M-DAC 100 receives a clock input and M N-bit digital data words for conversion into a single analog value. In each clock cycle, the M-DAC receives M digital data words representing a continuous digital input, which are converted into a sequence of M corresponding analog words at a rate M times the clock rate. For example, if M=4 and the clock frequency is 1GHz, the M-DAC receives 4*10^2 N bits per second. 9 Each digital word is used for conversion to an analog signal; during the first quarter of the clock cycle, the M-DAC converts the first of the four digital words to an analog value, during the second quarter of the clock cycle, the M-DAC converts the second digital word to an analog value, and so on.

[0024] In the following text, we will refer to the bit weights of the M bits of each digit word, starting from the bit weight of 0 assigned to the least significant bit of the digit word, up to the bit weight of N-1 for the most significant bit.

[0025] The M-DAC 100 includes a suitable input interface (not shown) for receiving M N-bit digital data words in each clock cycle. The M-DAC 100 also includes N M-bit multiplexers 102, each with a bit weight of one bit. Each multiplexer receives M bit inputs with equal bit weights from each of the M N-bit inputs. A phase generator 104 is configured to generate M phase signals in a recursive sequence repeated after each of the M clock cycles. In this embodiment, the active and inactive times of each phase signal are greater than the clock cycle time divided by M (greater than 0.25 ns in the 1 GHz example above). Therefore, in this embodiment, the generation of very fast signals is avoided.

[0026] Each of the bit multiplexers is configured to produce a single bit selected from M bit inputs based on a phase signal; therefore, the output of each bit multiplexer comprises a sequence of bits.

[0027] We call the ordered set of phase signals the set that includes all phase signals, ordered according to the corresponding time of the inactive-to-active transition. If two phase signals are adjacent to each other in the ordered set, they are said to be adjacent to each other (however, since the sequence of phase signals is cyclic, the Mth phase signal is also adjacent to the first phase signal).

[0028] In this embodiment, the activity times of adjacent phase signals partially overlap. For example, assuming M=4, if we designate four consecutive quarters of the clock cycle as T0, T1, T2, and T3, then the first phase signal may be active at T0 and T1, the second phase signal at T1 and T2, the third phase signal at T2 and T3, and the fourth phase signal at T3 and T0. It can be seen that the first and second phase signals overlap at T0, the second and third phase signals overlap at T1, the third and fourth phase signals overlap at T2, and the fourth phase signal overlaps with the first phase signal at T3.

[0029] In an embodiment, the bit multiplexer is configured to generate an output in response to the overlap between two adjacent phase signals. For example, when the first phase signal overlaps with the second phase signal, the output of the bit multiplexer corresponding to bit weight n will be equal to the nth bit of input 1; when the second phase signal overlaps with the third phase signal, it will be equal to the nth bit of input 2; when the third phase signal overlaps with the fourth phase signal, it will be equal to the nth bit of input 3; and when the fourth phase signal overlaps with the first phase signal, it will be equal to the nth bit of input 4. The resulting bit sequence will include set I. 11 , I 12 , I 13 , I 14 (I)mn It is the m-th bit of the n-th input.

[0030] The outputs generated by the N bit multiplexers are input to corresponding bit-to-analog converters 106; each bit-to-analog converter is configured to convert a bit value (logic 1 or logic 0) into an analog value scaled according to a given bit weight. For example, when the input bit is logic 1, the bit-to-analog converter corresponding to the least significant bit can output a voltage of 10mV, and when the input bit is logic 0, it outputs a voltage of 0; the converter corresponding to bit weight 1 will output 20mV or 0mV depending on the input bit, and so on (in another embodiment, the bit-to-analog converter can generate current).

[0031] The outputs of all bit-to-analog converters 106 are input to summing circuit 108, which is configured to sum the input signals and generate analog output signals.

[0032] Therefore, in this embodiment, the M-DAC 100 receives a clock signal and M digital data words, each data word comprising N bits, and uses a series of bit multiplexers, bit-to-analog converters, and summing circuitry to generate a sequence of M corresponding analog values. Each bit multiplexer is configured to multiplex the input bits in response to overlap between phase signals generated by a phase generator and including relatively low-frequency signals.

[0033] Referenced through examples Figure 1 The configuration of the M-DAC 100 shown and presented above is illustrated. Other configurations may be used in alternative embodiments. For example, in one embodiment, the bit multiplexer is configured to produce an analog output based on the overlap between the bit input and the phase signal (and therefore the bit-to-analog 106 is not used). In another embodiment, the summing circuit 108 includes a resistor network where the resistor values ​​are set according to corresponding bit weights, thus eliminating the need for both the bit-to-analog circuit 106 and the summing circuit 108.

[0034] We will now continue to describe the bit multiplexer of the M-DAC, where bit multiplexing is accomplished by switching P-channel metal-oxide-semiconductor (PMOS) transistors.

[0035] Figure 2This is a schematic block diagram of a P-channel metal-oxide-silicon (PMOS) 4-bit multiplexer 200 according to an embodiment of the present invention. The 4-bit multiplexer 200 receives four complementary inputs (M=4) and produces differential outputs. The 4-bit multiplexer has a complementary structure, generating a positive OUT+ output and a negative OUT- output. A common current source 202 provides current to a common node 204. A set of four PMOS transistors 206 directs current to ground through a resistor 208; if any one of the transistors is turned on, the positive OUT+ output is driven high. Similarly, a set of four PMOS transistors 210 directs current to ground through a resistor 212; if any one of the transistors 210 is turned on, the negative OUT- output is driven high.

[0036] The bit multiplexer includes eight identical gate circuits 214, each including a NOR gate 216 with a PHI-A phase input and a D data input, and a NAND gate 218 with a PHI-B phase input and a NOR gate output at a second input. Four gate circuits 214A drive the gate of PMOS transistor 206, and four gate circuits 214B drive the gate of PMOS transistor 210. The inputs of gate circuits 214A and 214B are connected to the positive and negative polarities of phase signals PHI0 to PHI3, and to the D0 to D3 inputs (and their inverse polarities), such that the logic function used to drive OUT+ high is: , And the logic function used to drive OUT- high is: , Where Φ0 to Φ3 represent phase generator 104 ( Figure 1 The generated phase signals PHI0 to PHI3. Therefore, the OUT+ output will be set to high (logic 1) in response to a D input that is high when two adjacent phase signals are active, and similarly, the OUT- output will be set to high in response to a D input that is low when the same two adjacent phase signals are active.

[0037] Figure 3 This is a timing diagram schematically showing the waveform 300 of a 4-input multiplexer according to an embodiment of the present invention.

[0038] It should be noted that although the 4-bit input (for other values ​​of M, the input is M-bit) is represented as D0, D1, D2, and D3, the logic value applied to the input bit lines is represented as I. nm , where m indicates the input bit line and ranges from 0 to M-1, and n is an index indicating the number of clock cycles.

[0039] Waveform 302 shows the logic value on D0; waveform 304 shows the logic value on D1; waveform 306 shows the logic value on D2; and waveform 308 shows the logic value on D3.

[0040] Waveform 310 shows PHI0, waveform 312 shows PHI1, waveform 314 shows PHI2, and waveform 316 shows PHI3.

[0041] Waveform 318 shows PG0—four PMOS transistors 206 ( Figure 2 The voltage at the gate of the first PMOS transistor in ). When PHI0=1 and PHI1=1 (e.g., during the overlap of PHI0 and PHI1), PG0 presents a low voltage only when D0 is at logic 1 during the overlap (thus turning on the corresponding PMOS transistor 206).

[0042] Similarly, waveform 320 shows PG1, which is low only when D1 is at logic 1 at the overlap time of PHI1 and PHI2; waveform 322 shows PG2, which is low only when D2 is at logic 1 at the overlap time of PHI2 and PHI3; and waveform 324 shows PG3, which is low only when D3 is at logic 1 at the overlap time of PHI3 and PHI0.

[0043] Drive gate circuit 214B ( Figure 2 The signal is the same as the signal driving the corresponding gate circuit 214A, except that the polarity of the D input is reversed. When any one of the PMOS transistors 206 is turned on, the corresponding PMOS transistor 210 will not be turned on; the current source 202 ( Figure 2 The current supplied will create a voltage drop across resistor 208, setting OUT+ to a high voltage. Conversely, when any of the PMOS transistors 210 is turned on, the corresponding PMOS transistor 206 will not be turned on, and the current will create a voltage drop across resistor 212, setting OUT- to a high voltage.

[0044] Waveforms 326 and 328 show the OUT+ and OUT- voltages, respectively, each switching at four times the rate at the D input. OUT+ and OUT- are complementary outputs.

[0045] In some embodiments, the M-DAC includes a bit multiplexer that uses N-channel metal-oxide-semiconductor (PMOS) transistors for multiplexing.

[0046] Figure 4This is a block diagram schematically illustrating an N-channel metal-oxide-silicon (NMOS) 4-way bit multiplexer 400 according to an embodiment of the present invention. In some aspects, bit multiplexer 400 is bit multiplexer 200 ( Figure 2 The complementary implementation of the NMOS transistors 400 and 410 has inverted signal polarity and uses NMOS transistors instead of PMOS transistors. Similar to the NMOS multiplexer 200, the NMOS multiplexer 400 receives four complementary inputs (M=4) and produces differential outputs. The NMOS multiplexer has a complementary structure and generates a positive OUT+ output and a negative OUT- output. A common current source 402 draws current from a common node 404. A set of four NMOS transistors 406 directs current from the positive supply rail to node 404 through a resistor 408, driving the negative OUT- output high if any one of the transistors is on. Similarly, a set of four NMOS transistors 410 directs current to node 404 through a resistor 412, driving the positive OUT+ output high if any one of the transistors is on.

[0047] Bit multiplexer 400 includes eight identical gate circuits 414, each including a NAND gate 416 with a PHI-A phase input and a D data input, and a NOR gate 418 with a PHI-B phase input and a NAND gate output at a second input. Four gate circuits 414A drive the gates of NMOS transistors 406, and four gate circuits 414B drive the gates of NMOS transistors 410. The inputs of gate circuits 414A and 414B are connected to the positive and negative polarities of phase signals PHI0 to PHI3 and the D0 to D3 inputs (and their inverse polarities). It can be seen that the logic functions for OUT+ and OUT- are the same as those for bit multiplexer 200. , .

[0048] In some embodiments, the M-DAC includes a bit multiplexer that uses complementary metal-oxide-silicon (CMOS) gates for multiplexing.

[0049] Figure 5This is a schematic block diagram illustrating a CMOS bit multiplexer 500 according to an embodiment of the present invention. The bit multiplexer 500 includes a common node 502 driven by four pairs of transistors, each pair including pull-up PMOS transistors 504 (designated 504A, 504B, 504C, and 504D) and pull-down NMOS transistors 506 (designated 506A, 506B, 506C, and 506D). Four P-gate circuits 508 (designated 508A, 508B, 508C, and 508D) drive the PMOS transistors 504, and four N-gate circuits 510 (designated 510A, 510B, 510C, and 510D) drive the NMOS transistors 506.

[0050] Each P-gated circuit 508 includes a NOR gate 512 and a NAND gate 514. The P-gated circuit receives PHI-A input, D input, and PHI-B input, and implements the following logic functions: Out = ~(PHI-A & ~D & PHI-B).

[0051] Each N-gated circuit 510 includes a NAND gate 516 and a NOR gate 518. Similar to P-gated circuits, N-gated circuits receive PHI-A input, D input, and PHI-B input and implement complementary logic functions: Out = PHI-A & D & ~PHI-B.

[0052] The table below depicts the on / off states of all PMOS transistors 504 and NMOS transistors 506 based on the overlap between phase signals and the input logic value of the D input (for given positioning weights). In the embodiment, phase generator 104 ( Figure 1 A phase signal is generated such that at any given time, one and only one pair of adjacent phase signals overlap. Therefore, node 502 will always be driven by a single PMOS transistor 504 or a single NMOS transistor 506 and has low impedance to either the low or high power rail.

[0053] The CMOS bit multiplexer 500 also includes a resistor 520 that buffers nodes 502 from other circuitry; in some embodiments, multiple CMOS bit multiplexers involving different bit weights are connected to a common node. The ratio of the resistor 520 is set according to the bit weight (e.g., the resistance of the resistor 520 for a given CMOS bit multiplexer is equal to 1 / 2). bsWhere bs are the bit weights connected to the bit line inputs of the bit multiplexer. If the voltage at the common node is 0 (e.g., virtual ground), the sum of the currents input to the common node is proportional to the desired analog output of the M-DAC. Therefore, the CMOS bit multiplexer 500 includes a bit-to-analog converter 106. Figure 1 The summing circuit 108 includes a bit multiplexed to a common node electrical connection (and in some embodiments, includes current-to-voltage conversion).

[0054] exist Figure 2 , Figure 4 and Figure 5 The configurations of the bit multiplexers 200, 400, and 500 shown and described above are exemplary embodiments cited for clarity of concept only. Other configurations may be used in alternative embodiments. For example, in some embodiments, the gating circuitry or portions thereof may be replaced by additional PMOS or NMOS transistors (e.g., to select a bit input when the first and second phase signals overlap, three transistors may be connected in series, gated by the first and second phase signals and by the bit input). In some embodiments, the bit multiplexer selects a bit input in response to the overlap of the three phase signals. In other embodiments, the bit multiplexer outputs current instead of voltage.

[0055] Reduce competition High-speed multiplexing often requires contention because, due to inaccuracies in the selection signal, the multiplexer output may be temporarily driven to different values. Figure 2 and Figure 3 In the example embodiment shown, direct competition in the bit multiplexer is impossible because the PMOS or NMOS transistors drive current in the same direction; however, in this embodiment, to improve speed, the bit-to-analog converter 106 ( Figure 1 This can include differential classifications, and if OUT+ and OUT- have the same polarity, competition may occur (referred to as indirect competition in this paper). Figure 5 In the example embodiment shown, contention can occur within the bit multiplexer.

[0056] In this embodiment, contention can be mitigated by adding delays to the gates of the gating circuit or by adjusting the start or end of overlapping periods.

[0057] Figure 6 This is a timing diagram schematically illustrating the waveform 600 of indirect contention in a PMOS-based bit multiplexer according to an embodiment of the present invention. D0 and D1 are initially at logic 0 and logic 1 (respectively), and become logic 1 and logic 0 with the falling edge of PHI1.

[0058] The timing diagram shows the gate circuit 214A ( Figure 2 The signals include ~PHI0 waveform 602, ~D0 waveform 604, NOR waveform 606 (showing the logic level on the NOR gate 216 of the gate circuit 214A), PHI1 waveform 608, and PG0(+) waveform 610, which show the voltage level on the gate of the corresponding PMOS transistor 206.

[0059] The timing diagram also includes gate circuit 214B ( Figure 2 The signals include ~PHI1 waveform 612, D1 waveform 614, NOR waveform 616 (showing the logic level on the NOR gate 216 of the gate circuit 214B), PHI2 waveform 608, and PG1(-) waveform 620, which show the voltage level on the gate of the corresponding PMOS transistor 210.

[0060] The thick arc arrow indicates the location of a potential contention. When PG1(-) goes low, PG0(+) goes high. If the delay is not adjusted, there may be a time interval where PG0(+) is still low (and therefore OUT+ is high) but PG1(-) is already low (and therefore OUT- is also high).

[0061] The thin arrow indicates that the falling edge of PG1(-) is driven by the rising edge in PHI2, and its propagation occurs through NAND gate 218 ( Figure 2 Therefore, in an embodiment, if a delay is added to the NAND gate (from phase input to output), race conditions can be avoided.

[0062] Similar analysis can be performed on other embodiments, which may require delays in other gates for race avoidance.

[0063] Figure 7 This is a flowchart 700 schematically illustrating a method for multiplexing digital-to-analog conversion according to an embodiment of the present invention. The flowchart is provided by M-DAC 100 ( Figure 1 )implement.

[0064] The flowchart begins with a clock and data receiving operation 702, where the M-DAC receives a clock input having a frequency of F, and a stream of word groups synchronized with the clock edge for conversion into an analog signal, each word group comprising M N-bit words. In some embodiments, the stream of word groups is synchronized with the rising edge of the clock input; in other embodiments, the stream is synchronized with the falling edge of the clock; and in still other embodiments, the stream is synchronized with both the rising and falling edges of the clock. In embodiments where the stream is synchronized with either the rising or falling edge of the clock, the rate R of the input word groups is F, while in embodiments where the stream is synchronized with both the rising and falling edges, R = 2 * F.

[0065] At phase signal generation operation 704, the M-DAC generates M phase signals. The frequency of the phase signals is R, and the activity period is k / (R*M), where k is an integer greater than 1 and less than M. Each pair of two adjacent phase signals will have an overlap period of 1 / (R*M).

[0066] For example, if M=4, the M-DAC generates four phase signals, designated PHI0, PHI1, PHI2, and PHI3. Assuming R=250MHz, the clock period is 4ns. We divide this time into four 1ns intervals, designated T0, T1, T2, and T3. PHI0 will then be active during T0 and T1; PHI1 will be active during T1 and T2; PHI2 will be active during T2 and T3; and PHI3 will be active during T3 and T0. Each pair of adjacent phase signals overlaps during a single 1ns interval. Note that no phase signal is narrower than 2ns.

[0067] Next, at bit multiplexing operation 706, the M-DAC performs bit multiplexing on N groups of M bit inputs with equal bit weights. For example, the M bit inputs include the least significant bits of the M words, the M bit inputs include the M bits of the input 1, and so on. Each bit multiplexer responds to the overlap between two phase signals to select the bit line. In the example of M=4 above, each bit multiplexer can select the first bit input when PHI0 overlaps with PHI1, the second bit input when PHI1 overlaps with PHI2, the third bit input when PHI2 overlaps with PHI3, and the fourth bit input when PHI3 overlaps with PHI0.

[0068] At bit-to-analog conversion operation 708, the M-DAC then converts the outputs of the N-bit multiplexers to analog values ​​according to their respective bit weights. For example, if N=8 and the MDAC resolution is 10mV, the M-DAC will convert the output of logic 0 in any bit multiplexer to 0V; for the corresponding bit weights 0, 1, 2, etc., the M-DAC will convert the output of logic 1 to 10mV, 2*10mV, 4*10mV, 8*10mV, and so on. The logic 1 at the bit multiplexer output corresponding to the most significant bit (bit weight = 7) will be converted to 2. 7 *10mV = 1.28V.

[0069] Finally, at signal summation operation 710, the M-DAC sums N analog values ​​to produce an analog signal representing the stream of input words.

[0070] Referenced through examples Figure 7The configuration of flowchart 700, shown in the diagram and described above, is illustrated. Other suitable flowcharts may be used in alternative embodiments. For example, in some embodiments, the M-DAC produces complementary outputs, including a positive output signal and a negative output signal. In embodiments, the bit multiplexer may select bit inputs in response to the overlap of more than two phase signals (this may be useful for large values ​​of M, such as M=16). In some embodiments, the bit multiplexer outputs analog values ​​according to bit weights, and bit-to-analog conversion is not required (operation 708).

[0071] The above references Figures 1 to 7 The described apparatus and methods; the configurations of the M-DAC 100, bit multiplexers 200, 400, and 500, waveforms 300 and 600, and the method of flowchart 700 (including all its units and subunits) are illustrative configurations, waveforms, and methods shown purely for conceptual clarity. Any other suitable methods and configurations may be used in alternative embodiments. For example, in one embodiment, a bit multiplexer based on a voltage source may be used instead of a current source.

[0072] In various embodiments, the M-DAC 100 (including its sub-units) can be implemented using suitable hardware, such as one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), or a combination of ASICs and FPGAs.

[0073] While the embodiments described herein primarily address multiplexed digital-to-analog converters, the methods and systems described herein can also be used in other applications.

[0074] Therefore, it should be understood that the above embodiments are cited by way of example, and the invention is not limited to what has been specifically shown and described above. Rather, the scope of the invention includes combinations and sub-combinations of the various features described above, as well as variations and modifications of the invention that would be conceived by one of skill in the art upon reading the above description and that are not disclosed in the prior art. Documents incorporated herein by reference are considered part of this application, and the definitions in this specification should be considered only, unless any terms are defined in these incorporated documents in a manner that conflicts to some extent with the definitions expressly or implicitly made in this specification.

Claims

1. A multiplexed digital-to-analog converter (M-DAC) circuit, comprising: An input interface is configured to receive M digital data words for conversion into a sequence of M corresponding analog values, each of the M data words comprising N bits; A phase generator is configured to receive a clock signal having a clock cycle length and generate M phase signals of the clock signal, wherein the activity times of adjacent phase signals partially overlap with each other. A group of N bit multiplexers, each bit multiplexer being configured to multiplex M bits of a corresponding digital data word with assigned bit weights from the M digital data words in response to the overlap between adjacent phase signal pairs from the M phase signals, thereby generating a corresponding bit sequence; A set of N bit-to-analog converters configured to convert a bit sequence generated by the N bit multiplexers into a corresponding bit-level analog value sequence; and A summing circuit is configured to sum the corresponding bit-level analog values ​​from the sequence of bit-level analog values, thereby producing a sequence of M analog values ​​representing the M digital data words.

2. The circuit according to claim 1, wherein, The active time of the phase signal of the clock signal is longer than the clock period length divided by M.

3. The circuit according to claim 1 or 2, wherein, The location-to-analog converter associated with the location weight is configured to scale the bit-level analog value according to the location weight.

4. The circuit according to claim 1 or 2, wherein, The phase generator is configured to adjust the overlap period between the active times of at least two phase signals in the phase signal.

5. The circuit according to claim 1 or 2, wherein, The summing circuit includes electrical connections to the sequence of bit-level analog values ​​generated by at least some of the bit-to-analog converters.

6. A method for digital-to-analog conversion, comprising: Receive M digital data words for conversion into a sequence of M corresponding analog values, each of the M data words comprising N bits; Receive a clock signal with a clock cycle length and generate M phase signals of the clock signal, wherein the activity times of adjacent phase signals partially overlap with each other; In response to the overlap between adjacent phase signal pairs from the M phase signals, the M bits with assigned positioning weights from a corresponding digital data word taken from the M digital data words are multiplexed to generate a corresponding bit sequence. Convert the bit sequence into a corresponding bit-level analog value sequence; and The corresponding bit-level analog values ​​from the bit-level analog value sequence are summed to generate a sequence of M analog values ​​representing the M digital data words.

7. The method according to claim 6, wherein, The active time of the phase signal of the clock signal is longer than the clock period length divided by M.

8. The method of claim 6 or 7 further comprises scaling the bit-level analog value associated with the positioning weight by a factor set according to the positioning weight.

9. The method according to claim 6 or 7, wherein, Generating the phase signal includes adjusting the overlap period between the activity times of at least two phase signals in the phase signal.

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