Interleaver design for modulation with polar codes

Abstract

Aspects of the present disclosure relate to techniques for wireless communication, and in particular to methods for interleaving and deinterleaving wireless data. In some examples, a wireless node may encode a plurality of bits to produce encoded bits. In some examples, a wireless node may interleave (i) a first subset of one or more coded bits via a first interleaving scheme, and (ii) a second subset of one or more coded bits via a second interleaving scheme, where one or more coded bits in the second subset are different from one or more coded bits in the first subset. In some examples, a wireless node may map (i) the interleaved first subset to a first bit level, and (ii) the interleaved second subset to a second bit level.

Description

Technical Field

[0001] This disclosure relates generally to communication systems, and more specifically to the design of interleavers that utilize polar codes for modulation. Background Technology

[0002] Wireless communication systems are widely deployed to provide a variety of telecommunications services, such as telephone, video, data, messaging, and broadcasting. Typical wireless communication systems may employ multiple access technologies capable of supporting communication with multiple users by sharing available system resources. Examples of such multiple access technologies include Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal Frequency Division Multiple Access (OFDMA) systems, Single Carrier Frequency Division Multiple Access (SC-FDMA) systems, and Time Division Synchronous Code Division Multiple Access (TD-SCDMA) systems.

[0003] These multiple access technologies have been adopted in various telecommunications standards to provide a common protocol that enables different wireless devices to communicate at the city, national, regional, and even global levels. An example telecommunications standard is 5G New Radio (NR). 5G NR is part of the Continuous Evolution of Mobile Broadband (CEM) program issued by the 3rd Generation Partnership Project (3GPP) to meet new requirements associated with latency, reliability, security, scalability (e.g., with the Internet of Things (IoT),) and other requirements. 5G NR includes services associated with enhanced mobile broadband (eMBB), massive machine-type communications (mMTC), and ultra-reliable low-latency communications (URLLC). Some aspects of 5G NR can be based on the 4G Long Term Evolution (LTE) standard. Further improvements to 5G NR technology are needed. Furthermore, these improvements can also be applied to other multiple access technologies and telecommunications standards that adopt these technologies. Summary of the Invention

[0004] The following is a simplified summary of one or more aspects of the invention to provide a basic understanding of these aspects. This summary is not a broad overview of all anticipated aspects, nor is it intended to identify key or essential elements of all aspects, nor to depict the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed descriptions that follow.

[0005] In some aspects, the technology described herein relates to an apparatus for wireless communication, the apparatus comprising: one or more memories having instructions individually or in combination; and one or more processors configured individually or in combination to execute the instructions and cause the apparatus to: encode a plurality of bits to produce coded bits; perform interleaving: (i) interleaving a first subset of one or more coded bits via a first interleaving scheme, and (ii) interleaving a second subset of one or more coded bits via a second interleaving scheme, wherein one or more coded bits in the second subset are different from one or more coded bits in the first subset; mapping the interleaved first subset and the interleaved second subset to one or more modulation symbols based on corresponding bit levels of each of the interleaved first subset and the interleaved second subset; and outputting the interleaved first subset and the interleaved second subset via the one or more modulation symbols for transmission.

[0006] In some aspects, the technology described herein relates to an apparatus for wireless communication, the apparatus comprising: one or more memories having instructions individually or in combination; and one or more processors configured individually or in combination to execute the instructions and cause the apparatus to: obtain a first subset of one or more interleaved bits and a second subset of one or more interleaved bits via one or more symbols, wherein one or more interleaved bits in the second subset are different from one or more interleaved bits in the first subset; deinterleave the first subset of one or more interleaved bits via a first interleaving scheme and deinterleave the second subset of one or more interleaved bits via a second interleaving scheme; and decode the deinterleaved first subset of one or more deinterleaved bits and the deinterleaved second subset of one or more deinterleaved bits.

[0007] In some aspects, the techniques described herein relate to a method for wireless communication at a wireless node, the method comprising: encoding a plurality of bits to produce coded bits; interleaving: (i) interleaving a first subset of one or more coded bits via a first interleaving scheme, and (ii) interleaving a second subset of one or more coded bits via a second interleaving scheme, wherein one or more coded bits in the second subset are different from one or more coded bits in the first subset; mapping the interleaved first subset and the interleaved second subset to one or more modulation symbols based on corresponding bit levels of each of the interleaved first subset and the interleaved second subset; and outputting the interleaved first subset and the interleaved second subset via the one or more modulation symbols for transmission.

[0008] In some aspects, the technology described herein relates to a method for wireless communication at a wireless node, the method comprising: obtaining a first subset of one or more interleaved bits and a second subset of one or more interleaved bits via one or more symbols, wherein one or more interleaved bits in the second subset are different from one or more interleaved bits in the first subset; deinterleaving the first subset of one or more interleaved bits via a first interleaving scheme and deinterleaving the second subset of one or more interleaved bits via a second interleaving scheme; and decoding the deinterleaved first subset of one or more deinterleaved bits and the deinterleaved second subset of one or more deinterleaved bits.

[0009] In some aspects, the technology described herein relates to an apparatus for wireless communication, the apparatus comprising: means for encoding a plurality of bits to produce coded bits; means for interleaving: (i) interleaving a first subset of one or more coded bits via a first interleaving scheme, and (ii) interleaving a second subset of one or more coded bits via a second interleaving scheme, wherein one or more coded bits in the second subset are different from one or more coded bits in the first subset; means for mapping the interleaved first subset and the interleaved second subset to one or more modulation symbols based on corresponding bit levels of each of the interleaved first subset and the interleaved second subset; and means for outputting the interleaved first subset and the interleaved second subset via one or more modulation symbols for transmission.

[0010] In some aspects, the technology described herein relates to an apparatus for wireless communication, the apparatus comprising: means for obtaining a first subset of one or more interleaved bits and a second subset of one or more interleaved bits via one or more symbols, wherein the one or more interleaved bits in the second subset are different from the one or more interleaved bits in the first subset; means for deinterleaving the first subset of one or more interleaved bits via a first interleaving scheme and deinterleaving the second subset of one or more interleaved bits via a second interleaving scheme; and means for decoding the deinterleaved first subset of one or more deinterleaved bits and the deinterleaved second subset of one or more deinterleaved bits.

[0011] A non-transitory computer-readable medium comprising computer-executable code, which, when executed by one or more processors, causes the one or more processors, individually or in combination, to: encode a plurality of bits to produce coded bits; perform interleaving: (i) interleaving a first subset of one or more coded bits via a first interleaving scheme, and (ii) interleaving a second subset of one or more coded bits via a second interleaving scheme, wherein one or more coded bits in the second subset are different from one or more coded bits in the first subset; mapping the interleaved first subset and the interleaved second subset to one or more modulation symbols based on corresponding bit levels of each of the interleaved first subset and the interleaved second subset; and outputting the interleaved first subset and the interleaved second subset via one or more modulation symbols for transmission.

[0012] A non-transitory computer-readable medium comprising computer-executable code, which, when executed by one or more processors, causes the one or more processors, individually or in combination, to: obtain a first subset of one or more interleaved bits and a second subset of one or more interleaved bits via one or more symbols, wherein one or more interleaved bits in the second subset are different from one or more interleaved bits in the first subset; deinterleave the first subset of one or more interleaved bits via a first interleaving scheme and deinterleave the second subset of one or more interleaved bits via a second interleaving scheme; and decode the deinterleaved first subset of one or more deinterleaved bits and the deinterleaved second subset of one or more deinterleaved bits.

[0013] To achieve the foregoing and related objectives, one or more aspects include the features fully described below and specifically pointed out in the claims. The following description and drawings illustrate some exemplary features of one or more aspects in detail. However, these features indicate only some of the various ways in which the principles of the various aspects may be employed, and this description is intended to include all such aspects and their equivalents. Attached Figure Description

[0014] Figure 1 This is a diagram illustrating an example of a wireless communication system and an access network.

[0015] Figure 2A This is an illustration of an example of the first frame according to various aspects of this disclosure.

[0016] Figure 2B This is a diagram illustrating examples of DL channels within a subframe according to various aspects of this disclosure.

[0017] Figure 2C This is an illustration of an example of a second frame according to various aspects of this disclosure.

[0018] Figure 2DThis is a diagram illustrating examples of UL channels within a subframe according to various aspects of this disclosure.

[0019] Figure 3 This is a diagram illustrating examples of base stations and user equipment (UEs) in an access network.

[0020] Figure 4 This is a block diagram illustrating an example decomposed base station architecture.

[0021] Figure 5 This is a block diagram illustrating an example of a device used in wireless communication that supports polar codes and modulation mapping.

[0022] Figure 6 This is a block diagram illustrating another example of a device that supports polar codes and modulation mapping used in wireless communication.

[0023] Figure 7 This is a block diagram illustrating an example technique for separating blocks of coded bits (X).

[0024] Figure 8 This is a block diagram illustrating an example of a pair of interleavers that receive a subset of coded bits and output an interleaved subset.

[0025] Figure 9 This is a flowchart of a wireless communication method.

[0026] Figure 10 This is a diagram illustrating an example of a hardware implementation used in an example device.

[0027] Figure 11 This is a flowchart of a wireless communication method.

[0028] Figure 12 This is a diagram illustrating another example of a hardware implementation for another example device. Detailed Implementation

[0029] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing the only configuration in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring these concepts.

[0030] Various aspects of this disclosure relate to interleaver designs for modulation using polar codes. In some examples, the interleaver design can be coupled with higher-order modulation schemes (e.g., modulation with 4th or higher order, such as quadrature phase shift keying (QPSK) and... m Quadrature Amplitude Modulation mUse it together with QAM.

[0031] Generally, the described techniques involve transmitting entities (e.g., base stations or other network entities) and receivers (e.g., user equipment or other mobile entities) including polar decoders, interleavers, and modulation mappers that cooperate to provide polar coding / decoding. In some aspects, the transmitting entity is configured to use multiple interleavers to interleave polar coded bits. The transmitting entity can then map the interleaved coded bits to different bit levels. For example, instead of using a single interleaver to interleave an entire block of coded bits, the transmitting entity can split the block of coded bits into subsets of coded bits and feed each subset into one of the multiple interleavers to maximize diversity combination.

[0032] In some examples, multiple interleavers may all use the same interleaver pattern (e.g., each interleaver in the interleaver is a triangular interleaver, a rectangular interleaver, or any other suitable interleaver pattern). In some examples, different interleavers may be used for different bit levels. Here, the coded bit block can be split such that the number of subsets of coded bits equals the number of bit levels. Thus, for example, using a 4-QAM modulation scheme, each modulation symbol can be... k = log2(4) = 2 bits to represent.

[0033] In some respects, multiple interleavers can all be the same interleaver, but configured to shift coded bits based on their respective indices. For example, a transmitting device can split an eight-coded-bit block into two subsets of four-coded-bits, where each subset's four bits can be identified by an index value. Here, the four coded bits in the first subset can be indexed as 1-4, and the four coded bits in the second subset can also be indexed as 1-4. Therefore, the coded bits in the first subset can be fed into the first interleaver in sequence (e.g., 1, 2, 3, 4). However, the coded bits in the second subset can be fed into the second interleaver after a cyclic shift (e.g., 2, 3, 4, 1). Thus, in this example, the cyclic shift can be a shift of 1 bit relative to the previous interleaver (e.g., by continuously applying a 1-bit shift to an additional interleaver by shifting the corresponding four-bit subset by 1 bit relative to the previous shift).

[0034] Therefore, multiple interleavers, each with a pseudo-random input order of bits, can be used across different bit levels to increase polarization and improve the performance of polarization decoding schemes.

[0035] Various apparatuses and methods will now be used to present several aspects of a telecommunications system. These apparatuses and methods will be described in detail below and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively, “elements”). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0036] As an example, an element, any part of an element, or any combination of elements may be implemented as a "processing system" including one or more processors. Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, system-on-a-chip (SoCs), baseband processors, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic devices, discrete hardware circuits, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors in the processing system can execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, software should be broadly interpreted as meaning instructions, instruction sets, code, code segments, program code, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc.

[0037] Therefore, in one or more example embodiments, the described functionality may be implemented in hardware, software, or any combination thereof. If implemented in software, the functionality may be stored or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media can be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disc storage devices, magnetic disk storage devices, other magnetic storage devices, combinations of computer-readable media of the types described above, or any other medium capable of storing computer-executable code in the form of computer-accessible instructions or data structures.

[0038] Figure 1This is an illustration of an example of a wireless communication system and access network 100. The wireless communication system (also referred to as a wireless wide area network (WWAN)) includes a base station 102, user equipment (UE) 104, an evolved packet core (EPC) 160, and another core network 190 (e.g., a 5G core (5GC)). The base station 102 may include macro cells (high-power cellular base stations) and / or small cells (low-power cellular base stations). Macro cells include base stations. Small cells include femtocells, picocells, and microcells.

[0039] Base station 102 configured for 4G Long Term Evolution (LTE) (collectively referred to as Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN)) can interface with EPC 160 via a first backhaul link 132 (e.g., S1 interface). Base station 102 configured for 5G New Radio (NR) (collectively referred to as Next Generation RAN (NG-RAN)) can interface with core network 190 via a second backhaul link 184. Among other functions, base station 102 can also perform one or more of the following functions: user data delivery, radio channel encryption and decryption, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection establishment and release, load balancing, distribution of Non-Access Stratum (NAS) messages, NAS node selection, synchronization, Radio Access Network (RAN) sharing, Multimedia Broadcast Multicast Service (MBMS), subscriber and equipment tracking, RAN Information Management (RIM), paging, location, and delivery of alarm messages. Base stations 102 can communicate directly or indirectly with each other via a third backhaul link 134 (e.g., an X2 interface) (e.g., via EPC 160 or core network 190). The first backhaul link 132, the second backhaul link 184, and the third backhaul link 134 can be wired or wireless.

[0040] Base station 102 can wirelessly communicate with UE 104. Each base station in base station 102 can provide communication coverage for a corresponding geographic coverage area 110. Overlapping geographic coverage areas 110 may exist. For example, small cell 102' may have a coverage area 110' that overlaps with the coverage areas 110 of one or more macro base stations 102. A network that includes both small cells and macro cells can be referred to as a heterogeneous network. The heterogeneous network may also include evolved home node B (eNB) (HeNB), which can provide services to restricted groups referred to as closed subscriber groups (CSG). The communication link 120 between base station 102 and UE 104 may include uplink (UL) (also known as reverse link) transmission from UE 104 to base station 102 and / or downlink (DL) (also known as forward link) transmission from base station 102 to UE 104. The communication link 120 may use multiple-input multiple-output (MIMO) antenna technologies, including spatial multiplexing, beamforming, and / or transmit diversity. The communication link may use one or more carriers. For the total maximum amount used for sending in each direction, up to Yx MHz ( x For each carrier allocated in carrier aggregation (of component carriers), base station 102 / UE 104 can use up to [number] carriers. Y A spectrum with a bandwidth of MHz (e.g., 5MHz, 10MHz, 15MHz, 20MHz, 100MHz, 400MHz, etc.). Carriers may be adjacent to each other or may not be adjacent to each other. Carrier allocation may be asymmetric with respect to DL and UL (e.g., more or fewer carriers may be allocated to DL compared to UL). Component carriers may include primary component carriers and one or more secondary component carriers. The primary component carrier may be referred to as the primary cell (PCell) and the secondary component carrier may be referred to as the secondary cell (SCell).

[0041] Some UEs 104 can communicate with each other using device-to-device (D2D) communication link 158. D2D communication link 158 can use DL / UL WWAN spectrum. D2D communication link 158 can use one or more sidelink channels, such as Physical Sidelink Broadcast Channel (PSBCH), Physical Sidelink Discovery Channel (PSDCH), Physical Sidelink Shared Channel (PSSCH), and Physical Sidelink Control Channel (PSCCH). D2D communication can be achieved through a variety of wireless D2D communication systems, such as, for example, WiMedia, Bluetooth, ZigBee, Wi-Fi based on the IEEE 802.11 standard, LTE, or NR.

[0042] The wireless communication system may also include a Wi-Fi access point (AP) 150 that communicates with a Wi-Fi station (STA) 152 via a communication link 154 in, for example, unlicensed spectrum at 5 GHz. When communicating in unlicensed spectrum, the STA 152 / AP 150 may perform a free channel assessment (CCA) to determine whether the channel is available before communication.

[0043] Small cell 102' can operate in licensed and / or unlicensed spectrum. When operating in unlicensed spectrum, small cell 102' can employ NR and use the same unlicensed spectrum (e.g., 5 GHz, etc.) as the Wi-Fi AP 150. Small cell 102' employing NR in unlicensed spectrum can improve the coverage of the access network and / or increase the capacity of the access network.

[0044] The electromagnetic spectrum is typically subdivided into various categories, bands, channels, etc., based on frequency / wavelength. In 5G NR, two initial operating bands have been designated as frequency ranges FR1 (410MHz–7.125GHz) and FR2 (24.25GHz–52.6GHz). The frequencies between FR1 and FR2 are generally referred to as mid-band frequencies. Although a portion of FR1 is greater than 6GHz, in various documents and articles, FR1 is often (interchangeably) referred to as the “sub-6GHz” band. Similar naming issues sometimes occur with FR2, which is often (interchangeably) referred to as the “millimeter wave” band in documents and articles, although this is different from the extremely high frequency (EHF) band (30GHz to 300GHz) designated as a “millimeter wave” band by the International Telecommunication Union (ITU).

[0045] In light of the above, unless otherwise specifically stated, it should be understood that when the term "below 6 GHz" is used herein, it can broadly refer to frequencies that are less than 6 GHz, within FR1, or may include intermediate frequency band frequencies. Furthermore, unless otherwise specifically stated, it should be understood that when the term "millimeter wave" is used herein, it can broadly refer to frequencies that may include intermediate frequency band frequencies, within FR2, or within the EHF band.

[0046] Base station 102 (whether a small cell 102' or a large cell (e.g., a macro base station)) may include and / or be referred to as an eNB, gNodeB (gNB), or another type of base station. Some base stations (such as gNB 180) may operate in conventional sub-6 GHz spectrum, in millimeter wave frequencies, and / or near-millimeter wave frequencies to communicate with UE 104. When gNB 180 operates in millimeter wave or near-millimeter wave frequencies, gNB 180 may be referred to as a millimeter wave base station. Millimeter wave base station 180 may utilize beamforming 182 with UE 104 to compensate for path loss and short range. Base station 180 and UE 104 may each include multiple antennas (such as antenna elements, antenna panels, and / or antenna arrays) to facilitate beamforming.

[0047] Base station 180 may transmit beamformed signals to UE 104 in one or more transmit directions 182'. UE 104 may receive beamformed signals from base station 180 in one or more receive directions 182''. UE 104 may also transmit beamformed signals to base station 180 in one or more transmit directions. Base station 180 may receive beamformed signals from UE 104 in one or more receive directions. Base station 180 / UE 104 may perform beam training to determine the optimal receive and transmit directions for each of base station 180 / UE 104. The transmit and receive directions of base station 180 may be the same or different. The transmit and receive directions of UE 104 may be the same or different.

[0048] EPC 160 may include Mobility Management Entity (MME) 162, other MMEs 164, Serving Gateway 166, MBMS Gateway 168, Broadcast Multicast Service Center (BM-SC) 170, and Packet Data Network (PDN) Gateway 172. MME 162 can communicate with Home Subscriber Server (HSS) 174. MME 162 is the control node that handles signaling between UE 104 and EPC 160. Generally, MME 162 provides bearer and connection management. All user Internet Protocol (IP) packets are delivered through Serving Gateway 166, which is itself connected to PDN Gateway 172. PDN Gateway 172 provides UE IP address allocation and other functions. PDN Gateway 172 and BM-SC 170 are connected to IP Service 176. IP Service 176 may include the Internet, intranet, IP Multimedia Subsystem (IMS), PS streaming service, and / or other IP services. BM-SC 170 provides functions for MBMS user service dispatch and delivery. The BM-SC 170 can serve as an entry point for content provider MBMS transmission, authorizing and initiating MBMS bearer services within a Public Land Mobile Network (PLMN), and scheduling MBMS transmissions. The MBMS gateway 168 can distribute MBMS services to base station 102 within a Multicast-Broadcast Single Frequency Network (MBSFN) area belonging to a broadcast-specific service, and is responsible for session management (start / stop) and collecting eMBMS-related billing information.

[0049] The core network 190 may include Access and Mobility Management Functions (AMF) 192, other AMFs 193, Session Management Functions (SMF) 194, and User Plane Functions (UPF) 195. AMF 192 can communicate with Unified Data Management (UDM) 196. AMF 192 is the control node that handles signaling between UE 104 and the core network 190. Generally, AMF 192 provides Quality of Service (QoS) streaming and session management. All user IP packets are delivered via UPF 195. UPF 195 provides UE IP address allocation and other functions. UPF 195 connects to IP services 197. IP services 197 may include the Internet, intranet, IMS, packet switching (PS) streaming services, and / or other IP services.

[0050] Base stations may include and / or be referred to as gNB, Node B, eNB, access point, base transceiver, radio base station, radio transceiver, transceiver function, Basic Service Set (BSS), Extended Service Set (ESS), Transmitter Receiver Point (TRP), or some other suitable terminology. Base station 102 provides access to EPC 160 or core network 190 for UE 104. Examples of UE 104 include cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, personal digital assistants (PDAs), satellite radios, GPS devices, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, tablet computers, smart devices, wearable devices, vehicles, electricity meters, air pumps, large or small kitchen appliances, healthcare devices, implants, sensors / actuators, displays, or any other similarly functional devices. Some UEs in UE 104 may be referred to as IoT devices (e.g., parking timers, air pumps, toasters, vehicles, heart monitors, etc.). UE 104 may also be referred to as a station, mobile station, subscriber station, mobile unit, subscriber unit, radio unit, remote unit, mobile device, radio device, wireless communication device, remote device, mobile subscriber station, access terminal, mobile terminal, radio terminal, remote terminal, mobile phone, user agent, mobile client, client, or some other suitable term. A radio node may include a UE, a base station, or a network entity of that base station.

[0051] Wireless devices in access network 100 may support polar decoding techniques for wireless communication. Transmitting devices (e.g., UE 104, base station 102 / 180, and / or another network entity) may perform polar decoding to encode information bits (e.g., data bits, control bits, etc.). Polar decoding may include using polar code length-based techniques. N Multiple component channels () W The transmitting device may use multiple interleavers to interleave coded bits and map the interleaved coded bits to one or more bit levels. Interleaving of coded bits may be based on multiple bit levels.

[0052] See you again Figure 1UE 104 may include an interleaver module 198. As described in more detail elsewhere herein, the interleaver module 198 may be configured to encode a plurality of bits to produce coded bits; perform interleaving: (i) interleaving a first subset of one or more coded bits via a first interleaving scheme, and (ii) interleaving a second subset of one or more coded bits via a second interleaving scheme, wherein one or more coded bits in the second subset are different from one or more coded bits in the first subset; perform mapping: (i) mapping the interleaved first subset to a first bit level, and (ii) mapping the interleaved second subset to a second bit level; and output the interleaved first subset and the interleaved second subset via the first bit level and the second bit level of one or more modulation symbols for transmission. Additionally or alternatively, the interleaver module 198 may perform one or more other operations described herein.

[0053] Base station 102 / 180 may include interleaver module 199. As described in more detail elsewhere herein, interleaver module 199 may be configured to: obtain a first subset of one or more coded bits and a second subset of one or more coded bits via one or more symbols, wherein one or more coded bits in the second subset are different from one or more coded bits in the first subset, wherein the first subset of one or more coded bits is interleaved via a first interleaving scheme, and wherein the second subset of one or more coded bits is interleaved via a second interleaving scheme; deinterleave the first subset of one or more coded bits via the first interleaving scheme and deinterleave the second subset of one or more coded bits via the second interleaving scheme; and decode the deinterleaved first subset of one or more coded bits and the deinterleaved second subset of one or more coded bits. Additionally or alternatively, interleaver module 199 may perform one or more other operations described herein.

[0054] Figure 2A Figure 200 illustrates an example of the first subframe within a 5G NR frame structure. Figure 2B Figure 230 illustrates an example of a DL channel within a 5G NR subframe. Figure 2C Figure 250 is an example of a second subframe within a 5G NR frame structure. Figure 2D Figure 280 illustrates an example of a UL channel within a 5G NR subframe. The 5G NR frame structure can be Frequency Division Duplex (FDD) (where subframes within a specific set of subcarriers (carrier system bandwidth) are dedicated to either DL or UL) or Time Division Duplex (TDD) (where subframes within a specific set of subcarriers (carrier system bandwidth) are dedicated to both DL and UL). In the process of... Figure 2A , Figure 2CIn the provided example, the 5G NR frame structure is assumed to be TDD, where subframe 4 is configured with slot format 28 (mostly DL), where D is DL, U is UL, and F is flexible and can be used between DL / UL, and subframe 3 is configured with slot format 34 (mostly UL). Although subframes 3 and 4 are shown as having slot formats 34 and 28 respectively, any particular subframe can be configured with any of the various available slot formats 0-61. Slot formats 0 and 1 are both DL and UL, respectively. Other slot formats 2-61 include a mixture of DL, UL, and flexible symbols. The UE is configured using the slot format via the received Slot Format Indicator (SFI) (dynamically configured via DL Control Information (DCI) or semi-statically / statically configured via Radio Resource Control (RRC) signaling). Note that the following description also applies to the 5G NR frame structure as TDD.

[0055] Other wireless communication technologies may have different frame structures and / or different channels. For example, a 10-millisecond (ms) frame may be divided into 10 equal-sized subframes (1ms). Each subframe may include one or more time slots. Subframes may also include micro-time slots, which may include 7, 4, or 2 symbols. Each time slot may include 7 or 14 symbols, depending on the time slot configuration. For time slot configuration 0, each time slot may include 14 symbols, and for time slot configuration 1, each time slot may include 7 symbols. Symbols on the DL may be Cyclic Prefix (CP) Orthogonal Frequency Division Multiplexing (OFDM) (CP-OFDM) symbols. Symbols on the UL may be CP-OFDM symbols (for high-throughput scenarios) or Discrete Fourier Transform (DFT) Extended OFDM (DFT-s-OFDM) symbols (also known as Single Carrier Frequency Division Multiple Access (SC-FDMA) symbols) (for power-constrained scenarios; limited to single-stream transmission). The number of time slots within a subframe is based on the time slot configuration and parameter set (numerology). For slot configuration 0, different parameter sets µ 0 to 4 allow for 1, 2, 4, 8, and 16 slots per subframe, respectively. For slot configuration 1, different parameter sets 0 to 2 allow for 2, 4, and 8 slots per subframe, respectively. Correspondingly, for slot configuration 0 and parameter set µ, there are 14 symbols per slot and 2 per subframe. µ Each time slot. Subcarrier spacing and symbol length / duration are functions of the parameter set. Subcarrier spacing can be equal to... kilohertz (kHz), where The parameter sets are 0 to 4. Therefore, the subcarrier spacing for parameter set µ=0 is 15kHz, and the subcarrier spacing for parameter set µ=4 is 240kHz. The symbol length / duration is negatively correlated with the subcarrier spacing. Figures 2A to 2DExamples are provided for slot configuration 0 with 14 symbols per slot and parameter set µ=2 with 4 slots per subframe. Slot duration is 0.25 ms, subcarrier spacing is 60 kHz, and symbol duration is approximately 16.67 μs. Within the frame set, there may be one or more distinct bandwidth portions (BWPs) of frequency division multiplexing (see [link to relevant documentation]). Figure 2B Each BWP can have a specific set of parameters.

[0056] A resource grid can be used to represent the frame structure. Each time slot consists of a resource block (RB) extending for 12 consecutive subcarriers (also known as a physical RB (PRB)). The resource grid is divided into multiple resource elements (REs). The number of bits carried by each RE depends on the modulation scheme.

[0057] like Figure 2A As illustrated, some of the REs carry reference (pilot) signals (RS) for the UE. The RS may include a demodulated RS (DM-RS) (indicated as R for a particular configuration). x (where 100x is the port number, but other DM-RS configurations are also possible) and the Channel State Information Reference Signal (CSI-RS) used for channel estimation at the UE. RS may also include Beam Measurement RS (BRS), Beam Refinement RS (BRRS), and Phase Tracking RS (PT-RS).

[0058] Figure 2BExamples of various DL channels within a subframe of a frame are illustrated. The Physical Downlink Control Channel (PDCCH) carries the DCI within one or more Control Channel Elements (CCEs), each CCE comprising nine RE Groups (REGs), each REG comprising four consecutive REs in an OFDM symbol. The PDCCH within a BWP can be referred to as a Control Resource Set (CORESET). Additional BWPs may be located at higher and / or lower frequencies in the channel bandwidth. The Primary Synchronization Signal (PSS) is located within symbol 2 of a specific subframe of the frame. The PSS is used by UE 104 to determine subframe / symbol timing and physical layer identification. The Secondary Synchronization Signal (SSS) is located within symbol 4 of a specific subframe of the frame. The SSS is used by the UE to determine the Physical Layer Cell Identifier Group Number and radio frame timing. Based on the Physical Layer Identifier and Physical Layer Cell Identifier Group Number, the UE can determine the Physical Cell Identifier (PCI). Based on the PCI, the UE can determine the location of the aforementioned DM-RS. The Physical Broadcast Channel (PBCH), carrying the Master Information Block (MIB), can be logically grouped with the PSS and SSS to form a Synchronization Signal (SS) / PBCH block (also known as an SS block (SSB)). The MIB provides the System Frame Number (SFN) and the number of Restricted Frames (RBs) in the system bandwidth. The Physical Downlink Shared Channel (PDSCH) carries user data, broadcast system information not transmitted via the PBCH (such as System Information Blocks (SIBs)), and paging messages.

[0059] like Figure 2C As illustrated, some REs in the REs carry DM-RS (indicated as R for one particular configuration, but other DM-RS configurations are possible) for channel estimation at the base station. The UE can transmit DM-RS for the Physical Uplink Control Channel (PUCCH) and DM-RS for the Physical Uplink Shared Channel (PUSCH). The PUSCH DM-RS can be transmitted in the first or first two symbols of the PUSCH. Depending on whether a short or long PUCCH is transmitted and depending on the specific PUCCH format used, the PUCCH DM-RS can be transmitted in different configurations. The UE can transmit a Sounding Reference Signal (SRS). The SRS can be transmitted in the last symbol of a subframe. The SRS can have a comb structure, and the UE can transmit the SRS on one of the comb teeth. The SRS can be used by the base station for channel quality estimation to enable frequency-dependent scheduling of the UL.

[0060] Figure 2DExamples of various UL channels within a subframe of a frame are illustrated. The PUCCH can be located as indicated in one configuration. The PUCCH carries uplink control information (UCI), such as scheduling requests, channel quality indicators (CQI), pre-decoding matrix indicators (PMI), rank indicators (RI), and hybrid automatic repeat request (HARQ) acknowledgment (ACK) / negative acknowledgment (NACK) feedback. The PUSCH carries data and may additionally be used to carry buffer status reports (BSR), power clearance reports (PHR), and / or UCI.

[0061] Figure 3 This is a block diagram illustrating communication between base stations 102 / 180 and UE 104 in the access network. In the DL, IP packets from EPC160 can be provided to the controller / processor 375. The controller / processor 375 implements Layer 3 and Layer 2 functionality. Layer 3 includes the Radio Resource Control (RRC) layer, and Layer 2 includes the Serving Data Adaptation Protocol (SDAP) layer, Packet Data Convergence Protocol (PDCP) layer, Radio Link Control (RLC) layer, and Media Access Control (MAC) layer. The controller / processor 375 provides RRC layer functionality associated with broadcasting system information (e.g., MIB, SIB), RRC connection control (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), inter-Radio Access Technology (RAT) mobility, and measurement configuration for UE measurement reporting; PDCP layer functionality associated with header compression / decompression, security (encryption, decryption, integrity protection, integrity verification), and handover support functions; RLC layer functionality associated with the delivery of upper-layer packet data units (PDUs), error correction via ARQ, concatenation, segmentation, and reassembly of RLC service data units (SDUs), resegmentation of RLC data PDUs, and reordering of RLC data PDUs; and MAC layer functionality associated with mapping between logical channels and transport channels, multiplexing of MAC SDUs onto transport blocks (TBs), demultiplexing of MAC SDUs from TBs, scheduling information reporting, error correction via HARQ, priority handling, and logical channel priority ordering.

[0062] Transmit (TX) processor 316 and receive (RX) processor 370 implement Layer 1 functionality associated with various signal processing functions. Layer 1 (which includes the physical (PHY) layer) may include error detection on the transport channel, forward error correction (FEC) decoding / decoding of the transport channel, interleaving, rate matching, mapping to the physical channel, modulation / demodulation of the physical channel, and MIMO antenna processing. TX processor 316 processes the mapping to the signal constellation based on various modulation schemes (e.g., binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), M-order phase shift keying (M-PSK), M-order quadrature amplitude modulation (M-QAM)). The decoded and modulated symbols can then be divided into parallel streams. Each stream can then be mapped to OFDM subcarriers, multiplexed with a reference signal (e.g., a pilot) in the time and / or frequency domains, and then combined using inverse fast Fourier transform (IFFT) to produce a physical channel carrying a stream of time-domain OFDM symbols. The OFDM stream undergoes spatial pre-decoding to generate multiple spatial streams. A channel estimate from channel estimator 374 can be used to determine the decoding and modulation scheme, as well as for spatial processing. This channel estimate can be derived from a reference signal transmitted by UE 104 and / or channel condition feedback. Each spatial stream can then be provided to a different antenna 320 via a separate transmitter 318TX. Each transmitter 318TX can modulate an RF carrier with the corresponding spatial stream for transmission.

[0063] At UE 104, each receiver 354RX receives signals via its corresponding antenna 352. Each receiver 354RX recovers the information modulated onto the RF carrier and provides that information to the receive (RX) processor 356. The TX processor 368 and RX processor 356 implement Layer 1 functionality associated with various signal processing functions. The RX processor 356 can perform spatial processing on the information to recover any spatial stream destined for UE 104. If multiple spatial streams are destined for UE 104, the RX processor 356 can combine them into a single OFDM symbol stream. The RX processor 356 then uses a Fast Fourier Transform (FFT) to transform the OFDM symbol stream from the time domain to the frequency domain. The frequency domain signal includes a separate OFDM symbol stream for each subcarrier of the OFDM signal. The symbols on each subcarrier, along with the reference signal, are recovered and demodulated by determining the signal constellation points most likely to be transmitted by base stations 102 / 180. These soft decisions can be based on a channel estimate calculated by the channel estimator 358. These soft decisions are then decoded and deinterleaved to recover the original data and control signals transmitted by base stations 102 / 180 on the physical channel. The data and control signals are then provided to controller / processor 359, which implements layer 3 and layer 2 functionality.

[0064] The controller / processor 359 may be associated with a memory 360 that stores program code and data. The memory 360 may be referred to as a computer-readable medium. In the UL, the controller / processor 359 provides demultiplexing, packet reassembly, decryption, header decompression, and control signal processing between the transport and logical channels to recover IP packets from the EPC 160. The controller / processor 359 is also responsible for error detection using ACK and / or NACK protocols to support HARQ operation.

[0065] Similar to the functionality described in conjunction with DL transmissions performed by base stations 102 / 180, controller / processor 359 provides RRC layer functionality associated with system information (e.g., MIB, SIB) acquisition, RRC connectivity, and measurement reporting; PDCP layer functionality associated with header compression / decompression and security (encryption, decryption, integrity protection, integrity verification); RLC layer functionality associated with upper-layer PDU delivery, error correction via ARQ, concatenation, segmentation, and reassembly of RLC SDUs, resegmentation of RLC data PDUs, and reordering of RLC data PDUs; and MAC layer functionality associated with mapping between logical channels and transport channels, multiplexing of MAC SDUs onto TBs, demultiplexing of MAC SDUs from TBs, scheduling information reporting, error correction via HARQ, priority handling, and logical channel priority ordering.

[0066] The channel estimate derived by the channel estimator 358 from the reference signal or feedback transmitted by the base station 102 / 180 can be used by the TX processor 368 to select an appropriate decoding and modulation scheme, and to facilitate spatial processing. The spatial stream generated by the TX processor 368 can be provided to different antennas 352 via individual transmitters 354TX. Each transmitter 354TX can use the corresponding spatial stream to modulate an RF carrier for transmission.

[0067] UL transmission is processed at base station 102 / 180 in a manner similar to that described in conjunction with the receiver function at UE 104. Each receiver 318RX receives the signal via its corresponding antenna 320. Each receiver 318RX recovers the information modulated onto the RF carrier and provides that information to the RX processor 370.

[0068] The controller / processor 375 may be associated with a memory 376 that stores program code and data. The memory 376 may be referred to as a computer-readable medium. In the UL, the controller / processor 375 provides demultiplexing, packet reassembly, decryption, header decompression, and control signal processing between the transport and logical channels to recover IP packets from the UE 104. IP packets from the controller / processor 375 may be provided to the EPC 160. The controller / processor 375 is also responsible for error detection using ACK and / or NACK protocols to support HARQ operation.

[0069] At least one of the TX processor 368, RX processor 356, and controller / processor 359 can be configured to interact with Figure 1 The interleaver module 198 performs various aspects in combination.

[0070] At least one of the TX processor 316, RX processor 370, and controller / processor 375 can be configured to interact with Figure 1 The interleaver module 199 performs various aspects in combination.

[0071] Figure 4 This is a block diagram illustrating an example decomposed base station 400 architecture. The decomposed base station 400 architecture may include one or more CUs 410, which may communicate directly with the core network 420 via a backhaul link, or indirectly with the core network 420 via one or more decomposed base station units, such as near real-time (RT) RICs 425 via E2 links, or non-RT RICs 415 associated with a Service Management and Orchestration (SMO) framework 405, or both. CUs 410 may communicate with one or more DUs 430 via corresponding midhaul links (such as F1 interfaces). DUs 430 may communicate with one or more RUs 440 via corresponding fronthaul links. RUs 440 may communicate with corresponding UEs 104 via one or more radio frequency (RF) access links. In some implementations, UE 104 may be served simultaneously by multiple RUs 440. As used herein, network entities may correspond to base stations or decomposed aspects of base stations (e.g., CU / DU / RU, etc.).

[0072] Each of the units, namely CU 410, DU 430, RU 440, and near-RT RIC 425, non-RT RIC 415, and SMO frame 405, may include or be coupled to one or more interfaces configured to receive or transmit signals, data, or information (collectively, signals) via wired or wireless transmission media. Each unit in the units, or an associated processor or controller providing instructions to the communication interfaces of these units, may be configured to communicate with one or more other units via transmission media. For example, these units may include wired interfaces configured to receive signals or transmit signals to one or more other units via wired transmission media. Additionally, these units may include wireless interfaces that may include receivers, transmitters, or transceivers (such as radio frequency (RF) transceivers) configured to receive signals or transmit signals to one or more other units, or both, via wireless transmission media.

[0073] In some respects, the CU 410 can host higher-level control functions. These control functions may include Radio Resource Control (RRC), Packet Data Convergence Protocol (PDCP), Serving Data Adaptation Protocol (SDAP), etc. Each control function can be implemented using an interface configured to signal to other control functions hosted by the CU 410. The CU 410 can be configured to handle user plane functionality (i.e., Central Unit-User Plane (CU-UP)), control plane functionality (i.e., Central Unit-Control Plane (CU-CP)), or a combination thereof. In some implementations, the CU 410 can be logically divided into one or more CU-UP units and one or more CU-CP units. When implemented in an O-RAN configuration, the CU-UP units can communicate bidirectionally with the CU-CP units via an interface such as an E1 interface. The CU 410 can be implemented to communicate with the DU 430 for network control and signaling, as needed.

[0074] DU 430 may correspond to a logic unit that includes one or more base station functions for controlling the operation of one or more RU 440s. In some aspects, DU 430 may at least partially host one or more of the Radio Link Control (RLC) layer, Medium Access Control (MAC) layer, and one or more high physical (PHY) layers (such as modules for forward error correction (FEC) encoding and decoding, scrambling, modulation and demodulation, etc.) according to functional splits (such as those defined by the 3rd Generation Partnership Project (3GPP). In some aspects, DU 430 may further host one or more low PHY layers. Each layer (or module) may be implemented using an interface configured to communicate signals with other layers (and modules) hosted by DU 430 or with control functions hosted by CU 410.

[0075] Lower-layer functionality can be implemented by one or more RU 440s. In some deployments, an RU440 controlled by a DU 430 may correspond to a logical node that hosts RF processing functions or low-PHY layer functions (such as performing Fast Fourier Transform (FFT), Inverse FFT (iFFT), digital beamforming, or Physical Random Access Channel (PRACH) extraction and filtering, or both, based at least in part on functional decomposition (such as lower-layer functional decomposition). In such architectures, the RU 440 may be implemented to handle over-the-air (OTA) communications with one or more UE 104s. In some specific implementations, the real-time and non-real-time aspects of control plane and user plane communications with the RU 440 may be controlled by the corresponding DU 430. In some scenarios, this configuration allows the DU430 and CU 410 to be implemented in cloud-based RAN architectures such as Virtual RAN (vRAN) architectures.

[0076] SMO framework 405 can be configured to support RAN deployment and provisioning of both non-virtualized and virtualized network elements. For non-virtualized network elements, SMO framework 405 can be configured to support the deployment of dedicated physical resources for RAN coverage requirements, which can be managed via operation and maintenance interfaces such as the O1 interface. For virtualized network elements, SMO framework 405 can be configured to interact with cloud computing platforms such as Open Cloud (O-cloud) 490 to perform network element lifecycle management (such as instantiating virtualized network elements) via cloud computing platform interfaces such as the O2 interface. Such virtualized network elements may include, but are not limited to, CU 410, DU 430, RU 440, and near-RT RIC 425. In some implementations, SMO framework 405 can communicate with the hardware aspects of the 4G RAN (such as Open eNB (O-eNB) 411) via the O1 interface. Additionally, in some implementations, SMO framework 405 can communicate directly with one or more RU 440s via the O1 interface. SMO framework 405 may also include a non-RT RIC 415 configured to support the functionality of SMO framework 405.

[0077] The non-RT RIC 415 can be configured to include logical functions that enable non-real-time control and optimization of RAN elements and resources, including artificial intelligence / machine learning (AI / ML) workflows for model training and updates, or policy-based guidance for applications / features in the near-RT RIC 425. The non-RT RIC 415 can be coupled to or communicate with the near-RT RIC 425, such as via an A1 interface. The near-RT RIC 425 can be configured to include logical functions that enable near real-time control and optimization of RAN elements and resources via data collection and actions on interfaces connecting one or more CU 410s, one or more DU 430s, or both, and O-eNBs to the near-RT RIC 425, such as via an E2 interface.

[0078] In some implementations, to generate AI / ML models to be deployed in the near-RT RIC 425, the non-RT RIC 415 may receive parameters or external enrichment information from an external server. This information can be utilized by the near-RT RIC 425 and may be received from non-network data sources or network functions at the SMO framework 405 or the non-RT RIC 415. In some examples, the non-RT RIC 415 or near-RT RIC 425 may be configured to tune RAN behavior or performance. For example, the non-RT RIC 415 may monitor long-term trends and patterns in performance and employ AI / ML models to perform corrective actions via the SMO framework 405 (e.g., via O1 reconfiguration) or via the creation of RAN management policies (e.g., A1 policies).

[0079] Figure 5 This is a block diagram illustrating an example of a device 500 supporting polar codes and modulation mapping used in wireless communication. In some cases, device 500 may represent a transmitting device (such as a reference device). Figure 1 and Figure 3 The described aspects of the technology performed by the UE 104 or base station 102 / 180. In some cases, device 500 may be a transmitter, transceiver, or a sub-component of a transmitter or transceiver. Device 500 may include a polarization decoder 505, an interleaver 510, a modulation mapper 515, and an analog front-end (AFE) 520. Although device 500 is shown as having one polarization decoder 505, it should be understood that device 500 may include more than one polarization decoder 505 (e.g., a set of polarization decoders 505).

[0080] As background, the basic principle of polarimetric decoding can be understood by starting with a binary input memoryless channel W: X → Y. The capacity of channel W can be given as C = I(X; Y), where I represents the mutual information between X and Y. In the example of binary input 0 ≤ C ≤ 1, where C is the capacity of channel W as indicated above, the following transformation can begin with N replicas of channel W. Using a one-to-one mapping from U to X, where G... N×N {0, 1} N →{0, 1} N It can create efficient channel W vec , where X N =U N ·G N×N And U N A vector representing the bits to be encoded.

[0081] Polarization decoding can be given as C(W) vec )=I(U N ; Y N )=Σ i=1 N I(U i ; Y N |U i-1 )=Σ i=1 N C(W i ) = N·C(W), where the channel W i :U i →(Y N U i-1 For some values ​​of the matrix, G N×N C(W3) becomes polarized. That is, the linear one-to-one transformation G... N×NTransform N channels W of equal capacity into N channels W of unequal capacity. i As N approaches infinity, C(W) i It degenerates into a bimodal distribution around 0 and 1 of a binary input (i.e., polarization).

[0082] For example, considering the case where N=2, we have: In this example, W is a binary erase channel (BEC) with an erase probability of “ε”. It can be deduced that U1 = X1⊕X2 = Y1⊕Y2 and U2 = X2 = X1⊕U1. For channel W1: U1 → Y N The erasure probability can be ε - =1-(1-ε) 2 =2ε-ε 2 For channel W2: U1→Y N , (Y N The erasure probability can be ε (U1). + =ε 2 (representing W) + =W2 and W - =W1). This indicates that channel W2 can be considered a better performing channel than channel W1. This operation can be performed recursively, thus generating more polarization on N. It should be understood that the example BEC erasure probability is only for illustrative purposes. The described technique can also be applied to other channel types (e.g., additive white Gaussian noise (AWGN) channels, fading channels, etc.).

[0083] Turning now to example device 500, polar decoder 505 performs polar decoding to encode multiple bits, as shown in the uncoded bits U1-U4. The polar decoding can have a polar code length N, which defines the number of component channels (also called bit channels) used for polar decoding. For ease of explanation and as a non-limiting example only, the polar code length N of device 500 is four, corresponding to four component channels and a set of four bits encoded in parallel. Each component channel can have an associated reliability ε, which can correspond to the channel's erase probability.

[0084] In example device 500, polar decoder 505 performs polar decoding on bits U1-U4 and outputs coded bits X1-X4. Polar decoder 505 can create polarizations for the coded bits, i.e., with higher and lower reliability. Therefore, each component channel can have a different reliability ε. For the component channels corresponding to coded bits X1 and X2, the reliability is exemplified as ε. + Furthermore, for the component channels corresponding to coded bits X3 and X4, the reliability is exemplified as ε. + Component channel reliability ε +(For example, high erase probability) means a low probability that the encoded bits will be successfully decoded after being sent to the receiver via a physical channel, and the reliability ε - (For example, low erase probability) represents a high probability that the encoded bits will be successfully decoded after being transmitted to the receiver via the physical channel. In some respects, the component channel is viewed from the perspective of the interleaver / modulation map. That is, for example, unequal reliability ε can be assumed. + and ε - It comes from the modulator. Therefore, the modulator can, to some extent, act as a polarizer.

[0085] The interleaver 510 relies on the asymmetry in polarization decoding to determine how to interleave with different reliability (e.g., ε) - and ε + The associated coded bits are connected to X1-X4. In other words, the interleaver 510 is based on the matrix G of the polar code structure. N×N The asymmetry will be reordered by the bits output from the polarization decoder 505. In some cases, the output of the interleaver 510 (e.g., Z1-Z4) may differ from the input of the coded bits.

[0086] The order of the coded bits output by interleaver 510 affects how modulation mapper 515 maps these bits to modulation symbols. For example, in a 16th-order quadrature amplitude modulation (16-QAM) scheme, the first two bits input to modulation mapper 515 control the first dimension of the modulation symbol (e.g., the selected quadrant in the modulation constellation or its positioning along the first axis of the constellation), and the last two bits input to modulation mapper 515 control the second dimension of the modulation symbol (e.g., its positioning within the selected quadrant or its positioning along the second axis of the constellation). Interleaver 510 can feed coded bits (e.g., by polarization decoder 505) and interleaved bits to modulation mapper 515 such that bits of similar polarization affect the same dimension of the modulation mapping performed by modulation mapper 515. For example, with reliability ε + The encoded bits (e.g., X1 and X2) can control the selection of the object limit or the positioning along the first axis of the modulation constellation, and have reliability ε - The coded bits (e.g., X3 and X4) can control the selection of positioning within a selected quadrant or along the second axis of the modulation constellation.

[0087] Modulation mapper 515 maps interleaved coded bits to modulation symbols. The mapping scheme implemented by modulation mapper 515 maximizes polarization while maintaining the reliability of each component channel during modulation. Because the polarization of the coded bits is a result of the asymmetry in the matrix used to encode the bits, both the interleaving scheme and the modulation mapping scheme can be selected based on the asymmetry in the polar code construction. Modulation mapper 515 can select or use a mapping scheme based on the modulation scheme being used. In one example, modulation mapper 515 can use a natural binary mapping or a Gray mapping for a 16-QAM scheme. In another example, modulation mapper 515 can use a 2... 2M -QAM modulation schemes use Gray mapping or random mapping.

[0088] In some aspects, such as for quadrature phase shift keying (QPSK) modulation, an inverse Gray map can be used (e.g., a Gray map can make the modulated bits non-polarized). For 16-QAM, a Gray map can polarize the output of the log-likelihood ratio (LLR). As an example, the described techniques can increase polarization independently using natural binary maps in the in-phase (I) and quadrature (Q) dimensions. Two-dimensional (2-D) modulation maps (e.g., combined with I and Q) can be associated with more complex demappers, although 2-D modulation maps can further increase polarization.

[0089] In some respects, QPSK (anti-Gray mapping) and 16-QAM can work with regular polar codes derived from the following: .

[0090] For example, the first subset of the interleaved coded bits (e.g., The second subset interwoven with the coded bits (e.g., A bit can be mapped to different bit indices of one or more symbols according to a given bit-to-symbol mapping rule (e.g., Gray mapping). In this example, the first and second subsets can be sent via four symbols defined as follows: ,in f (...) is the bit-to-symbol mapping function. In the case of 16QAM modulation, the bit quadruple... It can be mapped to complex-valued modulation symbols according to the following formula. : here, , The bits corresponding to the first subset of interleaved coded bits, and , It is the bits of the second subset of interleaved bits from the encoded bits.

[0091] The described techniques are scalable to general modulation methods such as Phase Shift Keying (PSK), Amplitude Shift Keying (ASK), etc. In some aspects, improved performance can be achieved by combining multi-stage decoder receivers (through decoding and modulation). In some non-Gray mapping cases, single-trigger demodulation preceding the polarization decoder may be less desirable.

[0092] The AFE 520 can transmit interleaved coded bits as modulated according to the mapping. For example, the AFE 520 can transmit the interleaved coded bits via one or more antennas.

[0093] As discussed above, device 500 uses interleaver 510, which can be designed to improve polarization, thereby resulting in improved performance of wireless communication. In some examples, polarization can be maximized by using multiple interleavers based on the number of bit layers associated with a block of coded bits.

[0094] In some respects, for relatively high-order modulated polar codes, interleavers can be used to improve wireless communication by reducing bit error rates and increasing transmission efficiency in fading channels. For example, interleaving the polar-coded bits distributes the transmitted bits over time to achieve a desired bit error distribution, thereby combating the effects of fading channels. Interleavers can alter the arrangement of the signal bit stream without changing the information content. Therefore, interleavers can maximize the dispersion of consecutive error bits caused by bursts during transmission. In this way, the error correction and detection capabilities of the receiver can be improved. To further randomize the inter-symbol bit-level log-likelihood ratio (LLR) at the receiver, different interleavers can be used at different bit levels.

[0095] Figure 6 This is a block diagram illustrating another example of a device 600 supporting polar codes and modulation mapping used in wireless communication. In some cases, device 600 may represent a device transmitted by a transmitting device (such as a reference device). Figure 1 and Figure 3 The described aspects of the technology implemented by the UE 104 or base station 102 / 180. In some cases, device 600 may be a transmitter, transceiver, or a sub-component of a transmitter or transceiver. Device 600 may include a polarization decoder 605, multiple interleavers (e.g., a first interleaver 610a and a second interleaver 610a). n Interweaver 610 n These are collectively referred to as interleaver 610, modulation mapper 615, and AFE 620. Although device 600 is shown as having one polar decoder 605, it should be understood that device 600 may include more than one polar decoder 605 (e.g., a set of polar decoders 605).

[0096] Polar decoder 605 can perform polar decoding to encode multiple bits, shown as a block of uncoded bits U. For example, device 600 can generate data including blocks of uncoded bits for transmission to another wireless node. Polar decoder 605 can perform polar decoding on the block of bits U and output coded bits X.

[0097] In some respects, the coded bit X can be divided into coded bits. n A subset (e.g., such as) Figure 6 The first encoded subset X1 and the second coded subset X1 are illustrated. n Encoding subset X n Number of subsets () n The number of bits associated with the modulation scheme used by the modulation mapper 615 can be used as a basis. For example, the coded subset (X1-X...) n Each of the bits in the 4-ASK modulation scheme can be mapped to a different bit level of the QAM symbol. Therefore, two bit levels can produce two subsets of coded bits. The modulation mapper 615 can use any suitable modulation scheme, including phase shift keying (PSK), amplitude shift keying (ASK), etc. For example, the coded bits X can be divided into two subsets based on a 4-ASK modulation scheme with two bit levels, such that the two subsets of coded bits are mapped to two bit levels of the QAM symbol. Therefore, in this example, n Equals 2. In another example, the number of bit levels can be based on log2 of the modulation order. For example, QAM 256 can be used to carry 8 bit levels, but the two 8-bit levels from the I and Q branches are 16 ASK, so there are 4 different bit levels with different capacities. Therefore, in this example, n It equals four. It should be noted that in some examples, each subset of the encoded bits may be exclusive relative to all other subsets. For example, as... Figure 7 As illustrated, each subset of bits may not share any bits with another subset.

[0098] Figure 7 This is a block diagram illustrating an example technique for separating coded bits (X) in block 700. Initially, Figure 6The device 600 can generate blocks of uncoded bits (U) and input the uncoded bits into a polar decoder 605. For example, U can be a 10-bit data block, and the polar decoder 605 can transform U into a 16-bit block 700 of coded bits. Each bit of the block 700 includes an index 1-16 for identifying each block and its position within the block 700. The device 600 can then divide the block 700 of coded bits into two subsets 702a of bits: a first subset 704 and a second subset 706a. For illustrative purposes, the two subsets 702a of bits maintain the same indexes as the block 700. In some examples, the indexes of the second subset can be renumbered, as illustrated in another subset 702b. Here, the other subset 702b includes the same bits as the second subset 706a, but the indexes have been renumbered, as illustrated in a third subset 706b. It should be noted that any suitable indexing system can be used to index the block 700 of coded bits and the subsets.

[0099] refer to Figure 6 , block n A coded subset (X1-X) n Each of these can be input into the corresponding parallel interleaver 610a-610. n For example, in n When the value equals 2, the first subset (X1) can be input into the first interleaver 610a, and the second subset can be input into the second interleaver (e.g., 610). n Therefore, device 600 can interleave each bit level of the encoded bits individually. In some examples, each interleaver 610 may be defined by one or more of an interleaver pattern and / or a shift pattern. For example, an interleaver pattern may include a triangular interleaver, a rectangular interleaver, and any other suitable shape of interleaver.

[0100] The interleaver shift pattern may include a cyclic shift of one or more subsets of the coded bits input to each interleaver 610. For example, a first coded subset (X1) of bits may be input to the first interleaver 610a without a cyclic shift. Here, the first subset of coded bits may be input to the first interleaver 610a in the unmodified order, while the second subset (X... n The bits can be cyclically shifted and then fed into the second interleaver 610. n middle.

[0101] Figure 8 This is a block diagram illustrating an example of a pair of interleavers that receive a subset of coded bits and output an interleaved subset. While this example shows two interleavers using a triangular interleaver shape (e.g., first interleaver 806 and second interleaver 808), any other suitable interleaver shape can be used. Although Figure 8Two interleavers are illustrated, but it should be understood that device 600 may include more than two interleavers and may include more than two subsets of coded bits.

[0102] The polar decoder 605 can output twenty coded blocks and can divide the blocks into two subsets of coded bits (e.g., a first subset 802 and a second subset 804). Initially, each subset can be sorted such that the order of the bits is not the same as the order in which they are output from the polar decoder 605. For example, the first and second subsets can be indexed as 1-10. However, before being fed into the corresponding interleaver, the device 600 can shift one or more subsets of these subsets by one or more spaces. One or more subsets can be shifted by any suitable number (e.g., 0, 1, 2, 3, etc.). Figure 8 In the example, the first subset 802 is not shifted, but the second subset 804 is cyclically shifted by 1.

[0103] In some examples, the cyclic shifts may be consecutive for each additional subset of coded bits. For example, a third subset of coded bits (not shown) may be cyclically shifted by 2, a fourth subset of coded bits (not shown) may be cyclically shifted by 3, and so on. In another example, the second interleaver may be based on a cyclically shifted version of the first interleaver. That is, the bit order in the second subset 804 may be rearranged to match the order of the bits output from the first interleaver 806 (e.g., the first interleaved bit 810). In this example, the second subset 804 may be input into the second interleaver 808, where the bits are rearranged to [1, 2, 4, 7, 3, 5, 8, 6, 9, 10]. This arrangement may be used consecutively for any additional subset of coded bits.

[0104] As illustrated, subsets of coded bits can be input into their respective interleaver "row inputs" and output as "column outputs". That is, each interleaver performs interleaving of each subset of bits by filling the interleaver matrix row by row with the input bits and then outputting the matrix contents column by column. The first interleaver 806 can output a first interleaved bit subset 810 (e.g., Figure 6 Z1) and the output, and the second interleaver 808 can output a second interleaved bit subset 812 (e.g., Figure 6 Z n ).

[0105] Return to reference Figure 6 The interleaver 610 can output its corresponding interleaving bit subset (Z1 and Z2). n The modulation mapper 615 can use the interleaver output as input. The modulation mapper 615 can map the interleaved coded bits to one or more bit levels of the modulation symbol, and the AFE 620 can transmit the interleaved coded bits as modulated according to the mapping.

[0106] Figure 9 This is a flowchart 900 of a wireless communication method. This method can be performed by a wireless node (e.g., UE 104; base station 102; device 1002). At 902, the UE can optionally output an indication of one or more of an interleaving mode and a cyclic shift mode applied to a plurality of interleavers associated with a first interleaving scheme and a second interleaving scheme for transmission. For example, 902 can be performed by an output component 1040. Here, the wireless node can provide information to a receiving device relating to how the wireless node encodes and interleaves the data it will send to the receiving device. In some aspects, the cyclic shift mode is configured to define a cyclic shift of a first index order of one or more coded bits input to the second interleaving scheme relative to a second index order of the first subset of one or more coded bits. For example, the wireless node can divide a data block into subsets and encode and interleave each subset. Different modes and / or different indexing schemes can be used to interleave each subset. For example, if each subset has N Units digit (index 1-) N Then the first subset can be ordered as 1, 2, 3, ... N The order in which they are interwoven. However, the second subset can be interleaved by cyclically shifting the index bits by 1 (2, 3, ...). N 1) to interleave. In some examples, the third subset may be cyclically shifted by 1 relative to the second subset (3, ..., N 1, 2) are intertwined.

[0107] In some respects, the interleaving pattern is based on the shape of each of the first and second interleaving schemes. For example, the interleaving pattern could be a triangular pattern (e.g., Figure 8 (as illustrated in the example) or one of the rectangular patterns.

[0108] At position 904, the wireless node can encode multiple bits to produce encoded bits. For example, position 904 can be performed by encoding component 1042. Here, the wireless node can have a block of bits to be transmitted to the receiving device. The wireless node can encode the bits before transmission.

[0109] At position 906, the wireless node may optionally split the coded bits into a first subset and a second subset. n A subset, of which n This is the number of bit levels associated with the modulation scheme used to map the first and second interleaved subsets. For example, 906 can be performed by the splitting component 1044. Here, the wireless node can divide a bit block into multiple subsets, where the number of subsets is based on the bit levels associated with the modulation scheme used to map each subset to a corresponding symbol.

[0110] At 908, the wireless node can perform interleaving: (i) interleaving a first subset of one or more coded bits via a first interleaving scheme, and (ii) interleaving a second subset of one or more coded bits via a second interleaving scheme, wherein one or more coded bits in the second subset are different from one or more coded bits in the associated first subset. For example, 908 can be performed by interleaving component 1046. Here, the wireless node can interleave each subset of coded bits such that each subset is interleaved independently. In some examples, different interleaving schemes and / or cyclic shifts can be used to interleave each subset.

[0111] At 910, the wireless node can perform mapping: (i) mapping the first interleaved subset to a first bit level, and (ii) mapping the second interleaved subset to a second bit level. For example, 910 can be performed by mapping component 1048. Here, the wireless node can map each subset to a bit level of a symbol.

[0112] At 912, the wireless node can output a first interleaved subset and a second interleaved subset for transmission via the first and second levels of one or more modulation symbols. For example, 912 can be performed by output component 1040. Here, the wireless node can map each subset to one or more symbols for transmission.

[0113] In some respects, the first interleaving scheme is configured to interleave a first subset of one or more coded bits based on a first index order of one or more coded bits in the first subset, and the second interleaving scheme is configured to interleave a second subset of one or more coded bits based on a cyclic shift of a second index order of one or more coded bits in the second subset.

[0114] In some respects, cyclic shifting is based on shift patterns applied to multiple interleavers associated with the first and second interleaver schemes.

[0115] In some respects, the first subset of interleaving includes an index order of one or more coded bits, and the second subset of interleaving one or more coded bits also includes interleaving the second subset based on the index order of the first subset of interleaving.

[0116] In some respects, the cyclic shift mode is configured to define a cyclic shift of a first index order of a second subset of one or more coded bits input into a second interleaving scheme relative to a second index order of the first subset of one or more coded bits.

[0117] In some respects, the interleaving pattern is based on the shape of each of the first and second interleaving schemes.

[0118] In some respects, a first subset of one or more coded bits is interleaved in parallel with a second subset of one or more coded bits.

[0119] In some respects, multiple bits are encoded via polar coding.

[0120] Figure 10 Figure 1000 illustrates an example of a hardware implementation for device 1002. Device 1002 can be implemented as a UE, a network entity, or a base station. Device 1002 includes a cellular baseband processor 1004 (also referred to as a modem) coupled to a cellular RF transceiver 1022 and one or more Subscriber Identity Module (SIM) cards 1020, an application processor 1006 coupled to a Secure Digital Card (SD) card 1008 and a screen 1010, a Bluetooth module 1012, a Wireless Local Area Network (WLAN) module 1014, a Global Positioning System (GPS) module 1016, and a power supply 1018. The cellular baseband processor 1004 communicates with the UE 104 and / or BS 102 / 180 via the cellular RF transceiver 1022. The cellular baseband processor 1004 may include computer-readable media / memory. This computer-readable media / memory may be non-transitory. The cellular baseband processor 1004 is responsible for general processing, including executing software stored on the computer-readable media / memory. When executed by the cellular baseband processor 1004, the software causes the cellular baseband processor 1004 to perform the various functions described above. The computer-readable medium / memory can also be used to store data manipulated by the cellular baseband processor 1004 during software execution. The cellular baseband processor 1004 also includes a receiving component 1030, a communication manager 1032, and a transmitting component 1034. The communication manager 1032 includes one or more exemplary components. Components within the communication manager 1032 may be stored in a computer-readable medium / memory and / or configured as hardware within the cellular baseband processor 1004. The cellular baseband processor 1004 may be a component of the UE 104 and may include a memory 360 and / or at least one of a TX processor 368, an RX processor 356, and a controller / processor 359. In one configuration, the device 1002 may be a modem chip and include only the baseband processor 1004, and in another configuration, the device 1002 may be an entire wireless node and include the aforementioned additional modules of the device 1002. In various examples, device 1002 may be a chip, SoC, chipset, package, or device that may include: one or more modems (such as a Wi-Fi (IEEE 802.11) modem or a cellular modem such as a 3GPP 4G LTE or 5G compatible modem); one or more processors, processing blocks, or processing elements (collectively, “processors”); one or more radio components (collectively, “radio components”); and one or more memories or blocks of memory (collectively, “memory”).

[0121] Communication manager 1032 includes output component 1040 configured to: output an indication of one or more of the interleaving modes and cyclic shift modes applied to a plurality of interleavers associated with a first interleaving scheme and a second interleaving scheme for transmission; and output a first subset and a second subset of interleaved data for transmission via a first bit level and a second bit level of one or more modulation symbols; for example, as in combination Figure 9 As described in 902 and 912.

[0122] The communication manager 1032 also includes an encoding component 1042, which is configured to encode multiple bits to produce encoded bits, for example, as described in conjunction with 904.

[0123] Communication manager 1032 also includes a splitting component 1044 configured to split coded bits into a first subset and a second subset. n A subset, of which n It is the number of bit levels associated with the modulation scheme used to map the first and second interleaved subsets, for example, as described in conjunction with 906.

[0124] The communication manager 1032 also includes an interleaving component 1046 configured to perform interleaving: (i) interleaving a first subset of one or more coded bits via a first interleaving scheme, and (ii) interleaving a second subset of one or more coded bits via a second interleaving scheme, wherein one or more coded bits in the second subset are different from one or more coded bits in the first subset, for example, as described in conjunction with 908.

[0125] The communication manager 1032 also includes a mapping component 1048 configured to perform mappings: (i) mapping a first subset of the interleaved data to a first bit level, and (ii) mapping a second subset of the interleaved data to a second bit level, for example, as described in conjunction with 910.

[0126] The apparatus may include execution Figure 9 The additional components of each box in the algorithm's box in the aforementioned flowchart. Therefore, Figure 9 Each box in the diagram can be executed by a component, and the apparatus can include one or more of those components. These components can be one or more hardware components specifically configured to perform the stated process / algorithm, implemented by a processor configured to perform the stated process / algorithm, stored in a computer-readable medium for implementation by a processor, or some combination thereof.

[0127] In one configuration, device 1002 (and specifically cellular baseband processor 1004) includes: means for outputting indications of one or more of an interleaving mode and a cyclic shift mode applied to a plurality of interleavers associated with a first interleaving scheme and a second interleaving scheme for transmission; means for encoding a plurality of bits to produce coded bits; and means for splitting the coded bits into a subset comprising a first subset and a second subset. n A subset of components, of which n It is the number of bit levels associated with the modulation scheme used to map the first interleaved subset and the second interleaved subset; the components for interleaving: (i) interleaving a first subset of one or more coded bits via a first interleaving scheme, and (ii) interleaving a second subset of one or more coded bits via a second interleaving scheme, wherein one or more coded bits in the second subset are different from one or more coded bits in the first subset; the components for mapping: (i) mapping the first interleaved subset to a first bit level, and (ii) mapping the second interleaved subset to a second bit level; and the components for outputting the first interleaved subset and the second interleaved subset via the first bit level and the second bit level of one or more modulation symbols for transmission.

[0128] The aforementioned components may be one or more of the aforementioned components of the device 1002 configured to perform the functions described therein. As described above, the device 1002 may include a TX processor 368, an RX processor 356, and a controller / processor 359. Therefore, in one configuration, the aforementioned components may be the TX processor 368, the RX processor 356, and the controller / processor 359 configured to perform the functions described therein.

[0129] The components for receiving or obtaining may include Figure 3 The receiver (such as RX processor 370) and / or antenna 320 of base station 102 / 180 illustrated herein, or the RX processor 356 and / or antenna 352 of UE 104. Components for transmitting or for output may include... Figure 3 The transmitter (such as TX processor 316) or antenna 320 of the base station 102 / 180 illustrated, or the TX processor 368 or antenna 352 of the UE 104. Components for encoding, demultiplexing, interleaving, and mapping may include a processing system that may include one or more processors (such as controllers / processors 359 / 375), memory 360 / 376, and / or Figure 3 The UE 104 and any other suitable hardware components of the base station 102 / 180 illustrated herein.

[0130] In some cases, a device may have an interface (output component) for outputting frames for transmission, rather than actually transmitting the frames. For example, a processor may output frames to a radio frequency (RF) front end for transmission via a bus interface. Similarly, a device may have an interface (acquisition component) for receiving frames from another device, rather than actually receiving the frames. For example, a processor may acquire (or receive) frames from an RF front end for receiving via a bus interface.

[0131] Figure 11 This is a flowchart 1100 of a wireless communication method. This method can be performed by a wireless node (e.g., UE 104; base station 102 / 180; device 1202). At 1102, the wireless node may optionally obtain an indication of one or more of the interleaving modes and cyclic shift modes applied to a plurality of interleavers associated with a first interleaving scheme and a second interleaving scheme. For example, 1102 may be performed by an obtaining component 1240. Here, the wireless node may receive from a transmitting device an indication of the interleaver (e.g., interleaving mode, cyclic shift, etc.) that the transmitting device will use to transmit data to the wireless node.

[0132] At 1104, the wireless node can obtain a first subset of one or more coded bits and a second subset of one or more coded bits via one or more symbols, wherein one or more coded bits in the second subset are different from one or more coded bits in the first subset, wherein the first subset of one or more coded bits is interleaved via a first interleaving scheme, and wherein the second subset of one or more coded bits is interleaved via a second interleaving scheme. For example, 1104 can be performed by obtaining component 1240. Here, the transmitting device can divide a data block into multiple subsets and interleave each subset individually using a unique interleaver mode, cyclic shifting of bits in the corresponding subset, etc. The transmitting device can transmit each subset, and the wireless node can receive these subsets (e.g., the wireless node determines the first and second subsets of coded bits by demodulating one or more modulation symbols it receives).

[0133] At 1106, the wireless node can deinterleave a first subset of one or more coded bits via a first interleaving scheme and a second subset of one or more coded bits via a second interleaving scheme. For example, 1106 can be performed by deinterleaving component 1242. Here, the wireless node can deinterleave each subset of data received from the transmitting device individually. In some examples, one or more subsets of multiple subsets can be interleaved based on another subset. For example, the first subset can be interleaved based on the bit index of the second subset. Therefore, the wireless node can deinterleave each subset based on the specific interleaving of each subset.

[0134] Finally, at 1108, the wireless node can decode a first subset of the deinterleaved data and a second subset of the deinterleaved data of one or more coded bits. For example, 1108 can be performed by decoding component 1244. Here, the wireless node can decode and process the deinterleaved subset of the data.

[0135] In some respects, the cyclic shift mode is configured to define a cyclic shift of a first index order of a second subset of one or more coded bits input into a second interleaving scheme relative to a second index order of the first subset of one or more coded bits.

[0136] In some respects, the interleaving pattern is based on the shape of each of the first and second interleaving schemes.

[0137] In some respects, the interlacing pattern is either the triangle pattern or the rectangle pattern.

[0138] In some respects, a first subset of one or more coded bits is deinterleaved in parallel with a second subset of one or more coded bits.

[0139] In some respects, each of the first subset of one or more coded bits and each of the second subset of one or more coded bits is decoded via polarization decoding.

[0140] Figure 12Figure 1200 illustrates an example of a hardware implementation for device 1202. Device 1202 may be implemented as a wireless node and includes a baseband unit 1204. Baseband unit 1204 can communicate with another wireless node device via a cellular RF transceiver. Baseband unit 1204 may include computer-readable medium / memory. Baseband unit 1204 is responsible for general processing, including executing software stored on the computer-readable medium / memory. The software, when executed by baseband unit 1204, causes baseband unit 1204 to perform the various functions described above. The computer-readable medium / memory can also be used to store data manipulated by baseband unit 1204 when executing the software. Baseband unit 1204 also includes a receiving component 1230, a communication manager 1232, and a transmitting component 1234. Communication manager 1232 includes one or more illustrated components. Components within communication manager 1232 may be stored in computer-readable medium / memory and / or configured as hardware within baseband unit 1204. The baseband unit 1204 may be a component of BS 102 / 180 and may include memory 376, and / or at least one of TX processor 316, RX processor 370, and controller / processor 375. In various examples, the device 1202 may be a chip, SoC, chipset, package, or device, which may include: one or more modems (such as a Wi-Fi (IEEE 802.11) modem or a cellular modem such as a 3GPP 4G LTE or 5G compatible modem); one or more processors, processing blocks, or processing elements (collectively, “processors”); one or more radio components (collectively, “radio components”); and one or more memories or blocks of memory (collectively, “memory”).

[0141] The communication manager 1232 includes an acquisition component 1240 configured to: acquire an indication of one or more of an interleaving mode and a cyclic shift mode applied to a plurality of interleavers associated with a first interleaving scheme and a second interleaving scheme; and acquire, via one or more symbols, a first subset of one or more coded bits and a second subset of one or more coded bits, wherein one or more coded bits in the second subset are different from one or more coded bits in the first subset, wherein the first subset of one or more coded bits is interleaved via the first interleaving scheme, and wherein the second subset of one or more coded bits is interleaved via the second interleaving scheme; for example, as in combination Figure 11 As described in 1102 and 1104.

[0142] The communication manager 1232 also includes a deinterleaving component 1242 configured to deinterleave a first subset of one or more coded bits via a first interleaving scheme and a second subset of one or more coded bits via a second interleaving scheme, for example, as described in conjunction with 1106.

[0143] The communication manager 1232 also includes a decoding component 1244 configured to decode a first subset of deinterleaved one or more coded bits and a second subset of deinterleaved one or more coded bits, for example, as described in conjunction with 1108.

[0144] The apparatus may include execution Figure 11 The aforementioned flowchart contains additional components for each box in the algorithm's boxes. Therefore, each box in the aforementioned flowchart can be executed by a component, and the apparatus may include one or more of these components. These components may be one or more hardware components specifically configured to execute the stated process / algorithm, implemented by a processor configured to execute the stated process / algorithm, stored in a computer-readable medium for implementation by a processor, or some combination thereof.

[0145] In one configuration, device 1202 (and specifically baseband unit 1204) includes: means for obtaining indications of one or more of an interleaving mode and a cyclic shift mode applied to a plurality of interleavers associated with a first interleaving scheme and a second interleaving scheme; means for obtaining a first subset of one or more coded bits and a second subset of one or more coded bits via one or more symbols, wherein one or more coded bits in the second subset are different from one or more coded bits in the first subset, wherein the first subset of one or more coded bits is interleaved via the first interleaving scheme, and wherein the second subset of one or more coded bits is interleaved via the second interleaving scheme; means for deinterleaving the first subset of one or more coded bits via the first interleaving scheme and deinterleaving the second subset of one or more coded bits via the second interleaving scheme; and means for decoding the deinterleaved first subset of one or more coded bits and the deinterleaved second subset of one or more coded bits.

[0146] The aforementioned components may be one or more of the aforementioned components of the device 1202 configured to perform the functions described therein. As described above, the device 1202 may include a TX processor 316, an RX processor 370, and a controller / processor 375. Therefore, in one configuration, the aforementioned components may be the TX processor 316, the RX processor 370, and the controller / processor 375 configured to perform the functions described therein.

[0147] The components for receiving or obtaining may include Figure 3The receiver (such as RX processor 370) and / or antenna 320 of the base station 102 / 180 illustrated herein, or the RX processor 356 and / or antenna 352 of the UE 104. Components for encoding and for deinterleaving may include a processing system, which may include one or more processors (such as controller / processor 359 / 375), memory 360 / 376, and / or Figure 3 The UE 104 and any other suitable hardware components of the base station 102 / 180 illustrated herein.

[0148] In some cases, a device may have an interface (output component) for outputting frames for transmission, rather than actually transmitting the frames. For example, a processor may output frames to a radio frequency (RF) front end for transmission via a bus interface. Similarly, a device may have an interface (acquisition component) for receiving frames from another device, rather than actually receiving the frames. For example, a processor may acquire (or receive) frames from an RF front end for receiving via a bus interface.

[0149] As used herein, a processor configured to perform or be operable to perform a plurality of actions, at least one processor, and / or one or more processors (alone or in combination) are intended to include at least two different processors capable of performing different subsets, overlapping subsets, or non-overlapping subsets of the plurality of actions, or a single processor capable of performing all of the plurality of actions. In a non-limiting example of a plurality of processors capable of performing different combinations of the plurality of actions, the description of a processor configured to perform or be operable to perform actions X, Y, and Z, at least one processor, and / or one or more processors may include at least a first processor configured to perform or be operable to perform a first subset of X, Y, and Z (e.g., performing X) and at least a second processor configured to perform or be operable to perform a second subset of X, Y, and Z (e.g., performing Y and Z). Alternatively, the first, second, and third processors may be configured to perform corresponding actions in actions X, Y, and Z, respectively. It should be understood that any combination of one or more processors may each be configured to perform or be operable to perform any one of the plurality of actions or any combination of the plurality of actions.

[0150] As used herein, a memory, at least one memory, and / or one or more memories (individually or in combination) configured to store or have thereon instructions executable by one or more processors for performing multiple actions are intended to include at least two different memories capable of storing different subsets, overlapping subsets, or non-overlapping subsets of instructions for performing the multiple actions, or a single memory capable of storing instructions for performing all of the multiple actions. In a non-limiting example of one or more memories (alone or in combination) capable of storing different subsets of instructions for performing different actions among the plurality of actions, the description of a memory configured or operable to store or thereon instructions for performing actions X, Y, and Z, at least one memory, and / or one or more memories may include at least a first memory configured or operable to store or thereon instructions for performing a first subset of X, Y, and Z (e.g., instructions for performing X), and at least a second memory configured or operable to store or thereon instructions for performing a second subset of X, Y, and Z (e.g., instructions for performing Y and Z). Alternatively, the first, second, and third memories may be configured to store or thereon a corresponding one of the first subset of instructions for performing X, the second subset of instructions for performing Y, and the third subset of instructions for performing Z. It should be understood that any combination of one or more memories may be configured or operable to store or have thereon any instruction or any combination of instructions executable by one or more processors to perform any of a plurality of actions or any combination of such actions. Furthermore, one or more processors may each be coupled to at least one of the one or more memories and configured or operable to execute instructions to perform the plurality of actions. For example, in the above non-limiting example of different subsets of instructions for performing actions X, Y, and Z, a first processor may be coupled to a first memory storing instructions for performing action X, at least a second processor may be coupled to at least a second memory storing instructions for performing actions Y and Z, and the first and second processors may combine to execute the respective subsets of instructions to complete the execution of actions X, Y, and Z. Alternatively, three processors may access one of three different memories, each storing instructions for performing action X, Y, or Z, and the three processors may combine to execute the respective subsets of instructions to complete the execution of actions X, Y, and Z. Alternatively, a single processor may execute instructions stored in a single memory or distributed across multiple memories to complete the execution of actions X, Y, and Z.

[0151] It should be understood that the specific order or hierarchy of the boxes in the disclosed process / flowcharts is merely an example of the exemplary method. It should be understood that the specific order or hierarchy of the boxes in the process / flowcharts may be rearranged based on design preferences. Furthermore, some boxes may be combined or omitted. The appended method claims present the elements of various boxes in a sample order, but this does not imply limitation to the given specific order or hierarchy.

[0152] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are to be consistent with the full scope of the language claims, wherein elements referred to in the singular are not intended to mean “one and only one,” but rather “one or more” unless specifically stated otherwise. Terms such as “if,” “when,” and “at the same time as” should be interpreted as “in the circumstances of,” rather than implying an immediate temporal relationship or reaction. That is, these phrases, such as “when,” do not imply an immediate action in response to or during the occurrence of an action, but simply suggest that if a condition is met, then the action will occur, without requiring a specific or immediate time limit for the occurrence of the action. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to other aspects. Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" include any combination of A, B, and / or C, and may include multiple A's, multiple B's, or multiple C's. Specifically, combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, wherein any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the various aspects described throughout this disclosure, which are now or hereafter known to those skilled in the art, are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is explicitly stated in the claims. Terms such as “module,” “mechanism,” “element,” and “device” cannot replace the term “component.” Therefore, no claim element will be interpreted as a functional component unless the element is explicitly stated using the phrase “component for…”.

[0153] The following embodiments are merely illustrative and may be combined with other implementations or aspects of the teachings described herein, but are not limited thereto.

[0154] Clause 1. A method for wireless communication at a wireless node, the method comprising: encoding a plurality of bits to generate coded bits; interleaving: (i) interleaving a first subset of one or more coded bits via a first interleaving scheme, and (ii) interleaving a second subset of one or more coded bits via a second interleaving scheme, wherein the one or more coded bits in the second subset are different from the one or more coded bits in the first subset; mapping the interleaved first subset and the interleaved second subset to one or more modulation symbols based on corresponding bit levels of each of the interleaved first subset and the interleaved second subset; and outputting the interleaved first subset and the interleaved second subset via the one or more modulation symbols for transmission.

[0155] Clause 2. The method according to Clause 1, the method further comprising: splitting the coded bits into n subsets comprising the first subset and the second subset, wherein n is the number of bit levels associated with a modulation scheme for mapping the interleaved first subset and the interleaved second subset.

[0156] Clause 3. The method according to any one of Clauses 1 and 2, wherein the first interleaving scheme is configured to interleave the first subset based on a first index order of the one or more coded bits in the first subset, and wherein the second interleaving scheme is configured to interleave the second subset based on a cyclic shift of a second index order of the one or more coded bits in the second subset.

[0157] Clause 4. The method according to Clause 3, wherein the cyclic shift is based on a shift pattern applied to a plurality of interleavers associated with the first interleaver scheme and the second interleaver scheme.

[0158] Clause 5. The method according to any one of Clauses 1 to 4, wherein the first subset of interleaving includes an index order of one or more coded bits in the first subset, and wherein the second subset of interleaving one or more coded bits further includes interleaving the second subset based on the index order of the first subset of interleaving.

[0159] Clause 6. The method according to any one of Clauses 1 to 5, the method further comprising: outputting an indication of an interleaving mode for transmission, wherein the interleaving mode is applied to an interleaver associated with the first interleaving scheme and the second interleaving scheme.

[0160] Clause 7. The method according to Clause 6, further comprising: configuring the second interleaving scheme using a cyclic shift pattern, the cyclic shift pattern defining a cyclic shift of a first index order of one or more coded bits input into the second interleaving scheme relative to a second index order of the first subset of one or more coded bits interleaved via the first interleaving scheme.

[0161] Clause 8. The method according to any one of Clauses 6 and 7, wherein the interlacing pattern is based on the shape of each of the first interlacing scheme and the second interlacing scheme.

[0162] Clause 9. The method according to any one of Clauses 6 to 8, wherein the interlacing pattern is one of a triangle pattern or a rectangle pattern.

[0163] Clause 10. The method according to any one of Clauses 1 to 9, wherein the first subset and the second subset are interleaved in parallel.

[0164] Clause 11. The method according to any one of Clauses 1 to 10, wherein the plurality of bits are encoded via polar coding.

[0165] Clause 12. A method for wireless communication at a wireless node, the method comprising: obtaining a first subset of one or more interleaved bits and a second subset of one or more interleaved bits via one or more symbols, wherein the one or more interleaved bits in the second subset are different from the one or more interleaved bits in the first subset; deinterleaving the first subset of one or more interleaved bits via a first interleaving scheme and deinterleaving the second subset of one or more interleaved bits via a second interleaving scheme; and decoding the deinterleaved first subset of one or more deinterleaved bits and the deinterleaved second subset of one or more deinterleaved bits.

[0166] Clause 13. The method according to Clause 12, the method further comprising: obtaining an indication of one or more of an interleaving mode and a cyclic shift mode applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme.

[0167] Clause 14. The method according to Clause 13, wherein the cyclic shift mode is configured to define a cyclic shift of a first index order of one or more interleaved bits input to the second interleaving scheme relative to a second index order of the first subset of one or more interleaved bits.

[0168] Clause 15. The method according to any one of Clauses 13 and 14, wherein the interlacing pattern is based on the shape of each of the first interlacing scheme and the second interlacing scheme.

[0169] Clause 16. The method according to any one of Clauses 13 to 15, wherein the interlacing pattern is one of a triangle pattern or a rectangle pattern.

[0170] Clause 17. The method according to any one of Clauses 12 to 16, wherein the first subset of one or more interleaving bits is deinterleaved in parallel with the second subset of one or more interleaving bits.

[0171] Clause 18. The method according to any one of Clauses 12 to 17, wherein each of the first subset of one or more deinterleaved bits and the second subset of one or more deinterleaved bits is decoded via polarization decoding.

[0172] Clause 19. A wireless node comprising: a transceiver; one or more memories having instructions individually or in combination; and one or more processors configured individually or in combination to execute the instructions and cause the wireless node to perform a method according to any one of embodiments 1 to 11, wherein the transceiver is configured to transmit an interleaved first subset and an interleaved second subset for transmission.

[0173] Clause 20. A wireless node comprising: a transceiver; one or more memories having instructions individually or in combination; and one or more processors configured individually or in combination to execute the instructions and cause the wireless node to perform a method according to any one of embodiments 12 to 18, wherein the transceiver is configured to: receive a first subset of one or more interleaved bits and a second subset of one or more interleaved bits.

[0174] Clause 21. An apparatus for wireless communication, the apparatus comprising components for performing the method according to any one of Embodiments 1 to 11.

[0175] Clause 22. An apparatus for wireless communication, the apparatus comprising components for performing the method according to any one of embodiments 12 to 18.

[0176] Clause 23. A non-transitory computer-readable medium comprising instructions that, when executed by a device, cause the device to perform the method according to any one of Examples 1 to 11.

[0177] Clause 24. A non-transitory computer-readable medium comprising instructions that, when executed by a device, cause the device to perform the method according to any one of Examples 12 to 18.

[0178] Clause 25. An apparatus for wireless communication, the apparatus comprising: one or more memories having instructions individually or in combination; and one or more processors configured individually or in combination to execute the instructions and cause the apparatus to perform the method according to any one of Embodiments 1 to 11.

[0179] Clause 26. An apparatus for wireless communication, the apparatus comprising: one or more memories having instructions individually or in combination; and one or more processors configured individually or in combination to execute the instructions and cause the apparatus to perform the method according to any one of Embodiments 12 to 18.

Claims

1. An apparatus for wireless communication, the apparatus comprising: One or more memories, wherein the one or more memories individually or in combination have instructions; and One or more processors, individually or in combination, are configured to execute the instructions and cause the device to: Encode multiple bits to produce coded bits; Interleaving: (i) interleaving a first subset of one or more coded bits via a first interleaving scheme, and (ii) interleaving a second subset of one or more coded bits via a second interleaving scheme, wherein the one or more coded bits in the second subset are different from the one or more coded bits in the first subset; The first and second interleaved subsets are mapped to one or more modulation symbols based on the corresponding bit levels of each of the first and second interleaved subsets. as well as The first interlaced subset and the second interlaced subset are output via the one or more modulation symbols for transmission.

2. The apparatus of claim 1, wherein the one or more processors are further configured to cause the apparatus to: The encoded bits are split into a subset including the first subset and the second subset. n A subset, of which n It is the number of bits associated with the modulation scheme used to map the first and second interleaved subsets.

3. The apparatus of claim 1, wherein the first interleaving scheme is configured to interleave the first subset based on a first index order of the one or more coded bits in the first subset, and wherein the second interleaving scheme is configured to interleave the second subset based on a cyclic shift of a second index order of the one or more coded bits in the second subset.

4. The apparatus of claim 3, wherein the cyclic shift is based on a shift pattern applied to a plurality of interleavers associated with the first interleaver scheme and the second interleaver scheme.

5. The apparatus of claim 1, wherein the first subset of interleaving includes an index order of one or more coded bits in the first subset, and wherein the second subset of interleaving one or more coded bits further includes interleaving the second subset based on the index order of the first subset of interleaving.

6. The apparatus of claim 1, wherein the one or more processors are further configured to cause the apparatus to: Output an indication of the interleaving mode for transmission, wherein the interleaving mode is applied to the interleaver associated with the first interleaving scheme and the second interleaving scheme.

7. The apparatus of claim 6, wherein the one or more processors are further configured to cause the apparatus to: The second interleaving scheme is configured using a cyclic shift pattern, which defines a cyclic shift of a first index order of one or more coded bits input into the second interleaving scheme relative to a second index order of the first subset of one or more coded bits interleaved via the first interleaving scheme.

8. The apparatus of claim 6, wherein the interlacing pattern is based on the shape of each of the first interlacing scheme and the second interlacing scheme.

9. The apparatus of claim 6, wherein the interlacing pattern is one of a triangular pattern or a rectangular pattern.

10. The apparatus of claim 1, wherein the first subset and the second subset are interleaved in parallel.

11. The apparatus of claim 1, wherein the plurality of bits are encoded via polarization coding.

12. The apparatus of claim 1, further comprising a transceiver configured to: Transmit the first interleaved subset and the second interleaved subset, wherein the device is configured as a wireless node.

13. An apparatus for wireless communication, the apparatus comprising: One or more memories, wherein the one or more memories individually or in combination have instructions; and One or more processors, individually or in combination, are configured to execute the instructions and cause the device to: A first subset of one or more interleaving bits and a second subset of one or more interleaving bits are obtained via one or more symbols, wherein the one or more interleaving bits in the second subset are different from the one or more interleaving bits in the first subset; The first subset of one or more interleaved bits is deinterleaved using a first interleaving scheme and the second subset of one or more interleaved bits is deinterleaved using a second interleaving scheme; as well as Decode the first subset of the deinterleaved bits of one or more deinterleaved bits and the second subset of the deinterleaved bits of one or more deinterleaved bits.

14. The apparatus of claim 13, wherein the one or more processors are further configured to cause the apparatus to: Obtain indication of one or more of the interleaving modes and cyclic shift modes applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme.

15. The apparatus of claim 14, wherein the cyclic shift mode is configured to define a cyclic shift of a first index order of one or more interleaved bits input to the second interleaving scheme relative to a second index order of the first subset of one or more interleaved bits.

16. The apparatus of claim 14, wherein the interlacing pattern is based on the shape of each of the first interlacing scheme and the second interlacing scheme.

17. The apparatus of claim 14, wherein the interlacing pattern is one of a triangular pattern or a rectangular pattern.

18. The apparatus of claim 13, wherein the first subset of one or more interleaving bits is deinterleaved in parallel with the second subset of one or more interleaving bits.

19. The apparatus of claim 13, wherein each of the first subset of one or more deinterleaved bits and the second subset of one or more deinterleaved bits is decoded via polarization decoding.

20. A method for conducting wireless communication at a wireless node, the method comprising: Encode multiple bits to produce coded bits; Interleaving: (i) interleaving a first subset of one or more coded bits via a first interleaving scheme, and (ii) interleaving a second subset of one or more coded bits via a second interleaving scheme, wherein the one or more coded bits in the second subset are different from the one or more coded bits in the first subset; The first and second interleaved subsets are mapped to one or more modulation symbols based on the corresponding bit levels of each of the first and second interleaved subsets. as well as The first interlaced subset and the second interlaced subset are output via the one or more modulation symbols for transmission.

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