Release layer for IR laser lift-off process

Abstract

A method of processing a substrate, the method including: forming an infrared (IR) absorbing separation layer on a first substrate; forming one or more layers on the IR absorbing separation layer; bonding the first substrate and a second substrate at a bonding interface between the one or more layers and the second substrate using a direct bonding technique to form a wafer stack; the wafer stack is exposed to infrared (IR) light irradiation to separate the first substrate from the one or more layers.

Description

Cross-references to related applications

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 531,840, filed August 10, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention generally relates to methods of processing substrates, and in specific embodiments relates to release layers for infrared (IR) laser lift-off (LLO) processes. Background Technology

[0003] Semiconductor devices, such as integrated circuits (ICs), are typically fabricated by sequentially depositing and patterning dielectric, conductive, and semiconductor layers on a substrate to form a network of electronic components and interconnects (e.g., transistors, resistors, capacitors, metal wires, contacts, and vias) integrated into a monolithic structure. Miniaturization has significantly increased the number of transistors and other electrical components per unit area, further enabling the development of three-dimensional (3D) semiconductor devices in which various components are stacked one on top of the other. As technology nodes advance, the number of stacked layers also increases. One 3D integration method for fabricating such stacks for 3D semiconductor devices is wafer-to-wafer bonding, in which individual electrical components are fabricated on two or more wafers and these wafers are bonded to form a permanent bonding structure for these electrical components.

[0004] In some manufacturing methods, after fabricating the device structure by bonding electrical components, one of the wafers used in the bonding process can be debonded from the device structure. One common technique for this debonding process is mechanical back-end polishing, in which a carrier wafer (e.g., the top silicon wafer) is removed by mechanical polishing. However, this method consumes the carrier wafer, and therefore results in high costs because the carrier wafer needs to be replaced for each debonding process. Furthermore, mechanical back-end polishing presents various problems, including environmental impacts (e.g., high water consumption and sludge formation), high technology implementation costs (e.g., carrier wafer consumption), and consumables used in the process (e.g., polishing wheels and polishing fluids). Importantly, mechanical polishing may also inherently carry the risk of damaging the underlying semiconductor device structure. Alternative techniques for debonding include, for example, thermal release, chemical dissolution, and laser ablation. Summary of the Invention

[0005] According to an embodiment of the present invention, a method for processing a substrate includes: forming an infrared (IR) absorption separation layer on a first substrate; forming one or more layers on the IR absorption separation layer; bonding the first substrate and the second substrate at a bonding interface between the one or more layers and a second substrate using a direct bonding technique to form a wafer stack; and exposing the wafer stack to infrared (IR) light irradiation to separate the first substrate from the one or more layers.

[0006] According to an embodiment of the present invention, a method for processing a wafer includes: forming a release layer stack on a first silicon (Si) wafer, the release layer stack including a conductive layer and a dielectric layer below the conductive layer; forming a semiconductor device structure on the release layer; bonding the first Si wafer and a second Si wafer to form a bonding structure, the semiconductor device structure being disposed between the release layer stack and the second Si wafer; and scanning an infrared (IR) laser on the bonding structure to separate the first Si wafer from the bonding structure at the release layer stack, the IR laser irradiating from one side of the first Si wafer in the bonding structure.

[0007] According to an embodiment of the present invention, a method for processing a wafer includes: forming a release layer stack on a first wafer by forming a first dielectric layer on the first wafer and forming a first conductive layer on the first dielectric layer; forming an array of first devices on the release layer stack; forming an array of second devices on a second wafer; bonding the array of first devices and the array of second devices to form a bonding structure, the array of first devices and the array of second devices being disposed in the bonding structure between the release layer stack and the second wafer; and scanning an infrared (IR) laser on the bonding structure to separate the first wafer and the second wafer at the release layer stack, such that the second wafer after separation includes the stack of the array of first devices and the array of second devices, the IR laser irradiating from one side of the first wafer of the bonding structure. Attached Figure Description

[0008] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A cross-sectional view of an example carrier wafer, including a release layer stack and a semiconductor device stack, prior to bonding, is shown according to various embodiments.

[0010] Figure 2 Cross-sectional views of example device wafers prior to bonding are shown according to various embodiments;

[0011] Figure 3Cross-sectional views of example bonding structures following a bonding carrier wafer and a device wafer, according to various embodiments, are shown.

[0012] Figures 4A to 4B Cross-sectional views of example bond structures during an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer from the bond structure, according to various embodiments, are shown. Figure 4A The material bonding structure under IR laser irradiation was demonstrated, and Figure 4B The image shows a separated wafer after the IR LLO process;

[0013] Figure 5 A cross-sectional view of an example separated wafer after an IR laser lift-off (LLO) process, according to an embodiment, is shown.

[0014] Figures 6A to 6B This illustration shows a cross-sectional view of another example bonding structure during an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer from the bonding structure, according to certain embodiments. Figure 6A The material bonding structure under IR laser irradiation was demonstrated, and Figure 6B The image shows a separated wafer after the IR LLO process;

[0015] Figures 7A to 7B A cross-sectional view of an example carrier wafer after the IR LLO process is shown, in which... Figure 7A A carrier wafer with a damaged surface was demonstrated, and Figure 7B The image shows a carrier wafer planarized using gas cluster ion beam (GCIB) processing; and

[0016] Figures 8A to 8C A process flow diagram of an IR laser lift-off (LLO) process according to various embodiments is shown, wherein, Figure 8A An example is shown. Figure 8B Another embodiment is shown, and Figure 8C Yet another embodiment is shown. Detailed Implementation

[0017] This application relates to a method for processing a substrate, and more specifically to an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer, die, or other substrate from a bonded device structure formed by a bonding process. In semiconductor device manufacturing processes, wafer bonding / debonding can be used for the 3D integration of semiconductor devices. Typically, a carrier wafer carrying a first set of electrical components can be bonded to a device wafer carrying a second set of electrical components to form a bonded device structure, and after bonding, the carrier wafer can be separated from the bonded device structure. A promising technique for debonding to separate the carrier wafer is the laser lift-off (LLO) process. Unlike conventional mechanical back-side polishing, the LLO process can be a non-contact method, thereby reducing the risk of damaging the semiconductor device structure. In a typical LLO process, laser irradiation is used to provide energy to modify the layers within the bonded structure physically, thermally, or chemically, leading to debonding. However, layer separation at fault interfaces (e.g., within the device structure) in LLO remains a significant challenge. This is particularly challenging for advanced semiconductor device applications, such as NAND flash memory, which may have a large number of layers (e.g., > 200 layers), resulting in thick layer stacks (e.g., > 10 µm). Furthermore, common LLO techniques typically use glass wafers as carrier wafers and are irradiated with ultraviolet (UV) lasers, which presents other problems such as electrostatic chuck damage, surface inhomogeneities after separation, incompatibility in silicon fabrication facilities, and tooling contamination. Therefore, a more reliable and target-interface-specific improved LLO process is desirable.

[0018] Embodiments of this application disclose a method for infrared (IR) laser lift-off (LLO) processes, wherein an improved release layer design is interposed between a carrier wafer and a semiconductor device structure. In various embodiments, the IR LLO process may use a release layer stack comprising at least one IR reflective layer (e.g., containing a metal layer) and at least one IR absorber layer (e.g., containing a silicon dielectric layer). In one example embodiment, the release layer stack may consist of an IR reflective layer stacked below or above an IR absorber layer. In another example embodiment, the release layer stack may consist of multiple IR reflective layers stacked below and / or above one or more IR absorber layers. This design of the release layer stack is particularly advantageous in preventing IR radiation from reaching the underlying semiconductor device structure and thus confining debonding to a target layer within the release layer stack. Therefore, debonding at incorrect interfaces can be avoided. The IR LLO process can offer various advantages over conventional methods such as mechanical back-end polishing. For example, it can be a non-contact method that does not consume the carrier wafer, thereby allowing the same carrier wafer to be reused in multiple debonding process cycles. These methods are potentially more environmentally friendly because they do not require the large amounts of water and sludge generated by mechanical or chemical-mechanical planarization (CMP) processes. The IR LLO process can further eliminate costly additional steps and consumables. Furthermore, the IR LLO process can outperform UV LLO processes using glass wafers because IR can penetrate silicon wafers, and therefore the silicon wafer can be used as a carrier wafer. The ability to use silicon wafers makes the IR LLO process compatible with most silicon manufacturing facilities. In addition, the IR wavelength is compatible with the properties of a variety of thin-film materials suitable for NAND applications, such as silicon oxide and TEOS.

[0019] In various embodiments, the IR LLO process can be particularly suitable for debonding permanently bonded structures formed by permanent bonding processes, which are bonded structures with stable chemical bonds that do not require the use of any binder layer. For example, such permanent bonds can be formed by direct (fusion) bonding or hybrid bonding processes that utilize covalent bonding to fix opposing surfaces of a target substrate without any intermediate layer. In contrast, conventional UV LLO processes are typically used to debond bonded structures with thick binder layers (formed by temporary bonding processes). In one example, the binder layer can be a polymer matrix that is reversibly viscous or chemically degradable in response to UV irradiation. Therefore, the UV LLO process may not be suitable for debonding permanently bonded structures, but IR LLO can be advantageously used as an alternative. This disclosure primarily describes embodiments for debonding such permanently bonded structures. However, in other embodiments, the IR LLO method can be applied to a variety of other bonded structures, regardless of whether these bonded structures use an intermediate layer during bonding.

[0020] The following describes various embodiments of bonding / debonding processes, including IR laser lift-off (LLO) technology. First, based on these various embodiments, reference is made to… Figures 1 to 2 A carrier wafer for carrying a semiconductor device structure and a device wafer for receiving the semiconductor device structure from the carrier wafer are described. Subsequently, reference is made to... Figure 3 The bond structure formed through a permanent bonding process is described. For the debonding steps, refer to [reference needed]. Figure 4A and Figure 4B , Figure 5 and Figures 6A to 6B An IR LLO process for separating a carrier wafer from a bonding structure is described. (Reference) Figures 7A to 7B An optional post-separation flattening step is described. Figures 8A to 8C An example process flow diagram is shown. All figures in this disclosure are for illustrative purposes only and are not drawn to scale, including aspect ratios of features. Although this disclosure primarily describes embodiments of bonding / debonding methods using two wafers, these methods can also be applied to bonding structures of any two substrates (e.g., wafers, dies, or other fabrication / reconstruction structures).

[0021] Figure 1 A cross-sectional view of an example carrier wafer 110, including a release layer stack 120 and a semiconductor device stack 130, prior to bonding, is shown according to various embodiments.

[0022] In various embodiments, the carrier wafer 110 may be a silicon wafer or a silicon-on-insulator (SOI) wafer that is sufficiently transparent to infrared (IR) light at a certain wavelength for use in IR LLO processes. In some embodiments, the carrier wafer 110 may include silicon-germanium wafers, silicon carbide wafers, gallium arsenide wafers, gallium nitride wafers, and other compound semiconductors. In other embodiments, the carrier wafer 110 includes heterolayers such as silicon-on-germanium, gallium-on-silicon, silicon-on-carbon, and silicon-on-silicon layers on silicon or SOI substrates. In some embodiments, the carrier wafer 110 has a thickness of approximately 750 µm. In one or more embodiments, the carrier wafer 110 may have a diameter of 200 mm or 300 mm. However, the techniques described herein can be applied to supports of other sizes, including panels, dies, and other suitable substrates of various sizes.

[0023] In various embodiments, the carrier wafer 110 may be transparent to infrared (IR) light. See below for reference. Figures 4A to 4BFurther described, the IR light used in the IR LLO process needs to efficiently reach the release layer stack 120. In various embodiments, the IR light can be irradiated from the back surface 100b side of the carrier wafer 110, opposite to the front surface 100a side of the carrier wafer 110. Therefore, the material and thickness of the carrier wafer 110 can be selected such that the IR light can efficiently pass through the carrier wafer 110. For example, in one embodiment, at least 50% of the IR light can pass through the carrier wafer 110 and reach the underlying layer (e.g., the release layer stack 120) during the IR LLO process, but in other embodiments, less IR can pass through the carrier wafer 110. The IR irradiation conditions (e.g., intensity) can be adjusted accordingly.

[0024] like Figure 1 As shown, the release layer stack 120 can be formed on the carrier wafer 110. The release layer stack 120 is designed to include layers or layer stacks to be separated by an IR LLO process. In various embodiments, the release layer stack 120 may include at least one absorber layer 122 and at least one reflector layer 124, such as Figure 1 As shown. In Figure 1 In this configuration, the reflective layer 124 can be disposed above the absorber layer 122, such that the absorber layer 122 is interposed between the carrier wafer 110 and the reflective layer 124. In some embodiments, the release layer stack 120 may include two or more absorber layers or two or more reflective layers, as described below. Figure 6A Further description.

[0025] In various embodiments, the absorber layer 122 may include a dielectric material capable of efficiently absorbing IR light. In one or more embodiments, the absorber layer 122 may employ a silicon-containing dielectric material. For example, the absorber layer 122 may include silicon oxide prepared by plasma-enhanced CVD or flow CVD using tetraethyl orthosilicate (TEOS) as a precursor. In one embodiment, the absorber layer 122 may be a metal-free layer. In some embodiments, the absorber layer 122 may include SiN, SiCN, SiON, TiO, HfO, AlO, or ZrO. The absorber layer 122 may be deposited using suitable techniques such as vapor deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD)) and other plasma processes such as plasma-enhanced CVD (PECVD) and other processes. In one embodiment, the absorber layer 122 has a thickness between 5 nm and 200 nm, and in another embodiment, it has a thickness between 50 nm and 150 nm.

[0026] A simplified method of IR laser lift-off (LLO) can use only the absorber layer as the release layer to induce debonding of the stacked structure. The inventors of this application have determined that this absorber layer may need to be sufficiently thick (e.g., > 1 μm) to prevent undesirable IR penetration into the underlying layers. Forming a thick release layer (e.g., > 1 μm) structure may be incompatible with advanced device fabrication processes (e.g., for NAND devices) because it may interfere with subsequent processes or the tooling used in those processes. The inventors of this application have demonstrated that various embodiments can overcome this problem by introducing at least one reflective layer, thereby enabling thinner absorber layers and thinner release layer stacks suitable for advanced device fabrication processes. Therefore, in various embodiments, the total thickness of the release layer stack 120 may be 500 nm or less. In one or more embodiments, the total thickness may be 300 nm or less. Further, in some embodiments, the release layer stack has a thickness less than half the thickness of the semiconductor device stack 130.

[0027] Still referencing Figure 1 The reflective layer 124 of the release layer stack 120 may include a material capable of efficiently reflecting IR light. In one or more embodiments, the materials used for the reflective layer 124 and the absorption layer 122 are selected such that total internal reflection is induced at the interface between these layers. In various embodiments, the reflective layer 124 may include a conductive material comprising a metal. For example, the reflective layer 124 may include a pure metal, a metal alloy, a metal nitride, or a metal silicide. Examples of metal elements used for the reflective layer 124 include, but are not limited to, W, Ti, Mo, Ta, and Ru. The material of the reflective layer 124 may be selected considering IR reflectivity, cost, thermal stability, and compatibility with manufacturing processes. In some embodiments, the reflective layer 124 may employ a conductive material suitable for front-end process (FEOL) processes. The reflective layer 124 may be deposited using appropriate techniques such as vapor deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD)) as well as other plasma processes such as plasma-enhanced CVD (PECVD) and other processes. In one embodiment, the reflective layer 124 has a thickness between 5 nm and 50 nm. In some embodiments, the thickness of the reflective layer 124 can be less than the thickness of the absorber layer 122, because the thickness of the reflective layer 124 can be minimized as long as it can efficiently reflect the incident IR light.

[0028] In various embodiments, the absorber layer 122, the reflector layer 124, and thus the entire release layer stack 120 can have high thermal stability (e.g., up to 1000°C), and the materials of these layers can be selected accordingly. The thermal stability of the release layer stack 120 is particularly advantageous in applications requiring high-temperature processes (e.g., annealing at >350°C), such as NAND device fabrication. In one embodiment, the release layer stack 120 can have thermal stability up to 1000°C.

[0029] The release layer stack 120 can be designed to maximize IR absorption of one or more absorption layers and IR reflection of one or more reflection layers. Therefore, the layer thickness and material of each layer can be selected with reference to the wavelength of IR light used in the IR LLO process in order to maximize IR absorption / reflection performance.

[0030] Using conductive materials for the reflective layer 124 can be advantageous because it can mitigate charge buildup issues during subsequent plasma etching processes, such as high aspect ratio contact (HARC) etching for NAND device fabrication or device 3D integration.

[0031] In various embodiments, the carrier wafer 110 may include semiconductor devices and may have undergone multiple processing steps, such as conventional processes. Therefore, the carrier wafer 110 may include semiconductor layers suitable for various microelectronic devices. For example, as... Figure 1 As shown, the carrier wafer 110 may include a semiconductor device stack 130.

[0032] In various embodiments, the semiconductor device stack 130 may include a memory device structure (e.g., NAND flash memory) and is a stack of various dielectric layers, semiconductor layers and conductive layers. Figure 1 The dashed lines in the diagram are used to indicate example layer interfaces within the semiconductor device stack 130. Although not specifically shown, in one embodiment, the semiconductor device stack 130 may be patterned for use in a memory device. For example, the semiconductor device stack 130 may include a channel structure and a stack of alternating word line layers (e.g., made of a conductive material such as tungsten) and dielectric layers for separating the word lines.

[0033] Figure 1 The semiconductor device stack 130 shown is a simplified example for illustrative purposes only. In various embodiments, the semiconductor device stack 130 may include any number of layers (e.g., >200 layers) for example to form a memory cell stack, and may have any total thickness. In one embodiment, the total thickness may be 10 µm or greater. The semiconductor device stack 130 may be formed directly on the carrier wafer 110 or transferred from another substrate to the carrier wafer 110.

[0034] Figure 2 A cross-sectional view of an example device wafer 210 prior to bonding is shown according to various embodiments.

[0035] In various embodiments, device wafer 210 is a semiconductor device stack 130 that can be derived from a carrier wafer (e.g., Figure 1 The carrier wafer 110 is transferred onto the device wafer. The device wafer 210 can be a silicon wafer or a silicon-on-insulator (SOI) wafer. In some embodiments, the device wafer 210 may include a silicon-germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, and other compound semiconductors. In other embodiments, the device wafer 210 includes a heterolayer, such as silicon-germanium on silicon, gallium nitride on silicon, silicon-carbon on silicon, and a silicon layer on a silicon or SOI substrate.

[0036] In various embodiments, device wafer 210 may include semiconductor devices formed thereon or within it, and may have undergone multiple processing steps, such as conventional processes. Therefore, device wafer 210 may include semiconductor layers suitable for various microelectronic devices. For example, although not specifically shown, in an example embodiment, device wafer 210 may include a logic device structure that may be mechanically and electrically connected to… Figure 1 The carrier wafer 110 represents a memory device structure. In various embodiments, the carrier wafer 110 and device wafer 210 may contain different types of electrical components, which may require different types of processing with different parameters, including different thermal budgets and material requirements. Therefore, these different processes can be performed on separate workpieces, and then these separate workpieces can be combined after such processing is complete. Furthermore, the carrier wafer 110 and device wafer 210 can be obtained from different manufacturers or different facilities, allowing for flexibility in circuit design and device sourcing.

[0037] like Figure 2As further illustrated, device wafer 200 may include a dielectric layer 220. In one or more embodiments, device wafer 210 may include a reconfigurable wafer including redistribution lines, wherein dielectric layer 220 includes a redistribution layer. In some embodiments, dielectric layer 220 may include a passivation layer for protecting underlying devices and circuitry. In various embodiments, dielectric layer 220 may include a front surface 220a of device wafer 210 at its outermost surface, and device wafer 210 may include a rear surface 220b opposite to the front surface 220a. Front surface 220a may be a bonding interface for bonding processes. In various embodiments, dielectric layer 220 may include silicon oxide thermally grown from device wafer 210. In one embodiment, dielectric layer 220 may have a thickness between 50 nm and 300 nm. In some embodiments, conductive interconnects may be additionally provided at the front surface 220a for electrically coupling devices on device wafer 201 to devices on carrier wafer 110 via hybrid bonding structures and techniques.

[0038] Figure 3 A cross-sectional view of an example bonding structure 300 following a bonding carrier wafer and a device wafer, according to various embodiments, is shown.

[0039] In various embodiments, the bonding structure 300 can be formed by bonding a carrier wafer carrying a set of electrical components and a device wafer receiving the set of electrical components. For example, a NAND flash memory cell stack can be carried by a carrier wafer and, through a bonding process, can be mechanically and electrically connected to logic cells on a device wafer. The bonding process can include various types of wafer bonding processes, such as the previously mentioned direct bonding or hybrid bonding. In some embodiments, where high-temperature annealing (e.g., > 350°C) is required, the bonding process can be based on any binder-free permanent bonding process.

[0040] exist Figure 3 In the middle, the bonding structure 300 includes Figure 1 The carrier wafer 110, which is bonded to Figure 2 The device wafer 210 has a front surface 110a of a carrier wafer 110 in contact with a front surface 200a of the device wafer 210, serving as a bonding interface. These surfaces are bonded using direct bonding or hybrid bonding processes, which are well-known and documented elsewhere. After the bonding process, a semiconductor device stack 130 is interposed between a release layer stack 120 and a dielectric layer 220 on the device wafer 210. Figure 3 In the illustration, the carrier wafer 110 is relative to... Figure 1 It is displayed upside down.

[0041] As described above, in various embodiments, the bonding between the semiconductor device stack 130 and the device wafer 210 can be made permanent. Further, the device wafer 210 may include a second set of electrical components (e.g., logic devices), and the bonding can directly form an electrical connection between the semiconductor device stack 130 and the second set of electrical components. In other embodiments, the electrical connection can be achieved through further manufacturing processes.

[0042] Figures 4A to 4B A cross-sectional view of an example bonding structure 400 during an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer from the bonding structure, according to various embodiments, is shown. Figure 4A The IR laser irradiation of the incoming bonding structure 400 was demonstrated, and Figure 4B This demonstrates the separation of wafers after the IR LLO process. The bonding structure 400 can be coupled with... Figure 3 The bonding structure shown here is the same as that described above (300), so its details will not be repeated.

[0043] The IR LLO process can be performed by exposing the bonded structure 400 to IR light. In various embodiments, such as... Figure 4A As shown, this IR exposure can be performed by scanning an IR laser 410 across the bonding structure 400. The IR light can be in the near-IR, mid-IR, or far-IR range. Various light sources can be used to generate the IR light. For example, in one embodiment, an Nd:YAG laser can be used for near-IR (~1060 nm wavelength). In various embodiments, the IR can have a wavelength between 2 µm and 10 µm. Typically, the absorption coefficient of silicon decreases significantly at wavelengths above 1000 nm. Therefore, it is advantageous to use a longer IR to avoid absorption by the silicon substrate (e.g., carrier wafer 110). On the other hand, the material used for the absorption layer 122 (e.g., silicon dioxide) can have a higher absorption coefficient at the IR wavelength, such that most of the radiation is absorbed without passing through the absorption layer 122.

[0044] Absorbed IR can be converted into heat, which travels rapidly downwards through the potentially thermally conductive reflective layer 124 and damages sensitive device regions. The amount of heat absorbed within the absorption layer 122 can depend on the thickness of the absorption layer 122, the absorption coefficient of the absorption layer 122 for the specific IR wavelength being irradiated, and the parameters of the radiation (e.g., intensity, scan rate, spot size, angle, etc.). Therefore, in various embodiments, the absorption layer 122 and processing parameters are selected to avoid overheating, which could damage sensitive areas such as the semiconductor device stack 130.

[0045] IR can efficiently penetrate the carrier wafer 110 and enter the absorber layer 122 of the release layer stack 120, thereby causing debonding (separation) of the bonded structure 400. While not wishing to be limited by any theory, debonding can be caused by the energy of the IR absorbed in the absorber layer 122. In various embodiments, the absorbed IR can cause thermal expansion of the absorber layer 122, which creates an initiation point for debonding within the release layer stack 120.

[0046] In various embodiments, the IR LLO process is a heat release-based process that can be performed without ablation of the absorber layer 122, wherein IR does not cause any decomposition or vaporization of the absorber layer 122.

[0047] In various embodiments, the IR laser 410 can be oriented perpendicular to the back surface 100b of the carrier wafer 110, such as... Figure 4A As shown. In other embodiments, the IR laser 410 may be tilted relative to a vertical line perpendicular to the rear surface 100b. The incident angle of the IR laser 410 may be selected to minimize reflection at the rear surface 100b and maximize reflection at the reflective layer 124.

[0048] like Figure 4B As shown, in some embodiments, debonding can occur at the interface between the absorber layer 122 and the reflector layer 124, resulting in a debonded carrier wafer 400a and a debonded device wafer 400b. In other embodiments, debonding can occur at different interfaces within the release layer stack 120.

[0049] Figure 5 A cross-sectional view of an example separated wafer following an IR laser lift-off (LLO) process, according to an alternative embodiment, is shown.

[0050] In some embodiments, debonding can occur on the top surface of the release layer stack 120, i.e., Figure 5 The debonding occurs at the interface between the carrier wafer 110 and the absorber layer 122. The location of the debonding can depend on the material and design of the release layer stack 120 and the IR exposure conditions. Figure 4B and Figure 5 In both cases shown, debonding occurs within or at the interface of the release layer stack 120 due to improved IR absorption / reflection properties. The design of the absorption / reflection layer stack can advantageously eliminate or minimize IR penetration into the underlying layer beneath the release layer stack 120 (e.g., semiconductor device stack 130). Therefore, various embodiments of these methods can prevent debonding from occurring at undesired locations, such as undesired locations within the semiconductor device stack 130 (e.g., ...). Figure 6B (Any interface indicated by the dashed line within the semiconductor device stack 130).

[0051] Figures 6A to 6B A cross-sectional view of another example bonding structure 600 during an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer from a bonding structure, according to other embodiments, is shown. Figure 6A The 600-type in-feed bonding structure under IR laser irradiation was demonstrated, and Figure 6B The image shows a separated wafer after the IR LLO process.

[0052] exist Figure 6A In this embodiment, the elements of the bonding structure 600 can be used with those of the previous embodiment. Figure 3 or Figure 4A The bonding structures 300 or 400 shown are identical, the difference being that the release layer stack 620 includes two absorption layers (a first absorption layer 622 and a second absorption layer 626) and two reflective layers (a first reflective layer 624 and a second reflective layer 628). Using alternating IR absorption and reflection layers advantageously allows for achieving the same IR LLO performance with a thinner layer stack structure compared to using only a single layer for each of IR absorption and reflection.

[0053] In various embodiments, the upper portion of the stacked body (e.g., Figure 6A The first absorbing layer 622 and the first reflective layer 624 in the stack can be larger than the bottom portion of the stack (e.g., Figure 6A The second absorber layer 626 and the second reflective layer 628 are thinner, thereby allowing a portion of the IR to reach the bottom portion of the layer stack. In some embodiments, the first reflective layer 624 or the second reflective layer 628 may have a thickness between 5 nm and 250 nm, and the first absorber layer 622 or the second absorber layer 626 may have a thickness between 10 nm and 500 nm. In some embodiments, a pair of absorber and reflective layers may be formed such that the reflective layer (e.g., the first or second reflective layer) is thinner than the absorber layer (e.g., the first or second absorber layer) in the same pair. Each of the absorber layers or each of the reflective layers may be made of the same material or different materials.

[0054] Figure 4A and Figure 6A The layer stack structures shown (release layer stacks 120 and 620) are merely examples, and in other embodiments, other suitable layer stack designs with any number of layers can be used as release layer stacks. In one embodiment, each of IR absorption and reflection may employ more than two layers. In another embodiment, two reflective layers and an absorbing layer interposed between them may be used.

[0055] Although this disclosure uses the term "released layer stack," it may not be limited to interface-defined discrete layer stacks, such as... Figure 1 , Figure 4A and Figure 6A As shown. In one or more embodiments, the interfaces within the release layer stack 120 may not have a well-defined chemical composition gradient.

[0056] like Figure 6B As shown, in some embodiments, debonding can occur at the interface between the carrier wafer 110 and the first absorber layer 622, resulting in a debonded carrier wafer 600a and a debonded device wafer 600b. In other embodiments, debonding can occur at different interfaces within the release layer stack 620, for example, Figure 6B The middle arrow indicates any interface.

[0057] As referenced above Figure 4B , Figure 5 and Figure 6B As described, the debonded carrier wafer can be a carrier wafer 110 with or without residual portions of the release layer stack 120 (e.g., in...). Figure 4B In this embodiment, the debonded carrier wafer 400a has an attached absorber layer 122. In any of these embodiments, the IR LLO process successfully separates the carrier wafer from the bonding structure and prevents debonding at any interface or layer outside the release layer stack 120 (e.g., inside the semiconductor device stack 130). Because the IR LLO process can be advantageously performed without consuming or damaging the carrier wafer 110, the substrate can be reused for another IR LLO process. In some embodiments, a removal step may be performed to remove any residual layers (e.g., absorber layer 122) that may remain on the carrier wafer 110 after debonding. Figure 4B (Absorbing layer 122 in the substrate). Alternatively, this residual layer on the carrier wafer 110 can even be used as part of a new release layer stack, thereby omitting the removal step. In one or more embodiments, this removal step can be performed using a dry etching process or a wet etching process.

[0058] After debonding is completed, the device wafer can be further processed through subsequent manufacturing steps (e.g., Figure 6B (The debonded device wafer 600b). For example, in one embodiment, the device wafer can be diced into individual dies. In another embodiment, a process for providing electrical connections between semiconductor device components can be performed.

[0059] Figures 7A to 7B A cross-sectional view of an example carrier wafer 110 after the IR LLO process is shown.

[0060] In various embodiments, after performing the IR LLO process, the carrier wafer 110 can be completely recovered and reused for another cycle of the IR LLO process. In some embodiments, such as Figure 7A As shown, the IR LLO process may result in a damaged surface 100c of the carrier wafer 110, wherein the damaged surface 100c has significant roughness. An optional post-separation planarization process can be performed to planarize the damaged surface 100c. In one or more embodiments, planarization can be performed using a gas cluster ion beam (GCIB) process. For example, the carrier wafer 110 can be scanned under a beam comprising ionized gas clusters 700. Figure 7A ), and a restored flat surface 110d can be obtained ( Figure 7B In the case of the restored planar surface 110d, the carrier wafer 110 after an optional post-separation planarization process can be used for another IR LLO process. Typically, the GCIB process uses electrically accelerated clusters of gaseous atoms or molecules that are guided as beams to bombard the substrate, and the bombardment of these ions removes, modifies, or smooths the surface layer of the substrate. Due to its low energy per atom / molecule, GCIB can provide unique characteristics in surface processing, such as low damage, low thermal load, and shallow effects on the surface, as well as lateral sputtering, which enable surface smoothing. In various embodiments, the gases used for GCIB processing can include: inert gases such as helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and nitrogen (N2); reactive gases such as O2, CO2, NH3, NF3, SF6, CF4, CHF3, etc., or mixtures thereof. In other embodiments, other planarization techniques can be used to process the damaged surface 100c.

[0061] In various embodiments, for an IR LLO process, the substrate including the bonding structure 700 can be scanned using an IR laser, for example, by moving the substrate relative to a fixed IR laser beam. In this disclosure, "scanning" is used broadly to refer to processing a substrate with a beam and is not limited to any scanning mode (e.g., moving the substrate over a fixed beam or moving the beam over a fixed substrate). These methods allow for dynamic adjustment of the scanning direction and IR laser parameters (e.g., scanning speed and IR laser power) during substrate processing.

[0062] Figures 8A to 8C A process flow diagram illustrating a method for IR laser lift-off (LLO) according to various embodiments is provided. The process flow can follow the diagrams described above ( Figures 1 to 5 And therefore will no longer be described.

[0063] exist Figure 8AIn the process flow 80, the IR absorption separation layer (frame 810) is formed on the first substrate. Figure 1 ), and then one or more layers are formed on the IR absorption separation layer (box 820, Figure 1 Subsequently, direct bonding technology can be used to bond the first and second substrates at the bonding interface between one or more layers and the second substrate to form a wafer stack (box 830). Figure 3 Then, the wafer stack can be exposed to IR light irradiation to separate the first substrate from one or more layers (box 840, ...). Figures 4A to 5 ).

[0064] exist Figure 8B In the process flow 82, prior to the IR LLO process, a release layer stack is formed on the first wafer, wherein the release layer stack includes a conductive layer and a dielectric layer beneath the conductive layer (frame 812). Figure 1 Then, a semiconductor device structure is formed on the release layer (box 822). Figure 1 Next, the first and second wafers can be bonded to form a bonding structure, allowing the semiconductor device structure to be disposed between the release layer stack and the second wafer (box 832). Figure 3 Then, the IR LLO process can be performed by scanning an IR laser over the bonding structure to separate the carrier wafer from the bonding structure at the release layer stack, wherein the IR laser irradiates from one side of the first wafer of the bonding structure (box 842). Figures 4A to 5 ).

[0065] exist Figure 8C In the process flow 84, prior to the IR LLO process, a release layer stack is formed on the first wafer by forming a first dielectric layer on the first wafer and then forming a first conductive layer on the first dielectric layer (box 814). Figure 1 Then, an array of the first devices is formed on the release layer stack (box 824). Figure 1 Individually, an array of second devices can be formed on the second wafer (box 816, ...). Figure 2 Then, arrays of the first and second devices can be bonded to form a bonding structure, such that these arrays are positioned between the release layer stack and the second wafer (box 834). Figure 3 An IR LLO process can be performed by scanning an IR laser over the bonding structure to separate the first wafer from the second wafer at the release layer stack, such that the debonded second wafer comprises an array of the first device and an array of the second device, wherein the IR laser irradiates from one side of the first wafer of the bonding structure (box 844). Figures 4A to 4B ).

[0066] As described above, various embodiments of the IR LLO process method, employing a novel release layer stack design, offer advantages in debonding wafers during permanent bonding / debonding processes due to their efficient IR absorption / reflection, no wafer consumption during processing (i.e., the carrier can be reused), release layer stack thickness compatibility, and reduced environmental footprint. Therefore, these methods can improve the overall process for 3D integration of semiconductor devices (e.g., NAND flash memory devices), where it is necessary to debond the silicon carrier wafer from the permanent bonding device structure as an alternative to mechanical back-side polishing.

[0067] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood in light of the entire specification and the claims set forth herein.

[0068] Example 1. A method of processing a substrate, the method comprising: forming an infrared (IR) absorption separation layer on a first substrate; forming one or more layers on the IR absorption separation layer; bonding the first substrate and the second substrate at a bonding interface between the one or more layers and a second substrate using a direct bonding technique to form a wafer stack; and exposing the wafer stack to infrared (IR) light irradiation to separate the first substrate from the one or more layers.

[0069] Example 2. The method as described in Example 1, wherein the exposure includes scanning an IR laser on the first substrate from the opposite side of the one or more layers.

[0070] Example 3. The method as described in either Example 1 or 2 further includes forming an IR reflective layer on the IR absorption separation layer prior to forming the one or more layers.

[0071] Example 4. The method as described in any one of Examples 1 to 3, wherein the IR reflective layer is conductive and comprises a metal, a metal silicide, or a metal nitride, and wherein the IR absorption separation layer comprises silicon oxide.

[0072] Example 5. The method as described in any one of Examples 1 to 4 further includes forming an additional IR reflective layer, wherein the IR absorption separation layer is disposed between the IR reflective layer and the additional IR reflective layer.

[0073] Example 6. The method as described in any one of Examples 1 to 5, wherein the IR reflective layer has thermal stability up to 1000°C.

[0074] Example 7. A method of processing a wafer, the method comprising: forming a release layer stack on a first silicon (Si) wafer, the release layer stack including a conductive layer and a dielectric layer below the conductive layer; forming a semiconductor device structure on the release layer; bonding the first Si wafer and a second Si wafer to form a bonding structure, the semiconductor device structure being disposed between the release layer stack and the second Si wafer; and scanning an infrared (IR) laser on the bonding structure to separate the first Si wafer from the bonding structure at the release layer stack, the IR laser irradiating from one side of the first Si wafer of the bonding structure.

[0075] Example 8. The method of Example 7, wherein forming the release layer stack comprises: performing a chemical vapor deposition (CVD) process to deposit silicon oxide as the dielectric layer; and depositing the conductive layer on the dielectric layer, the conductive layer comprising a metal, a metal silicide, or a metal nitride.

[0076] Example 9. The method as described in one of Examples 7 or 8, wherein forming the release layer stack further includes depositing another dielectric layer on the conductive layer.

[0077] Example 10. The method as described in any one of Examples 7 to 9, wherein forming the release layer stack further includes depositing another conductive layer on the other dielectric layer.

[0078] Example 11. The method as described in any one of Examples 7 to 10, wherein the semiconductor device structure is patterned and includes a plurality of electrically interconnected electrical components.

[0079] Example 12. The method as described in any one of Examples 7 to 11, wherein the first Si wafer is separated at the interface between the conductive layer and the dielectric layer, or the first Si wafer is separated at the interface between the dielectric layer and the first Si wafer.

[0080] Example 13. A method of processing a wafer, the method comprising: forming a release layer stack on a first wafer by forming a first dielectric layer on the first wafer and forming a first conductive layer on the first dielectric layer; forming an array of first devices on the release layer stack; forming an array of second devices on a second wafer; bonding the array of first devices and the array of second devices to form a bonding structure, the array of first devices and the array of second devices being disposed in the bonding structure between the release layer stack and the second wafer; and scanning an infrared (IR) laser over the bonding structure to separate the first wafer and the second wafer at the release layer stack, such that the second wafer after separation comprises the stack of the array of first devices and the array of second devices, the IR laser irradiating from one side of the first wafer of the bonding structure.

[0081] Example 14. The method as described in Example 13, wherein the IR laser has a wavelength between 2 µm and 10 µm.

[0082] Example 15. The method as described in any one of Examples 13 or 14, wherein the first conductive layer comprises a metal, a metal silicide, or a metal nitride, the method further comprising selecting the thickness of the first conductive layer to prevent the IR laser from penetrating the first conductive layer from the first dielectric layer to reach the array of the first device.

[0083] Example 16. The method as described in any one of Examples 13 to 15, wherein the first dielectric layer comprises silicon, and wherein the thickness of the first dielectric layer is between 5 nm and 200 nm.

[0084] Example 17. The method as described in any one of Examples 13 to 16, wherein the release layer stack has a thickness less than half the thickness of the array of the first device.

[0085] Example 18. The method as described in any one of Examples 13 to 17, wherein the array of the first device is electrically connected to the circuit elements of the array of the second device after the bonding.

[0086] Example 19. The method as described in any one of Examples 13 to 18, wherein the array of the first devices includes memory device components, wherein the array of the second devices includes logic device components, and wherein the bonding includes a hybrid bonding process to form an electrical connection between the memory device components and the logic device components.

[0087] Example 20. The method as described in any one of Examples 13 to 19 further includes performing another bonding process using the first wafer after the separation.

[0088] Although the invention has been described with reference to illustrative embodiments, this specification is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this specification. As an illustration, in other embodiments, Figure 1 The embodiments described in Figure 7C can be combined with each other. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for processing a substrate, the method comprising: An infrared (IR) absorption separation layer is formed on the first substrate; One or more layers are formed on the IR absorption separation layer; The first substrate and the second substrate are bonded at the bonding interface between the one or more layers and the second substrate using direct bonding technology to form a wafer stack. The wafer stack is exposed to infrared (IR) light to separate the first substrate from the one or more layers.

2. The method as described in claim 1, wherein, The exposure includes scanning an IR laser onto the first substrate from the opposite side of the one or more layers.

3. The method of claim 1, further comprising forming an IR reflective layer on the IR absorption separation layer prior to forming the one or more layers.

4. The method of claim 3, wherein, The IR reflective layer is conductive and comprises a metal, a metal silicide, or a metal nitride, wherein the IR absorption separation layer comprises silicon oxide.

5. The method of claim 3, further comprising forming an additional IR reflective layer, wherein, The IR absorption separation layer is disposed between the IR reflection layer and the other IR reflection layer.

6. The method of claim 3, wherein, The IR reflective layer exhibits thermal stability up to 1000°C.

7. A method for processing a wafer, the method comprising: A release layer stack is formed on a first silicon (Si) wafer, the release layer stack including a conductive layer and a dielectric layer below the conductive layer; A semiconductor device structure is formed on this release layer; The first Si wafer and the second Si wafer are bonded to form a bonding structure, and the semiconductor device structure is disposed between the release layer stack and the second Si wafer; as well as An infrared (IR) laser is scanned over the bonding structure to separate the first Si wafer from the bonding structure at the release layer stack, and the IR laser irradiates one side of the first Si wafer in the bonding structure.

8. The method of claim 7, wherein, The release layer stack comprises: Perform a chemical vapor deposition (CVD) process to deposit silicon oxide as the dielectric layer; and The conductive layer is deposited on the dielectric layer, and the conductive layer includes a metal, a metal silicide, or a metal nitride.

9. The method of claim 8, wherein, Forming the release layer stack further includes depositing another dielectric layer on the conductive layer.

10. The method of claim 9, wherein, Forming the release layer stack further includes depositing another conductive layer on the other dielectric layer.

11. The method of claim 7, wherein, The semiconductor device structure is patterned and includes multiple electrically interconnected electrical components.

12. The method of claim 7, wherein, The first Si wafer is separated at the interface between the conductive layer and the dielectric layer, or the first Si wafer is separated at the interface between the dielectric layer and the first Si wafer.

13. A method for processing a wafer, the method comprising: A release layer stack is formed on the first wafer by forming a first dielectric layer on the first wafer and forming a first conductive layer on the first dielectric layer; An array of the first devices is formed on the release layer stack; An array of second devices is formed on a second wafer; The array of the first device and the array of the second device are bonded together to form a bonding structure, wherein the array of the first device and the array of the second device are disposed in the bonding structure between the release layer stack and the second wafer; as well as An infrared (IR) laser is scanned over the bonding structure to separate the first wafer and the second wafer at the release layer stack, such that the second wafer after separation comprises a stack of an array of the first device and an array of the second device, the IR laser irradiating from one side of the first wafer of the bonding structure.

14. The method of claim 13, wherein, This IR laser has a wavelength between 2 µm and 10 µm.

15. The method of claim 13, wherein, The first conductive layer includes a metal, a metal silicide, or a metal nitride, and the method further includes selecting the thickness of the first conductive layer to prevent the IR laser from penetrating the first conductive layer from the first dielectric layer to reach the array of the first device.

16. The method of claim 13, wherein, The first dielectric layer comprises silicon, and wherein the thickness of the first dielectric layer is between 5 nm and 200 nm.

17. The method of claim 13, wherein, The release layer stack has a thickness less than half the thickness of the array of the first device.

18. The method of claim 13, wherein, The array of the first device is electrically connected to the circuit elements of the array of the second device after the bonding.

19. The method of claim 13, wherein, The array of the first device includes memory device components, the array of the second device includes logic device components, and the bonding includes a hybrid bonding process to form an electrical connection between the memory device components and the logic device components.

20. The method of claim 13, further comprising performing another bonding process using the first wafer after the separation.

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