Hot-pluggable dual-redundancy server based on LRM architecture

Abstract

The invention discloses a hot-pluggable dual-redundancy server based on an LRM architecture, relates to the field of computers, realizes hot plugging of a CPU module through a modular LRM slot design, and solves the problems of complex maintenance, low redundancy efficiency and inflexible configuration of a traditional server in combination with dual-path redundancy state synchronization, fault switching and a single-path mode adaptive mechanism. The method is suitable for a high-availability data center and a key service scene.

Description

Technical Field

[0001] This invention relates to the field of computers, and more specifically to a hot-swappable dual-redundant server based on LRM architecture. Background Technology

[0002] With the rapid development of cloud computing, big data, and artificial intelligence, the reliability, maintainability, and flexibility of servers, as the core carriers of computing power, have become critical requirements. In traditional server architectures, CPUs are typically soldered directly to the motherboard, and redundancy designs often rely on dual-socket (or more) configurations at the motherboard level. However, this approach has the following drawbacks: 1. High maintenance complexity: When the CPU fails, the system needs to be shut down and the motherboard needs to be removed, resulting in long business interruption time (usually several hours to several days), which cannot meet the 24 / 7 critical business needs; 2. Low redundancy efficiency: Although traditional dual-socket servers provide redundancy, the two CPUs need to be strictly synchronized. Resource utilization is limited by the master-slave mode (such as the master CPU bearing the main load and the slave CPU only synchronizing the state), and it cannot be flexibly adjusted to single-socket mode to reduce costs. 3. Limited scalability: The motherboard is too integrated, making it difficult to dynamically adjust the number or specifications of CPUs for different scenarios (such as edge computing and small and medium-sized enterprises).

[0003] The Line Replaceable Module (LRM) architecture, through its modular design, enables hot-swapping and rapid replacement of key components, and is widely used in avionics and communication equipment. However, the current server field lacks a mature dual-redundancy solution based on the LRM architecture, particularly lacking server designs that balance high availability, flexible configuration (dual-socket / single-socket adaptive), and efficient management. Therefore, there is an urgent need for a dual-redundant server based on the LRM architecture to solve the problems of complex maintenance, low redundancy efficiency, and inflexible configuration of traditional servers. Summary of the Invention

[0004] To overcome the shortcomings of the above technologies, this invention provides a hot-swappable dual-redundant server based on an LRM architecture that combines dual-path redundancy state synchronization, fault switching, and single-path mode adaptive mechanisms.

[0005] The technical solution adopted by this invention to overcome its technical problems is: A hot-swappable dual-redundant server based on LRM architecture includes: The chassis contains a motherboard with N LRM slots. There are N CPU modules. Each CPU module consists of a CPU core, memory that communicates with the CPU core, a control module that is connected to the CPU core, and a hot-swappable module. The CPU modules are installed in the corresponding LRM slots in a hot-swappable manner through the hot-swappable module. The management module communicates with the control modules of N CPU modules via a management bus to monitor the status of each CPU module. The power module supplies power to the corresponding CPU module via the LRM slot; After the server is powered on, it enters the dual-CPU module redundancy mode; When the administrator actively removes any CPU module, or when any CPU module fails or is manually shut down, the system enters single-path mode. The server dynamically adjusts the resource allocation of the CPU module based on the workload.

[0006] Preferably, N is 2.

[0007] Furthermore, the aforementioned N LRM slots are arranged horizontally along the chassis, and each LRM slot integrates a high-speed connector and a management interface. The high-speed connector is a PCIe 5.0 interface and / or an HCCS interface, and the management interface is an I2C interface and / or a serial port.

[0008] Furthermore, the aforementioned control module communicates with the CPU core via GPIO and UART. The hot-swappable module communicates with the CPU core via HCCS, PCIE, and network. The hot-swappable module communicates with the control module via GPIO, UART, IIC, and heartbeat mechanism. The hot-swappable module communicates with the management signal interface of the LRM slot via GPIO, UART, IIC, and heartbeat mechanism, and communicates with the high-speed signal interface of the LRM interface via HCCS, PCIE, and network.

[0009] Furthermore, the aforementioned management module is a BMC chip, which communicates with the control modules of N CPU modules via the IIC bus. The BMC chip monitors the temperature, voltage, and operation logs of each CPU module.

[0010] Furthermore, the aforementioned power module contains N+1 or 2N sub-power supplies, with at least one sub-power supply connected to each LRM slot.

[0011] Furthermore, the method for the server to enter dual-CPU module redundancy mode after power-on is as follows: S1-1. Select two CPU modules as the main CPU and the backup CPU respectively. When the management module detects that the main CPU and the backup CPU are inserted into the corresponding LRM slots through the I2C bus, it sends a reset signal to the main CPU and the backup CPU respectively. The main CPU and the backup CPU synchronize the memory page table, cache data and I / O status in real time through the HCCS bus. The synchronization delay between the main CPU and the backup CPU is ≤1μs. S1-2. The main CPU synchronizes its memory page table, cache data, and PCIe device mapping table to the standby CPU. After synchronization is complete, it enters the business processing state. S1-3. The management module sends heartbeats to the main CPU and the backup CPU every 10ms, and at the same time detects the temperature, voltage and error logs of the main CPU and the backup CPU. The management module monitors the status of the main CPU and the backup CPU through error verification. The self-test unit BIST built into the main CPU and the backup CPU runs periodically to check whether its hardware is abnormal when it starts up. S1-4. When the main CPU experiences a core failure or bus disconnection, the management module suspends all I / O operations of the main CPU, refreshes unfinished cache transactions to shared memory through HCCS, and the standby CPU takes over the memory address space and device mapping of the main CPU. Based on the synchronized state, it continues to process business, updates the routing table of the management module, and directs subsequent requests to the standby CPU. The management module records fault logs and sends them to the operation and maintenance platform through the network. S1-5. After the main CPU is repaired and reinserted into the corresponding LRM slot, the management module detects that the main CPU voltage and temperature are normal. Then, the backup CPU synchronizes the current piling to the main CPU, and the main CPU takes over the business again.

[0012] Furthermore, the method to enter single-path mode is as follows: S2-1. When any CPU module fails, the management module sends a single-path mode instruction to other CPUs. The other CPUs close the redundant cache partition and the synchronization link with the failed CPU module, and close the clock gating of the failed CPU module. S2-2. When a CPU module is manually shut down, the management module sends a single-path mode instruction to other CPUs. The other CPUs then disable the redundant cache partitions and the synchronization link with the shut-down CPU module, and disable the clock gating of the shut-down CPU module. S2-3. When the administrator actively removes any CPU module, the management module sends a single-path mode instruction to other CPUs. The other CPUs then disable the redundant cache partition and the synchronization link with the removed CPU module, and disable the clock gating of the removed CPU module. S2-4. The management module updates the system status page, showing that it is running in single-path mode.

[0013] Furthermore, the method for dynamically adjusting CPU module resource allocation based on business load is as follows: S3-1. The management module collects the load of the CPU module in real time through the CPU module's performance counter; S3-2. When the load of a CPU module exceeds 80%, the management module migrates the light-load tasks of that CPU module to another CPU module. If the remaining CPU modules are also under high load, the management module utilizes the hyper-threading technology or virtualization technology of that CPU module to improve its concurrent processing capabilities. The beneficial effects of this invention are: by realizing hot-swapping of CPU modules through modular LRM slot design, combined with dual-path redundancy state synchronization, fault switching and single-path mode adaptive mechanism, it solves the problems of complex maintenance, low redundancy efficiency and inflexible configuration of traditional servers, and is suitable for high-availability data centers and mission-critical scenarios. Attached Figure Description

[0014] Figure 1 This is a structural diagram of the server of the present invention; Figure 2 This is a structural diagram of the CPU module of the present invention; Figure 3 This is a flowchart illustrating the state synchronization and switching process of the dual-path redundancy mode of the present invention. Figure 4 This is a flowchart of the single-path mode switching process of the present invention. Detailed Implementation

[0015] The following is in conjunction with the appendix Figure 1 To be continued Figure 4 The present invention will be further described below.

[0016] A hot-swappable dual-redundant server based on LRM architecture includes: The chassis contains a motherboard with N LRM slots.

[0017] There are N CPU modules. Each CPU module consists of a CPU core, memory connected to the CPU core, a control module connected to the CPU core, and a hot-swappable module. The CPU modules are installed in the corresponding LRM slots in a hot-swappable manner through the hot-swappable module.

[0018] The management module communicates with the control modules of N CPU modules via a management bus to monitor the status of each CPU module.

[0019] The power module supplies power to the corresponding CPU module via the LRM slot.

[0020] After the server is powered on, it enters the dual-CPU module redundancy mode.

[0021] When the administrator actively removes any CPU module, or when any CPU module fails or is manually shut down, the system enters single-path mode. The server dynamically adjusts the resource allocation of the CPU module based on the workload.

[0022] Rapid replacement is possible without system downtime in case of failure. Real-time status synchronization between dual CPU modules ensures seamless switching to the backup module during failures, resulting in zero service interruption and high efficiency with dual redundancy. The default dual-path mode also supports single-path mode (e.g., if a single CPU module is removed or fails, the remaining module automatically takes over the full load), enabling flexible configuration. A unified management module enables module status monitoring, fault warnings, and dynamic resource allocation, achieving intelligent management.

[0023] In this invention, preferably, N is 2. Preferably, there are two LRM slots, supporting expansion.

[0024] In one embodiment of the present invention, N LRM slots are arranged horizontally along the chassis, and each LRM slot integrates a high-speed connector and a management interface. The high-speed connector is a PCIe 5.0 interface and / or an HCCS interface, and the management interface is an I2C interface and / or a serial port.

[0025] In one embodiment of the present invention, the control module is connected to the CPU core via GPIO and UART, the hot-swappable module is connected to the CPU core via HCCS, PCIE, and network, the hot-swappable module is connected to the control module via GPIO, UART, IIC, and heartbeat mechanism, the hot-swappable module is connected to the management signal interface of the LRM slot via GPIO, UART, IIC, and heartbeat mechanism, and is connected to the high-speed signal interface of the LRM interface via HCCS, PCIE, and network.

[0026] In one embodiment of the present invention, the management module is a BMC chip, which is connected to the control module of N CPU modules via an IIC bus. The BMC chip monitors the temperature, voltage, and operation log of each CPU module.

[0027] In one embodiment of the invention, the power module includes N+1 or 2N sub-power supplies, with at least one sub-power supply connected to each LRM slot. If a single sub-power supply fails, the other CPU modules can still obtain stable power.

[0028] In one embodiment of the present invention, the method for entering the dual-CPU module redundancy mode after the server is powered on is as follows: S1-1. Select two CPU modules as the primary CPU and the backup CPU respectively. When the management module detects that the primary CPU and the backup CPU are inserted into the corresponding LRM slots through the I2C bus, it sends a reset signal to the primary CPU and the backup CPU respectively. The primary CPU and the backup CPU synchronize the memory page table, cache data and I / O status in real time through the HCCS bus. The synchronization delay between the primary CPU and the backup CPU is ≤1μs to ensure that there is no loss of service context during the switch.

[0029] S1-2. The main CPU synchronizes its memory page table, cache data, and PCIe device mapping table to the standby CPU. After synchronization is complete, it enters the business processing state.

[0030] S1-3. The management module sends a heartbeat (0x55AA) to the main CPU and the backup CPU every 10ms. At the same time, it checks whether the temperature of the main CPU and the backup CPU is less than or equal to 95℃, the voltage, and the error log (if the number of ECC error corrections is ≥10 times / minute, an alarm will be triggered). The management module monitors the status of the main CPU and the backup CPU through error verification (such as ECC memory error count, PCIe CRC error). The self-test unit BIST built into the main CPU and the backup CPU runs periodically when it starts up to check whether its hardware is abnormal (such as whether the core is failed or whether the bus is disconnected).

[0031] S1-4. When the main CPU experiences core failure or bus disconnection, the management module detects the loss of the main CPU's heartbeat packet, reads its error log, confirms that the fault type is unrecoverable, and suspends all I / O operations of the main CPU. At this time, the main CPU can be removed at will without affecting the motherboard's operation. Unfinished cache transactions are flushed to shared memory via HCCS. The standby CPU takes over the main CPU's memory address space and device mapping, continues to process business based on the synchronized state, updates the management module's routing table, and directs subsequent requests to the standby CPU. The management module records the fault log and sends it to the operation and maintenance platform via the network.

[0032] S1-5. After the main CPU is repaired and reinserted into the corresponding LRM slot, the management module detects that the main CPU voltage and temperature are normal. Then, the backup CPU synchronizes the current piling to the main CPU, the main CPU takes over the business again, the backup CPU returns to hot standby state, and the system restores the dual-redundancy mode.

[0033] In one embodiment of the present invention, the method for entering single-path mode is as follows: S2-1. When any CPU module fails, the management module sends a single-path mode instruction to other CPUs. The other CPUs disable redundant cache partitions (e.g., release 50% of the L3 cache) and the synchronization link with the failed CPU module (disconnect the HCCS connection with the CPU), and disable the clock gating of the failed CPU module.

[0034] S2-2. When a CPU module is manually shut down, the management module sends a single-path mode instruction to other CPUs. The other CPUs then disable the redundant cache partitions and the synchronization link with the shut-down CPU module, and disable the clock gating of the shut-down CPU module.

[0035] S2-3. When the administrator actively removes any CPU module, the management module sends a single-path mode command to the other CPUs. The other CPUs disable the redundant cache partition and the synchronization link with the removed CPU module, and disable the clock gating of the removed CPU module, but keep the power connection of the CPU connected, so as to quickly restore the dual-path mode.

[0036] S2-4. The management module updates the system status page, showing that it is running in single-path mode.

[0037] In one embodiment of the present invention, the method for dynamically adjusting the resource allocation of the CPU module by the server according to the business load is as follows: The S3-1 management module collects the CPU module's load in real time through its performance counters. The CPU module's load includes CPU utilization, memory bandwidth, and I / O throughput.

[0038] S3-2. When the load of a CPU module exceeds 80%, the management module migrates the light-load tasks of that CPU module to another CPU module. If the remaining CPU modules are also under high load, the hyper-threading technology or virtualization technology of that CPU module is used to improve its concurrent processing capabilities. Light-load tasks include background processes and batch calculations.

[0039] In addition, the number of LRM slots can be increased to achieve horizontal expansion, and newly added CPU modules can be automatically registered to the management module and participate in load balancing.

[0040] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A hot-pluggable dual-redundant server based on LRM architecture, characterized in that, The application relates to a dual-CPU module redundant server. The server comprises a case, a mainboard installed in the case, N LRM slots arranged on the mainboard, N CPU modules, a management module and a power module. Each CPU module is composed of a CPU core, a memory in communication connection with the CPU core, a control module connected with the CPU core and a hot plug module. The management module is in communication connection with the control modules of the N CPU modules through a management bus and is used for monitoring the states of the CPU modules. The power module supplies power for the corresponding CPU modules through the LRM slots. After the server is powered on, the server enters a dual-CPU module redundant mode. When an administrator actively removes any CPU module or any CPU module fails or manually closes a CPU module, the server enters a single-path mode. The server dynamically adjusts resource allocation of the CPU modules according to business load.

2. The hot-pluggable dual-redundant server based on LRM architecture according to claim 1, characterized in that: N is 2.

3. The hot-pluggable dual-redundant server based on LRM architecture according to claim 1, characterized in that: The N LRM slots are arranged transversely along the case, each LRM slot is integrated with a high-speed connector and a management interface, the high-speed connector is a PCIe 5.0 interface and / or an HCCS interface, and the management interface is an I2C interface and / or a serial port.

4. The hot-pluggable dual-redundant server based on LRM architecture according to claim 1, characterized in that: The control module is in communication connection with the CPU core through GPIO and UART, the hot plug module is in communication connection with the CPU core through HCCS, PCIE and network, the hot plug module is in communication connection with the control module through GPIO, UART, IIC and a heartbeat mechanism, the hot plug module is in communication connection with a management signal interface of the LRM slot through GPIO, UART, IIC and the heartbeat mechanism and is in communication connection with a high-speed signal interface of the LRM interface through HCCS, PCIE and network.

5. The hot-pluggable dual-redundant server based on LRM architecture according to claim 1, characterized in that: The management module is a BMC chip, which is in communication connection with the control modules of the N CPU modules through an IIC bus, and the BMC chip monitors the temperature, voltage and running log of each CPU module.

6. The hot-pluggable dual-redundant server based on LRM architecture according to claim 1, characterized in that: The power module comprises N+1 or 2N sub-power supplies, and each LRM slot is connected with at least one sub-power supply.

7. The hot-pluggable dual-redundant server based on LRM architecture according to claim 1, wherein, After the server is powered on, the method for entering the dual-CPU module redundant mode is as follows: S1-1. Two CPU modules are selected as a master CPU and a backup CPU, a reset signal is sent to the master CPU and the backup CPU through an I2C bus when the management module detects that the master CPU and the backup CPU are inserted into corresponding LRM slots, the master CPU and the backup CPU synchronise a memory page table, cache data and I / O states through an HCCS bus in real time, and the synchronisation delay of the master CPU and the backup CPU is less than or equal to 1 mu s; S1-2. The master CPU synchronises a memory page table, cache data and a PCIe device mapping table to the backup CPU, and enters a service processing state after the synchronisation is completed; S1-3. The management module sends a heartbeat to the master CPU and the backup CPU at a period of 10 ms, detects the temperature, voltage and error log of the master CPU and the backup CPU, monitors the states of the master CPU and the backup CPU through error checking, and a built-in self-checking unit BIST of the master CPU and the backup CPU is started to periodically detect whether the hardware is abnormal during operation. S1-4. When the main CPU core fails or the bus is disconnected, the management module suspends all I / O operations of the main CPU, flushes the unfinished cache transactions to the shared memory through the HCCS, the standby CPU takes over the memory address space and device mapping of the main CPU, continues to process the business based on the synchronized state, updates the routing table of the management module, and directs the subsequent request to the standby CPU. The management module records the fault log and sends it to the operation and maintenance platform through the network; S1-5. When the main CPU is repaired and reinserted into the corresponding LRM slot, the management module detects that the voltage and temperature of the main CPU are normal, the standby CPU synchronizes the current stake body to the main CPU, and the main CPU takes over the business again.

8. The hot-pluggable dual-redundant server based on LRM architecture according to claim 1, wherein, The method for entering single-path mode after the server is powered on is: S2-1. When any CPU module fails, the management module sends a single-path mode instruction to the other CPU, the other CPU closes the redundant cache partition and the synchronization link with the failed CPU module, and closes the clock gate of the failed CPU module; S2-2. When manually closing a CPU module, the management module sends a single-path mode instruction to the other CPU, the other CPU closes the redundant cache partition and the synchronization link with the closed CPU module, and closes the clock gate of the closed CPU module; S2-3. When the administrator actively removes any CPU module, the management module sends a single-path mode instruction to the other CPU, the other CPU closes the redundant cache partition and the synchronization link with the removed CPU module, and closes the clock gate of the removed CPU module; S2-4. The management module updates the system status page to display single-path mode running.

9. The hot-pluggable dual-redundant server based on LRM architecture according to claim 1, wherein, The method for dynamically adjusting the resource allocation of the CPU module according to the business load of the server is: S3-1. The management module collects the load of the CPU module in real time through the performance counter of the CPU module; S3-2. When the load of a certain CPU module exceeds 80%, the management module migrates the light load task of the CPU module to another CPU module, and if the remaining CPU modules are also in a high load state, the super-thread technology or virtualization technology of the CPU module is used to improve its concurrent processing capability.

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