Multi-FPGA collaborative high-performance digital signal processing system and health monitoring method thereof

Abstract

The invention discloses a multi-FPGA collaborative high-performance digital signal processing system and a health monitoring method thereof, and belongs to the technical field of digital signal processing. The system comprises a plurality of FPGA processing boards (1) and a chassis (3) which are interconnected through a VPX backboard (2). Each FPGA processing board (1) is integrated with an FPGA chip (11) responsible for core processing and an onboard MCU (12) responsible for system health management. The VPX backboard (2) not only provides inter-board high-speed interconnection (GTY / LVDS), but also provides a synchronous clock for all processing boards through the high-precision crystal oscillator (21) and the clock fan-out chip (22). And the case (3) is integrated with a power supply and a cooling fan. According to the invention, the onboard MCU (12) monitors the voltage and temperature of each processing board in real time, executes accurate power-on time sequence management and abnormal power-off protection, and reports state information through the FPGA chip (11). The problems of low reliability, difficulty in clock synchronization, extensive heat dissipation management and the like of a multi-FPGA system are solved, the stability, availability and maintainability of the system are remarkably improved, and the system is particularly suitable for the high-performance signal processing fields of large-scale MIMO communication, radar and the like.

Description

Technical Field

[0001] This invention belongs to the field of high-performance computing and digital signal processing technology, specifically relating to a multi-FPGA (Field Programmable Gate Array) collaborative processing system based on VPX architecture, and in particular a high-performance digital signal processing module with high reliability, high synchronization accuracy and intelligent health management capabilities. Background Technology

[0002] With the rapid development of technologies in modern communications, radar, electronic warfare, aerospace, and other fields, unprecedented demands have been placed on the processing power, data throughput, and reliability of digital signal processing systems. Applications such as massive MIMO (Multiple-Input Multiple-Output) systems and satellite communication baseband processing often require processing data from hundreds of channels and supporting high-speed fiber optic interfaces of tens of Gbps.

[0003] Currently, using a single high-performance FPGA is insufficient to meet the computing power and I / O requirements of such applications. Therefore, the industry commonly employs an architecture where multiple FPGA boards are interconnected via a backplane to build high-performance processing platforms. However, existing multi-FPGA systems suffer from the following technical challenges: Insufficient system reliability: When multiple FPGA boards work together, there is a lack of system-level health monitoring and a unified fault management mechanism. When a board experiences power failure, overheating, or functional failure, it often leads to the entire system crashing, and fault location is difficult, resulting in poor maintainability.

[0004] Signal integrity challenges: Signal integrity design is crucial when high-speed serial communication (e.g., above 25Gbps) is performed between boards via backplanes. Existing designs often fail to adequately consider PCB (printed circuit board) routing, impedance matching, and clock jitter control, resulting in high bit error rates and poor system stability in high-speed links.

[0005] Low clock synchronization accuracy: Parallel processing of multiple boards requires a high-precision synchronization clock to ensure the timing consistency of data processing. In traditional designs, each board uses an independent clock source, or the clock accuracy distributed from the backplane is insufficient, resulting in large synchronization errors between boards and affecting processing performance.

[0006] Inadequate thermal and power management: Multiple high-performance FPGA boards are integrated in a sealed chassis, resulting in high power density and significant heat dissipation challenges. Existing systems lack sophisticated thermal monitoring and power management, which may lead to localized overheating, resulting in performance degradation or permanent damage to devices.

[0007] Poor maintainability: The system status is not transparent, and when a failure occurs, it requires professional personnel to use specialized tools to troubleshoot for a long time. The mean time to repair (MTTR) is long, which cannot meet the high availability requirements of mission-critical tasks.

[0008] Therefore, there is an urgent need for a multi-FPGA collaborative signal processing system that can solve the above problems and has high reliability, high stability, and high maintainability. Summary of the Invention

[0009] (a) Purpose of the invention This invention aims to overcome the shortcomings of existing technologies and provide a high-performance digital signal processing system with multi-FPGA collaboration. This system achieves high reliability, high synchronization accuracy, and high stability by introducing an onboard intelligent health management unit, a centralized high-precision clock distribution on the backplane, deeply optimized high-speed interconnect channels, and a systematic thermal design.

[0010] Another objective of this invention is to provide a health monitoring method for the above-mentioned system, which enables real-time monitoring, intelligent diagnosis, and proactive protection of power supply, temperature, and functional status, thereby significantly improving the availability and maintainability of the system.

[0011] (II) Technical Solution To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a high-performance digital signal processing system with multi-FPGA collaboration. The system includes: multiple FPGA processing boards, a VPX backplane, and a chassis.

[0012] The VPX backplane is installed inside the chassis, and the multiple FPGA processing boards are plugged into the VPX backplane via standard VPX connectors to form an integrated processing unit.

[0013] The FPGA processing board is the core computing unit of the system, comprising: an FPGA chip as the main processor, used to execute high-speed digital signal processing algorithms; an onboard microcontroller (MCU) as the system's "health manager," communicating with the FPGA chip and specifically used for power timing management, voltage monitoring, temperature monitoring, and abnormal state protection of the FPGA processing board; a high-speed optical communication module, including an integrated high-integration POB optical module and / or a pluggable SFP28 optical module, used to achieve high-speed data exchange with external devices; and memory, such as DDR4 SDRAM, used for large data caching. The VPX backplane not only provides mechanical support and power distribution for each FPGA processing board, but more importantly, it provides high-speed signal interconnection paths between the multiple FPGA processing boards. These paths include a GTY high-speed serial interface, an LVDS differential interface, and an LVTTL single-ended interface, enabling low-latency, high-bandwidth data exchange and control signal transmission between the boards.

[0014] Preferably, the onboard MCU performs the following functions: sequentially controls the enable pins of various power conversion chips of the FPGA chip through its general purpose input / output ports (GPIO) to achieve a strict power-on sequence; periodically samples the key power supply voltage on the FPGA processing board through its internal analog-to-digital converter (ADC); reads data from the onboard temperature sensor through the digital interface; when the voltage or temperature data exceeds a preset safety threshold, the onboard MCU controls the main power supply of the board to be cut off, and sends a message containing fault details to the FPGA chip through the serial peripheral interface (SPI).

[0015] Preferably, the VPX backplane integrates a high-precision crystal oscillator and a clock fan-out chip. The high-precision crystal oscillator generates a reference clock signal. The input terminal of the clock fan-out chip is connected to the high-precision crystal oscillator, and its multiple output terminals are respectively connected to the clock pins of each FPGA processing board slot, thereby synchronously distributing the reference clock signal to all FPGA processing boards. Further, the frequency stability of the high-precision crystal oscillator is better than ±10ppm, for example, a temperature-compensated crystal oscillator with ±2.5ppm is used; the frequency of the reference clock signal is 100MHz or 200MHz.

[0016] Preferably, the VPX backplane supports N (e.g., 8) FPGA processing board slots, which are divided into M (e.g., 2) processing board groups. FPGA processing boards within the same processing board group are interconnected via pre-defined wiring on the VPX backplane to achieve the interconnection of GTY, LVDS, and LVTTL signals, while FPGA processing boards in different processing board groups have no direct signal connection. Each FPGA processing board is interconnected with K other (e.g., 3) processing boards within the same group via the backplane.

[0017] Preferably, the high-speed optical communication module includes a highly integrated optical engine soldered onto the board and / or a panel-pluggable optical module. For example, the highly integrated optical engine is a parallel optical on-board (POB) module that provides multiple (e.g., 12 transmit and 12 receive) parallel fiber optic channels, with a single-channel rate supporting 25.78125 Gbps and backward compatibility; the pluggable optical module is SFP28 sized.

[0018] Preferably, the GTY signal interconnect channel between the FPGA processing board and the VPX backplane has undergone signal integrity design during the PCB design stage, including impedance continuity control, reference plane integrity, crosstalk suppression and loss optimization, and is ensured to work stably at the target rate through simulation and actual measurement.

[0019] Preferably, the chassis is a standard 19-inch 6U forced-air-cooled chassis. It integrates an AC-DC power module, converting AC input to +12V DC and supplying power through the backplane. Multiple cooling fans are installed on the side walls of the chassis, forming a directional airflow channel that runs through the FPGA processing board's heat dissipation fins and the power module. The number of fans, airflow, and airflow layout are determined based on thermal simulation analysis to ensure that the FPGA chip junction temperature and the temperature of key components remain below their maximum allowable values ​​under the highest operating ambient temperature.

[0020] Secondly, the present invention provides a health monitoring method for the above-mentioned system. The method includes the following steps: Power-on and initialization: The onboard MCU performs power-on timing control of the FPGA processing board to ensure that the various power supplies of the FPGA chip (such as core voltage, GTY power supply, and IO power supply) are powered on in the correct order and timing, avoiding latch-up or damage caused by improper power-on sequence.

[0021] Real-time data acquisition: The onboard MCU acquires voltage data (by sampling key power nodes through its internal ADC) and temperature data (by the onboard temperature sensor) from the FPGA processing board in real time.

[0022] Status judgment and threshold comparison: The onboard MCU compares the collected voltage and temperature data with the preset safety threshold.

[0023] Anomaly Protection: If any parameter is detected to exceed the safety threshold, the onboard MCU will immediately trigger the anomaly protection mechanism. This mechanism includes, but is not limited to: cutting off the power supply to this board to prevent the fault from escalating, and reporting detailed anomaly information to the FPGA chip via the SPI interface.

[0024] Information reporting and display: After receiving abnormal information reported by the MCU, the FPGA chip uploads the information to an external host computer through the serial port (such as USB to serial port) on the board panel for real-time display, recording and alarm, which facilitates rapid response by maintenance personnel.

[0025] (III) Beneficial Effects Compared with the prior art, the present invention has the following significant advantages: High reliability and high availability: By introducing an onboard MCU as an independent health monitoring unit, comprehensive monitoring and intelligent protection from power supply and temperature to functional status are achieved. The system has the ability to self-diagnose faults, self-protect, and report status, which greatly reduces the risk of system-wide failure due to a single point of failure and significantly improves the mean time between failures (MTBF).

[0026] Superior signal integrity: For high-speed interconnects with speeds of 25Gbps and above, in-depth signal integrity simulation and optimization were carried out during the PCB design stage (such as impedance control, ground vias, and back-drilling process), and the results were verified by tools such as IBERT (Integrated Bit Error Rate Test) to ensure long-term stable and code-free operation of high-speed links.

[0027] Precise global clock synchronization: High-precision (e.g., ±2.5ppm) clock sources are centrally distributed through the backplane, eliminating synchronization errors caused by differences in clock sources among processing boards, and providing a precise timing reference for multi-board collaborative processing of large-scale parallel data.

[0028] Efficient heat dissipation and power consumption management: Chassis and heat dissipation design based on thermal simulation analysis ensures that the operating junction temperature of core components (such as FPGAs) remains within a safe range even at high ambient temperatures (such as 50°C). Combined with real-time power consumption monitoring, this enables refined management of system energy consumption.

[0029] Excellent maintainability: System status is intuitively presented through indicator lights and a host computer interface, and fault information is accurately located. Hot-swapping of boards is supported, allowing for rapid replacement of faulty boards and significantly reducing the system's mean time to repair (MTTR). Attached Figure Description

[0030] Figure 1 This is a block diagram of the FPGA processing board design in an embodiment of the present invention.

[0031] Figure 2 This is a block diagram of the overall clock design according to an embodiment of the present invention.

[0032] Figure 3 This is a block diagram of the panel interface design in an embodiment of the present invention.

[0033] Figure 4 This is a block diagram of the VPX backplane design in an embodiment of the present invention.

[0034] Figure 5 This is a chassis design dimension drawing in an embodiment of the present invention. Detailed Implementation

[0035] The technical solution of the present invention will now be described in detail.

[0036] Example: A multi-FPGA system for baseband processing in massive MIMO satellite communication This embodiment constructs a signal processing module that includes 8 FPGA processing boards, 1 VPX backplane, and 1 6U rackmount chassis.

[0037] 1. Implementation of FPGA Processing Board FPGA chip: Xilinx Virtex UltraScale+ series XCVU13P-FHGB2104-2-I. This chip provides ample logic resources, DSP units, and up to 76 32.75Gbps GTY transceivers to meet the requirements of high-performance processing and high-speed interface.

[0038] Onboard MCU: STMicroelectronics' STM32F103RBT6 is selected. This MCU controls the enable (EN) pin of the power supply chip via GPIO, strictly adhering to the power-on sequence required by the FPGA manufacturer (e.g., VCCO -> VCCAUX -> VCCINT -> MGTAVCC...) to power the FPGA. Its built-in ADC periodically samples key voltages such as +12V input, +1.8V, +1.0V, and +0.85V (FPGA core voltage), and reads data from the DS18B20 temperature sensor distributed on the board via the I2C interface.

[0039] High-speed optical communication module: Configured with three HTG8532 12-receive / 12-transmit integrated POB optical modules from Xinghang Optoelectronics, providing a total of 36 pairs of 25.78-125Gbps fiber optic channels. Also configured with four SFP28 optical cages, which can accommodate LTF8505 and other optical modules, providing four additional fiber optic interfaces.

[0040] Interconnection interface: Connects to the backplane via VPX connector, providing 30 pairs of GTY, 15 pairs of LVDS and 24 pairs of LVTTL signals for inter-board communication.

[0041] 2. Implementation of VPX Backplane The backplane uses VPX connectors that conform to the VITA 46 standard (such as Gree's VPX20-1111-0004).

[0042] Interconnection Design: The eight slots are divided into two banks (BANK1: SLOT1-4, BANK2: SLOT5-8). The four FPGA processing boards within each bank are connected in pairs via backplane wiring using 10 GTY pairs, 5 LVDS pairs, and 8 LVTTL signals, achieving full interconnection. There are no digital signal connections between the two banks to reduce wiring complexity and signal crosstalk.

[0043] Clock System: The OY2EIBXFM-200M differential crystal oscillator (accuracy ±2.5ppm) from Yangxing Technology is selected as the reference source. Its output 200MHz LVDS clock signal is input to the ADCLK954 clock fan-out chip from Analog Devices. This chip generates 8 channels of 200MHz differential clock at LVPECL level, which are provided to the 8 slots of the FPGA and connected to their global clock (GC) pins.

[0044] 3. Implementation of Chassis and Heat Dissipation The chassis dimensions are 482.6mm (width) × 265.9mm (height) × 380mm (depth).

[0045] Power supply: Built-in Fleck CX18S-ABBBBB-PAF AC-DC power module, input 85~264VAC, output +12V / 1500W, to power the entire system.

[0046] Heat dissipation: Six 6015 DC cooling fans are installed on one side of the chassis, forming a horizontal airflow from left to right. The FPGA processing board adopts a heat-conducting plate design to transfer heat from high-power devices such as the FPGA and optical modules to the heat dissipation fins on the side of the board. Thermal simulation using ANSYS Icepak software confirmed that at an ambient temperature of 50℃ and under full load, the highest FPGA junction temperature is 65.1℃, and the power module temperature is 57.3℃, both lower than their maximum allowable operating temperatures.

[0047] 4. Implementation of health monitoring methods After the system is powered on, the health monitoring process begins: The MCUs on each board enable the power supply on the board according to a preset timing sequence.

[0048] The MCU continuously collects voltage and temperature data.

[0049] Suppose that the MCU on the SLOT3 board detects an abnormal increase in the core voltage from +0.85V to 0.95V (exceeding the threshold of 0.90V).

[0050] The MCU immediately pulls down the enable signals of all power chips, cutting off the power supply to the board.

[0051] At the same time, the MCU sends a fault message to the FPGA chip on this board via the SPI bus, which includes the fault type (abnormal voltage), fault channel (core voltage), and measured value (0.95V).

[0052] Before power loss, the FPGA chip sends the fault information to the connected host computer via a USB-to-serial chip (such as CH340).

[0053] The host computer software interface immediately popped up an alarm, displaying "SLOT3 board core pressure abnormal, protective power-off has been performed", and recorded the log.

[0054] Based on the alarm information, maintenance personnel can accurately locate the faulty board and replace it. The whole process is quick and requires no complicated diagnosis.

[0055] 5. Signal integrity guarantee To ensure the stability of the 25Gbps GTY signal on the VPX connector, several measures were taken during the PCB design phase: Panasonic M7 high-speed board material was used; strict impedance control (100Ω) and equal length design were implemented for the GTY differential lines; ground vias were added on both sides of the traces to reduce crosstalk; and back-drilling was performed on the vias at the connector to eliminate residual stake effects. Simulation optimization was performed using ANSYS HFSS, and actual testing was conducted using a Xilinx IBERT IP core. Long-term testing of the PRBS31 code pattern at a rate of 27.8125Gbps showed a zero bit error rate, verifying the effectiveness of the design.

[0056] In summary, this invention constructs a high-performance, highly reliable, and easy-to-maintain multi-FPGA signal processing platform through intelligent health management with hardware and software collaboration, high-precision clock synchronization at the backplane level, deeply optimized high-speed interconnection, and systematic thermal design. It is particularly suitable for application scenarios with extreme requirements for processing power and reliability.

[0057] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A multi-FPGA cooperative high-performance digital signal processing system, characterized in that, The application relates to a FPGA processing board, which comprises a VPX backboard and a chassis. The FPGA processing board comprises an FPGA chip, a built-in MCU, a high-speed optical communication module and a memory.

2. The multi-FPGA co-syntesized high performance digital signal processing system of claim 1, wherein, The built-in MCU is connected with the FPGA chip and is used for executing power timing management, voltage monitoring, temperature monitoring and abnormal state protection of the FPGA processing board.

3. The multi-FPGA co-syntesized high performance digital signal processing system of claim 1 or 2, wherein, The VPX backboard is integrated with a high-precision crystal oscillator and a clock fan-out chip.

4. The multi-FPGA co-syntesized high performance digital signal processing system of claim 3, wherein, The high-precision crystal oscillator generates a reference clock signal.

5. The multi-FPGA co-syntetic high performance digital signal processing system of claim 1, wherein, The clock fan-out chip distributes the reference clock signal to each FPGA processing board plugged on the VPX backboard to realize clock synchronization among the FPGA processing boards.

6. The multi-FPGA co-syntesized high performance digital signal processing system of claim 5, wherein, The frequency stability of the high-precision crystal oscillator is better than + / -10ppm, preferably + / -2.5ppm. The frequency of the reference clock signal is 200MHz. The high-speed signal interconnection channel provided by the VPX backboard comprises a GTY high-speed serial interface, an LVDS differential interface and an LVTTL single-end interface. The VPX backboard supports eight FPGA processing board slots and is divided into two processing board groups, each of which contains four FPGA processing boards. The FPGA processing boards in the same processing board group are connected through the VPX backboard, and the FPGA processing boards in different processing board groups are not connected.

7. The multi-FPGA co-syntetic high performance digital signal processing system of claim 1, wherein, The high-speed optical communication module (13) comprises an integrated high-integration POB optical module and / or a pluggable SFP28 optical module; the POB optical module provides 36 pairs of high-speed fiber channels, and a single channel rate supports 25.78125 Gbps and is compatible with 8.5 Gbps to 10.3125 Gbps rate; the SFP28 optical module provides 4 pairs of high-speed fiber channels, and a single channel rate supports 25.78125 Gbps and is compatible with 10.3125 Gbps rate.

8. The multi-FPGA co-syntetic high performance digital signal processing system of claim 1, wherein, The cabinet (3) is a 19-inch 6U air-cooled cabinet, and an AC-DC power module (31) and a plurality of cooling fans (32) are integrated in the cabinet (3); the AC-DC power module (31) converts input 220V AC power into +12V DC power, and supplies power to each FPGA processing board (1) through the VPX backplane (2); the air duct formed by the cooling fans (32) is used for forced air cooling of the FPGA processing board (1) and the AC-DC power module (31).

9. A health monitoring method for use with the system of any of claims 1-8, wherein, The method comprises the following steps: The power-on timing control of the FPGA processing board (1) is performed by the on-board MCU (12); the voltage data and the temperature data of the FPGA processing board (1) are collected in real time by the on-board MCU (12); the collected voltage data and temperature data are compared with the preset safety threshold by the on-board MCU (12); if the voltage data or the temperature data exceeds the safety threshold, the on-board MCU (12) triggers an abnormal protection mechanism, the abnormal protection mechanism comprises cutting off the power supply of the FPGA processing board (1), and reporting abnormal information to the FPGA chip (11) through the SPI interface; the abnormal information received by the FPGA chip (11) through the SPI interface is uploaded to the host computer through the serial port for display and recording.

10. The health monitoring method of claim 9, wherein, During the system operation, the method further comprises: performing a self-checking operation on each functional interface by the FPGA chip (11), the functional interface comprising a DDR4 interface, an optical interface and a gigabit network interface; sending the self-checking result to the on-board MCU (12) through the SPI interface by the FPGA chip (11); controlling the state indicator light on the panel of the FPGA processing board (1) according to the received self-checking result by the on-board MCU (12) to indicate "running", "loading complete" and "fault" states.

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