Heterogeneous dual-core-based electric energy meter data interaction system and method

Abstract

The invention relates to the technical field of heterogeneous dual-core chip data interaction, in particular to an electric energy meter data interaction system and method based on heterogeneous dual cores, and the system comprises the steps that a first core exclusively stores peripheral drive control and data reading authority, and after the dual cores are powered on, the first core is started preferentially, loads a drive, reads storage data, stores the data into a memory and sets a first flag bit; the second core is powered on and waits in an operating system level, data is taken to configure a communication peripheral when the first flag bit is detected to be true, and then the flag bit is cleared; the method comprises the steps that dual cores are powered on, a second core waits, a first core starts a loading drive, a data storage memory is read, and a first flag bit is set; a communication peripheral is configured after the second core detects the first core; the communication peripheral receives data and sets a second flag bit, and the first core processes the data and clears the data; if reply is needed, the first core sets a third flag bit, the second core sends the third flag bit, and interaction is repeated. Operation conflicts are avoided, second core code redundancy is reduced, other functions are not affected, and it is guaranteed that interaction is safe and efficient.

Description

Technical Field

[0001] This invention belongs to the field of heterogeneous dual-core chip data interaction technology, specifically relating to a data interaction system and method for electricity meters based on heterogeneous dual-core chips. Background Technology

[0002] As the demands for data processing efficiency and stability from smart metering devices (such as electricity meters) and industrial control terminals continue to increase, heterogeneous dual-core chips, with their advantage of multi-task parallel processing, are gradually becoming the mainstream choice for the core control modules of these devices. However, while heterogeneous dual-core chips are now widely used in the core control modules of these devices, existing heterogeneous dual-core data interaction solutions have significant technical shortcomings in practical applications and cannot meet the core requirements of the devices. Specific problems are as follows: (1) The dual-core's ambiguous division of permissions for storage peripherals leads to strong dependence on the second core, code redundancy, and frequent operation conflicts: In the existing solution, both the first core and the second core have the driver control and data reading permissions for storage peripherals. The second core needs to be adapted separately to the storage peripheral driver to realize data reading, resulting in redundant code and high maintenance costs. At the same time, the parallel operation of the dual cores on storage peripherals is prone to resource conflicts, causing data reading errors or peripheral failures. (2) Design flaws in the core waiting mechanism, which block other application functions of the device: In the existing solution, when one core has not completed the pre-processing tasks such as reading stored data, the other core often adopts the waiting method of occupying computing resources (non-operating system task-level waiting), which causes other key application functions of the device (such as data processing and peripheral monitoring) to be blocked and unable to operate normally; (3) There are no clear rules for the operation of the flag bit in data transmission and reception, which can easily lead to interaction conflicts and data security issues: In the existing solution, there is no fixed "flag bit setting / clearing execution subject" in the process of data transmission and reception of communication peripherals. The operation logic of the dual core on the flag bit and data is chaotic, which can easily lead to problems such as data duplication and loss of reply data. Moreover, the parallel operation of the dual core on data can easily cause conflicts and cannot guarantee the security of data interaction. At the same time, the solution is not flexible enough and it is difficult to adapt to different types of storage peripherals and communication peripherals.

[0003] In view of this, the present invention is hereby proposed. Summary of the Invention

[0004] To address the aforementioned technical problems in the existing technology, this invention provides a data interaction system and method for electricity meters based on heterogeneous dual-core architecture, which solves the problems of peripheral operation conflicts, core code redundancy, waiting and blocking functions, and data interaction insecurity in the existing heterogeneous dual-core data interaction.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows: In the first aspect, a data interaction system for an energy meter based on heterogeneous dual-core includes: a first core, a second core, and storage peripherals; The first core is used to prioritize the startup after the heterogeneous dual-core chip is powered on, load the driver of the storage peripheral, read and store the data in the storage peripheral through the driver, and output the data received by the communication peripheral as needed after the data storage is completed. The second core is used to enter a system-level waiting state after the heterogeneous dual-core chip is powered on. When needed, it configures the parameters of the communication peripheral. After the configuration is completed, it enters a communication peripheral data receiving waiting state. When needed, it retrieves the reply data stored in the peripheral from the first core and transmits it to the communication peripheral. The storage peripheral is used to establish a data interaction link with the first core through a driver, store data for the first core to read, and for the second core to obtain corresponding data through the first core.

[0006] Furthermore, it also includes: A communication peripheral device is used to connect to the second core, receive external data frames, and send response data obtained from the second core. The memory unit is used to associate the first core and the second core, store the data read by the first core from the storage peripheral, and provide the corresponding data to the second core.

[0007] Furthermore, it also includes a first flag bit, a second flag bit, and a third flag bit; After the first core stores the data read from the storage peripheral into the memory unit, it sets the first flag bit. The second core detects the status of the first flag bit in real time. When the first flag bit is detected to be true, it performs the operation of obtaining configuration data from the memory unit and configuring the parameters of the communication peripheral. After the configuration is completed, the first flag bit is cleared. After receiving an external data frame, the communication peripheral sets the second flag bit. The first core detects the status of the second flag bit in real time. When the second flag bit is detected to be true, it performs the operation of outputting the data received by the communication peripheral. After the data output is completed, the second flag bit is cleared. When the first core needs to reply to the outside via a communication peripheral, it sets the third flag. The second core detects the status of the third flag bit in real time. When the third flag bit is detected to be true, it performs the operation of obtaining reply data from the first core and transmitting it to the communication peripheral. After the data transmission is completed, the third flag bit is cleared.

[0008] Furthermore, the storage peripheral includes: EE memory and Dataflash memory; the driver loaded by the first core is used to adapt to the read and write requirements of EE memory and Dataflash memory.

[0009] Furthermore, the data read by the first core from the storage peripheral includes preset configuration parameters of the communication peripheral; The second core performs parameter configuration operations on the communication peripherals based on the preset configuration parameters, ensuring that the configuration parameters of the communication peripherals are consistent with the parameters pre-stored in the storage peripherals.

[0010] Secondly, a data interaction method for electricity meters based on heterogeneous dual-core architecture, used in conjunction with the data interaction system for electricity meters based on heterogeneous dual-core architecture as described in any one of claims 1-6, wherein the data interaction method for electricity meters includes: S1: The first core starts first, and the second core enters a system-level waiting state; S2. After the first core starts up, it loads the driver for the storage peripheral, establishes a data interaction link with the storage peripheral through the driver, reads the pre-stored data in the storage peripheral, and stores the read data. S3. When it is necessary to configure the parameters of the communication peripheral, the second core obtains the reply data stored in the peripheral from the first core, and performs parameter configuration operation on the communication peripheral based on the data. S4. After the second core completes the configuration of the communication peripheral parameters, it enters the communication peripheral data receiving waiting state.

[0011] Furthermore, it also includes: S5. First core outputs data received by communication peripherals: When a communication peripheral receives external data, if further processing of the data is required, the first core will output the data received by the communication peripheral as needed. S6. When it is necessary to send reply data to the outside, the second core obtains the reply data from the first core and transmits the reply data to the communication peripheral, which then completes the external transmission of the reply data.

[0012] Furthermore, it also includes the operation steps for the first flag bit and the second flag bit: In step S2, after the first core stores the read data into the memory unit, it sets the first flag bit. Before setting the first flag bit, the current state of the first flag bit needs to be checked. The setting operation is only performed when the first flag bit is false. In step S3, the criteria for determining when to configure the communication peripheral are as follows: the second core detects that the first flag is true in real time; and the second core clears the first flag after completing the configuration of the communication peripheral parameters; the second core only performs the operation of obtaining data from the first core and configuring the communication peripheral parameters when it detects that the first flag is true.

[0013] Furthermore, step S5 also includes the operation of the second flag bit and the data processing path: after the communication peripheral receives external data, it first sets the second flag bit; when the first core detects that the second flag bit is true, it outputs the data received by the communication peripheral as required, and the output object is the data processing unit; after the first core completes the data output, it clears the second flag bit. Step S6 also includes the operation of the third flag bit: when it is necessary to send reply data to the outside, the first core sets the third flag bit before providing the reply data to the second core; when the second core detects that the third flag bit is true, it then obtains the reply data from the first core; after the second core completes the reply data transmission, it clears the third flag bit.

[0014] Furthermore, after the external transmission of the response data is completed in step S6, steps S5 to S6 are repeated to achieve continuous data interaction between the electricity meter and the outside world.

[0015] Compared with existing technologies, the present invention provides a data interaction system and method for electricity meters based on heterogeneous dual-core architecture. The system includes: a first core, a second core, at least one storage peripheral, at least one communication peripheral, a memory unit, and a data processing unit. The first core exclusively controls the storage peripheral driver and data reading permissions. After power-on, the dual core prioritizes startup and loading the driver, reads and stores data into memory, and sets a first flag. The second core, upon power-on, enters an operating system-level waiting state. When it detects that the first flag is true, it retrieves memory data to configure the communication peripheral, and clears the first flag after configuration. The first, second, and third flags are initially false, ensuring a unique operating entity to prevent conflicts. The method includes: upon power-on, the second core enters a system-level waiting state; the first core prioritizes startup, loading the driver, reads and stores data into memory, and sets the first flag; when the second core detects that the flag is true, it configures the communication peripheral; after receiving data, the communication peripheral sets the second flag, and the first core processes and clears the flag; when a response is needed, the first core sets the third flag, and the second core sends data and clears the flag, repeating this process for continuous interaction. This invention avoids operational conflicts and ensures safe and efficient data interaction for electricity meters. This invention avoids operational conflicts in electricity meter data interaction and reduces code redundancy in the second core by using a first core to exclusively store peripheral driver control and data reading permissions, dual cores to rely on a flag bit that is initially false and the operating subject is unique, and the second core to adopt operating system-level waiting. At the same time, it does not affect other functions and ensures safe and efficient electricity meter data interaction. Attached Figure Description

[0016] Figure 1 This is a structural diagram of the electricity meter data interaction system provided in an embodiment of the present invention; Figure 2 A flowchart of a data interaction method for electricity meters provided in an embodiment of the present invention. Detailed Implementation

[0017] The technical solution of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are not all embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0018] It should be noted that, unless otherwise specifically stated, the relative arrangement and numerical expressions of the components and steps described in these embodiments should not be construed as limiting the scope of the invention.

[0019] The following description of exemplary embodiments is merely illustrative and is not intended to limit the invention or its application or use in any way. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail herein, but where applicable, such techniques, methods, and apparatus should be considered part of this specification.

[0020] The term "EE memory" used in this article refers to Electrically Erasable Programmable Read-Only Memory (EEPROM), which is a system storage peripheral that is adapted to the first core driver and stores data such as preset configuration parameters of communication peripherals for the first core to read in order to support interaction.

[0021] The term "Dataflash memory" used in this article refers to a non-volatile flash memory peripheral that is adapted to the first core driver, stores business data such as historical interaction records, and provides data support for data interaction.

[0022] The term "OS task level" used in this article refers to the task waiting mode of the heterogeneous dual-core chip operating system, in which the second core does not occupy exclusive resources and does not affect other application functions of the chip.

[0023] The term "AMP approach" used in this article refers to the existing asymmetric multiprocessing and multicore collaboration model, which has fixed core tasks, simple interaction, and poor peripheral compatibility.

[0024] Example 1 See Figure 1 , Figure 1 The present invention provides an architecture diagram of a data interaction system for an energy meter based on a heterogeneous dual-core architecture, comprising: a first core, a second core, at least one storage peripheral, at least one communication peripheral, a memory unit, and a data processing unit. M1, the first core, is used to prioritize startup after the heterogeneous dual-core chip is powered on, load the driver program of the storage peripheral, read and store the data in the storage peripheral through the driver program, and output the data received by the communication peripheral as needed after the data storage is completed. Specifically, the driver for the storage peripheral is loaded, the data in the storage peripheral is read through the driver and stored in the memory unit, the first flag is set after the data storage is completed, the second flag is detected and the data received by the communication peripheral is transmitted to the data processing unit when the second flag is true, the second flag is cleared after the data transmission is completed, and the third flag is set when data needs to be replied through the communication peripheral.

[0025] The first core has exclusive access to the drive control and data read permissions of the storage peripherals; the initial state of the first flag, the second flag, and the third flag are all false; only the first core is allowed to set the first and third flags and clear the second flag, only the second core is allowed to clear the first and third flags, and only the communication peripherals are allowed to set the second flag.

[0026] M2, the second core, is used to enter a system-level waiting state after the heterogeneous dual-core chip is powered on. When needed, it configures the parameters of the communication peripheral. After the configuration is completed, it enters a communication peripheral data receiving waiting state. When needed, it obtains the reply data stored in the peripheral from the first core and transmits it to the communication peripheral. Specifically, the system continuously monitors the first and third flag bits. When the first flag bit is true, it retrieves data from the memory unit and configures the parameters of the communication peripheral. After configuration, it clears the first flag bit and enters a data reception waiting state for the communication peripheral. When the third flag bit is true, it retrieves reply data from the first core and transmits it to the communication peripheral. After data transmission is complete, it clears the third flag bit. The second core does not participate in the driver control and data reading operations of the storage peripheral.

[0027] M3 is a storage peripheral used to establish a data interaction link with the first core through a driver, store data for the first core to read, and for the second core to obtain corresponding data through the first core.

[0028] Specifically, the storage peripherals include: EEE memory, Dataflash memory and other storage devices; and the driver loaded by the first core is used to adapt to the read and write requirements of EEE memory, Dataflash memory and other storage devices.

[0029] The first core reads data from the storage peripheral containing the preset configuration parameters of the communication peripheral; the second core performs parameter configuration operations on the communication peripheral based on the preset configuration parameters, ensuring that the configuration parameters of the communication peripheral are consistent with the parameters pre-stored in the storage peripheral.

[0030] M4, a communication peripheral, is used to connect to the second core, receive external data frames and set the second flag bit, and send reply data transmitted by the second core.

[0031] M5, a memory unit, is used to associate the first core and the second core, storing data read by the first core from storage peripherals for the second core to access.

[0032] M6, Data Processing Unit, is used to connect to the first core, receive and process communication peripheral data transmitted by the first core.

[0033] Example 2 See Figure 2 , Figure 2 This is a flowchart of a data interaction method for electricity meters based on heterogeneous dual-core proposed in this invention. The specific steps include: S1: The first core starts first, and the second core enters a system-level waiting state; Specifically, when the heterogeneous dual-core chip is powered on, the second core enters a system-level waiting state (this waiting state does not occupy the exclusive resources of the heterogeneous dual-core chip, and does not affect the normal operation of other application functions in the heterogeneous dual-core chip except for data interaction), and the first core prioritizes starting up and loading the driver for the storage peripherals. S2. After the first core starts up, it loads the driver for the storage peripheral, establishes a data interaction link with the storage peripheral through the driver, reads the pre-stored data in the storage peripheral, and stores the read data. Specifically, the first core reads data from the storage peripheral through the loaded driver and stores the read data in the memory unit; before setting the first flag, it checks the current state of the first flag and only sets the first flag when the first flag is false. S3. When it is necessary to configure the parameters of the communication peripheral, the second core obtains the reply data stored in the peripheral from the first core, and performs parameter configuration operation on the communication peripheral based on the data. Specifically, the second core detects the first flag bit in real time. Only when the first flag bit is detected to be true does it obtain data from the memory unit and configure the parameters of the communication peripheral based on the data. After the configuration is completed, the second core clears the first flag bit and enters the communication peripheral data receiving waiting state to avoid conflicting operations between the two cores on the first flag bit and the associated memory data. S4. After the second core completes the configuration of the communication peripheral parameters, it enters the communication peripheral data receiving waiting state.

[0034] Specifically, when the communication peripheral receives an external data frame, it sets the second flag bit (the setting operation of the second flag bit is only performed by the communication peripheral); when the first core detects that the second flag bit is true, it transmits the data received by the communication peripheral to the data processing unit for processing. After the data processing is completed, the first core clears the second flag bit (the clearing operation of the second flag bit is only performed by the first core). S5. First core outputs data received by communication peripherals: When a communication peripheral receives external data, if further processing of the data is required, the first core will output the data received by the communication peripheral as needed. Specifically, if the processing result of the data processing unit needs to be replied to the outside through the communication peripheral, the first core sets the third flag bit (the setting operation of the third flag bit is only performed by the first core); when the second core detects that the third flag bit is true, it obtains the reply data from the first core and transmits it to the communication peripheral to complete the transmission. After the transmission is completed, the second core clears the third flag bit (the clearing operation of the third flag bit is only performed by the second core). The operation and data processing path of the second flag bit: After the communication peripheral receives external data, it first sets the second flag bit; when the first core detects that the second flag bit is true, it outputs the data received by the communication peripheral as required, and the output object is the data processing unit; after the first core completes the data output, it clears the second flag bit. The operation steps of the third flag bit are as follows: When it is necessary to send reply data to the outside, the first core sets the third flag bit before providing the reply data to the second core; when the second core detects that the third flag bit is true, it then obtains the reply data from the first core; after the second core completes the reply data transmission, it clears the third flag bit.

[0035] S6. When it is necessary to send response data to the outside, the second core obtains the response data from the first core and transmits the response data to the communication peripheral, which then completes the external transmission of the response data. After the external transmission of the response data is completed, steps S5 to S6 are repeated to achieve continuous data interaction between the energy meter and the outside world.

[0036] In summary, the present invention has the following advantages: 1. The first core exclusively controls and reads data from the storage peripheral, and uses a data loading completion flag to indicate memory availability. The second core does not participate in storage peripheral operations. This solves the problems of the second core depending on the storage peripheral, code redundancy, and dual-core operation conflicts. It also reduces the amount of code in the second core, lowers maintenance costs, and avoids storage peripheral conflicts. 2. By using the second core to wait for the data loading completion flag at the OS task level, and with closed-loop control of the flag bit, the problems of waiting occupying resources and blocking other functions, as well as dual-core operation conflicts, are resolved; the operation of other applications on the chip is not affected, and the orderly configuration of peripherals is ensured. 3. Through dedicated operations for receiving / sending flags, it resolves data transmission and reception conflicts, data loss / duplication issues, and ensures data interaction security, making it more flexible and versatile than the AMP method.

[0037] The above specific embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A power meter data interaction system based on heterogeneous dual-core, characterized in that, Comprise: The first core, the second core and the storage peripheral device; The first core is used for starting preferentially after the power-on of the heterogeneous dual-core chip, loading the driver program of the storage peripheral device, reading the data in the storage peripheral device through the driver program and storing, and outputting the data received by the communication peripheral device according to the need after the data storage is completed; The second core is used for entering the system-level waiting state after the power-on of the heterogeneous dual-core chip, performing the parameter configuration on the communication peripheral device when needed, entering the communication peripheral device data reception waiting state after the configuration is completed, and obtaining the reply data in the storage peripheral device from the first core and transmitting to the communication peripheral device when needed; The storage peripheral device is used for establishing the data interaction link with the first core through the driver program, storing the data for the first core to read, and obtaining the corresponding data for the second core through the first core.

2. The isomeric dual-core based data interaction system for electric energy meter according to claim 1, characterized in that, Further comprise: The communication peripheral device is used for connecting with the second core, receiving the external data frame, and sending the reply data obtained from the second core; The memory unit is used for associating the first core and the second core, storing the data read by the first core from the storage peripheral device, and the corresponding data is obtained by the second core.

3. The isomeric dual-core based data interaction system for electric energy meter as claimed in claim 1, wherein, Further comprise the first flag bit, the second flag bit and the third flag bit, and; The first core sets the first flag bit after storing the data read from the storage peripheral device to the memory unit; The second core detects the state of the first flag bit in real time, when detecting that the first flag bit is true, executes the operation of obtaining the configuration data from the memory unit and performing the parameter configuration on the communication peripheral device, and clears the first flag bit after the configuration is completed; The communication peripheral device sets the second flag bit after receiving the external data frame; The first core detects the state of the second flag bit in real time, when detecting that the second flag bit is true, executes the operation of outputting the data received by the communication peripheral device, and clears the second flag bit after the data output is completed; The first core sets the third flag bit when it needs to reply data to the outside through the communication peripheral device; The second core detects the state of the third flag bit in real time, when detecting that the third flag bit is true, executes the operation of obtaining the reply data from the first core and transmitting to the communication peripheral device, and clears the third flag bit after the data transmission is completed.

4. The isomeric dual-core based data interaction system for electric energy meter according to claim 1, characterized in that, The storage peripheral device comprises: EE memory and Dataflash memory; the driver program loaded by the first core is used for adapting the read-write requirement of the EE memory and the Dataflash memory.

5. The heterogeneous dual-core based electric energy meter data interaction system according to claim 1, characterized in that, The data read by the first core from the storage peripheral device contains the preset configuration parameters of the communication peripheral device; The parameter configuration operation of the second core on the communication peripheral device is executed based on the preset configuration parameters, ensuring that the configuration parameters of the communication peripheral device are consistent with the pre-stored parameters in the storage peripheral device.

6. A method for data interaction of an electricity meter based on a heterogeneous dual-core, characterized in that, The electric energy meter data interaction method is used in cooperation with the heterogeneous dual-core based electric energy meter data interaction system of any one of claims 1-6, comprising: S1, the first core starts preferentially, and the second core enters the system-level waiting state; S2, after the first core is started, the driving program of the storage peripheral is loaded, the data interaction link is established with the storage peripheral through the driving program, the pre-stored data in the storage peripheral is read, and the read data is stored; S3, when the parameter configuration of the communication peripheral is needed, the second core obtains the reply data in the storage peripheral from the first core, and performs the parameter configuration operation on the communication peripheral based on the data; S4, after the second core completes the parameter configuration of the communication peripheral, the communication peripheral data receiving waiting state is entered.

7. The isomeric dual-core based data interaction system for electric energy meter as claimed in claim 6, wherein, Further comprising: S5, the first core outputs the communication peripheral receiving data: when the communication peripheral receives external data, if subsequent processing of the data is needed, the first core outputs the data received by the communication peripheral according to the requirement; S6, when the reply data needs to be sent to the outside, the second core obtains the reply data from the first core, and transmits the reply data to the communication peripheral, so that the external sending of the reply data is completed by the communication peripheral.

8. The method for data interaction of the isomerous dual-core based electric energy meter according to claim 6, characterized in that, Further comprising the operation steps of the first flag bit and the second flag bit: In step S2, after the first core stores the read data in the memory unit, the first flag bit is set; before setting the first flag bit, the current state of the first flag bit needs to be detected, and only when the first flag bit is false, the setting operation is executed; In step S3, the judgment basis when the parameter configuration of the communication peripheral is needed is that the second core detects that the first flag bit is true in real time; and the first flag bit is cleared after the second core completes the parameter configuration of the communication peripheral; the second core only executes the data acquisition from the first core and the parameter configuration of the communication peripheral when it detects that the first flag bit is true.

9. The method for data interaction of the isomerous dual-core based electric energy meter according to claim 7, characterized in that, In step S5, the operation of the second flag bit and the data processing path are further included: after the communication peripheral receives external data, the second flag bit is first set; when the first core detects that the second flag bit is true, the data received by the communication peripheral is output according to the requirement, and the output object is the data processing unit; After the first core completes the data output, the second flag bit is cleared; Further comprising the operation steps of the third flag bit: when the reply data needs to be sent to the outside, the first core sets the third flag bit before providing the reply data to the second core; the second core detects that the third flag bit is true, and then obtains the reply data from the first core; after the second core completes the transmission of the reply data, the third flag bit is cleared.

10. The method for data interaction of the isomerous dual-core based electric energy meter according to claim 7, characterized in that, After the external sending of the reply data is completed in step S6, steps S5 to S6 are repeatedly executed to realize the continuous data interaction between the electric energy meter and the outside.

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