Spin computing unit, reconfigurable ising machine and chip based on fefet

Abstract

The application relates to the technical field of integrated circuit design, and discloses a spin computing unit based on FeFET, a reconfigurable Ising machine and a chip. The spin computing unit is constructed by two N-type FeFET transistors M1-M2 to form an XNOR cell, and is programmed into four states to adapt to different parameters of the Ising model, and the spin independent variable of the Ising model is input in the form of a bit line input, so that the spin effective field is simulated in the form of voltage sharing through bit line charging and discharging, thereby supporting the construction of the reconfigurable Ising machine through a mapping method. The application is provided with a capacitor CAP for each XNOR cell, and the capacitor CAP is separated from an output bus ScL by using a transmission gate Gate, so that the output result of each row is controlled by each XNOR cell to keep or release the electric charge of the capacitor CAP, and finally, the electric charge is shared to obtain, thereby greatly improving the linearity and working stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and more particularly, to: 1. a spin computing unit based on FeFET; 2. a reconfigurable Ising machine constructed based on spin computing; 3. a CIM chip adopting a circuit layout of the spin computing unit based on FeFET or a circuit layout of the reconfigurable Ising machine constructed based on spin computing. BACKGROUND

[0002] The Ising machine is a new type of computing architecture constructed based on the Ising model, which can gradually converge the system energy to the ground state through simulating the spin interaction and annealing process, and thus obtain an optimized solution, thereby providing a new way for quickly solving the combinatorial optimization problem and the quadratic unconstrained binary optimization (QUBO) problem.

[0003] The Ising machine can be divided into two categories according to the hardware topology structure: 1. a locally connected Ising machine; and 2. a fully connected Ising machine. For the locally connected Ising machine, although it can achieve convenient expansion by means of interconnection between chips, it lacks flexibility when embedding more extensive combinatorial optimization problems (COP), and it is generally implemented in the form of an iterative Ising machine, which has the disadvantage of high hardware overhead. SUMMARY

[0004] Therefore, it is necessary to provide a reconfigurable Ising machine and a chip constructed based on spin computing in order to solve the problems of the existing locally connected Ising machine, such as lack of flexibility and high hardware overhead.

[0005] The present application adopts the following technical solutions:

[0006] In a first aspect, the present application provides a spin computing unit based on FeFET, which comprises: 2 N-type FeFET transistors M1-M2, 1 capacitor CAP, and 1 transmission gate Gate.

[0007] The gate of M1 is connected with a bit line BL; the gate of M2 is connected with a bit line BLB; the drain of M1 and the drain of M2 are connected together and connected with a word line WL; the source of M1, the source of M2, and the upper plate of CAP are connected together; the lower plate of CAP is grounded GND; the C control end of Gate is connected with a control signal SW, the C reverse control end is connected with a control signal SWB, the input end is connected with the upper plate of CAP, and the output end is connected with an output bus ScL.

[0008] BL and BLB are used for inputting spin independent variables of the Ising model; when the spin independent variable is +1, BL is connected with a power supply VDD and BLB is connected with GND; when the spin independent variable is -1, BL is connected with GND and BLB is connected with VDD.

[0009] M1, M2 constitute a XNOR unit; when storing the coupling coefficient of the Ising model, and not the correction row, XNOR is a 1 or 0 state; when storing the external magnetic field strength of the Ising model, and not the correction row, XNOR is a constant 1 or 0 state; when storing the irrelevant state, XNOR is a constant 0 state; when it is a correction row, XNOR is a 0 state.

[0010] The implementation of the spin computing unit based on the FeFET is realized according to the method or process of the embodiment of the present disclosure.

[0011] In a second aspect, the present application discloses a reconfigurable Ising machine constructed based on spin computing, which comprises a storage array, an analog-to-digital converter, and an addition tree.

[0012] The storage array comprises: M The column N The spin computing unit based on the FeFET disclosed in the first aspect is distributed in rows; the spin computing units in the same row share the same WL, the same ScL, and the same S3; the spin computing units in the same column share the same BL and the same BLB.

[0013] The ScL of each row is connected to the addition tree through the analog-to-digital converter, for quantization and weighting to obtain the spin effective field of the Ising model, and further to obtain the current solution of the spin dependent variable.

[0014] The implementation of the reconfigurable Ising machine constructed based on spin computing is realized according to the method or process of the embodiment of the present disclosure.

[0015] In a third aspect, the present application discloses a CIM chip adopting the circuit layout of the spin computing unit based on the FeFET disclosed in the first aspect, or adopting the circuit layout of the reconfigurable Ising machine constructed based on spin computing disclosed in the second aspect.

[0016] The implementation of the CIM chip is realized according to the method or process of the embodiment of the present disclosure.

[0017] Compared with the prior art, the present application has the following beneficial effects:

[0018] 1. The present application provides a spin computing unit based on FeFET, which adopts two N-type FeFET transistors M1-M2 to construct an XNOR unit, and supports programming into four states to adapt to the storage of different parameters of the Ising model, and further inputs the spin independent variable of the Ising model through the bit line input mode, so as to simulate the spin effective field through the voltage sharing mode of the bit line charge and discharge, thereby supporting the construction of a reconfigurable Ising machine through a mapping method.

[0019] 2. The application is equipped with a capacitor CAP for each XNOR unit, and uses a transmission gate Gate to separate from the output bus ScL, so that each row of output results controls the capacitor CAP of each XNOR unit to charge or release, and finally obtains charge sharing, greatly improving the linearity and working stability.

[0020] 3. The application provides a reconfigurable Ising machine constructed based on spin calculation, which can be flexibly programmed according to the Ising model to be mapped to match the required storage, support the mapping of complex irregular spin networks, support the simultaneous calculation of the interaction relationship of multiple spins, effectively reduce the timing overhead; and because the array is built by using FeFET transistors, the hardware overhead can be further reduced, and the read-write consumption can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0022] Figure 1 The spin network example diagram of the Ising model provided by the present application;

[0023] Figure 2 The architecture diagram of the reconfigurable Ising machine constructed based on spin calculation provided by embodiment 1 of the present application;

[0024] Figure 3 The working principle diagram of the XNOR unit XNOR in the spin calculation unit of Figure 1 The structure diagram of the spin calculation unit based on FeFET in the present application;

[0025] Figure 4 The working principle diagram of the XNOR unit XNOR in the spin calculation unit of Figure 3 The working principle diagram of the XNOR unit XNOR in the spin calculation unit of

[0026] Figure 5 The working principle diagram of the XNOR unit XNOR in the spin calculation unit of Figure 3 The working principle diagram of the XNOR unit XNOR in the spin calculation unit of

[0027] Figure 6 The working principle diagram of the XNOR unit XNOR in the spin calculation unit of Figure 3 The working principle diagram of the XNOR unit XNOR in the spin calculation unit of

[0028] Figure 7 The working principle diagram of the XNOR unit XNOR in the spin calculation unit of Figure 3 The working principle diagram of the XNOR unit XNOR in the spin calculation unit of

[0029] Figure 8 for Figure 2 A schematic diagram showing how the storage array is divided into Y+1 rows;

[0030] Figure 9 for Figure 1 A schematic diagram of the Ising model mapped to a reconfigurable Ising machine. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] First, it should be noted that the reconfigurable Ising device designed in this invention is based on the Ising model. It spontaneously solves the Hamiltonian of the Ising model by mapping the combinatorial optimization problem based on the circuit structure (designed according to the formula of the Ising model), and realizes the spin flipping, continuously iterating the calculation to reach the minimum energy state of the system.

[0035] Specifically, for the Ising model, its overall Hamiltonian is expressed as:

[0036] ;

[0037] In the formula, H σ Denotes the overall Hamiltonian of the Ising model; σ i Indicates the first i The spin values ​​at each lattice point (i.e., as spin dependent variables); σj represents the spin value at the j th lattice point (i.e., as a spin independent variable); J i,j represents the coupling strength between the spin at the i th lattice point and the spin at the j th lattice point (also referred to as a coupling coefficient); h i represents the external magnetic field strength at the i th lattice point (also referred to as an external magnetic field parameter).

[0038] Then, the Hamiltonian corresponding to the i th spin is represented as:

[0039]

[0040] In the formula, represents the Hamiltonian corresponding to the i th spin; S i represents the effective field (referred to as a spin effective field) to which the spin at the i th lattice point is subjected.

[0041] wherein, σ i satisfies:

[0042] .

[0043] That is, the minimum value to be solved is the minimum value of H σ .

[0044] In addition, in order to avoid falling into a local minimum value, a judgment probability P i may be added to determine a new solution of σ i :

[0045] According to P i , 1 or 0 is generated; if 1 is generated, it indicates that the current solution of σ i falls within P i , and the opposite value of the current solution of σ i is taken as the new solution of σ i ; if 0 is generated, the current solution of σ i is not within P i , and the current solution of σ ​​i The current solution is as σ i A new interpretation.

[0046] in, P i The data formula is: ; σ i,now express σ i The current solution; T This indicates the current temperature.

[0047] For easier understanding, please refer to Figure 1 It provides a specific example of the Ising model, which takes the form of a spin network, consisting of 6 lattice points; each lattice point has 1 spin.

[0048] like Figure 1 As shown, with σ 1. Those exhibiting spin relationships include: σ 4. σ 6; That is to say, σ When 1 is used as the spin dependent variable, its spin independent variables are: σ 4. σ 6.

[0049] and σ 2. Those exhibiting spin relationships include: σ 3. σ 4. σ 5. σ 6; That is to say, σ When 2 is used as the spin dependent variable, its spin independent variables are: σ 3. σ 4. σ 5. σ 6.

[0050] and σ 3. Those exhibiting spin relationships include: σ 2. σ 6; That is to say, σ When 3 is used as the spin dependent variable, its spin independent variables are: σ 2. σ 6.

[0051] and σ 4. Those exhibiting spin relationships include: σ 1. σ 2. σ 5; that is to say, σ When 4 is used as the spin dependent variable, its spin independent variables are: σ 1. σ 2. σ 5.

[0052] With σ 5 there are spin relationships: σ 2, σ 4; that is, σ 5 as spin dependent variable, its spin independent variable has: σ 2, σ 4.

[0053] With σ 6 there are spin relationships: σ 1, σ 2, σ 3; that is, σ 6 as spin dependent variable, its spin independent variable has: σ 1, σ 2, σ 3.

[0054] In general, different Ising models have different spin networks, and whether there is a connection between the spins is also different.

[0055] Embodiment 1

[0056] Referring to the above, . That is, S i contains J i,j , σ j , h i There are three types of objects, and there are products, accumulations, and additions.

[0057] In general, the reconfigurable Ising device of the present application, on the one hand, constructs a coefficient storage unit with the same circuit structure but programmable state to store J i,j , h i , on the other hand, σ j as an external input, so as to realize S i by charging and discharging in the form of voltage sharing, and then through subsequent analog-to-digital conversion and addition tree to realize quantization, and then determine positive and negative, and if necessary, through the voter to simulate P to determine the new solution of Figure 2 i .

[0058] Therefore, based on the above mechanism, referring to Figure 3 , the present embodiment 1 provides a circuit structure diagram of a reconfigurable Ising machine constructed based on spin calculation, which comprises: a storage array, an analog-to-digital converter, and an addition tree; and can further comprise: a voter.

[0059] The following will be introduced in detail:

[0060] (I) the storage array includes: M Column N Row distribution of FeFET-based spin computing unit.

[0061] It should be noted that, in order to distinguish with the subsequent coefficient storage part of the array distribution, this N Row is called N Small row.

[0062] Referring to Figure 4 , the FeFET-based spin computing unit is specifically designed to include: 2 N-type FeFET transistors M1-M2, 1 capacitor CAP, 1 transmission gate Gate; It can also include: 1 pre-charge tube PMOS S3.

[0063] The circuit connection relationship is as follows:

[0064] The gate of M1 is connected with the bit line BL; the gate of M2 is connected with the bit line BLB; the drain of M1 and the drain of M2 are connected together and connected with the word line WL; the source of M1, the source of M2 and the upper plate of CAP are connected together; the lower plate of CAP is grounded GND. The C control end of Gate is connected with the control signal SW, the C reverse control end is connected with the control signal SWB, the input end is connected with the upper plate of CAP, and the output end is connected with the output bus ScL. The gate of S3 is connected with the enable signal EN, the drain is connected with ScL, and the source is connected with the power supply VDD.

[0065] Wherein, when SW is 1 and SWB is 0, Gate is turned on, and CAP is connected with ScL; when SW is 0 and SWB is 1, Gate is turned off, and CAP is disconnected with ScL. When EN is 0, S3 is turned on, and VDD is connected with ScL; when EN is 1, S3 is turned off, and VDD is disconnected with ScL.

[0066] In this way, through the cooperation control of Gate and S3, the pre-charge of CAP and the subsequent charge sharing on ScL after discharge are realized.

[0067] It should be noted that Gate and S3 can also be designed with other gating switches, but they need to meet the corresponding control timing requirements.

[0068] Both M1 and M2 are N-type FeFET transistors, which can be programmed to either a high-resistance or low-resistance state. Taking M1 as an example: if BL is set to the programming voltage V1, the threshold voltage of M1 is adjusted to the low threshold LVT, and M1 is in a low-resistance state; if BL is set to the programming voltage V0, the threshold voltage of M1 is adjusted to the high threshold HVT, and M1 is in a high-resistance state; V0 < V1; LVT < VDD < HVT. The situation for M2 is similar and will not be repeated here.

[0069] It should be noted that for N-type FeFET transistors in the low-resistivity state, they can be turned on when VDD is applied to the gate and turned off when GND is applied; for N-type FeFET transistors in the high-resistivity state, they will not be turned on regardless of whether VDD or GND is applied to the gate.

[0070] Therefore, M1 and M2 form an XNOR unit, which can be programmed into 4 states:

[0071] ①, such as Figure 5 The diagram shows a stored state (corresponding to M1 being programmed as low resistance and M2 as high resistance). Therefore, after the upper plate of CAP is pre-charged to VDD, XNOR will be activated when BL is VDD and BLB is GND; if WL is connected to GND, CAP will discharge to GND; and when BL is GND and BLB is VDD, XNOR will not be activated, and CAP will always maintain a constant VDD.

[0072] ②, such as Figure 6 The state shown is 0 (corresponding to M1 being programmed as high resistance and M2 as low resistance). Therefore, after the upper plate of CAP is pre-charged to VDD, XNOR will be turned on when BL is GND and BLB is VDD; if WL is connected to GND, CAP will discharge to GND; and when BL is VDD and BLB is GND, XNOR will not be turned on, and CAP will always maintain a constant VDD.

[0073] ③, such as Figure 7 The constant state shown corresponds to when M1 and M2 are programmed to be in a low-resistance state. Therefore, after the upper plate of CAP is pre-charged to VDD, XNOR will be turned on when BL is VDD and BLB is GND; XNOR will not be turned on when BL is GND and BLB is VDD; if WL is connected to GND, CAP will discharge to GND.

[0074] ④, such as Figure 8 The constant 0 state shown corresponds to when M1 and M2 are programmed as high resistance. Therefore, after the upper plate of CAP is pre-charged to VDD, XNOR will not be turned on when BL is GND and BLB is VDD; XNOR will also not be turned on when BL is VDD and BLB is GND; CAP always keeps VDD constant.

[0075] In summary, the XNOR will perform a XOR calculation according to its own programming state and input to determine whether the CAP is discharged.

[0076] Based on the above structure of the FeFET-based spin computing unit, on the one hand, different parameters of the Ising model are supported to be stored: when the coupling coefficient of the Ising model is stored and is not a correction row, the XNOR is in a 1 or 0 state; when the external magnetic field strength of the Ising model is stored and is not a correction row, the XNOR is in a constant 1 or 0 state; when the irrelevant state is stored, the XNOR is in a constant 0 state; when it is a correction row, the XNOR is in a 0 state (the correction row is introduced to ensure the correctness of the subsequent calculation, which will not be expanded here); on the other hand, the spin independent variable of the Ising model is input through BL and BLB: when the spin independent variable is +1, BL is connected to the power supply VDD and BLB is connected to GND; when the spin independent variable is -1, BL is connected to GND and BLB is connected to VDD. And since it is based on FeFET transistor, it can further reduce hardware overhead and reduce read-write consumption.

[0077] Then, the storage array can be flexibly programmed to match the corresponding required storage, thereby adapting to different Ising models and realizing the mapping of complex irregular spin networks:

[0078] For the Ising model, there are X lattice points, and each lattice point has 1 spin, so the storage array satisfies: N = X , M = N ×( Y +1); Y represents the number of bits of the storage object; the storage object is the coupling coefficient or the external magnetic field strength.

[0079] In the storage array, every Y +1 small row in each column from top to bottom is a coefficient storage part of 1 storage object, forming a X column X row distribution. It should be noted that, in order to distinguish from the array distribution of the spin computing unit above, the X row here is called X large row— that is, each large row contains six small rows.

[0080] It should be noted that the coefficient storage part is divided because: since the coupling coefficient and the external magnetic field strength are generally stored in the form of a complement, at least Yspin calculation unit; since the spin calculation unit is to perform XOR calculation, and in the complement operation: if the complement and 1 perform XOR calculation, the result is unchanged; but the complement and 0 perform XOR calculation, then the result needs to be added 1 to be the correct result; therefore, an additional correction row needs to be set to add 1 for the case of input 0.

[0081] Then refer to σ , that is: the first small row in each coefficient storage part is the correction row, and the remaining Y small rows correspond to the storage of the corresponding storage object Y bit by bit from bottom to top - that is, the Y +1 small row stores the first bit of the corresponding storage object, the Y small row stores the second bit of the corresponding storage object, and so on, until the second small row stores the Y bit of the corresponding storage object.

[0082] Then, the storage and input of the storage array are specifically as follows:

[0083] If the spin at the i th lattice point and the spin at the j th lattice point do not exist spin connection, then the coefficient storage part located at the i th large row and the j th column is used to store the irrelevant state (which can be represented by D) - that is, the XNOR of the Y +1 spin calculation units inside it are all programmed to a constant 0 state; i , j ∈[1, X ]; i ≠ j .

[0084] If the spin at the i th lattice point and the spin at the j th lattice point exist spin connection, then the coefficient storage part located at the i th large row and the j th column is used to store the coupling strength J i,j between the spin at the i th lattice point and the spin at the j th lattice point - that is, in its Y +1 spin calculation units, the XNOR corresponding to the correction row is programmed to a store 0 state, and the remaining Y small rows are programmed to a store 1 or store 0 state according to the 1 or 0 state of each bit of J i,j .

[0085] The coefficient storage part located at the i th large row and the iThe coefficient storage unit of the column is used to store the external magnetic field intensity of the first i h i — that is, in its interior Y +1 spin calculation unit, the correction row is programmed to be XNOR with 0 state, and the rest Y h i of the small rows are programmed to be XNOR with 0 or 1 state of each bit of the small row as a constant 0 or a constant 1 state.

[0086] The BL and BLB of the coefficient storage unit of the first j column are used to input the spin value of the first j σ j — that is: σ j When the spin value is +1, the BL is connected to the power supply VDD, and the BLB is connected to GND; Figure 9 j When the spin value is -1, the BL is connected to GND, and the BLB is connected to VDD.

[0087] In addition, since it is an array design, in order to facilitate control, it is set that the spin calculation units of the same small row share the same WL, the same ScL, and the same S3; and the spin calculation units of the same column share the same BL and the same BLB.

[0088] Then, when the storage array is stored and input according to the Ising model, each time a column is opened for calculation: when the XNOR of the spin calculation unit is 1, the corresponding capacitor is discharged to 0; and when the calculation result is 0, the corresponding capacitor remains VDD. As for the first i large row, all of its spin calculation units are discharged through control to achieve: .

[0089] After the discharge of each row is completed, the corresponding transfer gate is turned on, so that the spin calculation units of the same row share charges on the ScL of the row— the voltage value of which represents how many of the same or results of the row are 1. Then, as for the first i large row, the ScL voltages of the 6 small rows in the interior respectively represent: C i,0、 C i,1 、C i,2 、C i,3 、C i,4 , C i,5 ; wherein, C i,0 the first i large row.​​Quantization value corresponding to the first bit to the fifth bit in the coefficient storage unit of the first row. C i,1 C i,5 respectively represent the first i Quantization value corresponding to the first bit to the fifth bit in the coefficient storage unit of the first row.

[0090] In order to facilitate the understanding of the above process of the storage array, refer to Figure 1 , still taking the Ising model of σ as an example:

[0091] The coupling coefficient and the external magnetic field strength are generally stored in the form of 5 bits complement (i.e. -16 to +15), that is, Y =5.

[0092] Refer to σ 1 of the first column of the spin relationship network - since only: σ 4, σ 6 have spin relationship with σ 1, then for the first row: the coefficient storage unit of the first column stores h1, the coefficient storage unit of the second column stores D, the coefficient storage unit of the third column stores D, the coefficient storage unit of the fourth column stores J 14 , the coefficient storage unit of the fifth column stores D, and the coefficient storage unit of the sixth column stores J 16 ; all BL and BLB of the first column input σ 1; all BL and BLB of the second column input σ 2; all BL and BLB of the third column input σ 3; all BL and BLB of the fourth column input σ 4; all BL and BLB of the fifth column input σ 5; all BL and BLB of the sixth column input σ 6; the first row performs calculation, then: the sum of all ScL voltages of the coefficient storage unit of the first column represents h1; the sum of all ScL voltages of the coefficient storage unit of the second column represents 0; the sum of all ScL voltages of the coefficient storage unit of the third column represents 0; the sum of all ScL voltages of the coefficient storage unit of the fourth column represents J 14 σ 4; the sum of all ScL voltages of the coefficient storage unit of the fifth column represents 0; and the sum of all ScL voltages of the coefficient storage unit of the sixth column represents J 16 σ 6. Then, the first column realizes: S 1= J 14 σ 4+ J 16 σ 6+ h1. ​

[0093] Similarly, the second to sixth rows of the storage array refer to... σ 2~ σ The spin relation network of 6, and input them respectively. σ 2~ σ 6. This will not be elaborated further here.

[0094] Therefore, the second major line achieves this by controlling the discharge: S 2= ​​J 23 σ 3+ J 24 σ 4+ J 25 σ 5+ J 26 σ 6+ h2;

[0095] The third major line achieved this by controlling the discharge: S 3= J 32 σ 2+ J 36 σ 6+ h3;

[0096] The fourth major line achieved this by controlling the discharge: S 4= J 41 σ 1+ J 42 σ 2+ J 45 σ 5+ h4;

[0097] The fifth major line achieves this by controlling the discharge: S 5 = J 52 σ 2+ J 54 σ 4+ h5;

[0098] The sixth major line achieves this by controlling the discharge: S 6 = J 61 σ 1+ J 62 Figure 1 2+J 63 σ 3+ h6.

[0099] (ii) The ScL in each row is connected to the addition tree through an analog-to-digital converter, which is used to first quantize and then weight to obtain the spin effective field of the Ising model, and then obtain the current solution of the spin dependent variable.

[0100] The current solution for the spin dependent variable can then be input into the storage array via the corresponding BL and BLB values ​​for a new round of calculation. This process continues until the annealing process ends (i.e., the current temperature is reached).T down to 0).

[0101] Referring to the above, each major row simulates the calculation process of spin effective field by controlling discharging. Then, the ScL voltage of each row is quantized by the analog-digital converter after the calculation is completed. Since each coefficient storage unit adopts Y +1 minor row to store multi-bit in complement format, the Y +1 ScL voltage quantization value of a major row is added after being given bit weight to obtain the spin effective field corresponding to the major row, which is still in complement format and contains numerical value and sign, and then the current solution of the spin dependent variable corresponding to the major row is obtained.

[0102] In fact, the above process simultaneously calculates the interaction relationship of multiple spins, which can effectively reduce the timing overhead.

[0103] For the convenience of understanding, still taking the Ising model of σ as an example:

[0104] The weighted formula of the addition tree is: S i =C i,0 +C i,1 + 2 C i,2 + 4 C i,3 + 8 C i,4 -16 C i,5 ;

[0105] wherein, S i represents the effective field received by the spin at the i th lattice point; C i,0 is the quantization value corresponding to the correction row in all coefficient storage units of the i th row; C i,1 ~ C i,5 respectively represent the quantization values corresponding to the 1st bit to the 5th bit in all coefficient storage units of the i th row.

[0106] That is to say, for the 1st major row, it contains 6 minor rows, and 6 ScL voltage quantization values C 1,0 ~ C 1,6 are obtained correspondingly; the C1,0 C 1,6 Addition is obtained S 1, and then by judging the positive and negative of S 1, the current solution of σ 1 is obtained.

[0107] The above similar operations are performed on the 2nd to 6th rows, and the current solutions of σ 2~6 are obtained. σ

[0108] The current solutions of σ 1~6 can then be input into the storage array through the corresponding BL and BLB for a new round of calculation. σ

[0109] As mentioned above, in order to avoid falling into a local minimum, the current solution of the spin variable is not directly input again, but a new solution of the spin variable is first selected by the voter, and then the new solution is input into the storage array through the corresponding BL and BLB for a new round of calculation.

[0110] Specifically, the voter can be connected to the output end of the addition tree to simulate the judgment probability to determine the new solution of the spin variable.

[0111] Referring to the above, the voter follows the following rules:

[0112] If the current solution of the spin variable falls within the judgment probability, the opposite value of the current solution of the spin variable is taken as the new solution of the spin variable; otherwise, the current solution of the spin variable is directly taken as the new solution of the spin variable.

[0113] Specifically, for the current solution of Figure 1 i σ i,now , the judgment probability is P i , and the specific formula is: .

[0114] For ease of understanding, the Ising model of σ is still taken as an example:

[0115] The current solutions of σ 1~6 have been obtained, so there is: σ

[0116] If the current solution of σ i falls within P i , the opposite value of the current solution of σ i is taken as σ ​​​​​i the new solution of σ i is not in P i , then directly take σ i the current solution as σ i the new solution of

[0117] Thus, the new solution of σ 1 σ 6 is obtained.

[0118] After that, the new solution of ​ 1 ​ 6 can be calculated through the corresponding BL, BLB input storage array for a new round.

[0119] Embodiment 2

[0120] The embodiment 2 discloses a CIM chip, which adopts the circuit layout of the reconfigurable Ising machine based on spin computing disclosed above, or the circuit layout of the spin computing unit based on FeFET disclosed above. The mode of packaging into a chip is more conducive to the popularization and application of the above-mentioned circuit.

[0121] Of course, the above-mentioned circuit layout can also be designed into a module - when designed into a module, the corresponding pin can be designed into a terminal.

[0122] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0123] The above-mentioned embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of variations and improvements can be made, which are within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. An FeFET-based spin computing unit, characterized in that, It comprises: 2 N-type FeFET transistors M1-M2, 1 capacitor CAP, 1 transmission gate Gate; The gate of M1 is connected with the bit line BL; the gate of M2 is connected with the bit line BLB; the drain of M1 and the drain of M2 are connected together and connected with the word line WL; the source of M1, the source of M2 and the upper plate of CAP are connected together; the lower plate of CAP is grounded GND; the C control end of Gate is connected with the control signal SW, the C reverse control end is connected with the control signal SWB, the input end is connected with the upper plate of CAP, and the output end is connected with the output bus ScL; Wherein, BL and BLB are used to input the spin independent variable of Ising model; when the spin independent variable is +1, BL is connected with the power supply VDD and BLB is connected with GND; when the spin independent variable is-1, BL is connected with GND and BLB is connected with VDD; M1 and M2 form an XNOR unit; when storing the coupling coefficient of Ising model and not being a correction row, XNOR is in a store 1 or store 0 state; when storing the external magnetic field intensity of Ising model and not being a correction row, XNOR is in a constant 1 or constant 0 state; when storing an irrelevant state, XNOR is in a constant 0 state; when being a correction row, XNOR is in a store 0 state.

2. The FeFET-based spin computing unit of claim 1, wherein, When M1 is programmed to be in a low resistance state and M2 is programmed to be in a high resistance state, XNOR is in a store 1 state; When M1 is programmed to be in a high resistance state and M2 is programmed to be in a low resistance state, XNOR is in a store 0 state; When M1 is programmed to be in a low resistance state and M2 is programmed to be in a low resistance state, XNOR is in a constant 1 state; When M1 is programmed to be in a high resistance state and M2 is programmed to be in a high resistance state, XNOR is in a constant 0 state.

3. The FeFET-based spin computing unit according to claim 1 or 2, characterized in that, Gate comprises: 1 NMOS tube S1, 1 PMOS tube S2; The gate of S1 is used as the C control end of the transmission gate; the gate of S2 is used as the C reverse control end of the transmission gate; the source of S1 and the source of S2 are connected together and used as the input end of the transmission gate; the drain of S1 and the drain of S2 are connected together and used as the output end of the transmission gate.

4. The FeFET-based spin computing unit of claim 3, wherein, It further comprises: 1 pre-charge tube PMOS tube S3; The gate of S3 is connected with the enable signal EN, the drain is connected with ScL, and the source is connected with the power supply VDD.

5. A reconfigurable Ising machine constructed based on spin computing, characterized in that, It comprises: a storage array, an analog-digital converter and an addition tree; The storage array includes: presents M Column N The FeFET-based spin computing unit of claim 4 is distributed by row; spin computing units in the same row share the same WL, the same ScL, and the same S3; spin computing units in the same column share the same BL and the same BLB. The ScL of each row is connected with the addition tree through the analog-digital converter, which is used to quantize and then weight to obtain the spin effective field of Ising model and further obtain the current solution of the spin dependent variable.

6. The reconfigurable Ising machine constructed based on spin computing of claim 5, wherein, If the Ising model exists X = 1 spin per lattice point, then N = 1 spin per lattice point, then X , M = 1 spin per lattice point, then N = 1 spin per lattice point, then Y +1); Y indicates the number of bits of the storage object; The storage object is the coupling coefficient or the external magnetic field intensity; In the storage array, each column stores each Y +1 row as a coefficient storage section of 1 storage object, forming a X column X row distribution; the 1st row in each coefficient storage section as a correction row, and the remaining Y rows correspondingly store the Y bit of the storage object from top to bottom.

7. The reconfigurable Ising machine based on spin computing construction of claim 6, wherein, In the storage array, if the spin on the first i lattice point is not spin-connected with the spin on the second j lattice point, the coefficient storage unit located at the first i row and the second j column is used to store the irrelevant state. Otherwise, the coefficient storage section at the i row and the j column stores the coupling strength between the spin at the i grid point and the spin at the j grid point J i,j ; i , j ∈[1, X ]; i ≠ j ; Located in the i Line number i The coefficient storage section of the column is used to store the first... i External magnetic field strength at each grid point h i ; The BL, BLB of the coefficient storage section of the column are used to input the spin values on the 1st j j It further comprises: a voter connected with the output end of the addition tree, which is used to simulate the judgment probability to determine the new solution of the spin dependent variable; j .​​ 8. The reconfigurable Ising machine based on spin computing construction of claim 7, wherein, Y =5； The weighted formula of the addition tree is S i =C i,0 +C i,1 + 2 C i,2 + 4 C i,3 + 8 C i,4 -16 C i,5 ; wherein S i denotes the effective field experienced by the spin at the i C i,0 is the quantized value corresponding to the correction row in the coefficient storage section of the i C i,1 ~ C i,5 denote the quantized values corresponding to the 1st to 5th bit positions in the coefficient storage section of the i row, respectively.​​ 9. The reconfigurable Ising machine based on spin computing construction according to any one of claims 5-8, characterized in that, If the current solution of the spin dependent variable falls within the judgment probability, the opposite value of the current solution of the spin dependent variable is taken as the new solution of the spin dependent variable; otherwise, the current solution of the spin dependent variable is directly taken as the new solution of the spin dependent variable. The circuit layout of the FeFET-based spin computing unit according to any one of claims 1-4 or the circuit layout of the reconfigurable Ising machine constructed based on the spin computing according to any one of claims 5-9.

10. A CIM chip, characterized by, ​

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