Linear and probabilistic logarithm counter

Abstract

The invention relates to a linear and probabilistic logarithm counter. In one aspect, a dual scale counter circuit is provided, the dual scale counter circuit comprising: a counter logic unit to store a current counter value; a range determination logic to determine an operating range of the dual scale counter circuit based on the current counter value and a predetermined threshold; and a counter delta logic unit. The counter delta logic is to linearly increase the current counter value for delta events in response to the dual scale counter circuit operating within a linear range, and probabilistically increase the current counter value for delta events in response to the dual scale counter circuit operating within a probability range. The dual-scale counter circuit further includes a linear feedback shift register to generate a random binary bit sequence, a counter delta logic to generate a random binary bit sequence when the dual-scale counter circuit operates within a probability range, and a linear feedback shift register to generate a random binary bit sequence. It is determined whether to increase a current counter value for an incremental event based on the random bin sequence.

Description

[0001] Government Funding Terms and Conditions Statement

[0002] This invention was carried out with government support under contract number H98230-23-C-0350 granted by the Maryland Procurement Office. The government holds certain rights to this invention. Background Technology Technical Field

[0003] This disclosure generally relates to counter design. More specifically, this disclosure relates to the design of a dual-scale counter that accurately counts smaller numbers and approximates larger numbers. Attached Figure Description

[0004] Figure 1 The illustration shows the incremental probability for different count value ranges according to one aspect of this application.

[0005] Figure 2 An example of a range of count values ​​according to one aspect of this application is illustrated.

[0006] Figure 3 A block diagram of an example dual-scale counter according to one aspect of this application is shown.

[0007] Figure 4 A flowchart illustrating an example process for increasing a dual-scale counter according to one aspect of this application is presented.

[0008] Figure 5 The illustration shows a computer system that facilitates the operation of a dual-scale counter according to one aspect of this application.

[0009] Figure 6 The illustration shows a computer-readable medium that facilitates the operation of a dual-scale counter according to one aspect of this application.

[0010] In these accompanying drawings, the same reference numerals refer to the same elements. Detailed Implementation

[0011] This application provides solutions to the problem of reducing the chip area occupied by counters. More specifically, a dual-scale counter with a much smaller footprint compared to a linear counter is described. The dual-scale counter can accurately count smaller numbers (e.g., grow linearly) and approximate larger numbers (e.g., grow probabilistically).

[0012] Silicon chip area is a common concern in computer system design because a larger chip area increases the overall system cost by reducing the number of chips that can be built onto a silicon wafer. Furthermore, a larger chip area can lead to lower yield rates, as it includes more transistors and therefore a greater likelihood of encountering defective transistors. Chip designers are typically highly motivated to reduce the chip area occupied by each device in order to lower component costs.

[0013] Counter circuitry is a critical component in network devices. For example, a dedicated standard product (ASIC) for switches may include multiple counters for debugging and network telemetry purposes. While the network device is in service, counters can collect data on network traffic, bandwidth usage, latency, packet loss, and other performance metrics. Telemetry data can be used to identify congestion in the network and is highly valuable to network administrators and architects. However, counter circuitry is area-intensive, especially for counters that count large numbers. Reducing the chip area consumed by counter circuitry can lower the overall component cost of the network device.

[0014] Counters using approximate counting algorithms typically occupy a smaller chip area (e.g., by reducing the number of bits required to record the counter value). However, approximate counting is only suitable for large count values ​​and can introduce unacceptable inaccuracies when counting smaller numbers. Some counter applications (e.g., telemetry data collection) require accurate counting at low count values ​​but can tolerate less accurate counters at high count values. For example, when count values ​​are high (e.g., when counting the number of packets arriving at a port), the order of magnitude of the tracked values ​​is sufficient. To take advantage of the relaxed accuracy requirements at large count values ​​without sacrificing accuracy at small count values, aspects of this disclosure provide a dual-scale counter that can accurately count smaller numbers and approximate count larger numbers.

[0015] Depending on several factors, the count value can be divided into a linear range and a probabilistic range. When the count value falls below a predetermined threshold, the counter can be configured to count linearly (i.e., the change in the counter value is proportional to the number of events being counted). In other words, for each occurrence of an event, the probability of the counter value incrementing is one. The occurrence of the counted event can also be referred to as an increment event. In the example of counting packets arriving at a port, for each packet, the counter value can be incremented by a fixed number (e.g., one or two).

[0016] When the occurrence of an event exceeds a predetermined threshold (i.e., within a probability range), the counter can be configured to approximate a count, meaning that the occurrence of the event may not cause the counter value to increase. In some examples, the probability of the counter value increasing may decrease linearly on a logarithmic scale (e.g., a logarithmic scale with base 2). Alternatively, the probability range may be divided into multiple subranges (e.g., n subranges) based on the count value, each subrange corresponding to a specific increment probability. The larger the count value, the lower the increment probability (i.e., the less likely the incrementing event is to cause an increment in the counter value). In some examples, the increment probability in the i-th subrange of the probability range may be 2. -i , where i is a positive integer representing the index of the subrange. In an alternative example, the incremental probability in the i-th subrange could be 10. -i .

[0017] Figure 1 The diagram illustrates the incremental probabilities of different count value ranges according to one aspect of this application. The horizontal axis represents the count value, starting from zero. Count values ​​can be divided into linear and probability ranges. Low count values ​​belong to the linear range. As the count value increases, it can move beyond the linear range into the probability range, which can be further divided into multiple sub-ranges. For example, as the count value increases to the point of exiting the linear range, it can fall into a first probability sub-range, a second probability sub-range, etc. The vertical axis represents the incremental probability within each range / sub-range. More specifically, the vertical axis is plotted on a logarithmic scale with a base of 2. Figure 1 As shown, within the linear range, the increment probability is 1, meaning that the counter increments by a fixed value each time an incremental event is detected. On the other hand, within the probability range, the increment probability is less than 1, meaning that for a detected incremental event, there is a non-zero probability that the counter will not increment. The increment probability varies for different sub-ranges. Figure 1 In the example shown, the incremental probability is 2 within the first probability subrange. -1 (or 1 / 2); within the second probability sub-range, the incremental probability is 2. -2 (or 1 / 4); and so on. In this example, the incremental probability decreases exponentially with respect to the subrange index i (i.e., for the i-th subrange, the incremental probability is 2). -i ).

[0018] Depending on some factors, the range of count values ​​can be arbitrarily assigned. Figure 2 An example of a range of count values ​​according to one aspect of this application is illustrated. Figure 2In the example shown, Table 200 includes four columns. The first column corresponds to the name of each count range or subrange (e.g., linear range, probability subrange 1, probability subrange 2, etc.). The second column corresponds to the actual or estimated count value within each range or subrange. The third column corresponds to the incremental probability within each range or subrange. For example, the incremental probability is 1 within the linear range, while it is 2 within the i-th probability subrange. -i The fourth column corresponds to the counter value for each range or subrange. Note that the count value is the number of increment events being counted (expressed in decimal), while the counter value represents the reading of the dual-scale counter (expressed in hexadecimal). Within the linear range, there is a one-to-one mapping between count values ​​and counter values. However, within the probabilistic range, since the increment probability is less than one, each counter value can represent multiple count values.

[0019] In this example, the 16-bit counter can increment linearly (e.g., the counter can advance by one for each increment event) until the counter reaches a predetermined threshold (e.g., 0x7FFF or nearly half of the counter's maximum value). The remaining half of the counter value (e.g., from 0x8000 to 0xFFFF) can be divided into 32 probability subranges, where the increment probability of each subrange is configured to be 2. -i Let i = 1, 2, ..., 32. For example, once the counter progresses from the linear range to probability subrange 1 (e.g., above 0x7FFF), the increment probability decreases to 1 / 2, meaning that for each increment event, the probability of the counter progressing is 50%. The increment probability is halved when the counter progresses from one probability subrange to the next. This decrease in increment probability means a reduction in counting accuracy. As discussed earlier, such inaccuracy is acceptable for large count values.

[0020] Table 2 also indicates that dual-scale counters can use a small number of bits (e.g., 16 bits) to handle very large numbers (e.g., up to 8.79 × 10⁻⁶). 12 This dual-scale counter performs the counting. In contrast, a linear counter would require 48 bits to count such a large number. Reducing the number of bits in the counter reduces its chip area. More specifically, a typical counter circuit may include multiple cascaded flip-flop circuits, each storing one bit. When the number of counter bits is reduced by two-thirds (e.g., from 48 to 16), the counter's footprint can be reduced by two-thirds. Therefore, implementing a dual-scale counter in network devices reduces component costs.

[0021] Various mechanisms can be used to determine the operating range (e.g., linear or probabilistic range) of a two-scale counter during its counting. Depending on several aspects, a table lookup mechanism can be used to determine the current operating range of the counter. In one example, the system can use... Figure 2 The table 200 shown performs a table lookup operation. More specifically, the system can read the instantaneous counter value and compare it with the counter value range / subrange shown in the fourth column of table 200. Once the counter value range / subrange is determined, the system can determine the corresponding increment probability in the third column of table 200. For example, if the instantaneous counter value is 0x8811, the system can determine that the counter operates in probability subrange 3, and the corresponding increment probability should be 2. -3 = 1 / 8. In another example, the instantaneous counter value is 0x95AF, and the system can determine that the counter operates within probability subrange 6, and the corresponding increment probability should be 2. -6 = 1 / 64.

[0022] Based on several aspects, when operating within a probability subrange with a predetermined increment probability, the system can determine whether to increment the counter based on the output of the random number generator. According to another aspect, the random number generator can be implemented using a linear feedback shift register (LFSR), which outputs a random binary bit sequence comprising multiple bits. Depending on the increment probability, a subset of the bits in the LFSR output will be evaluated. More specifically, for an increment probability of 2... -i The system evaluates a total of i bits of the LFSR output. For example, in probability subrange 1 with an increment probability of 1 / 2, only one bit of the LFSR output (e.g., bit 0) is evaluated to determine whether to increment the counter value. When an increment event is detected (e.g., an incoming packet matches a predetermined criterion), the system can determine whether bit 0 of the LFSR output is 1. If so, the counter increments; otherwise, the counter does not increment (i.e., the counter value remains unchanged). Similarly, in probability subrange 2 with an increment probability of 1 / 4, two bits (e.g., bit 0 and bit 1) are evaluated. For each increment event, if both bits are 1, the counter increments.

[0023] Other types of random number generators can also be used. In one example, the system can use a software-based random number generator to control the increment of the counter. For example, if the increment probability is 32, the random number generator can randomly generate a number between 0 and 31, and if the randomly generated number matches the target number (e.g., 0), the counter will increment for the increment event.

[0024] Figure 3 A block diagram of an example dual-scale counter according to one aspect of this application is illustrated. Figure 3The dual-scale counter 300 may include a counter logic unit 302, an event detection logic unit 304, a range determination logic unit 306, a counter increment logic unit 308, a random number generation logic unit 310, and a counter value output unit 312. Depending on some aspects, the dual-scale counter 300 may be part of a network device and may be used to collect specific types of network telemetry data. The various units within the dual-scale counter 300 may be implemented using software components, hardware components, or a combination thereof.

[0025] The counter logic unit 302 can be used to count the number of times an event occurs (e.g., the number of packets arriving at a port). The counter logic unit 302 can be implemented using different techniques (e.g., implemented as a synchronous counter or an asynchronous counter) and includes various digital logic units (e.g., flip-flops). The scope of this disclosure is not limited to any specific implementation of the counter logic unit 302.

[0026] Event detection logic unit 304 is responsible for detecting incremental events. When the dual-scale counter 300 is used for network telemetry purposes, event detection logic unit 304 can detect incremental events by performing a match on one or more header fields of incoming packets. These header fields include, but are not limited to, source and destination Internet Protocol (IP) addresses, source and destination Media Access Control (MAC) addresses, source and destination port numbers (e.g., Transmission Control Protocol (TCP) and / or General Datagram Protocol (UDP) port numbers), Virtual Local Area Network (VLAN) tags, Virtual Network Identifiers (VNIs), flow tags, Differentiated Services Code Point (DSCP) values, etc. In addition to network events (i.e., packet transmission and reception), depending on the use case, event detection logic unit 304 can be used to detect other types of events that can trigger increments in counter logic unit 302. The scope of this disclosure is not limited to the types of events detected by event detection logic unit 304. Furthermore, although shown as part of dual-scale counter 304, in some examples, event detection logic unit 304 may be part of a packet processing pipeline outside of dual-scale counter 304.

[0027] The range determination logic unit 306 is responsible for determining the operating range of the dual-scale counter 300. According to some aspects, the range determination logic unit 306 can obtain the current counter value from the counter logic unit 302 and determine the operating range accordingly. For example, the range determination logic unit 306 can determine that the operating range of the dual-scale counter 300 is a linear range in response to the current counter value being less than a predetermined threshold. The range determination logic unit 306 can further determine that the operating range is a probabilistic range in response to the current counter value being equal to or greater than the predetermined threshold. According to another aspect, the probabilistic range can be divided into multiple sub-ranges, and the range determination logic unit 306 can perform a table lookup to determine a specific probabilistic sub-range based on the current counter value. The lookup table can be similar to... Figure 2 Table 200 is shown.

[0028] The counter increment logic unit 308 is responsible for controlling the increment of the counter logic unit 302. According to some aspects, the counter increment logic unit 308 may receive a signal from the event detection logic unit 304 indicating that an increment event has been detected. The counter increment logic unit 308 may further receive the output of the range determination logic unit 306, which indicates the operating range of the dual-scale counter 300. If the dual-scale counter 300 operates within a linear range, the counter increment logic unit 308 may send a trigger signal to the counter logic unit 302, causing it to increment its value. In some examples, the counter increment logic unit 308 may increment the value of the counter logic unit 302 by one for each increment event. In alternative examples, the counter increment logic unit 308 may increment the value of the counter logic unit 302 by another positive value (e.g., two or three) for each increment event.

[0029] If the dual-scale counter 300 operates within a probability range, the counter increment logic unit 308 can obtain a random number generated by the random number generation logic unit 310 and determine whether to send a trigger signal to the counter logic unit 302 based on that random number. According to some aspects, the random number generation logic unit 310 may include an LFSR that outputs a random binary bit sequence. A subset of the bits output by the LFSR is evaluated depending on the specific probability subrange in which the dual-scale counter 300 operates. More specifically, when the current counter value belongs to the i-th probability subrange, a total of i bits of the LFSR output are evaluated. In one example, if all evaluated bits are "1", the counter increment logic unit 308 may send a trigger signal to the increment counter logic unit 302 for an increment event. In another example, if all evaluated bits are "0", the counter increment logic unit 308 may send a trigger signal to the increment counter logic unit 302 for an increment event. According to alternative aspects, the random number generation logic unit 310 may include components configured to generate a random number with a predetermined probability (e.g., 2^i).-i The software component that generates random numbers. If the output of the random number generation logic unit 310 matches a predetermined number (e.g., 0), the counter increment logic unit 308 can send a trigger signal to the increment counter logic unit 302 in response to an increment event.

[0030] The count output unit 312 is responsible for outputting the actual count of incremental events detected by the event detection logic unit 304 based on the counter value output of the counter logic unit 302. More specifically, the count output unit 312 can map the counter value to the actual or estimated count value. As previously discussed, when the dual-scale counter 300 operates within a linear range, there is a one-to-one mapping between the counter value and the actual count value. On the other hand, when the dual-scale counter 300 operates within a probabilistic range, due to the uncertainty of the probabilistic counter, each counter value can be mapped to multiple actual count values. In this case, the count output unit 312 can estimate the actual count value based on the counter value.

[0031] Depending on some aspects, the count value output unit 312 can use a lookup table (e.g., Figure 2 The actual count value is estimated using Table 200 shown. For example, the count value output unit 312 can determine a probability subrange corresponding to the counter value. Based on the determined subrange, the count value output unit 312 can determine the lower limit of the counter value for the subrange, the lower limit of the count value for the subrange (also called the count offset value), and the increment probability for the subrange. The count value output unit 312 can then estimate the actual count value by calculating the difference between the current counter value and the lower limit of the counter value for the subrange, multiplying the difference by the reciprocal of the increment probability (which provides an estimated number of increment events counted within the probability subrange), and then adding the result of the multiplication to the count offset value (i.e., the lower limit of the actual count value).

[0032] For example, if counter logic unit 302 outputs a counter value of 0x9009, which falls within probability subrange 5, based on Table 200, count value output unit 312 can determine that for probability subrange 5, the lower limit of the counter value is 0x9000, the count offset is 63488, and the increment probability is 1 / 32. Therefore, count value output unit 312 can calculate the difference between the current counter value and the lower limit of probability subrange 5 to obtain the number 9, which is the number of increments performed by the dual-scale counter 300 when operating within probability subrange 5. Then, count value output unit 312 can multiply the number of increments (i.e., 9) by the reciprocal of the increment probability (i.e., 1 / 32) to produce an estimated number of events (i.e., 288) that were counted when the dual-scale counter 300 operated within probability subrange 5. Finally, the count output unit 312 can add 288 and 63488 (i.e., the lower limit of the actual count value in the probability subrange 5) and output the result (i.e., 63776) as an estimate of the actual count value.

[0033] As previously discussed, the dual-scale counter 300 has a much smaller footprint compared to a linear counter that can output count values ​​within a similar range, because the counter logic unit 302 includes significantly fewer flip-flop circuitry than a linear counter. The only overhead in the dual-scale counter 300 is the random number generation logic unit 310, which is much smaller than the additional flip-flop circuitry required by a linear counter.

[0034] Figure 4 A flowchart illustrating an example process for incrementing a dual-scale counter according to one aspect of this application is presented. Although Figure 4 A specific sequence of operations is shown, but the method is not limited to this order. For example, operations shown consecutively in the flowchart can be performed in different orders, simultaneously, partially simultaneously, or in combination. During the operation, a dual-scale counter can detect incremental events (operation 402). Depending on the use case, various logical units in the network device can detect incremental events. In one example, Figure 3 The event detection logic unit 304 shown can detect incremental events. In network telemetry applications, detecting incremental events may include performing a match on one or more header fields of an incoming packet.

[0035] A dual-scale counter can determine the operating range of the counting circuit based on the current counter value and a predetermined threshold (operation 404). In some examples, the dual-scale counter may include comparator circuitry that compares the current counter value with the predetermined threshold. In some examples, the dual-scale counter may include a table lookup logic unit that can look up a table of counter value ranges (e.g., ...). Figure 2Table 200 (shown) is used to determine the operating range of the counting circuit. The counting circuit can operate within a linear range or a probability range. If the current counter value is less than a predetermined threshold, the counting circuit operates within the linear range. If the current counter value is equal to or greater than the predetermined threshold, the counting circuit operates within the probability range. Furthermore, the probability range can be divided into multiple probability sub-ranges. The table lookup logic unit determines the operating range / sub-range of the counting circuit by comparing the current counter value with the lower and / or upper boundaries of each range and sub-range.

[0036] If the counting circuit operates within a linear range, the counter value of the counting circuit can increase linearly with respect to incremental events (operation 406). In one example, the counter value can increase by one for each incremental event. In other examples, the counter value can increase by other positive numbers (e.g., two or three) for each incremental event.

[0037] If the counting circuit operates within a probability range, the counter value of the counting circuit can probabilistically increase for incremental events based on a randomly generated sequence of binary bits (operation 408). The incremental probability can be determined based on the probability subrange to which the current counter value belongs, depending on several factors. More specifically, a higher counter value can result in a lower incremental probability. Figure 2 Table 200 shown is used as an example, where the incremental probability of the i-th probability subrange is 2. -i Let i = 1, 2, ..., 32. In addition to the logarithmic base of 2, another logarithmic base (such as the logarithmic base of 10) can be used to divide the probability range.

[0038] Depending on several aspects, a dual-scale counter may include an LFSR capable of outputting a randomly generated sequence of binary bits. Depending on the increment probability, a subset of bits in the randomly generated binary bit sequence can be evaluated to determine whether to increment the counter value of the counting circuit. In one example, if all evaluated bits are either "1" or "0", the counting circuit increments.

[0039] Figure 5 The illustration depicts a computer system facilitating the operation of a dual-scale counter according to one aspect of this application. The computer system 500 includes processing resources 502, memory 504, and storage device 506. Furthermore, the computer system 500 may be coupled to peripheral input / output (I / O) user equipment 510 (e.g., display device 512, keyboard 514, and pointing device 516). Storage device 506 includes a non-transitory computer-readable storage medium and stores an operating system 518, a dual-scale counter control system 518, and data 540. The computer system 500 may be implemented on network devices (e.g., switches, routers, network interface cards (NICs), etc.) and may include components more than... Figure 5The number of entities shown is less or more.

[0040] In the examples described herein, processing resources may include, for example, one or more processors included in a single computing device or distributed across multiple computing devices. As used herein, a “processor” may be at least one of a central processing unit (CPU), a semiconductor-based microprocessor, a graphics processing unit (GPU), a field-programmable gate array (FPGA) configured to fetch and execute instructions, other electronic circuitry suitable for fetching and executing instructions stored on a computer-readable storage medium, or combinations thereof. In the examples described herein, processing resources may fetch, decode, and execute instructions stored on a storage medium to perform the function described with respect to the instructions stored on the computer-readable medium. In other examples, the function described with respect to any instructions described herein may be implemented in the form of electronic circuitry, executable instructions encoded on a computer-readable medium, or a combination thereof. The computer-readable storage medium may be located in or away from the computing device executing the instructions but accessible (e.g., via a computer network) for execution. In the examples illustrated herein, a node may be implemented by one or more computer-readable storage media.

[0041] When the dual-scale counter control system 520 is executed by the computer system 500 (or by the processing resource 502 of the computer system 500), the computer system 500 may perform the methods and / or processes described in this disclosure. Specifically, the dual-scale counter control system 520 may include methods for performing as described above. Figure 4 The operation 402 shown describes the instruction 522 for detecting incremental events. Depending on some aspects, detecting incremental events may include performing a match on one or more header fields of an incoming packet.

[0042] The dual-scale counter control system 520 may include components for use as described above. Figure 4 The instruction 524, as described in operation 404, determines the operating range of the counting circuit based on the current counter value and a predetermined threshold. According to some aspects, determining the operating range of the counting circuit may include obtaining the current counter value and comparing it with the predetermined threshold. According to another aspect, determining the operating range of the counting circuit may include looking up a range table (e.g., Figure 2 Table 200 is shown.

[0043] The dual-scale counter control system 520 may include components for use as described above. Figure 4The operation 406 shown is in response to an instruction 526 that determines the counting circuit is operating within a linear range, causing the counter value to increase linearly. When operating within the linear range, the counter value can increase by a predetermined amount (e.g., one) for each detected incremental event.

[0044] The dual-scale counter control system 520 may include components for use as described above. Figure 4 As described in operation 408, instruction 528 probabilistically increments the counter value based on a randomly generated binary bit sequence in response to determining that the dual-scale event counting circuit is operating within a probability range. When operating within a probability range, for each increment event, the counter value can be incremented based on the increment probability corresponding to the probability subrange to which the current counter value belongs.

[0045] The dual-scale counter control system 520 may include components for use as described above. Figure 3 The instruction 530, as described in the count value output unit 312, outputs an estimate of the actual count of events based on the counter value.

[0046] Data 540 may include the above information regarding... Figure 2 Table 200 shows the counter value ranges described in Table 542. The dual-scale counter control system 520 may include a ratio Figure 5 The instructions shown are further instructions. For example, the dual-scale counter control system 520 can also store instructions for generating random binary bit sequences or random numbers.

[0047] Figure 6 The illustration depicts a computer-readable medium facilitating the operation of a dual-scale counter according to one aspect of this application. CRM 600 may be a non-transitory computer-readable medium or device storing instructions that, when executed by a computer or processing resource, cause the computer or processing resource to perform a method.

[0048] CRM 600 can store data for purposes such as those mentioned above. Figure 4 Instruction 610 for detecting incremental events as described in operation 402; used as above regarding Figure 4 The instruction 620, as described in operation 404, determines the operating range of the counting circuit based on the current counter value and a predetermined threshold; used as described above regarding... Figure 4 As described in operation 406, this operation responds to instruction 630, which determines that the counting circuit operates within a linear range, causing the counter value to increase linearly; for use as described above regarding Figure 4 As described in operation 408, instruction 640 probabilistically increments the counter value based on a randomly generated binary bit sequence in response to determining that the dual-scale event counting circuit operates within a probability range; and for as described above regarding Figure 3 The instruction 650, as described in the count value output unit 312, outputs an estimate of the actual count of events based on the counter value.

[0049] CRM 600 can include more Figure 6 The instructions shown are additional instructions. For example, the CRM 600 can also store instructions for generating random binary bit sequences or random numbers.

[0050] As used herein, "computer-readable storage medium" can be any electronic, magnetic, optical, or other physical storage device for containing or storing information such as executable instructions, data, etc. For example, any computer-readable storage medium described herein can be any or a combination of RAM, EEPROM, volatile memory, non-volatile memory, flash memory, storage drives (e.g., HDD, SSD), any type of storage disk (e.g., compact disc, DVD, etc.). Furthermore, any computer-readable storage medium described herein can be non-transitory.

[0051] As used herein, circuits can be implemented using any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FPGAs, logic components, software routines, or other mechanisms can be implemented to constitute a circuit. In implementations, the various circuits described herein can be implemented as discrete circuits, or the described functions and features can be shared partially or wholly among one or more circuits. Although various features or functional elements can be described or claimed individually as separate circuits, these features and functions can also be shared within one or more common circuits, and such description should not require or imply the need for separate circuits to implement such features or functions. In cases where software is used to implement the circuit wholly or partially, such software can be implemented to operate in conjunction with a computing or processing system (such as computer system 500) capable of performing the functions described with respect to the software.

[0052] In general, the disclosed aspects provide a dual-scale counter that can accurately count smaller numbers and approximate larger numbers. When an increment event is detected, the counter control logic can read the current counter value and determine the operating range of the counter based on the current counter value. If the current counter value is below a predetermined threshold, the counter operates within a linear range, and the counter control logic can cause the counter to increment linearly (e.g., the counter value increments by one for each event). If the current counter value is above the predetermined threshold, the counter operates within a probabilistic range, and the counter control logic can cause the counter value to increment based on a predetermined probability. The larger the counter value, the lower the increment probability. The counter control logic may include an LFSR capable of generating a pseudo-random sequence of binary bits and determining whether to increment the counter value based on a subset of the bits output by the LFSR. Compared to a linear counter with the same counting range, the dual-scale counter has a much smaller footprint and can accurately count smaller numbers.

[0053] One aspect of this application provides a dual-scale counter circuit, comprising: a counter logic unit for storing a current counter value; a range determination logic unit for determining the operating range of the dual-scale counter circuit based on the current counter value and a predetermined threshold; and a counter increment logic unit. The counter increment logic unit is configured to: linearly increase the current counter value for an increment event in response to the range determination logic unit determining that the dual-scale counter circuit operates within a linear range; and probabilistically increase the current counter value for an increment event in response to the range determination logic unit determining that the dual-scale counter circuit operates within a probabilistic range. The dual-scale counter circuit further includes a linear feedback shift register for generating a random binary bit sequence, and the counter increment logic unit is configured to determine, based on the random binary bit sequence, whether to increase the current counter value for an increment event when the dual-scale counter circuit operates within the probabilistic range.

[0054] In a variation of this aspect, the range determination logic unit is further configured to: determine that the dual-scale counter circuit operates within a linear range in response to the current counter value being less than the predetermined threshold; and determine that the dual-scale counter circuit operates within a probability range in response to the current counter value being equal to or greater than the predetermined threshold.

[0055] In a variation of this, the range determination logic unit may include a table lookup logic unit for looking up a counter value range table based on the current counter value.

[0056] In a further variation, the counter value range table may include multiple rows, each corresponding to a counter value range having a range start value, a range end value, and a probability of incrementing the current counter value for an incremental event.

[0057] In a further variation, this probability can decrease as the current counter value increases from the first counter value range to the second counter value range.

[0058] In a further variation, this probability can be decreased exponentially by powers of two.

[0059] In a further variation, the dual-scale counter circuit may include a count value output unit for outputting an estimate of the total count of incremental events based on the current counter value and a counter value range table. Compared to a linear counter that outputs the total count of incremental events, this dual-scale counter has a smaller footprint.

[0060] In a further variation, each row can further specify a count offset value for the counter value range. The count value output unit can determine from the plurality of rows the row corresponding to the counter value range to which the current counter value belongs; subtract the range start value specified by the determined row from the current counter value to obtain the number of increments within the counter value range; multiply the number of increments by the reciprocal of the probability specified by the determined row to obtain an estimated number of increment events counted within the counter value range; and add the count offset value specified by the determined row to the estimated number of increment events.

[0061] In a variation of this, the random binary bit sequence may include multiple bits, and the counter increment logic may evaluate a subset of these bits based on a probability subrange corresponding to the current counter value.

[0062] In a further variation, if all bits in the subset are set to one, the counter increment logic unit can increment the current counter value.

[0063] One aspect of this application provides a system and method for incrementing a dual-scale counter circuit. During operation, the system can detect increment events, determine the operating range of the dual-scale counter circuit based on a current counter value and a predetermined threshold, linearly increment the current counter value in response to determining that the dual-scale counter circuit is operating within a linear range, and probabilistically increment the current counter value based on a randomly generated binary bit sequence in response to determining that the dual-scale counter circuit is operating within a probabilistic range.

[0064] The foregoing description is presented to enable any person skilled in the art to make and use the aspects and examples, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects and applications without departing from the spirit and scope of this disclosure. Therefore, the aspects described herein are not limited to those shown, but are intended to be consistent with the maximum scope of the principles and features disclosed herein.

[0065] Furthermore, the foregoing descriptions of the various aspects have been presented solely for illustrative and descriptive purposes. These descriptions are not intended to be exhaustive or to limit the aspects described herein to the disclosed forms. Accordingly, many modifications and variations will be apparent to those skilled in the art. Additionally, the foregoing disclosure is not intended to limit the aspects described herein. The scope of the aspects described herein is defined by the appended claims.

Claims

1. A dual-scale counter circuit, comprising: a counter logic unit to store a current counter value; a range determination logic unit to determine an operating range of the dual-scale counter circuit based on the current counter value and a predetermined threshold; a counter increment logic unit to: in response to the range determination logic unit determining that the dual-scale counter circuit operates in a linear range, cause the current counter value to linearly grow for an increment event; and in response to the range determination logic unit determining that the dual-scale counter circuit operates in a probabilistic range, cause the current counter value to probabilistically grow for the increment event; and a linear feedback shift register to generate a sequence of random binary bits, the counter increment logic unit to determine whether to increment the current counter value for the increment event based on the sequence of random binary bits when the dual-scale counter circuit operates in the probabilistic range. the range determination logic unit further to: in response to the current counter value being less than the predetermined threshold, determine that the dual-scale counter circuit operates in the linear range; and 2. The dual-scaled counter circuit of claim 1, wherein, in response to the current counter value being equal to or greater than the predetermined threshold, determine that the dual-scale counter circuit operates in the probabilistic range. the range determination logic unit comprising a table lookup logic unit to look up a counter value range table based on the current counter value. the counter value range table comprising a plurality of rows, each row corresponding to a counter value range having a range start value, a range end value, and a probability of the current counter value growing for the increment event.

3. The dual-scaled counter circuit of claim 1, wherein, the probability decreasing as the current counter value increases from a first counter value range to a second counter value range.

4. The dual-scaled counter circuit of claim 3, wherein, the probability exponentially decreasing according to powers of two.

5. The dual-scaled counter circuit of claim 4, wherein, the dual-scale counter having a smaller footprint than a linear counter that outputs a total count of the increment events.

6. The dual-scaled counter circuit of claim 5, wherein, each row further specifying a count offset value for the counter value range, the count value output unit to:

7. The dual-scale counter circuit of claim 4, further comprising a count value output unit for outputting an estimate of a total count of increment events based on the current counter value and the counter value range table, wherein, determine, from the plurality of rows, a row corresponding to a counter value range to which the current counter value belongs; 8. The dual-scaled counter circuit of claim 7, wherein, subtract, from the current counter value, the range start value specified by the determined row to obtain a number of increments made within the counter value range; multiply the number of increments by an inverse of the probability specified by the determined row to obtain an estimated number of increment events counted within the counter value range; and add the count offset value specified by the determined row to the estimated number of increment events. the sequence of random binary bits comprising a plurality of bits, and wherein the counter increment logic is to evaluate a subset of the bits based on a probabilistic sub-range corresponding to the current counter value. the counter increment logic unit to cause the current counter value to grow if all bits in the subset are set to one.

11. A method, comprising:

9. The dual-scaled counter circuit of claim 1, wherein, detecting an increment event; 10. The dual-scaled counter circuit of claim 9, wherein, ​ ​ ​ determining an operating range of the dual-scale counter circuit based on a current counter value and a predetermined threshold value; in response to determining that the dual-scale counter circuit is operating in a linear range, causing the current counter value to linearly grow; and in response to determining that the dual-scale counter circuit is operating in a probabilistic range, causing the current counter value to probabilistically grow based on a randomly generated sequence of binary bits.

12. The method of claim 11, comprising: in response to the current counter value being less than the predetermined threshold value, determining that the dual-scale counter circuit is operating in the linear range; and in response to the current counter value being equal to or greater than the predetermined threshold value, determining that the dual-scale counter circuit is operating in the probabilistic range.

13. The method of claim 11, further comprising looking up a counter value range table based on the current counter value, the counter value range table comprising a plurality of rows, each row corresponding to a counter value range, the counter value range having a range start value, a range end value, and a probability of causing the current counter value to grow for the increment event.

14. The method of claim 13, wherein, the probability decreasing as the current counter value increases from a first counter value range to a second counter value range.

15. The method of claim 14, wherein, the probability exponentially decreasing according to a power of two.

16. The method of claim 13, further comprising estimating a total count of increment events based on the current counter value and the counter value range table.

17. The method of claim 16, wherein, each row further specifying a count offset value for the counter value range, and wherein estimating the total count of increment events comprises: determining, from the plurality of rows, a row corresponding to a counter value range to which the current counter value belongs; subtracting, from the current counter value, the range start value specified by the determined row to obtain a number of increments made within the counter value range; multiplying the number of increments by an inverse of the probability specified by the determined row to obtain an estimated number of increment events counted within the counter value range; and adding the count offset value specified by the determined row to the estimated number of increment events.

18. The method of claim 11, wherein, the random sequence of binary bits comprises a plurality of bits, and wherein causing the current counter value to probabilistically grow comprises evaluating a subset of the bits based on a probability sub-range corresponding to the current counter value.

19. A non-transitory machine-readable storage medium storing instructions executable by a processing resource to: detect an increment event; determine an operating range of the dual-scale counter circuit based on a current counter value and a predetermined threshold value; in response to determining that the current counter value is less than the predetermined threshold value, cause the current counter value to linearly grow; and in response to determining that the current counter value is equal to or greater than the predetermined threshold value, cause the current counter value to probabilistically grow based on a randomly generated sequence of binary bits.

20. The non-transitory machine-readable storage medium of claim 19, the instructions further to look up a counter value range table based on the current counter value, the counter value range table comprising a plurality of rows, each row corresponding to a counter value range, the counter value range having a range start value, a range end value, and a probability of growing the current counter value for the increment event.

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