Integrated circuit device, read-only memory circuit and manufacturing method thereof

Abstract

The invention discloses an integrated circuit device, a read-only memory circuit and a manufacturing method thereof. An integrated circuit (IC) device includes a first transistor and a second transistor, a first transistor includes a first gate coupled to a first word line and including a first work function configuration, a first metal-type definition (MD) section adjacent to the first gate and coupled to one of a bit line or a reference line, a second MD section adjacent to the first gate and coupled to the other of the bit line or the reference line; the second transistor includes a second gate coupled to the second word line and including a second work function configuration different from the first work function configuration, a second MD section adjacent to the second gate, and a third MD section adjacent to the second gate and coupled to one of the bit line or the reference line.

Description

Technical Field

[0001] One embodiment disclosed herein relates to an integrated circuit device, a read-only memory circuit, and a method of manufacturing thereof, particularly to an integrated circuit device, a memory circuit, and a method of operating thereof capable of providing multi-level encoding. Background Technology

[0002] The ongoing trend towards miniaturization of integrated circuits (ICs) has resulted in devices becoming smaller, consuming less power, yet offering more functionality at a higher speed than earlier technologies. This miniaturization has been achieved through design and manufacturing innovations related to increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify semiconductor device designs while ensuring compliance with IC architecture design and manufacturing specifications. Summary of the Invention

[0003] One embodiment of the present disclosure provides an integrated circuit (IC) device including a first transistor and a second transistor. The first transistor includes a first gate, a first metal-matrix (MD) segment, and a second metal-matrix segment. The first gate is coupled to a first word line and includes a first work function configuration. The first metal-matrix segment is adjacent to the first gate and coupled to either a bit line or a reference line. The second metal-matrix segment is adjacent to the first gate and coupled to the other bit line or reference line. The second gate is coupled to a second word line and includes a second work function configuration different from the first work function configuration. The second metal-matrix segment is adjacent to the second gate. A third metal-matrix segment is adjacent to the second gate and coupled to either a bit line or a reference line.

[0004] Another embodiment of the present disclosure provides a read-only memory (ROM) circuit including a plurality of word lines, a plurality of bit lines, a plurality of reference lines, a plurality of read-only memory cells, and a sense amplifier. Each read-only memory cell includes a transistor, the transistor including a first gate, a first type of metal-defined segment, and a second type of metal-defined segment. The first gate is coupled to a corresponding word line among the word lines, and the first gate includes a corresponding work function configuration among a plurality of work function configurations. The first type of metal-defined segment is adjacent to the first gate and coupled to a corresponding bit line among the bit lines. The second type of metal-defined segment is adjacent to the first gate and coupled to a corresponding reference line among the reference lines. The sense amplifier is selectively coupled to each read-only memory cell among the read-only memory cells. The sense amplifier is used to output a plurality of bits having a plurality of values ​​based on the work function configurations among the work function configurations.

[0005] Another embodiment of the present disclosure provides a method for manufacturing an integrated circuit device, the method comprising the following steps: Constructing a first transistor, the step of constructing the first transistor comprising the following steps: Constructing a first gate including a first work function configuration; and forming first and second type metal boundary segments adjacent to the first gate. Constructing a second transistor, the step of constructing the second transistor comprising the following steps: Constructing a second gate adjacent to the second type metal boundary segment and including a second work function configuration different from the first work function configuration; and forming a third type metal boundary segment adjacent to the second gate. Forming first to fifth via structures on individual of these first to third type metal boundary segments and on the first and second gates. Forming one of a bit line or a reference line on each of the first and third via structures, and forming the other of a bit line or reference line on the second via structure. Forming first and second word lines on individual of these fourth and fifth via structures. Attached Figure Description

[0006] This disclosure presents an embodiment of the form in conjunction with the accompanying documents. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a schematic diagram of a memory circuit according to some embodiments;

[0008] Figures 2A to 2D These are plan views, side views, and cross-sectional views of an IC device and layout according to some embodiments;

[0009] Figures 3A to 3DThese are plan views, side views, and cross-sectional views of an IC device and layout according to some embodiments;

[0010] Figures 4A to 4D These are plan views, side views, and cross-sectional views of an IC device and layout according to some embodiments;

[0011] Figure 5A Describe memory circuit operating parameters according to some embodiments;

[0012] Figures 5B to 5D This is a cross-sectional view of the IC structure and layout according to some embodiments;

[0013] Figure 6 This is a flowchart of a method for operating a memory circuit according to some embodiments;

[0014] Figure 7 This is a flowchart of a method for manufacturing an IC device according to some embodiments;

[0015] Figure 8 This is a flowchart of a method for generating an IC layout diagram according to some embodiments;

[0016] Figure 9 The system block diagram is generated based on the IC layout diagram of some embodiments;

[0017] Figure 10 This is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments.

[0018] [Symbol Explanation]

[0019] 100: Memory Circuit

[0020] 110: Array

[0021] 112: Memory Unit

[0022] 120: Character line driver

[0023] 130: Read Interface

[0024] 140: Control Circuit

[0025] 142: Processor

[0026] 144: Storage Media

[0027] 200~400: IC Device / Layout Diagram

[0028] 500B~500D: IC Structure / Layout Diagram

[0029] 600: Method

[0030] 602~606: Operation

[0031] 700: Method

[0032] 702~706: Operation

[0033] 800: Method

[0034] 802~810: Operation

[0035] 900: IC Layout Generation System

[0036] 902: Processor

[0037] 904: Computer-readable storage media

[0038] 906: Instruction

[0039] 907: Unit Library

[0040] 908: Bus

[0041] 909: Layout Diagram

[0042] 910: I / O Interface

[0043] 912: Network Interface

[0044] 914: Network

[0045] 942:UI

[0046] 1000: IC Manufacturing System

[0047] 1020: Design Factory

[0048] 1022: (IC) Design Layout Diagram

[0049] 1030: Photomask Factory

[0050] 1032: Data Preparation

[0051] 1044: Photomask Manufacturing

[0052] 1045: Light Mask

[0053] 1050: (IC) Manufacturer

[0054] 1052: Manufacturing equipment

[0055] 1053: Semiconductor wafer

[0056] 1060: IC device

[0057] AA: Active Zone / Area

[0058] DG / G: Gate Region / Structure

[0059] MD:MD area / segment

[0060] SD:S / D area / structure S

[0061] VD / VG: Through-hole region / structure

[0062] VTh1~VTh4: Threshold voltage

[0063] WF: Work Function Configuration

[0064] WF1~WF4: Work function configuration

[0065] W1

[00] , W2

[01] : Signals

[0066] W3

[10] , W4

[11] : Signals

[0067] WL0~WL3: Character Lines

[0068] BL, BL0~BL3: Bit lines

[0069] VSS: Reference Line

[0070] CTRL: Control signal

[0071] CTRLB: Control Signal Bus Detailed Implementation

[0072] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific instances of components, values, operations, materials, configurations, or the like are described below to simplify one embodiment of this disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, configurations, or the like are also contemplated. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of an embodiment of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0073] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly.

[0074] In various embodiments, the integrated circuit (IC) device, read-only memory (ROM) circuit, and corresponding method include transistors having a predetermined number of work function configurations. The multiple work function configurations, and in some embodiments, threshold voltages corresponding to the work function configurations, represent encoding levels, enabling the ROM circuit to determine the encoding level by detecting the work function configuration of a single IC device transistor (e.g., by detecting threshold voltages) and output multiple bits based on the encoding level.

[0075] Therefore, compared to other methods, such as those that use a single transistor location to represent a binary code level based on the presence or absence of a working transistor, this IC device can achieve increased coding density by providing multi-level coding within a smaller area. Because the IC device includes working transistors at each transistor location, it is also less susceptible to decoding via reverse engineering (e.g., optical methods) compared to other methods, thus providing enhanced coding security.

[0076] As described below, according to various embodiments, Figure 1 This is a schematic diagram of memory circuit 100. Figures 2A to 2D , Figures 3A to 3D ,and Figures 4A to 4D These are the plan view, side view, cross-sectional view, and layout diagram of the corresponding IC device, ranging from 200 to 400. Figure 5A Describe the operating parameters of the memory circuit. Figures 5B to 5D These are cross-sectional views of the IC structure and IC layout diagrams 500B to 500D. Figure 6 This is a flowchart of method 600 for operating memory circuits. Figure 7 This is a flowchart of method 700 for manufacturing memory circuits. Figure 8 For example, using Figure 9 The IC layout diagram depicted in the diagram generates a system 900, and / or according to... Figure 10 The flowchart depicts the IC manufacturing process 1000 to generate an IC layout diagram 800.

[0077] For illustrative purposes, Figures 1 to 5D Simplified. In some embodiments, one or more of the memory circuit 100, IC device / layout diagrams 200-400, or IC structure / layout diagrams 500B-500D include, except... Figures 1 to 5D Features other than those described herein, such as global control and / or input / output (I / O) circuitry for generating, propagating, and / or receiving one or more signals, including the signals discussed below and / or other signals. Figures 1 to 5D Some circuit elements depicted include corresponding input and / or output terminals, which are not labeled for clarity.

[0078] Figure 1 This is a schematic diagram of a memory circuit 100 according to some embodiments. In some embodiments, the memory circuit 100 is some or all of an IC. In some embodiments, the memory circuit 100 is included in another IC circuit and / or package, such as digital circuitry, analog circuitry, compute-in-memory (CIM) circuitry, system-on-chip (SOC) circuitry, circuitry located in a fan-out, 3D, 2.5D, or other IC package, and / or other suitable circuitry.

[0079] The memory circuit 100 includes an array 110 of memory cells 112 coupled to a word line driver 120 and a read interface 130, and control circuitry 140 coupled to the word line driver 120 and the R / W interface 130 via a control signal bus CTLLB. The memory circuit 100 is configured to perform some or all of the methods described below. Figure 6 The method 600, wherein data is read from one or more instances of memory unit 112, as described below.

[0080] Figure 1 The configuration and orientation features of the memory circuit 100 depicted are non-limiting examples provided for illustrative purposes. Except... Figure 1 Configurations and orientations not depicted herein are also within the scope of one embodiment disclosed herein.

[0081] Two or more circuit elements are considered coupled based on one or more direct signal connections between them and / or one or more indirect signal connections including one or more logic devices (e.g., inverters or logic gates). In some embodiments, signal communication between two or more coupled circuit elements can be modified by one or more logic devices, for example, by reversing or making it conditional.

[0082] exist Figure 1In the embodiment depicted, the memory circuit 100 is configured as a ROM circuit, which includes memory cells 112 configured as ROM cells, wherein data storage is a part of the manufacturing process used to construct the memory circuit 100, for example, according to the following... Figure 7 The method 700 is based on one or more IC layout diagrams, for example, according to the following... Figure 8 The method described above generates 800.

[0083] Array 110 includes memory cells 112 arranged in columns and rows (unlabeled) (individual instances are labeled for clarity). Each memory cell 112 is coupled to an instance of one of the word lines WL0 to WL3, one of the bit lines BL0 to BL3, and a reference line VSS.

[0084] For clarity, in some embodiments, in addition to corresponding word lines, bit lines, and reference lines, reference indicators WL0 to WL3 also represent word line signals, reference indicators BL0 to BL3 also represent bit line signals, and reference indicator VSS also represents reference voltage level VSS, such as ground, as described below.

[0085] exist Figure 1 In the embodiments depicted, for illustrative purposes, array 110 includes a total of four columns and / or rows. In various embodiments, array 110 includes a total of less than or greater than four columns and / or rows.

[0086] exist Figure 1 In the embodiments depicted, array 110 includes columns and rows (not labeled) arranged along individual column and row dimensions. In some embodiments, array 110 has a three-dimensional (3D) configuration, also known as a stacked configuration, which includes one or more array layers (not shown) perpendicular to the [column and row dimensions]. Figure 1 The column and row dimension configuration of a single layer depicted in the diagram makes array 110 include, except for Figure 1 Columns and rows other than those depicted in the text.

[0087] exist Figure 1 In the embodiments depicted, each memory cell 112 is a three-terminal transistor device, including at least one gate coupled to one of the word lines WL0 to WL3, at least one source / drain (S / D) terminal coupled to one of the bit lines BL0 to BL3, and at least one S / D terminal coupled to one of the reference lines VSS. In some embodiments, one or more of the memory cells 112 include a fourth terminal, for example, a body terminal or main terminal coupled to one of the reference lines VSS.

[0088] In some embodiments, the memory circuit 100 includes, except Figure 1 The signal lines depicted in the image are different from or different from those in the image. Figure 1 The signal lines depicted herein are one or more signal lines, such as one or more control lines or power supply voltage lines. In some embodiments, one or more memory cells 112 include one or more terminals in addition to or as alternatives to the terminals described above.

[0089] In some embodiments, the transistor device of a given memory cell 112 includes a planar transistor, a fin field-effect transistor (FinFET), a gate-all-around (GAA) transistor, for example, having a nanosheet configuration, or another suitable configuration including at least one gate. In various embodiments, the transistor device of a given memory cell 112 includes an n-type transistor or a p-type transistor. In various embodiments, each memory cell 112 is included in one of IC devices 200-400, as referenced below. Figures 2A to 4D The aforementioned, and / or including at least one of the gate structures 500B to 500D, as described below regarding Figures 5A to 5D As stated above.

[0090] As described below, each memory cell 112 includes at least one gate, which has one of a predetermined number of work function configurations, for example, the following regarding Figures 2A to 5D The work function configuration is WF or WF1 to WF4. In some embodiments, each memory cell 112 thereby includes a transistor having one of a predetermined number of threshold voltages corresponding to the work function configuration.

[0091] In some embodiments, the total number of work function configurations is the same as the total number of threshold voltages. In some embodiments, based on more than one work function configuration corresponding to a given threshold voltage, the total number of work function configurations is greater than the total number of threshold voltages.

[0092] In various embodiments, a given work function configuration includes one or more layers of work function material positioned within the gate electrode of a transistor adjacent to one or more dielectric materials, which are used to electrically isolate the gate electrode from one or more channel regions included in the active region of the transistor.

[0093] Work function materials with one or more layers include n-type and / or p-type work function materials having one or more thicknesses, concentration levels, dopants, impurities, or the like, used to increase or decrease the work function of the gate electrode by a target value compared to the work function of an equivalent gate electrode that does not contain one or more layers of work function materials. Non-limiting examples of work function materials include Ti, Ag, Al, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr.

[0094] The threshold voltage of a transistor is a function of operating conditions (e.g., voltage bias level, and / or temperature) and the work function of the corresponding gate electrode. For a predetermined set of operating conditions, such as within a predetermined voltage and / or temperature range, a given target value for an increase or decrease in the work function is translated into an increase or decrease in the threshold voltage of a transistor including the corresponding gate electrode, compared to the threshold voltage of an equivalent transistor having an equivalent gate electrode that does not include one or more layers of work function material.

[0095] Therefore, each work function configuration corresponds to a predetermined threshold voltage of the corresponding transistor, so that multiple work function configurations can be used to define a predetermined number of threshold voltages.

[0096] As the total number of threshold voltages increases, the corresponding number of coding levels for each memory cell 112 also increases, thereby increasing the coding density of each memory cell 112. In some embodiments, as the total number of threshold voltages increases, one or more differences between threshold voltages decrease and / or the total span of threshold voltages increases, which may impair the ability to reliably detect each threshold voltage among the total number of threshold voltages.

[0097] In some embodiments, the total number of threshold voltages is in the range of two to 32. In some embodiments, the total number of threshold voltages is equal to four, eight, or 16. In some embodiments, the total number of threshold voltages is greater than 32.

[0098] The character line driver 120 is an electronic circuit that responds to one or more of the control signals CTRL received from the control circuit 140 on the control signal bus CTLLB and / or from one or more circuits (not shown) outside the memory circuit 100, by outputting character line signals WL0 to WL3 on individual character lines WL0 to WL3.

[0099] In some embodiments, a signal (e.g., a control signal CTRL) is a time-based series of transitions between high and low voltage levels, for example, corresponding to high and low logic levels. A high voltage or logic level corresponds to a voltage within a predetermined range of power supply voltage levels, such as the VDD voltage level; a low voltage or logic level corresponds to a voltage within a predetermined range of reference voltage levels, such as the VSS voltage level.

[0100] During a read operation, the word line driver 120 responds to one or more control signals CTRL by outputting word line signals WL0-WL3 on one of the corresponding word lines WL0-WL3, for example, corresponding to a column or row address, including one or more voltage levels, also referred to in some embodiments as one or more read or bias voltages WL0-WL3, to combine one or more bit line voltage levels BL0-BL3 with the read interface 130 operation discussed below, to detect the threshold voltage of the corresponding memory cell 112 transistor based on the corresponding work function configuration.

[0101] In some embodiments, the read interface 130, also referred to as the area I / O circuit 130, is an electronic circuit that responds to one or more control signals CTRL received from the control circuit 140 on the control signal bus CTLLB and / or from one or more circuits (not shown) outside the memory circuit 100, and outputs bit line signals BL0 to BL3 on bit lines BL0 to BL3.

[0102] During a read operation, the read interface 130 responds to one or more of the control signals CTRL by outputting bit line signals BL0-BL3 on the corresponding bit lines BL0-BL3. In some embodiments, these signals are also referred to as one or more read or bias voltages BL0-BL3, for example, corresponding to a row or column address, including one or more voltage levels. These voltage levels are used in conjunction with the aforementioned one or more word line voltage levels WL0-WL3 and the read interface 130 operation discussed below to detect the threshold voltage of the corresponding memory cell 112 transistor.

[0103] The read interface 130 includes one or more signal detection circuits (not shown), such as a current detector and / or a sense amplifier, to perform one or more read operations based on one or more signals received on one or more bit lines BL0 to BL3 and / or a reference line VSS or a combination thereof, such as measuring one or more currents, voltages, or voltage differences, wherein the threshold voltage of the transistor of the selected memory cell 112 is detected.

[0104] One or more signal detection circuits are used to determine the encoding level of the selected memory cell 112 based on the detected threshold voltage. In some embodiments, the encoding level is determined based on one or a combination of the detected threshold voltages, which are within one or more predetermined ranges of voltage levels, or are greater than and / or less than one or more predetermined voltage levels. In some embodiments, one or more signal detection circuits are used to determine the encoding level of the selected memory cell 112 based on one or more currents (e.g., channel currents) corresponding to one or more voltage levels of bit line signals BL0 to BL3, combined with the gate work function configuration of the gate of the corresponding memory cell 112 transistor as described above.

[0105] One or more signal detection circuits of the read interface 130 are used to generate one or more output signals, such as signals W1

[00] to W4

[11] discussed below, which include multiple bits having values ​​corresponding to the encoding level of the memory cell 112 corresponding to the threshold voltage.

[0106] In some embodiments, a given output signal is considered to correspond to a single memory cell 112, and the total number of bits N of the plurality of bits is 2 N The total number of threshold voltages for memory cell 112 is given. Non-limiting examples include a total number of bits N equal to two corresponding to a total of four threshold voltages, a total number of bits N equal to three corresponding to a total of eight threshold voltages, and a total number of bits N equal to four corresponding to a total of 16 threshold voltages.

[0107] According to the embodiments discussed herein, control circuitry 140 is an electronic circuit used to control the operation of memory circuitry 100 by generating one or more control signals CTRL on the control signal bus CTRLB and receiving them by word line driver 120 and read interface 130. In various embodiments, control circuitry 140 includes hardware processor 142 and non-transitory computer-readable storage medium 144. Among other things, storage medium 144 is also encoded with computer program code, i.e., a set of executable instructions. The instructions, executed by hardware processor 142, represent (at least partially) memory circuitry operation tools that implement the following... Figure 7 The method 700 (hereinafter referred to as the process and / or method) is a part or all of the method.

[0108] Processor 142 is electrically coupled to non-transitory computer-readable storage medium 144, an I / O interface, and a network via a bus (details not shown). The network interface is connected to a network (not shown) so that processor 142 and non-transitory computer-readable storage medium 144 can be connected to external components via the network. Processor 142 is used to execute computer program code encoded in non-transitory computer-readable storage medium 144 so that control circuitry 140 and memory circuitry 100 can be used to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 142 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0109] In one or more embodiments, the non-transitory computer-readable storage medium 144 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the non-transitory computer-readable storage medium 144 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random-access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the non-transitory computer-readable storage medium 144 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0110] In one or more embodiments, the non-transitory computer-readable storage medium 144 stores computer program code that causes the control circuitry 140 to generate control signals so as to be used to perform part or all of the mentioned process and / or method. In one or more embodiments, the non-transitory computer-readable storage medium 144 also stores information that facilitates the performance of part or all of the mentioned process and / or method.

[0111] With the above configuration, the memory circuit 100 includes memory cells 112 with multiple work function configurations, thereby having multiple threshold voltages representing the encoding level, so that the memory circuit 100 can determine the encoding level by detecting the threshold voltage of a single IC device transistor and output multiple bits based on the encoding level.

[0112] Therefore, compared to other methods, such as those that use a single transistor location to represent a binary code level based on the presence or absence of a working transistor, this given memory cell 112 can achieve increased coding density by providing multi-level coding within a smaller area. Because the memory cell 112 includes working transistors at each cell location, the array 110 of the memory cell 112 is also less easily decoded via reverse engineering (e.g., by optical methods) compared to other methods, thereby providing improved coding security.

[0113] The IC layout diagrams / devices 200-400 and IC layout diagrams / structures 500B-500D discussed below each include some or all of the configurations of at least one of semiconductor substrates, active regions / areas, S / D regions / structures, MD regions / segments, gate regions / structures, metal regions / segments, and / or via regions / structures, each of which is discussed below.

[0114] A semiconductor substrate is a semiconductor wafer (e.g., a silicon (Si) wafer) or a portion (e.g., a die) of an epitaxial Si layer suitable for forming one or more IC devices (e.g., IC devices 200-400). In each of the embodiments discussed below, the semiconductor substrate includes a front side and a back side. In the front side, a first subset of features of the IC device is formed via a first set of manufacturing processes, such as a front-end-of-line (FEOL) process, a middle-end-of-line (MEOL) process, and a back-end-of-line (BEOL) process. In the back side, a second subset of features of the IC device is formed via a second set of manufacturing processes, such as a back-side metallization process performed after the first set of manufacturing processes.

[0115] An active region / area (e.g., active region / area AA) is a region in the manufacturing process that defines an active region (also known as oxide diffusion or definition, OD) in an IC layout diagram, either directly in the semiconductor substrate or in an n-well or p-well region / area, where one or more IC device features, such as an S / D structure, are formed. In some embodiments, the active region is a planar transistor, a FinFET, a GAA transistor, or an n-type or p-type active region of another transistor configuration including a gate region / structure.

[0116] In various embodiments, the active region (structure) includes one or more of a semiconductor material (e.g., silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), or the like), a dopant material (e.g., boron (B), aluminum (Al), phosphorus (P), arsenic (As), gallium (Ga)), or another suitable material.

[0117] In some embodiments, the active region is a region included in the manufacturing process as part of an IC layout diagram that defines a nanosheet structure (e.g., a continuous volume of one or more layers of one or more semiconductor materials having n-type or p-type doping). In various embodiments, a single nanosheet layer comprises a single monolayer or multiple multilayers of a given semiconductor material.

[0118] An S / D region / structure (e.g., an S / D region / structure SD) is a region included in the manufacturing process in an IC layout diagram as a portion defining an S / D structure (also referred to in some embodiments as a semiconductor structure, intended to have a doping type opposite to the corresponding active region / region). In some embodiments, the S / D region / structure is intended to have a lower resistivity than adjacent channel features, such as a portion of the corresponding active region / region of a planar FET, the fin structure of a FinFET, or the gate structure of a GAA transistor. In some embodiments, the S / D region / structure includes one or more portions having a doping concentration greater than one or more doping concentrations present in the corresponding channel feature. In some embodiments, the S / D region / structure includes one or more epitaxial regions of a semiconductor material (e.g., Si, SiGe, and / or silicon carbide SiC). An S / D region / structure (also referred to in some embodiments as an S / D terminal) may refer individually or collectively to the source or drain, depending on the context.

[0119] MD regions / segments (e.g., MD regions / segments MD) are portions in an IC layout that define MD segments (also referred to as conductive segments or MD wires or traces) in and / or on a semiconductor substrate, and are included in the conductive regions during the manufacturing process. In some embodiments, the MD region overlaps with the active region at the location of the S / D region in the IC layout, and the corresponding MD segment contacts and is electrically connected to the S / D structure of the active region.

[0120] In some embodiments, the MD segment includes a portion of at least one metal layer (e.g., a contact layer) overlying and contacting the substrate, and has a thickness small enough to form an insulating layer between the MD segment and the overlying metal layer (e.g., a first metal layer). In various embodiments, the MD segment includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing low-resistance (i.e., resistance levels below predetermined threshold values ​​corresponding to one or more tolerance levels for the effect of resistance on circuit performance) electrical connections between IC structural elements.

[0121] In various embodiments, the MD segment includes a portion of a semiconductor substrate and / or an epitaxial layer having a doping level, for example based on the implantation process, sufficient to give the segment a low resistance level. In various embodiments, the doped MD segment includes one or more dopant materials having a doping concentration of about 1*10¹⁶ per cubic centimeter (cm⁻³) or higher.

[0122] In some embodiments, the manufacturing process includes two MD layers, and MD regions / segments (e.g., MD regions / segments MD) refer to both of the two MD layers in the manufacturing process.

[0123] A gate region / structure (e.g., gate region / structure G or DG) is a region included in the manufacturing process as part of the IC layout that defines the gate structure. A gate structure is a volume comprising one or more conductive segments (e.g., gate electrodes) comprising one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, substantially surrounded by one or more insulating materials, thereby controlling the voltage supplied at adjacent gate dielectric layers.

[0124] In some embodiments, a given gate region in the IC layout diagram is included as a portion defining the gate electrode in the manufacturing process. The gate electrode includes corresponding work function configurations of multiple work function configurations, for example, work function configurations WF1 to WF4, as described above. Figure 1 The discussion.

[0125] The gate dielectric layer, for example, the gate dielectric layer of a gate structure G or DG (such as the dielectric layer GD described below), is a volume comprising one or more insulating materials, such as silicon dioxide, silicon nitride (Si3N4), and / or one or more other suitable materials, such as low-k materials with a k value less than 3.8 or high-k materials with a k value greater than 3.8 or 7.0, such as alumina (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2), suitable for providing high resistance between IC structural elements, i.e., resistance levels higher than predetermined threshold values ​​corresponding to one or more tolerance levels of resistance's effect on circuit performance.

[0126] In some embodiments, the gate region / structure corresponds to a dummy gate region / structure, such as a dummy gate region / structure DG. In some embodiments, the dummy gate region / structure includes a gate electrode electrically connected (e.g., bound) to one or more features (e.g., power rails or other metal segments or adjacent instances of the S / D region / structure) to turn off transistors corresponding to the dummy gate region / structure and overlapping / underlying the active region / region. In some embodiments, the dummy gate region / structure overlapping / overlying the edge of the active region / region is referred to as a continuous polyon oxide definition edge (CPODE) region / structure.

[0127] Metal lines or regions (e.g., character lines WL0-WL3 or bit lines BL0-BL3) are areas in the IC layout that define metal lines or segments and are included in the manufacturing process. They include one or more conductive materials in a given front or back metal layer of the manufacturing process, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials.

[0128] In some embodiments, the metal region / segment corresponds to a first front metal layer (also referred to in some embodiments as a metal zero layer or front metal zero layer) or a second or higher level front metal layer in the manufacturing process. In some embodiments, the second front metal layer is referred to as a metal monolayer or front metal monolayer.

[0129] In some embodiments, a metal region / segment (e.g., a reference line VSS) corresponds to a component of a power distribution network used to distribute one or both of a power supply voltage (e.g., a power supply voltage VDD) and a reference or ground voltage (e.g., a reference voltage VSS). The power distribution network component is electrically connected to one or more features, such as additional metal regions / segments and / or via regions / structures, for distributing the corresponding power supply or reference voltage and is electrically isolated from IC components outside the distribution network.

[0130] A via region / structure (e.g., via region / structure VG or VD) is a region included in the manufacturing process as part of the IC layout that defines the via structure. The via structure includes one or more conductive materials used to provide electrical connection between a first (e.g., overlay) conductive structure (e.g., word lines WL0-WL3, bit lines BL0-BL3, or reference line VSS) and a second (e.g., underlay) conductive structure (e.g., metal segment, gate electrode of gate structure G or DG, instance of MD segment MD, or S / D structure). These conductive structures are aligned with the first conductive structure in the Z direction.

[0131] In some embodiments, the via region / structure VG corresponds to the underlying conductive structure of the gate electrode as the gate region / structure G or DG, and / or the via region / structure VD corresponds to the underlying conductive structure as the S / D region / structure or MD region / segment MD.

[0132] Figures 2A to 2D , Figures 3A to 3D ,and Figures 4A to 4D These are individual IC layout diagrams / devices 200-400, including plan views, side views, and cross-sectional views. Figure 2A , Figure 3A ,and Figure 4A It is a plan view, including the X and Y directions; Figure 2B , Figure 3B ,and Figure 3C Based on correspondence Figure 2A , Figure 3A ,or Figure 4A A side view of line A-A', including the X and Z directions; Figure 2C , Figure 3C ,and Figure 4C Is along the corresponding Figure 2A , Figure 3A ,or Figure 4A A cross-sectional view of line B-B', including the Y and Z directions; Figure 2D , Figure 3D ,and Figure 4D Is along the corresponding Figure 2A , Figure 3A ,or Figure 4A A cross-sectional view of line C-C', including the Y and Z directions.

[0133] IC layout diagrams / devices 200-400 including the above. Figure 1 The memory cell 112 described is a non-limiting example, and for illustrative purposes, corresponds to an n-type GAA transistor with a nanosheet configuration. IC layouts / devices of memory cells 112 corresponding to other transistor types (e.g., p-type transistors and / or FinFETs or planar transistors) are also within the scope of an embodiment disclosed herein.

[0134] like Figures 2A to 4D The IC layouts / devices 200-400 depicted include one or more instances of the active region / area AA, S / D region / structure SD, MD region / segment MD, via region / structure VD, gate region / structure G including work function configuration WF, dummy gate region / structure DG, via region / structure VG, bit line BL corresponding to one of the aforementioned bit lines BL0-BL3, reference line VSS, and word lines WL0 and WL1. The IC layouts / devices 300 and 400 also include word lines WL2 and WL3. In some cases, for clarity, not all instances of each feature are shown. Figures 2A to 4D The middle mark.

[0135] exist Figures 2A to 4D In the embodiments described above, the work function configuration WF represents as described above. Figure 1 Any one of the multiple work function configurations, WF, and in the following... Figures 5A to 5D The non-limiting examples discussed are illustrated in the figures.

[0136] like Figures 2A to 2DThe IC layout / device 200 depicted includes active regions / regions AA extending between first and second edges, which intersect / lie beneath instances of dummy gate regions / regions DG. A total of four instances of gate regions / structures G intersect / cover the active regions / regions AA, and a total of five instances of each of the S / D regions / structures SD and MD regions / segments MD intersect / cover the active regions / regions AA adjacent to instances of gate regions / structures DG and G.

[0137] Three instances of via region / structure VD overlap / overlay alternating instances of MD region / segment MD and overlap / under one of bit line BL or reference line VSS; two instances of via region / structure VD overlap / overlay instances of other MD region / segment MD and overlap / overlay another of bit line BL and reference line VSS; two instances of via region / structure VG overlap / overlay instances of via gate region / structure G and overlap / under word line WL1; and two instances of via region / structure VG overlap / overlay two instances of via gate region / structure G and overlap / under word line WL0.

[0138] The IC layout / device 200 is thus used to include a first instance (marked) of a memory cell 112 corresponding to a transistor comprising two instances of a gate region / structure G coupled to a word line WL1 via an instance of a via region / structure VG, two adjacent instances of each of the S / D region / structure SD and MD region / segment MD of one of the bit line BL or the reference line VSS coupled via an instance of a via region / structure VD, and a single instance of each of the S / D region / structure SD and MD region / segment MD of the other of the bit line BL or the reference line VSS coupled via an instance of a via region / structure VD.

[0139] A second instance (unlabeled) of memory cell 112 corresponds to a transistor comprising two instances of gate region / structure G coupled to word line WL0 via an instance of via region / structure VG, two adjacent instances of each of S / D region / structure SD and MD region / segment MD coupled to one of bit line BL or reference line VSS via an instance of via region / structure VD, and a single instance of each of S / D region / structure SD and MD segment MD coupled to the other of bit line BL or reference line VSS via an instance of via region / structure VD. One instance of each of S / D region / structure SD, MD segment MD, and via region / structure VD is shared by instances of memory cell 112.

[0140] like Figures 2A to 2D and Figures 3A to 3DThe IC layout diagrams / devices 300 and 400 depicted therein include a first instance of an active region / region AA extending between a first and a second instance of a dummy gate region / region DG.

[0141] IC layout / device 300 includes a first instance of an active region / region AA that extends continuously beyond instances of a dummy gate region / structure DG in both the positive and negative X directions. A via region / structure VG covers / overlays each instance of the dummy gate DG and covers / underlays a reference line VSS, such that during operation, by applying a reference voltage VSS to each instance of the dummy gate region / structure DG, portions of the active region AA between instances of the dummy gate region / structure DG are electrically isolated from the extended portions.

[0142] IC layout / device 400 includes a first instance of an active region / region AA extending between the first and second edges of an instance of a cross / underlying dummy gate region / region DG, and second and third instances of an active region / region AA extending beyond the instance of the dummy gate region / structure DG in the positive and negative X directions away from the first instance of the active region / region AA, thereby being electrically isolated from the first instance of the active region / region AA.

[0143] Each of the IC layout diagrams / devices 300 and 400 includes a total of two instances of a gate region / structure G, which crosses / overlays instances of active regions / regions AA between instances of a dummy gate region / structure DG; and a total of three instances of an S / D region / structure SD and an MD region / segment MD, which crosses / overlay instances of active regions / regions AA adjacent to instances of gate regions / structures DG and G.

[0144] Two instances of via region / structure VD overlap / overlay alternating instances of MD region / segment MD and overlap / overlay one of bit line BL or reference line VSS; one instance of via region / structure VD overlaps / overlays another instance of MD region / segment MD and overlaps / underlays the other of bit line BL and reference line VSS; one instance of via region / structure VG overlaps / overlays an instance of via gate region / structure G and overlaps / overlays word line WL2; and one instance of via region / structure VG overlaps / overlays an instance of via gate region / structure G and overlaps / underlays word line WL1.

[0145] The IC layout / device 200 is thus used to include a first instance (marked) of memory cell 112 corresponding to a transistor, the transistor including an instance of gate region / structure G coupled to word line WL2 via an instance of via region / structure VG, an adjacent instance of each of S / D region / structure SD and MD region / segment MD coupled to one of bit line BL or reference line VSS via an instance of via region / structure VD, and an adjacent instance of each of S / D region / structure SD and MD region / segment MD coupled to the other of bit line BL or reference line VSS via an instance of via region / structure VD.

[0146] A second instance (unlabeled) of memory cell 112 corresponds to a transistor comprising an instance of a gate region / structure G coupled to word line WL1 via an instance of a via region / structure VG; an adjacent instance of each of the S / D region / structure SD and MD region / segment MD coupled to one of bit line BL or reference line VSS via an instance of a via region / structure VD; and an adjacent instance of each of the S / D region / structure SD and MD region / segment MD coupled to the other of bit line BL or reference line VSS via an instance of a via region / structure VD. An instance of each of the S / D region / structure SD, MD segment MD, and via region / structure VD is shared by instances of memory cell 112.

[0147] exist Figures 3A to 4D In the embodiments depicted, each of IC layout diagrams / devices 300 and 400 includes third and fourth instances of memory cell 112, which correspond to word lines WL3 and WL0 and are configured similarly to the first and second instances of memory cell 112. In some embodiments, one or both of IC layout diagrams / devices 300 or 400 do not include one or both of the third or fourth instances of memory cell 112.

[0148] With the above configuration, each of the IC layouts / devices 200 to 400 includes one or more instances of memory cells 112 with multiple work function configurations, thereby having multiple threshold voltages representing encoding levels, so that the memory circuits including one or more of the IC layouts / devices 200 to 400 can achieve the benefits discussed above regarding the memory circuit 100.

[0149] According to various embodiments, Figure 5A Describe the operating parameters of the memory circuit. Figures 5B to 5D This is a cross-sectional view of the IC layout / structure 500B-500D (also referred to as gate region / structure 500B-500D in some embodiments). Each gate region / structure 500B-500D can be used as described above regarding... Figures 2A to 4D One or more instances of the gate region / structure G.

[0150] Figure 5A Including the channel current Id plotted as a function of the source-drain voltage VD of the transistor (e.g., the memory cell 112 described above), having one of the threshold voltages Vth1 to Vth4 corresponding to the gate work function configuration, a non-limiting example of which is... Figures 5B to 5D As depicted in the text.

[0151] exist Figures 5A to 5D In the embodiment depicted, a total of four work function configurations WF1 to WF4 (each corresponding to the aforementioned work function configuration WF) correspond to a total of four threshold voltages Vth1 to Vth4. The threshold voltages Vth1 to Vth4 are associated with individual two-bit signals W1

[00] to W4

[11] . Other numbers of work function configurations, threshold voltages, and signal bits are also within the scope of one embodiment disclosed herein. In some embodiments, signals WF1

[00] to WF4

[11] are as described above regarding... Figure 1 An example of the output signal of the read interface 130.

[0152] exist Figure 5A In the embodiments depicted, the increased threshold voltages Vth1 to Vth4 correspond to increased signal values ​​

[00] to

[11] . Other relationships between threshold voltages and signal values, such as an increased threshold voltage corresponding to a decreased signal value, are also within the scope of an embodiment disclosed herein.

[0153] like Figures 5B to 5D The gate regions / structures 500B to 500D described herein include a gate region / structure G, which includes one or more work function configurations WF1 to WF4, adjacent to one or more gate dielectric layers GD, and each gate dielectric layer GD is adjacent to the channel region of the corresponding active region / region AA. The work function configurations WF1 to WF4 correspond to individual threshold voltages Vth1 to Vth4 and signals W1

[00] to W4

[11] .

[0154] like Figures 5B to 5D As depicted, gate region / structure 500B corresponds to the nanosheet configuration of a GAA transistor, gate region / structure 500C corresponds to the gate configuration of a FinFET, and gate region / structure 500D corresponds to the gate configuration of a planar transistor.

[0155] like Figure 5A The IC layout diagrams / devices depicted herein, including one or more of the gate regions / structures 500B to 500D (e.g., the aforementioned IC layout diagrams or devices 200 to 400), thereby enable the aforementioned benefits of the memory circuit 100 and the IC layout diagrams and devices 200 to 400 to be realized.

[0156] Figure 6This is a flowchart of a method 600 for operating a memory circuit according to some embodiments. Method 600 can be used in memory circuits, for example, including those described above. Figures 1 to 5D The memory circuit 100 is an example of the memory cell 112. In some embodiments, the operation of method 600 is a subset of the operations of methods for operating an IC (e.g., a SOC).

[0157] In some embodiments, the operation of method 600 is repeated, for example, relative to a plurality of memory units (e.g., the above regarding...). Figures 1 to 5D The memory cell 112 (multiple instances) are repeated sequentially. In some embodiments, the operation of method 600 is part of an initialization sequence of an IC or IC package.

[0158] Figure 6 The order of operations of method 600 described herein is for illustrative purposes only; the operations of method 600 can be performed in conjunction with... Figure 6 Different execution sequences are described. In some embodiments, in Figure 6 The operations described in the text are performed before, between, during, and / or after the operations. Figure 6 Operations other than those described.

[0159] At operation 602, in some embodiments, a ROM cell of the memory circuit is selected. Selecting a ROM cell includes outputting a combination of word line and bit line signals based on one or more location identifiers (e.g., addresses) corresponding to the ROM cell.

[0160] In some embodiments, selecting a ROM unit includes selecting the above-mentioned... Figures 1 to 5D An example of the memory unit 112 of the memory circuit 100.

[0161] At operation 604, the threshold voltage of the selected memory cell is detected. Detecting the threshold voltage involves detecting one of a plurality of predetermined threshold voltages, each threshold voltage being based on a corresponding gate work function configuration among a plurality of work function configurations.

[0162] In some embodiments, detecting the threshold voltage includes detecting the threshold voltage of an instance of memory cell 112 including a gate G work function configuration, as described above regarding... Figures 1 to 5D As described above. In some embodiments, detecting the threshold voltage includes based on the above... Figures 2A to 4D The work function configuration WF and / or the above regarding Figures 5A to 5D The power function configurations WF1 to WF4 are used to detect the critical voltage.

[0163] In some embodiments, detecting the threshold voltage includes a read circuit using memory circuitry, for example, as described above regarding... Figure 1 The aforementioned read interface 130.

[0164] In some embodiments, detecting the threshold voltage includes detecting the above-mentioned... Figures 5A to 5D One of the threshold voltages Vth1 to Vth4.

[0165] At operation 606, in some embodiments, a plurality of bits are output having a value based on the detected threshold voltage of the selected memory cell. Outputting the plurality of bits includes outputting a number of bits corresponding to a number of possible predetermined threshold voltages of the selected memory cell, for example, as described above regarding... Figure 1 As stated above.

[0166] In some embodiments, outputting multiple bits includes a read circuit using memory circuitry, for example, as described above regarding... Figure 1 The aforementioned read interface 130.

[0167] In some embodiments, outputting multiple bits includes outputting the above about Figures 5A to 5D One of the signals W1

[00] to W4

[11] .

[0168] In some embodiments, outputting multiple bits includes circuitry that outputs multiple bits to a location outside the memory circuitry, such as a SOC or other IC.

[0169] By performing some or all of the operations of method 600, the encoding of the ROM cell of the memory circuit is determined, and multiple bits having values ​​based on the work function configuration of the ROM cell are output, thereby achieving the benefits described above regarding memory circuit 100, IC layout / device 200-400, and IC layout / structure 500B-500D.

[0170] Figure 7 This is a flowchart of a method 700 for manufacturing an IC device according to some embodiments. Method 700 is operable to form the above-mentioned... Figures 1 to 5D Some or all of one or more of the IC devices 200 to 400.

[0171] In some embodiments, some or all of the operations of performing method 700 are part of constructing a plurality of integrated circuit devices (e.g., transistors, logic gates, memory cells, interconnect structures, and / or other suitable devices) by performing a plurality of manufacturing operations (e.g., lithography, diffusion, deposition, etching, planarization, or one or more other operations suitable for constructing a plurality of IC devices in a semiconductor wafer).

[0172] In some embodiments, the operation of method 700 is as follows: Figure 7 The order in which the method is executed is as described. In some embodiments, the operation of method 700 is different from that described in the text. Figure 7The order in which the operations are described is executed. In some embodiments, one or more additional operations are performed before, during, and / or after the operation of method 700. In some embodiments, performing some or all of the operations of method 700 includes performing the following operations regarding the IC manufacturing system 1000 and Figure 10 The one or more operations mentioned above.

[0173] At operation 702, an active region is formed in the semiconductor substrate. Forming the active region includes forming an active region extending in a first direction between a first edge and a second edge. In some embodiments, forming the active region includes forming the above-mentioned... Figures 1 to 5D An example of the active region AA.

[0174] In some embodiments, forming an active region includes forming, for example, regions corresponding to the above-mentioned aspects. Figure 1 Multiple active regions of the memory cell array (such as array 110).

[0175] In some embodiments, forming an active region includes forming an active region according to a GAA transistor, FinFET, or planar transistor configuration, for example, as described above regarding Figures 1 to 5D As stated above.

[0176] In some embodiments, forming an active region includes performing a plurality of manufacturing processes, including lithography, diffusion, implantation, deposition, etching, planarization, or one or more of other suitable operations.

[0177] At operation 704, a first transistor including a first gate work function configuration and a second transistor including a second gate work function configuration different from the first work function configuration are constructed on the active region. Constructing the first and second transistors includes constructing corresponding gates having first and second work function configurations corresponding to the threshold voltages of each of the first and second transistors.

[0178] In some embodiments, constructing the first and second transistors includes constructing the above-mentioned... Figures 1 to 5D An example of the memory unit 112.

[0179] In some embodiments, constructing the first and second transistors includes constructing an array of memory cells, for example, as described above regarding... Figure 1 The array 110.

[0180] In some embodiments, constructing the first and second transistors includes constructing one or more of IC devices 200-400, including as described above. Figures 2A to 4D An example of the memory unit 112.

[0181] In some embodiments, constructing the gates of the first and second transistors includes constructing the gates described above. Figures 2A to 4D The gate structure G and / or the above regarding Figures 5A to 5D One or more of the gate structures 500B to 500D.

[0182] In some embodiments, constructing the first and second transistors includes constructing a GAA transistor, a FinFET, or a planar transistor.

[0183] In some embodiments, constructing the first and second transistors, including the first and second work function configurations, includes constructing the transistors described above. Figures 2A to 4D The work function configuration WF and / or the above regarding Figures 5A to 5D The first and second transistors of the examples of the work function states WF1 to WF4.

[0184] In some embodiments, constructing the first and second transistors including the first and second work function configurations includes performing a plurality of manufacturing processes, including one or more of lithography, diffusion, implantation, deposition, plasma treatment, etching, planarization, spin coating, soft baking, exposure, post-baking, development, rinsing, drying, or other suitable operations.

[0185] At operation 706, an electrical connection is formed from the first and second transistors to at least one of the word line, bit line, and reference line. Forming the electrical connection includes forming a via structure on the gate and S / D terminal of each transistor, and forming at least one corresponding word line, bit line, and reference line on the via structure, such that each of the first and second transistors is a working transistor.

[0186] In some embodiments, forming an electrical connection includes forming some or all of the following: a via structure VG on the gate structure G, a via structure VD on the MD segment MD, word lines WL0 to WL3 on the gate via structure VGA, bit lines BL0 to BL3 on the via structure VD, and a reference line VSS, as described above. Figures 1 to 5D As stated above.

[0187] In some embodiments, forming an electrical connection includes forming to a memory circuit assembly, for example, as described above. Figure 1 The electrical connection between the character line driver 120 and the read interface 130.

[0188] In some embodiments, forming an electrical connection includes performing multiple manufacturing operations, including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, thereby configuring one or more conductive materials to form multiple continuous low-resistance structures.

[0189] By performing some or all of the operations of method 700, an IC device is manufactured, wherein the first and second transistors include different work function configurations, thereby enabling the benefits described above with respect to memory circuit 100, IC devices 200-400, and IC structures 500B-500D.

[0190] Figure 8 This refers to the generation of IC layout diagrams based on some embodiments (e.g., the above regarding...). Figures 2A to 5D The flowchart of the method 800 (one or more IC layout diagrams 200-400) is described.

[0191] In some embodiments, generating an IC layout includes generating and manufacturing an IC device based on the generated IC layout (e.g., the above regarding...). Figures 2A to 5D The IC layout diagram corresponding to the IC devices 200-400.

[0192] In some embodiments, some or all of the methods 800 are executed by a computer processor, such as processor 902 of IC layout generation system 900, which will be referred to below. Figure 9 To elaborate.

[0193] Some or all of the operations in method 800 can be performed at the design plant (e.g., the following regarding...). Figure 10 The design process is executed in part of the design program in the design plant 1020.

[0194] In some embodiments, the operation of method 800 is as follows: Figure 8 The operations of method 800 are performed in the order described herein. In some embodiments, the operations of method 800 are performed simultaneously and / or in conjunction with... Figure 8 The different orders shown are executed. In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations of the execution method 800.

[0195] At operation 802, in some embodiments, multiple work function configurations are allocated according to a ROM encoding mode. In some embodiments, allocating multiple work function configurations includes obtaining ROM cells from a cell library, for example, as described below regarding... Figure 9 The aforementioned unit library 907, wherein each ROM unit includes a specific work function configuration.

[0196] In some embodiments, allocating multiple work functions includes allocating the above-mentioned... Figures 2A to 4D The work function configuration WF and / or the above regarding Figures 5A to 5D Examples of the work function configurations WF1 to WF4.

[0197] In some embodiments, allocating multiple work function configurations according to the ROM encoding mode includes configurations corresponding to the array (e.g., the above regarding...). Figure 1 The ROM encoding mode of the array 110.

[0198] In some embodiments, allocating multiple work function configurations includes performing a compilation operation to generate a ROM encoding pattern.

[0199] At operation 804, the first and second transistors are configured to include different work function configurations among a plurality of work function configurations. In some embodiments, configuring the first and second transistors includes configuring one or more IC layouts 200-400, including as described above regarding Figures 2A to 4D An example of the memory unit 112.

[0200] In some embodiments, configuring the first and second transistors includes configuring the above-mentioned... Figures 2A to 4D The gate region G and / or above regarding Figures 5A to 5D One or more of the gate regions 500B to 500D.

[0201] In some embodiments, configuring the first and second transistors includes configuring a GAA transistor, a FinFET, or a planar transistor.

[0202] At operation 806, the first and second transistors are overlapped with vias and metal regions. The overlapping vias and metal regions include overlapping via regions on the gate region and S / D region of each transistor, and overlapping the via regions with at least one corresponding word line, bit line, and reference line, such that each of the first and second transistors is a working transistor.

[0203] In some embodiments, overlapping vias and metal regions include overlapping some or all of the via regions VG with the gate region G, overlapping the via region VD with the MD region MD, overlapping word lines WL0 to WL3 with the gate via region VGA, and overlapping bit lines BL0 to BL3 and the reference line VSS with the via region VD, as described above. Figures 1 to 5D As stated above.

[0204] In some embodiments, the overlapping vias and metal regions include those configured to a memory circuit assembly (e.g., the above regarding...). Figure 1 Electrical connection of the character line driver 120 and the read interface 130.

[0205] At operation 808, in some embodiments, an IC layout diagram including the first and second transistors is stored in a storage device. In some embodiments, storing the IC layout diagram in the storage device includes storing the above-mentioned... Figures 2A to 5D One or more of the IC layout diagrams 200 to 400 are stored in a storage device.

[0206] In some embodiments, storing an IC layout diagram in a storage device includes storing the IC layout diagram in non-volatile computer-readable memory or a database, and / or includes storing the IC layout diagram via a network. In some embodiments, storing an IC layout diagram in a storage device includes storing an IC wiring diagram in layout diagram 909 of the IC layout diagram generation system 900 and / or via network 914, as will be referred to below. Figure 9 To elaborate.

[0207] At operation 810, in some embodiments, one or more manufacturing operations and one or more lithography exposures are performed based on the IC layout diagram. (The above is in conjunction with...) Figure 7 and the following text Figure 10 Non-limiting examples of performing one or more manufacturing operations (e.g., one or more lithography exposures) based on IC layout diagrams are discussed.

[0208] By performing some or all of the operations of method 800, an IC layout diagram corresponding to the IC devices with different work function configurations of the first and second transistors is generated, thereby enabling the benefits described above with respect to memory circuit 100, IC devices 200-400, and IC structures 500B-500D.

[0209] Figure 9 This is a block diagram of an IC layout generation system 900 according to some embodiments. The method for designing IC layouts described herein is implementable according to one or more embodiments; for example, according to some embodiments, an IC layout generation system 900 is used.

[0210] In some embodiments, the IC layout generation system 900 is a general-purpose computing device including a hardware processor 902 and a non-transitory computer-readable storage medium 904. Among other things, the storage medium 904 is also encoded (i.e., stores) with computer program code 906, i.e., a set of executable instructions. The hardware processor 902 executes the instructions 906 to represent (at least partially) an electronic design automation (EDA) tool, which implements part or all of a method, for example, as described above regarding... Figure 8 The method 800 for generating IC layout diagrams (hereinafter referred to as the process and / or method).

[0211] Processor 902 is electrically coupled to computer-readable storage medium 904 via bus 908. Processor 902 is also electrically coupled to I / O interface 910 via bus 908. Network interface 912 is also electrically connected to processor 902 via bus 908. Network interface 912 is connected to network 914, enabling processor 902 and computer-readable storage medium 904 to be connected to external components via network 914. Processor 902 is used to execute computer program code 906 encoded in computer-readable storage medium 904 so that IC layout generation system 900 can be used to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0212] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random-access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 904 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0213] In one or more embodiments, the computer-readable storage medium 904 stores computer program code 906 that enables the IC layout generation system 900 (wherein this execution representation (at least partially) EDA tool) to perform part or all of the mentioned processes and / or methods. In one or more embodiments, the computer-readable storage medium 904 also stores information that facilitates the performance of part or all of the mentioned processes and / or methods.

[0214] In one or more embodiments, computer-readable storage medium 904 stores a unit library 907 including the units disclosed herein, for example, those described above regarding Figures 1 to 5D The memory cell 112 in the IC layout diagrams 200-400.

[0215] In one or more embodiments, the computer-readable storage medium 904 stores a layout diagram 909, including the IC layout diagrams disclosed herein, for example, those mentioned above. Figures 1 to 5D The IC layout diagrams 200-400 are described above.

[0216] The IC layout generation system 900 includes an I / O interface 910. The I / O interface 910 is coupled to an external circuit system. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or directional keys for conveying information and commands to the processor 902.

[0217] The IC layout generation system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 allows the system 900 to communicate with a network 914 to which one or more other computer systems are connected. The network interface 912 includes a wireless network interface, such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethereum, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more IC layout generation systems 900.

[0218] The IC layout generation system 900 receives information via I / O interface 910. The information received via I / O interface 910 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 902. This information is transferred to processor 902 via bus 908. The IC layout generation system 900 also receives UI-related information via I / O interface 910. This information is stored as a user interface (UI) 942 in computer-readable medium 904.

[0219] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by an IC layout generation system 900. In some embodiments, a software application such as those available from CADENCE DESIGN SYSTEMS, Inc. is used. Use tools or another suitable layout generation tool to generate layout diagrams that include standard cells.

[0220] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards), and one or more of the like.

[0221] Figure 10 This is a block diagram of an IC manufacturing system 1000 according to some embodiments, and an associated IC manufacturing process. In some embodiments, based on an IC layout diagram, the manufacturing system 1000 is used to manufacture at least one of (A) one or more semiconductor photomasks or (B) at least one component of a layer of a semiconductor integrated circuit.

[0222] exist Figure 10 In this IC manufacturing system 1000, entities such as a design plant 1020, a photomask plant 1030, and an IC manufacturer / fab (“fab”) 1050 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 1060. These entities in system 1000 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as Ethernet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design plant 1020, photomask plant 1030, and IC fabrication plant 1050 are owned by a single larger company. In some embodiments, two or more of the design plant 1020, photomask plant 1030, and IC fabrication plant 1050 coexist in a common facility and use common resources.

[0223] The design firm (or design team) 1020 produces the IC design layout 1022. The IC design layout 1022 includes various geometric patterns, such as those mentioned above. Figures 1 to 5DOne or more of the IC layout diagrams 200 to 400 are described. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers constituting various components of the IC device 1060 to be manufactured. Various layers are combined to form various IC features. For example, a portion of the IC design layout diagram 1022 includes various IC features, such as active regions, gate electrodes, source and drain electrodes, vias for metal lines or interlayer interconnects, and openings for bonding pads, to be formed on a semiconductor substrate (such as a silicon wafer) and in various material layers disposed on the semiconductor substrate. The design plant 1020 performs appropriate design procedures to form the IC design layout diagram 1022. Design procedures include one or more of logic design, physical design, or placement and routing. The IC design layout diagram 1022 is presented in one or more data files containing geometric pattern information. For example, the IC design layout diagram 1022 may be expressed in GDSII or DFII file format.

[0224] Photomask fabrication plant 1030 includes data preparation 1032 and photomask fabrication 1044. Photomask fabrication plant 1030 uses an IC design layout 1022 to fabricate one or more photomasks 1045 for fabricating various layers of an IC device 1060 according to the IC design layout 1022. Photomask fabrication plant 1030 performs photomask data preparation 1032, in which the IC design layout 1022 is translated into a representative data file (RDF). Photomask data preparation 1032 provides the RDF to photomask fabrication 1044. Photomask fabrication 1044 includes a photomask writer. The photomask writer converts the RDF into an image on a substrate, such as a photomask (master photomask) 1045 or a semiconductor wafer 1053. The design layout 1022 is manipulated by photomask data preparation 1032 to conform to the specific characteristics of the photomask writer and / or the requirements of the IC fabrication plant 1050. Figure 10 In the figure, photomask data preparation 1032 and photomask manufacturing 1044 are shown as separate components. In some embodiments, photomask data preparation 1032 and photomask manufacturing 1044 may be collectively referred to as photomask data preparation.

[0225] In some embodiments, mask data preparation 1032 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors such as self-diffraction, interference, other process effects, and the like. OPC adjustment IC design layout diagram 1022 is shown. In some embodiments, mask data preparation 1032 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other adaptation techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0226] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that examines the IC design layout 1022 through processes in an OPC employing a set of mask production rules containing certain geometric and / or connectivity constraints to ensure sufficient margin, account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for constraints during mask fabrication 1044, which may undo modifications performed by the OPC to satisfy the mask production rules.

[0227] In some embodiments, mask data preparation 1032 includes lithography process checking (LPC), which simulates the process to be performed by IC fabrication plant 1050 to manufacture IC device 1060. LPC simulates this process based on IC design layout 1022 to produce a simulated fabricated device, such as IC device 1060. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors such as virtual image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitability factors, and similar or combinations thereof. In some embodiments, after the simulated fabricated device has been produced by LPC, if the simulated device does not sufficiently approximate the design rules in shape, OPC and / or MRC are repeated to further refine the IC design layout 1022.

[0228] It should be understood that the above description of photomask data preparation 1032 has been simplified for clarity. In some embodiments, data preparation 1032 includes additional features, such as logic operations (LOPs), to modify the IC design layout 1022 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1022 during data preparation 1032 can be performed in a variety of different sequences.

[0229] Following photomask data preparation 1032 and during photomask fabrication 1044, photomask 1045 or a group of photomasks 1045 is fabricated based on a modified IC design layout 1022. In some embodiments, photomask fabrication 1044 includes performing one or more lithography exposures based on the IC design layout 1022. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to pattern the photomask (photomask or reticle) 1045 based on the modified IC design layout 1022. Photomask 1045 can be formed using various techniques. In some embodiments, photomask 1045 is formed using a binary technique. In some embodiments, the photomask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams or EUV beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer, are blocked through the opaque areas and transmitted through the transparent areas. In one example, a binary photomask version of photomask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in opaque areas. In another example, photomask 1045 is formed using a phase shift mask (PSM) technique. In a phase shift mask (PSM) version of photomask 1045, various features in a pattern formed on the PSM are used to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The photomask produced by photomask fabrication 1044 is used in a variety of processes. For example, such photomasks are used in ion implantation processes to form various doped regions in semiconductor wafer 1053, in etching processes to form various etched regions in semiconductor wafer 1053, and / or in other suitable processes.

[0230] IC manufacturing plant 1050 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC manufacturing plant 1050 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end-of-line (FEOL) manufacturing of multiple IC products, a second manufacturing facility that provides back-end-of-line (BEOL) manufacturing for interconnecting and packaging of IC products, and a third manufacturing facility that provides other services for the foundry business.

[0231] IC manufacturing plant 1050 includes wafer fabrication equipment 1052 for performing various manufacturing operations on semiconductor wafers 1053 to manufacture IC devices 1060 based on photomasks (e.g., photomask 1045). In various embodiments, fabrication equipment 1052 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other fabrication equipment capable of performing one or more suitable manufacturing processes described herein.

[0232] IC manufacturing plant 1050 uses multiple photomasks 1045 manufactured by photomask plant 1030 to manufacture IC device 1060. Therefore, IC manufacturing plant 1050 uses IC design layout 1022 at least indirectly to manufacture IC device 1060. In some embodiments, semiconductor wafer 1053 is manufactured by IC manufacturing plant 1050 using multiple photomasks 1045 to form IC device 1060. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1053 further includes various doped regions, dielectric features, multilevel interconnects, and one or more of the like (formed in subsequent manufacturing steps).

[0233] In some embodiments, the IC device includes a first transistor and a second transistor. The first transistor includes a first gate coupled to a first word line and including a first work function configuration, a first metal-like defined (MD) segment adjacent to the first gate and coupled to one of the bit line or reference line, and a second MD segment adjacent to the first gate and coupled to the other of the bit line or reference line. The second transistor includes a second gate coupled to a second word line and including a second work function configuration different from the first work function configuration, a second MD segment adjacent to the second gate, and a third MD segment adjacent to the second gate and coupled to one of the bit line or reference line.

[0234] In some embodiments, the first transistor further includes a third gate, a fourth type of metal-defined segment, and a fourth type of metal-defined segment. The third gate is adjacent to the first type of metal-defined segment and coupled to a first word line. The fourth type of metal-defined segment is adjacent to the third gate and coupled to another of the bit line or reference line. The second transistor further includes a fourth gate and a fifth type of metal-defined segment. The fourth gate is adjacent to the third type of metal-defined segment and coupled to a second word line. The fifth type of metal-defined segment is adjacent to the fourth gate and coupled to the other of the bit line or reference line.

[0235] In some embodiments, the integrated circuit device further includes an active region, a fifth gate, and a sixth gate. The active region extends between a first edge adjacent to a fourth type of metal-defined segment and a second edge adjacent to a fifth type of metal-defined segment. The fifth gate covers the first edge. The sixth gate covers the second edge. The first to fifth types of metal-defined segments are located on the active region between the fifth and sixth gates.

[0236] In some embodiments, the integrated circuit device further includes an active region, a third gate, and a fourth gate. The third gate covers the active region adjacent to the first type of metal-defined segment and is coupled to a reference line. The fourth gate covers the active region adjacent to the third type of metal-defined segment and is coupled to the reference line. The first to third type of metal-defined segments are located on the active region between the third and fourth gates.

[0237] In some embodiments, the integrated circuit device further includes an active region, a third gate, and a fourth gate. The active region extends between a first edge adjacent to a first type of metal-defined segment and a second edge adjacent to a third type of metal-defined segment. The third gate covers the first edge. The fourth gate covers the second edge. The first to third type of metal-defined segments are located on the active region between the third and fourth gates.

[0238] In some embodiments, the integrated circuit device further includes a first via structure, a second via structure, and a third via structure. The first via structure extends between a first type of metal-defined region and either a bit line or a reference line. The second via structure extends between the second type of metal-defined region and either a bit line or a reference line. The third via structure extends between the third type of metal-defined region and either a bit line or a reference line.

[0239] In some embodiments, each of the first and second transistors comprises a gate-all-around (GAA) transistor, a fin field-effect transistor (FinFET), or a planar transistor.

[0240] In some embodiments, the ROM circuit includes a plurality of word lines, a plurality of bit lines, a plurality of reference lines, and a plurality of ROM cells. Each ROM cell in the plurality of ROM cells includes a transistor and a sense amplifier. The transistor includes a first gate, a first MD segment, and a second MD segment. The first gate is coupled to a corresponding word line in the plurality of word lines and includes a corresponding work function configuration in the plurality of work function configurations. The second MD segment is adjacent to the first gate and coupled to a corresponding reference line in the plurality of reference lines. The sense amplifier is selectively coupled to each ROM cell in the plurality of ROM cells. The sense amplifier is used to output a plurality of bits having a work function configuration based on the plurality of work function configurations.

[0241] In some embodiments, the total number of work function configurations in these work function configurations is equal to four, and the total number of bits in these bits is equal to two.

[0242] In some embodiments, the transistor of each read-only memory cell further includes a second gate and a third metal-bound segment. The second gate is coupled to a corresponding word line among the word lines. The third metal-bound segment is adjacent to the second gate. The second gate is adjacent to a first metal-bound segment and the third metal-bound segment is coupled to a corresponding reference line among the reference lines; or the second gate is adjacent to a second metal-bound segment and the third metal-bound segment is coupled to a corresponding bit line among the bit lines.

[0243] In some embodiments, each of the read-only memory cells further includes a second gate. The second gate is adjacent to one of the first or second type of metal-defined segments and coupled to a corresponding reference line among the reference lines.

[0244] In some embodiments, each of these read-only memory cells further includes a dummy gate. The dummy gate is adjacent to one of the first or second type of metal-defined segments.

[0245] In some embodiments, each read-only memory cell further includes a first via structure and a second via structure. The first via structure extends between a first type of metal-defined region and a corresponding bit line among the bit lines. The second via structure extends between a second type of metal-defined region and a corresponding reference line among the reference lines.

[0246] In some embodiments, the transistors of each read-only memory cell in these read-only memory cells include gate-all-around (GAA) transistors, fin field-effect transistors (FinFETs), or planar transistors.

[0247] In some embodiments, a method of manufacturing an IC device includes constructing a first transistor, the first transistor comprising constructing a first gate including a first work function configuration, and forming first and second MD segments adjacent to the first gate; constructing a second transistor, the second transistor comprising constructing a second gate adjacent to the second MD segment and including a second work function configuration different from the first work function configuration, and forming a third MD segment adjacent to the second gate; forming first to fifth via structures on individual first to third MD segments and the first and second gates, forming one of a bit line or a reference line on each of the first and third via structures and forming the other of a bit line or reference line on the second via; and forming first and second word lines on individual fourth and fifth via structures.

[0248] In some embodiments, the step of constructing the first transistor further includes the following steps: constructing a third gate adjacent to a first type of metal-defined segment; and forming a fourth type of metal-defined segment adjacent to the third gate. The step of constructing the second transistor further includes the following steps: constructing a fourth gate adjacent to a third type of metal-defined segment; and forming a fifth type of metal-defined segment adjacent to the fourth gate. The step of forming the first to fifth via structures further includes the following steps: forming sixth to ninth via structures on individual fourth and fifth type of metal-defined segments and third and fourth gates. The step of forming the other of the bit line or reference line includes the following steps: forming the other of the bit line or reference line on each of the sixth and seventh via structures. The step of forming the first and second word lines further includes the following steps: forming the first and second word lines on individual eighth and ninth via structures.

[0249] In some embodiments, the step of forming the first to fifth type metal defining segments includes the following steps: forming the first to fifth type metal defining segments on an active region extending between a first edge adjacent to the fourth type metal defining segment and a second edge adjacent to the fifth type metal defining segment. The method further includes the step of constructing fifth and sixth gates covering the first and second edges.

[0250] In some embodiments, the step of forming the first to third type metal-defined segments includes the following steps: forming the first to third type metal-defined segments on the active region. The method further includes the following steps: constructing a third gate covering the active region adjacent to the first type metal-defined segment; constructing a fourth gate covering the active region adjacent to the third type metal-defined segment; and constructing a plurality of electrical connections between each of the third and fourth gates and a reference line.

[0251] In some embodiments, the step of forming the first to third type metal defining segments includes the following steps: forming the first to third type metal defining segments on an active region extending between a first edge adjacent to the first type metal defining segment and a second edge adjacent to the third type metal defining segment. The method further includes the step of constructing third and fourth gates covering the first and second edges.

[0252] In some embodiments, the steps of constructing the first and second transistors include the following steps: constructing a plurality of gate-all-around (GAA) transistors; constructing a plurality of fin field-effect transistors (FinFETs); or constructing a plurality of planar transistors.

[0253] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of an embodiment disclosed herein. Those skilled in the art will understand that an embodiment disclosed herein can be used as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of an embodiment disclosed herein, and that such equivalent structures can be modified, substituted, and replaced in various ways without departing from the spirit and scope of an embodiment disclosed herein.

Claims

1. An integrated circuit device, characterized by Comprising: a first transistor comprising: a first gate coupled to a first word line and comprising a first work function configuration; a first metal gate defined segment adjacent to the first gate and coupled to one of a bit line or a reference line; and a second metal gate defined segment adjacent to the first gate and coupled to the other of the bit line or the reference line; and a second transistor comprising: a second gate coupled to a second word line and comprising a second work function configuration different from the first work function configuration, the second metal gate defined segment adjacent to the second gate; and a third metal gate defined segment adjacent to the second gate and coupled to the one of the bit line or the reference line.

2. The integrated circuit device of claim 1, wherein: the first transistor further comprises: a third gate adjacent to the first metal gate defined segment and coupled to the first word line; and a fourth metal gate defined segment adjacent to the third gate and coupled to the other of the bit line or the reference line, and the second transistor further comprises: a fourth gate adjacent to the third metal gate defined segment and coupled to the second word line; and a fifth metal gate defined segment adjacent to the fourth gate and coupled to the other of the bit line or the reference line.

3. The integrated circuit device of claim 2, wherein, further comprising: an active region extending between a first edge adjacent to the fourth metal gate defined segment and a second edge adjacent to the fifth metal gate defined segment: a fifth gate overlying the first edge; and a sixth gate overlying the second edge; and wherein the first through fifth metal gate defined segments are positioned on the active region between the fifth and sixth gates.

4. The integrated circuit device of claim 1, wherein, further comprising: an active region; a third gate overlying the active region adjacent to the first metal gate defined segment and coupled to the reference line; and a fourth gate overlying the active region adjacent to the third metal gate defined segment and coupled to the reference line, wherein the first through third metal gate defined segments are positioned on the active region between the third and fourth gates.

5. The integrated circuit device of claim 1, wherein, further comprising: an active region extending between a first edge adjacent to the first metal gate defined segment and a second edge adjacent to the third metal gate defined segment; a third gate overlying the first edge; and a fourth gate overlying the second edge, wherein the first through third metal gate defined segments are positioned on the active region between the third and fourth gates.

6. The integrated circuit device of claim 1, wherein, further comprising: a first via structure extending between the first metal gate defined segment and the one of the bit line or the reference line; a second via structure extending between the second metal gate defined segment and the other of the bit line or the reference line; and a third via structure extending between the third metal gate defined segment and the one of the bit line or the reference line. each of the first and second transistors comprises:

7. The integrated circuit device of claim 1, wherein, a gate-all-around transistor, a fin field effect transistor, or a planar transistor. comprising:

8. A read-only memory circuit, characterized by a plurality of word lines; a plurality of bit lines; a plurality of reference lines; ​ A plurality of read only memory cells, wherein each read only memory cell of the plurality of read only memory cells includes a transistor including: a first gate coupled to a corresponding word line of the plurality of word lines and including a corresponding work function configuration of a plurality of work function configurations; a first metal-like defined section adjacent to the first gate and coupled to a corresponding bit line of the plurality of bit lines; and a second metal-like defined section adjacent to the first gate and coupled to a corresponding reference line of the plurality of reference lines; and a sense amplifier selectively coupled to each read only memory cell of the plurality of read only memory cells, wherein the sense amplifier is to output a plurality of bits having a plurality of values based on the work function configuration of the plurality of work function configurations.

9. The read only memory circuit of claim 8, wherein: a total number of work function configurations of the plurality of work function configurations is equal to four, and a total number of bits of the plurality of bits is equal to two.

10. A method of fabricating an integrated circuit device, comprising: The method includes the steps of: constructing a first transistor, the step of constructing the first transistor including the steps of: constructing a first gate including a first work function configuration; and forming first and second metal-like defined sections adjacent to the first gate; constructing a second transistor, the step of constructing the second transistor including the steps of: constructing a second gate adjacent to the second metal-like defined section and including a second work function configuration different from the first work function configuration; and forming a third metal-like defined section adjacent to the second gate; forming first through fifth via structures on the respective first through third metal-like defined sections and first and second gates; forming one of a bit line or a reference line on each of the first and third via structures, the other of the bit line or the reference line on the second via structure; and forming first and second word lines on the respective fourth and fifth via structures.

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